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1 ;; ARM 926EJ-S Pipeline Description
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2 ;; Copyright (C) 2003, 2007 Free Software Foundation, Inc.
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3 ;; Written by CodeSourcery, LLC.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but
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13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 ;; General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>. */
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20
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21 ;; These descriptions are based on the information contained in the
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22 ;; ARM926EJ-S Technical Reference Manual, Copyright (c) 2002 ARM
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23 ;; Limited.
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24 ;;
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25
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26 ;; This automaton provides a pipeline description for the ARM
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27 ;; 926EJ-S core.
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28 ;;
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29 ;; The model given here assumes that the condition for all conditional
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30 ;; instructions is "true", i.e., that all of the instructions are
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31 ;; actually executed.
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32
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33 (define_automaton "arm926ejs")
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34
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35 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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36 ;; Pipelines
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37 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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38
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39 ;; There is a single pipeline
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40 ;;
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41 ;; The ALU pipeline has fetch, decode, execute, memory, and
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42 ;; write stages. We only need to model the execute, memory and write
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43 ;; stages.
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44
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45 (define_cpu_unit "e,m,w" "arm926ejs")
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46
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47 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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48 ;; ALU Instructions
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49 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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50
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51 ;; ALU instructions require three cycles to execute, and use the ALU
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52 ;; pipeline in each of the three stages. The results are available
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53 ;; after the execute stage stage has finished.
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54 ;;
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55 ;; If the destination register is the PC, the pipelines are stalled
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56 ;; for several cycles. That case is not modeled here.
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57
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58 ;; ALU operations with no shifted operand
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59 (define_insn_reservation "9_alu_op" 1
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60 (and (eq_attr "tune" "arm926ejs")
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61 (eq_attr "type" "alu,alu_shift"))
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62 "e,m,w")
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63
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64 ;; ALU operations with a shift-by-register operand
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65 ;; These really stall in the decoder, in order to read
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66 ;; the shift value in a second cycle. Pretend we take two cycles in
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67 ;; the execute stage.
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68 (define_insn_reservation "9_alu_shift_reg_op" 2
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69 (and (eq_attr "tune" "arm926ejs")
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70 (eq_attr "type" "alu_shift_reg"))
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71 "e*2,m,w")
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72
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73 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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74 ;; Multiplication Instructions
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75 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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76
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77 ;; Multiplication instructions loop in the execute stage until the
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78 ;; instruction has been passed through the multiplier array enough
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79 ;; times. Multiply operations occur in both the execute and memory
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80 ;; stages of the pipeline
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81
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82 (define_insn_reservation "9_mult1" 3
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83 (and (eq_attr "tune" "arm926ejs")
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84 (eq_attr "insn" "smlalxy,mul,mla"))
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85 "e*2,m,w")
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86
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87 (define_insn_reservation "9_mult2" 4
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88 (and (eq_attr "tune" "arm926ejs")
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89 (eq_attr "insn" "muls,mlas"))
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90 "e*3,m,w")
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91
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92 (define_insn_reservation "9_mult3" 4
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93 (and (eq_attr "tune" "arm926ejs")
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94 (eq_attr "insn" "umull,umlal,smull,smlal"))
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95 "e*3,m,w")
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96
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97 (define_insn_reservation "9_mult4" 5
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98 (and (eq_attr "tune" "arm926ejs")
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99 (eq_attr "insn" "umulls,umlals,smulls,smlals"))
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100 "e*4,m,w")
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101
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102 (define_insn_reservation "9_mult5" 2
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103 (and (eq_attr "tune" "arm926ejs")
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104 (eq_attr "insn" "smulxy,smlaxy,smlawx"))
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105 "e,m,w")
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106
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107 (define_insn_reservation "9_mult6" 3
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108 (and (eq_attr "tune" "arm926ejs")
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109 (eq_attr "insn" "smlalxy"))
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110 "e*2,m,w")
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111
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112 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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113 ;; Load/Store Instructions
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114 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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115
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116 ;; The models for load/store instructions do not accurately describe
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117 ;; the difference between operations with a base register writeback
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118 ;; (such as "ldm!"). These models assume that all memory references
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119 ;; hit in dcache.
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120
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121 ;; Loads with a shifted offset take 3 cycles, and are (a) probably the
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122 ;; most common and (b) the pessimistic assumption will lead to fewer stalls.
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123 (define_insn_reservation "9_load1_op" 3
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124 (and (eq_attr "tune" "arm926ejs")
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125 (eq_attr "type" "load1,load_byte"))
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126 "e*2,m,w")
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127
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128 (define_insn_reservation "9_store1_op" 0
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129 (and (eq_attr "tune" "arm926ejs")
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130 (eq_attr "type" "store1"))
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131 "e,m,w")
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132
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133 ;; multiple word loads and stores
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134 (define_insn_reservation "9_load2_op" 3
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135 (and (eq_attr "tune" "arm926ejs")
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136 (eq_attr "type" "load2"))
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137 "e,m*2,w")
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138
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139 (define_insn_reservation "9_load3_op" 4
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140 (and (eq_attr "tune" "arm926ejs")
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141 (eq_attr "type" "load3"))
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142 "e,m*3,w")
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143
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144 (define_insn_reservation "9_load4_op" 5
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145 (and (eq_attr "tune" "arm926ejs")
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146 (eq_attr "type" "load4"))
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147 "e,m*4,w")
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148
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149 (define_insn_reservation "9_store2_op" 0
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150 (and (eq_attr "tune" "arm926ejs")
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151 (eq_attr "type" "store2"))
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152 "e,m*2,w")
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153
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154 (define_insn_reservation "9_store3_op" 0
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155 (and (eq_attr "tune" "arm926ejs")
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156 (eq_attr "type" "store3"))
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157 "e,m*3,w")
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158
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159 (define_insn_reservation "9_store4_op" 0
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160 (and (eq_attr "tune" "arm926ejs")
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161 (eq_attr "type" "store4"))
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162 "e,m*4,w")
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163
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164 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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165 ;; Branch and Call Instructions
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166 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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167
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168 ;; Branch instructions are difficult to model accurately. The ARM
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169 ;; core can predict most branches. If the branch is predicted
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170 ;; correctly, and predicted early enough, the branch can be completely
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171 ;; eliminated from the instruction stream. Some branches can
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172 ;; therefore appear to require zero cycles to execute. We assume that
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173 ;; all branches are predicted correctly, and that the latency is
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174 ;; therefore the minimum value.
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175
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176 (define_insn_reservation "9_branch_op" 0
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177 (and (eq_attr "tune" "arm926ejs")
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178 (eq_attr "type" "branch"))
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179 "nothing")
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180
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181 ;; The latency for a call is not predictable. Therefore, we use 32 as
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182 ;; roughly equivalent to positive infinity.
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183
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184 (define_insn_reservation "9_call_op" 32
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185 (and (eq_attr "tune" "arm926ejs")
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186 (eq_attr "type" "call"))
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187 "nothing")
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