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1 ;; Cirrus EP9312 "Maverick" ARM floating point co-processor description.
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2 ;; Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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3 ;; Contributed by Red Hat.
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4 ;; Written by Aldy Hernandez (aldyh@redhat.com)
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5
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6 ;; This file is part of GCC.
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7
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8 ;; GCC is free software; you can redistribute it and/or modify
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9 ;; it under the terms of the GNU General Public License as published by
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10 ;; the Free Software Foundation; either version 3, or (at your option)
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11 ;; any later version.
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12
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13 ;; GCC is distributed in the hope that it will be useful,
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14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 ;; GNU General Public License for more details.
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17
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22
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23 ; Cirrus types for invalid insn combinations
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24 ; not Not a cirrus insn
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25 ; normal Any Cirrus insn not covered by the special cases below
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26 ; double cfldrd, cfldr64, cfstrd, cfstr64
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27 ; compare cfcmps, cfcmpd, cfcmp32, cfcmp64
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28 ; move cfmvdlr, cfmvdhr, cfmvsr, cfmv64lr, cfmv64hr
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29 (define_attr "cirrus" "not,normal,double,compare,move" (const_string "not"))
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30
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31
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32 (define_insn "cirrus_adddi3"
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33 [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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34 (plus:DI (match_operand:DI 1 "cirrus_fp_register" "v")
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35 (match_operand:DI 2 "cirrus_fp_register" "v")))]
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36 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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37 "cfadd64%?\\t%V0, %V1, %V2"
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38 [(set_attr "type" "mav_farith")
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39 (set_attr "cirrus" "normal")]
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40 )
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41
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42 (define_insn "*cirrus_addsi3"
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43 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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44 (plus:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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45 (match_operand:SI 2 "cirrus_fp_register" "v")))]
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46 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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47 "cfadd32%?\\t%V0, %V1, %V2"
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48 [(set_attr "type" "mav_farith")
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49 (set_attr "cirrus" "normal")]
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50 )
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51
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52 (define_insn "*cirrus_addsf3"
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53 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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54 (plus:SF (match_operand:SF 1 "cirrus_fp_register" "v")
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55 (match_operand:SF 2 "cirrus_fp_register" "v")))]
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56 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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57 "cfadds%?\\t%V0, %V1, %V2"
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58 [(set_attr "type" "mav_farith")
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59 (set_attr "cirrus" "normal")]
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60 )
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61
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62 (define_insn "*cirrus_adddf3"
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63 [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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64 (plus:DF (match_operand:DF 1 "cirrus_fp_register" "v")
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65 (match_operand:DF 2 "cirrus_fp_register" "v")))]
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66 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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67 "cfaddd%?\\t%V0, %V1, %V2"
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68 [(set_attr "type" "mav_farith")
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69 (set_attr "cirrus" "normal")]
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70 )
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71
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72 (define_insn "cirrus_subdi3"
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73 [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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74 (minus:DI (match_operand:DI 1 "cirrus_fp_register" "v")
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75 (match_operand:DI 2 "cirrus_fp_register" "v")))]
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76 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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77 "cfsub64%?\\t%V0, %V1, %V2"
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78 [(set_attr "type" "mav_farith")
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79 (set_attr "cirrus" "normal")]
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80 )
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81
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82 (define_insn "*cirrus_subsi3_insn"
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83 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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84 (minus:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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85 (match_operand:SI 2 "cirrus_fp_register" "v")))]
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86 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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87 "cfsub32%?\\t%V0, %V1, %V2"
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88 [(set_attr "type" "mav_farith")
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89 (set_attr "cirrus" "normal")]
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90 )
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91
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92 (define_insn "*cirrus_subsf3"
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93 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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94 (minus:SF (match_operand:SF 1 "cirrus_fp_register" "v")
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95 (match_operand:SF 2 "cirrus_fp_register" "v")))]
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96 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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97 "cfsubs%?\\t%V0, %V1, %V2"
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98 [(set_attr "type" "mav_farith")
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99 (set_attr "cirrus" "normal")]
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100 )
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101
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102 (define_insn "*cirrus_subdf3"
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103 [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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104 (minus:DF (match_operand:DF 1 "cirrus_fp_register" "v")
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105 (match_operand:DF 2 "cirrus_fp_register" "v")))]
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106 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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107 "cfsubd%?\\t%V0, %V1, %V2"
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108 [(set_attr "type" "mav_farith")
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109 (set_attr "cirrus" "normal")]
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110 )
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111
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112 (define_insn "*cirrus_mulsi3"
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113 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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114 (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v")
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115 (match_operand:SI 1 "cirrus_fp_register" "v")))]
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116 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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117 "cfmul32%?\\t%V0, %V1, %V2"
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118 [(set_attr "type" "mav_farith")
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119 (set_attr "cirrus" "normal")]
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120 )
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121
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122 (define_insn "muldi3"
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123 [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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124 (mult:DI (match_operand:DI 2 "cirrus_fp_register" "v")
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125 (match_operand:DI 1 "cirrus_fp_register" "v")))]
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126 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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127 "cfmul64%?\\t%V0, %V1, %V2"
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128 [(set_attr "type" "mav_dmult")
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129 (set_attr "cirrus" "normal")]
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130 )
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131
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132 (define_insn "*cirrus_mulsi3addsi"
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133 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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134 (plus:SI
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135 (mult:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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136 (match_operand:SI 2 "cirrus_fp_register" "v"))
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137 (match_operand:SI 3 "cirrus_fp_register" "0")))]
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138 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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139 "cfmac32%?\\t%V0, %V1, %V2"
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140 [(set_attr "type" "mav_farith")
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141 (set_attr "cirrus" "normal")]
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142 )
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143
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144 ;; Cirrus SI multiply-subtract
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145 (define_insn "*cirrus_mulsi3subsi"
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146 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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147 (minus:SI
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148 (match_operand:SI 1 "cirrus_fp_register" "0")
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149 (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v")
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150 (match_operand:SI 3 "cirrus_fp_register" "v"))))]
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151 "0 && TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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152 "cfmsc32%?\\t%V0, %V2, %V3"
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153 [(set_attr "type" "mav_farith")
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154 (set_attr "cirrus" "normal")]
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155 )
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156
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157 (define_insn "*cirrus_mulsf3"
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158 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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159 (mult:SF (match_operand:SF 1 "cirrus_fp_register" "v")
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160 (match_operand:SF 2 "cirrus_fp_register" "v")))]
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161 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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162 "cfmuls%?\\t%V0, %V1, %V2"
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163 [(set_attr "type" "mav_farith")
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164 (set_attr "cirrus" "normal")]
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165 )
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166
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167 (define_insn "*cirrus_muldf3"
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168 [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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169 (mult:DF (match_operand:DF 1 "cirrus_fp_register" "v")
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170 (match_operand:DF 2 "cirrus_fp_register" "v")))]
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171 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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172 "cfmuld%?\\t%V0, %V1, %V2"
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173 [(set_attr "type" "mav_dmult")
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174 (set_attr "cirrus" "normal")]
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175 )
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176
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177 (define_insn "cirrus_ashl_const"
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178 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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179 (ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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180 (match_operand:SI 2 "cirrus_shift_const" "")))]
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181 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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182 "cfsh32%?\\t%V0, %V1, #%s2"
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183 [(set_attr "cirrus" "normal")]
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184 )
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185
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186 (define_insn "cirrus_ashiftrt_const"
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187 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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188 (ashiftrt:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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189 (match_operand:SI 2 "cirrus_shift_const" "")))]
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190 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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191 "cfsh32%?\\t%V0, %V1, #-%s2"
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192 [(set_attr "cirrus" "normal")]
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193 )
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194
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195 (define_insn "cirrus_ashlsi3"
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196 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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197 (ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v")
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198 (match_operand:SI 2 "register_operand" "r")))]
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199 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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200 "cfrshl32%?\\t%V1, %V0, %s2"
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201 [(set_attr "cirrus" "normal")]
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202 )
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203
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204 (define_insn "ashldi3_cirrus"
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205 [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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206 (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v")
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207 (match_operand:SI 2 "register_operand" "r")))]
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208 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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209 "cfrshl64%?\\t%V1, %V0, %s2"
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210 [(set_attr "cirrus" "normal")]
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211 )
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212
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213 (define_insn "cirrus_ashldi_const"
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214 [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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215 (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v")
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216 (match_operand:SI 2 "cirrus_shift_const" "")))]
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217 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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218 "cfsh64%?\\t%V0, %V1, #%s2"
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219 [(set_attr "cirrus" "normal")]
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220 )
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221
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222 (define_insn "cirrus_ashiftrtdi_const"
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223 [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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224 (ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register" "v")
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225 (match_operand:SI 2 "cirrus_shift_const" "")))]
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226 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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227 "cfsh64%?\\t%V0, %V1, #-%s2"
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228 [(set_attr "cirrus" "normal")]
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229 )
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230
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231 (define_insn "*cirrus_absdi2"
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232 [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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233 (abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))]
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234 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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235 "cfabs64%?\\t%V0, %V1"
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236 [(set_attr "cirrus" "normal")]
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237 )
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238
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239 ;; This doesn't really clobber ``cc''. Fixme: aldyh.
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240 (define_insn "*cirrus_negdi2"
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241 [(set (match_operand:DI 0 "cirrus_fp_register" "=v")
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242 (neg:DI (match_operand:DI 1 "cirrus_fp_register" "v")))
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243 (clobber (reg:CC CC_REGNUM))]
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244 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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245 "cfneg64%?\\t%V0, %V1"
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246 [(set_attr "cirrus" "normal")]
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247 )
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248
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249 (define_insn "*cirrus_negsi2"
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250 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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251 (neg:SI (match_operand:SI 1 "cirrus_fp_register" "v")))]
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252 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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253 "cfneg32%?\\t%V0, %V1"
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254 [(set_attr "cirrus" "normal")]
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255 )
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256
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257 (define_insn "*cirrus_negsf2"
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258 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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259 (neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
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260 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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261 "cfnegs%?\\t%V0, %V1"
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262 [(set_attr "cirrus" "normal")]
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263 )
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264
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265 (define_insn "*cirrus_negdf2"
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266 [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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267 (neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
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268 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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269 "cfnegd%?\\t%V0, %V1"
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270 [(set_attr "cirrus" "normal")]
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271 )
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272
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273 ;; This doesn't really clobber the condition codes either.
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274 (define_insn "*cirrus_abssi2"
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275 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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276 (abs:SI (match_operand:SI 1 "cirrus_fp_register" "v")))
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277 (clobber (reg:CC CC_REGNUM))]
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278 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"
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279 "cfabs32%?\\t%V0, %V1"
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280 [(set_attr "cirrus" "normal")]
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281 )
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282
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283 (define_insn "*cirrus_abssf2"
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284 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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285 (abs:SF (match_operand:SF 1 "cirrus_fp_register" "v")))]
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286 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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287 "cfabss%?\\t%V0, %V1"
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288 [(set_attr "cirrus" "normal")]
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289 )
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290
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291 (define_insn "*cirrus_absdf2"
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292 [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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293 (abs:DF (match_operand:DF 1 "cirrus_fp_register" "v")))]
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294 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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295 "cfabsd%?\\t%V0, %V1"
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296 [(set_attr "cirrus" "normal")]
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297 )
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298
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299 ;; Convert Cirrus-SI to Cirrus-SF
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300 (define_insn "cirrus_floatsisf2"
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301 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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302 (float:SF (match_operand:SI 1 "s_register_operand" "r")))
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303 (clobber (match_scratch:DF 2 "=v"))]
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304 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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305 "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2"
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306 [(set_attr "length" "8")
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307 (set_attr "cirrus" "move")]
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308 )
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309
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310 (define_insn "cirrus_floatsidf2"
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311 [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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312 (float:DF (match_operand:SI 1 "s_register_operand" "r")))
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313 (clobber (match_scratch:DF 2 "=v"))]
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314 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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315 "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2"
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316 [(set_attr "length" "8")
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317 (set_attr "cirrus" "move")]
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318 )
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319
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320 (define_insn "floatdisf2"
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321 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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322 (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))]
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323 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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324 "cfcvt64s%?\\t%V0, %V1"
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325 [(set_attr "cirrus" "normal")])
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326
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327 (define_insn "floatdidf2"
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328 [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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329 (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))]
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330 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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331 "cfcvt64d%?\\t%V0, %V1"
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332 [(set_attr "cirrus" "normal")])
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333
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334 (define_insn "cirrus_truncsfsi2"
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335 [(set (match_operand:SI 0 "s_register_operand" "=r")
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336 (fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v"))))
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337 (clobber (match_scratch:DF 2 "=v"))]
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338 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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339 "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
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340 [(set_attr "length" "8")
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341 (set_attr "cirrus" "normal")]
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342 )
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343
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344 (define_insn "cirrus_truncdfsi2"
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345 [(set (match_operand:SI 0 "s_register_operand" "=r")
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346 (fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register" "v"))))
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347 (clobber (match_scratch:DF 2 "=v"))]
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348 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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349 "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2"
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350 [(set_attr "length" "8")]
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351 )
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352
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353 (define_insn "*cirrus_truncdfsf2"
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354 [(set (match_operand:SF 0 "cirrus_fp_register" "=v")
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355 (float_truncate:SF
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356 (match_operand:DF 1 "cirrus_fp_register" "v")))]
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357 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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358 "cfcvtds%?\\t%V0, %V1"
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359 [(set_attr "cirrus" "normal")]
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|
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360 )
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361
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362 (define_insn "*cirrus_extendsfdf2"
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363 [(set (match_operand:DF 0 "cirrus_fp_register" "=v")
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364 (float_extend:DF (match_operand:SF 1 "cirrus_fp_register" "v")))]
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365 "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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366 "cfcvtsd%?\\t%V0, %V1"
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367 [(set_attr "cirrus" "normal")]
|
|
|
368 )
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369
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370 (define_insn "*cirrus_arm_movdi"
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371 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v")
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|
|
372 (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))]
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|
|
373 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
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|
374 "*
|
|
|
375 {
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|
|
376 switch (which_alternative)
|
|
|
377 {
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|
|
378 case 0:
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|
379 return \"#\";
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|
380 case 1:
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|
|
381 case 2:
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|
382 return output_move_double (operands);
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|
|
383
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|
384 case 3: return \"cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\";
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|
|
385 case 4: return \"cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\";
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|
|
386
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|
|
387 case 5: return \"cfldr64%?\\t%V0, %1\";
|
|
|
388 case 6: return \"cfstr64%?\\t%V1, %0\";
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|
|
389
|
|
|
390 /* Shifting by 0 will just copy %1 into %0. */
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|
|
391 case 7: return \"cfsh64%?\\t%V0, %V1, #0\";
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|
|
392
|
|
|
393 default: gcc_unreachable ();
|
|
|
394 }
|
|
|
395 }"
|
|
|
396 [(set_attr "length" " 8, 8, 8, 8, 8, 4, 4, 4")
|
|
|
397 (set_attr "type" " *,load2,store2, *, *, load2,store2, *")
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|
398 (set_attr "pool_range" " *,1020, *, *, *, 1020, *, *")
|
|
|
399 (set_attr "neg_pool_range" " *,1012, *, *, *, 1008, *, *")
|
|
|
400 (set_attr "cirrus" "not, not, not,move,normal,double,double,normal")]
|
|
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401 )
|
|
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402
|
|
|
403 ;; Cirrus SI values have been outlawed. Look in arm.h for the comment
|
|
|
404 ;; on HARD_REGNO_MODE_OK.
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|
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405
|
|
|
406 (define_insn "*cirrus_movsf_hard_insn"
|
|
|
407 [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m")
|
|
|
408 (match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))]
|
|
|
409 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK
|
|
|
410 && (GET_CODE (operands[0]) != MEM
|
|
|
411 || register_operand (operands[1], SFmode))"
|
|
|
412 "@
|
|
|
413 cfcpys%?\\t%V0, %V1
|
|
|
414 cfldrs%?\\t%V0, %1
|
|
|
415 cfmvsr%?\\t%V0, %1
|
|
|
416 cfmvrs%?\\t%0, %V1
|
|
|
417 cfstrs%?\\t%V1, %0
|
|
|
418 mov%?\\t%0, %1
|
|
|
419 ldr%?\\t%0, %1\\t%@ float
|
|
|
420 str%?\\t%1, %0\\t%@ float"
|
|
|
421 [(set_attr "length" " *, *, *, *, *, 4, 4, 4")
|
|
|
422 (set_attr "type" " *, load1, *, *,store1, *,load1,store1")
|
|
|
423 (set_attr "pool_range" " *, 1020, *, *, *, *,4096, *")
|
|
|
424 (set_attr "neg_pool_range" " *, 1008, *, *, *, *,4084, *")
|
|
|
425 (set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")]
|
|
|
426 )
|
|
|
427
|
|
|
428 (define_insn "*cirrus_movdf_hard_insn"
|
|
|
429 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m")
|
|
|
430 (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))]
|
|
|
431 "TARGET_ARM
|
|
|
432 && TARGET_HARD_FLOAT && TARGET_MAVERICK
|
|
|
433 && (GET_CODE (operands[0]) != MEM
|
|
|
434 || register_operand (operands[1], DFmode))"
|
|
|
435 "*
|
|
|
436 {
|
|
|
437 switch (which_alternative)
|
|
|
438 {
|
|
|
439 case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\";
|
|
|
440 case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\";
|
|
|
441 case 2: return \"#\";
|
|
|
442 case 3: case 4: return output_move_double (operands);
|
|
|
443 case 5: return \"cfcpyd%?\\t%V0, %V1\";
|
|
|
444 case 6: return \"cfldrd%?\\t%V0, %1\";
|
|
|
445 case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\";
|
|
|
446 case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\";
|
|
|
447 case 9: return \"cfstrd%?\\t%V1, %0\";
|
|
|
448 default: gcc_unreachable ();
|
|
|
449 }
|
|
|
450 }"
|
|
|
451 [(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2")
|
|
|
452 (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4")
|
|
|
453 (set_attr "pool_range" " *, *, *, *, 252, *, 1020, *, *, *")
|
|
|
454 (set_attr "neg_pool_range" " *, *, *, *, 244, *, 1008, *, *, *")
|
|
|
455 (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")]
|
|
|
456 )
|
|
|
457
|
|
|
458 (define_insn "*cirrus_thumb2_movdi"
|
|
|
459 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v")
|
|
|
460 (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))]
|
|
|
461 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_MAVERICK"
|
|
|
462 "*
|
|
|
463 {
|
|
|
464 switch (which_alternative)
|
|
|
465 {
|
|
|
466 case 0:
|
|
|
467 case 1:
|
|
|
468 case 2:
|
|
|
469 return (output_move_double (operands));
|
|
|
470
|
|
|
471 case 3: return \"cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\";
|
|
|
472 case 4: return \"cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\";
|
|
|
473
|
|
|
474 case 5: return \"cfldr64%?\\t%V0, %1\";
|
|
|
475 case 6: return \"cfstr64%?\\t%V1, %0\";
|
|
|
476
|
|
|
477 /* Shifting by 0 will just copy %1 into %0. */
|
|
|
478 case 7: return \"cfsh64%?\\t%V0, %V1, #0\";
|
|
|
479
|
|
|
480 default: abort ();
|
|
|
481 }
|
|
|
482 }"
|
|
|
483 [(set_attr "length" " 8, 8, 8, 8, 8, 4, 4, 4")
|
|
|
484 (set_attr "type" " *,load2,store2, *, *, load2,store2, *")
|
|
|
485 (set_attr "pool_range" " *,4096, *, *, *, 1020, *, *")
|
|
|
486 (set_attr "neg_pool_range" " *, 0, *, *, *, 1008, *, *")
|
|
|
487 (set_attr "cirrus" "not, not, not,move,normal,double,double,normal")]
|
|
|
488 )
|
|
|
489
|
|
|
490 (define_insn "*thumb2_cirrus_movsf_hard_insn"
|
|
|
491 [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m")
|
|
|
492 (match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))]
|
|
|
493 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_MAVERICK
|
|
|
494 && (GET_CODE (operands[0]) != MEM
|
|
|
495 || register_operand (operands[1], SFmode))"
|
|
|
496 "@
|
|
|
497 cfcpys%?\\t%V0, %V1
|
|
|
498 cfldrs%?\\t%V0, %1
|
|
|
499 cfmvsr%?\\t%V0, %1
|
|
|
500 cfmvrs%?\\t%0, %V1
|
|
|
501 cfstrs%?\\t%V1, %0
|
|
|
502 mov%?\\t%0, %1
|
|
|
503 ldr%?\\t%0, %1\\t%@ float
|
|
|
504 str%?\\t%1, %0\\t%@ float"
|
|
|
505 [(set_attr "length" " *, *, *, *, *, 4, 4, 4")
|
|
|
506 (set_attr "type" " *, load1, *, *,store1, *,load1,store1")
|
|
|
507 (set_attr "pool_range" " *, 1020, *, *, *, *,4096, *")
|
|
|
508 (set_attr "neg_pool_range" " *, 1008, *, *, *, *, 0, *")
|
|
|
509 (set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")]
|
|
|
510 )
|
|
|
511
|
|
|
512 (define_insn "*thumb2_cirrus_movdf_hard_insn"
|
|
|
513 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m")
|
|
|
514 (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))]
|
|
|
515 "TARGET_THUMB2
|
|
|
516 && TARGET_HARD_FLOAT && TARGET_MAVERICK
|
|
|
517 && (GET_CODE (operands[0]) != MEM
|
|
|
518 || register_operand (operands[1], DFmode))"
|
|
|
519 "*
|
|
|
520 {
|
|
|
521 switch (which_alternative)
|
|
|
522 {
|
|
|
523 case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\";
|
|
|
524 case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\";
|
|
|
525 case 2: case 3: case 4: return output_move_double (operands);
|
|
|
526 case 5: return \"cfcpyd%?\\t%V0, %V1\";
|
|
|
527 case 6: return \"cfldrd%?\\t%V0, %1\";
|
|
|
528 case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\";
|
|
|
529 case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\";
|
|
|
530 case 9: return \"cfstrd%?\\t%V1, %0\";
|
|
|
531 default: abort ();
|
|
|
532 }
|
|
|
533 }"
|
|
|
534 [(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2")
|
|
|
535 (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4")
|
|
|
536 (set_attr "pool_range" " *, *, *, *,4092, *, 1020, *, *, *")
|
|
|
537 (set_attr "neg_pool_range" " *, *, *, *, 0, *, 1008, *, *, *")
|
|
|
538 (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")]
|
|
|
539 )
|
|
|
540
|
