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1 ;; ARM Cortex-A8 scheduling description.
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2 ;; Copyright (C) 2007 Free Software Foundation, Inc.
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3 ;; Contributed by CodeSourcery.
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4
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_automaton "cortex_a8")
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22
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23 ;; Only one load/store instruction can be issued per cycle
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24 ;; (although reservation of this unit is only required for single
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25 ;; loads and stores -- see below).
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26 (define_cpu_unit "cortex_a8_issue_ls" "cortex_a8")
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27
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28 ;; Only one branch instruction can be issued per cycle.
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29 (define_cpu_unit "cortex_a8_issue_branch" "cortex_a8")
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30
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31 ;; The two ALU pipelines.
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32 (define_cpu_unit "cortex_a8_alu0" "cortex_a8")
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33 (define_cpu_unit "cortex_a8_alu1" "cortex_a8")
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34
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35 ;; The usual flow of an instruction through the pipelines.
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36 (define_reservation "cortex_a8_default"
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37 "cortex_a8_alu0|cortex_a8_alu1")
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38
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39 ;; The flow of a branch instruction through the pipelines.
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40 (define_reservation "cortex_a8_branch"
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41 "(cortex_a8_alu0+cortex_a8_issue_branch)|\
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42 (cortex_a8_alu1+cortex_a8_issue_branch)")
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43
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44 ;; The flow of a load or store instruction through the pipeline in
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45 ;; the case where that instruction consists of only one micro-op...
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46 (define_reservation "cortex_a8_load_store_1"
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47 "(cortex_a8_alu0+cortex_a8_issue_ls)|\
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48 (cortex_a8_alu1+cortex_a8_issue_ls)")
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49
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50 ;; ...and in the case of two micro-ops. We don't need to reserve
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51 ;; cortex_a8_issue_ls here because dual issue is altogether forbidden
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52 ;; during the issue cycle of the first micro-op. (Instead of modelling
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53 ;; a separate issue unit, we instead reserve alu0 and alu1 to
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54 ;; prevent any other instructions from being issued upon that first cycle.)
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55 ;; Even though the load/store pipeline is usually available in either
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56 ;; ALU pipe, multi-cycle instructions always issue in pipeline 0. This
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57 ;; reservation is therefore the same as cortex_a8_multiply_2 below.
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58 (define_reservation "cortex_a8_load_store_2"
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59 "cortex_a8_alu0+cortex_a8_alu1,\
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60 cortex_a8_alu0")
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61
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62 ;; The flow of a single-cycle multiplication.
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63 (define_reservation "cortex_a8_multiply"
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64 "cortex_a8_alu0")
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65
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66 ;; The flow of a multiplication instruction that gets decomposed into
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67 ;; two micro-ops. The two micro-ops will be issued to pipeline 0 on
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68 ;; successive cycles. Dual issue cannot happen at the same time as the
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69 ;; first of the micro-ops.
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70 (define_reservation "cortex_a8_multiply_2"
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71 "cortex_a8_alu0+cortex_a8_alu1,\
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72 cortex_a8_alu0")
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73
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74 ;; Similarly, the flow of a multiplication instruction that gets
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75 ;; decomposed into three micro-ops. Dual issue cannot occur except on
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76 ;; the cycle upon which the third micro-op is issued.
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77 (define_reservation "cortex_a8_multiply_3"
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78 "cortex_a8_alu0+cortex_a8_alu1,\
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79 cortex_a8_alu0+cortex_a8_alu1,\
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80 cortex_a8_alu0")
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81
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82 ;; The model given here assumes that all instructions are unconditional.
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83
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84 ;; Data processing instructions, but not move instructions.
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85
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86 ;; We include CLZ with these since it has the same execution pattern
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87 ;; (source read in E2 and destination available at the end of that cycle).
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88 (define_insn_reservation "cortex_a8_alu" 2
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89 (and (eq_attr "tune" "cortexa8")
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90 (ior (and (eq_attr "type" "alu")
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91 (not (eq_attr "insn" "mov,mvn")))
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92 (eq_attr "insn" "clz")))
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93 "cortex_a8_default")
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94
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95 (define_insn_reservation "cortex_a8_alu_shift" 2
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96 (and (eq_attr "tune" "cortexa8")
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97 (and (eq_attr "type" "alu_shift")
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98 (not (eq_attr "insn" "mov,mvn"))))
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99 "cortex_a8_default")
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100
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101 (define_insn_reservation "cortex_a8_alu_shift_reg" 2
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102 (and (eq_attr "tune" "cortexa8")
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103 (and (eq_attr "type" "alu_shift_reg")
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104 (not (eq_attr "insn" "mov,mvn"))))
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105 "cortex_a8_default")
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106
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107 ;; Move instructions.
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108
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109 (define_insn_reservation "cortex_a8_mov" 1
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110 (and (eq_attr "tune" "cortexa8")
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111 (and (eq_attr "type" "alu,alu_shift,alu_shift_reg")
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112 (eq_attr "insn" "mov,mvn")))
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113 "cortex_a8_default")
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114
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115 ;; Exceptions to the default latencies for data processing instructions.
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116
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117 ;; A move followed by an ALU instruction with no early dep.
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118 ;; (Such a pair can be issued in parallel, hence latency zero.)
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119 (define_bypass 0 "cortex_a8_mov" "cortex_a8_alu")
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120 (define_bypass 0 "cortex_a8_mov" "cortex_a8_alu_shift"
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121 "arm_no_early_alu_shift_dep")
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122 (define_bypass 0 "cortex_a8_mov" "cortex_a8_alu_shift_reg"
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123 "arm_no_early_alu_shift_value_dep")
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124
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125 ;; An ALU instruction followed by an ALU instruction with no early dep.
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126 (define_bypass 1 "cortex_a8_alu,cortex_a8_alu_shift,cortex_a8_alu_shift_reg"
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127 "cortex_a8_alu")
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128 (define_bypass 1 "cortex_a8_alu,cortex_a8_alu_shift,cortex_a8_alu_shift_reg"
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129 "cortex_a8_alu_shift"
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130 "arm_no_early_alu_shift_dep")
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131 (define_bypass 1 "cortex_a8_alu,cortex_a8_alu_shift,cortex_a8_alu_shift_reg"
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132 "cortex_a8_alu_shift_reg"
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133 "arm_no_early_alu_shift_value_dep")
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134
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135 ;; Multiplication instructions. These are categorized according to their
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136 ;; reservation behavior and the need below to distinguish certain
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137 ;; varieties for bypasses. Results are available at the E5 stage
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138 ;; (but some of these are multi-cycle instructions which explains the
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139 ;; latencies below).
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140
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141 (define_insn_reservation "cortex_a8_mul" 6
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142 (and (eq_attr "tune" "cortexa8")
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143 (eq_attr "insn" "mul,smulxy,smmul"))
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144 "cortex_a8_multiply_2")
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145
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146 (define_insn_reservation "cortex_a8_mla" 6
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147 (and (eq_attr "tune" "cortexa8")
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148 (eq_attr "insn" "mla,smlaxy,smlawy,smmla,smlad,smlsd"))
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149 "cortex_a8_multiply_2")
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150
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151 (define_insn_reservation "cortex_a8_mull" 7
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152 (and (eq_attr "tune" "cortexa8")
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153 (eq_attr "insn" "smull,umull,smlal,umlal,umaal,smlalxy"))
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154 "cortex_a8_multiply_3")
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155
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156 (define_insn_reservation "cortex_a8_smulwy" 5
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157 (and (eq_attr "tune" "cortexa8")
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158 (eq_attr "insn" "smulwy,smuad,smusd"))
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159 "cortex_a8_multiply")
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160
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161 ;; smlald and smlsld are multiply-accumulate instructions but do not
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162 ;; received bypassed data from other multiplication results; thus, they
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163 ;; cannot go in cortex_a8_mla above. (See below for bypass details.)
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164 (define_insn_reservation "cortex_a8_smlald" 6
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165 (and (eq_attr "tune" "cortexa8")
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166 (eq_attr "insn" "smlald,smlsld"))
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167 "cortex_a8_multiply_2")
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168
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169 ;; A multiply with a single-register result or an MLA, followed by an
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170 ;; MLA with an accumulator dependency, has its result forwarded so two
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171 ;; such instructions can issue back-to-back.
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172 (define_bypass 1 "cortex_a8_mul,cortex_a8_mla,cortex_a8_smulwy"
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173 "cortex_a8_mla"
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174 "arm_mac_accumulator_is_mul_result")
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175
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176 ;; A multiply followed by an ALU instruction needing the multiply
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177 ;; result only at E2 has lower latency than one needing it at E1.
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178 (define_bypass 4 "cortex_a8_mul,cortex_a8_mla,cortex_a8_mull,\
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179 cortex_a8_smulwy,cortex_a8_smlald"
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180 "cortex_a8_alu")
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181 (define_bypass 4 "cortex_a8_mul,cortex_a8_mla,cortex_a8_mull,\
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182 cortex_a8_smulwy,cortex_a8_smlald"
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183 "cortex_a8_alu_shift"
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184 "arm_no_early_alu_shift_dep")
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185 (define_bypass 4 "cortex_a8_mul,cortex_a8_mla,cortex_a8_mull,\
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186 cortex_a8_smulwy,cortex_a8_smlald"
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187 "cortex_a8_alu_shift_reg"
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188 "arm_no_early_alu_shift_value_dep")
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189
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190 ;; Load instructions.
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191 ;; The presence of any register writeback is ignored here.
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192
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193 ;; A load result has latency 3 unless the dependent instruction has
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194 ;; no early dep, in which case it is only latency two.
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195 ;; We assume 64-bit alignment for doubleword loads.
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196 (define_insn_reservation "cortex_a8_load1_2" 3
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197 (and (eq_attr "tune" "cortexa8")
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198 (eq_attr "type" "load1,load2,load_byte"))
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199 "cortex_a8_load_store_1")
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200
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201 (define_bypass 2 "cortex_a8_load1_2"
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202 "cortex_a8_alu")
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203 (define_bypass 2 "cortex_a8_load1_2"
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204 "cortex_a8_alu_shift"
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205 "arm_no_early_alu_shift_dep")
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206 (define_bypass 2 "cortex_a8_load1_2"
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207 "cortex_a8_alu_shift_reg"
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208 "arm_no_early_alu_shift_value_dep")
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209
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210 ;; We do not currently model the fact that loads with scaled register
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211 ;; offsets that are not LSL #2 have an extra cycle latency (they issue
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212 ;; as two micro-ops).
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213
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214 ;; A load multiple of three registers is usually issued as two micro-ops.
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215 ;; The first register will be available at E3 of the first iteration,
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216 ;; the second at E3 of the second iteration, and the third at E4 of
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217 ;; the second iteration. A load multiple of four registers is usually
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218 ;; issued as two micro-ops.
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219 (define_insn_reservation "cortex_a8_load3_4" 5
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220 (and (eq_attr "tune" "cortexa8")
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221 (eq_attr "type" "load3,load4"))
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222 "cortex_a8_load_store_2")
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223
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224 (define_bypass 4 "cortex_a8_load3_4"
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225 "cortex_a8_alu")
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226 (define_bypass 4 "cortex_a8_load3_4"
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227 "cortex_a8_alu_shift"
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228 "arm_no_early_alu_shift_dep")
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229 (define_bypass 4 "cortex_a8_load3_4"
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230 "cortex_a8_alu_shift_reg"
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231 "arm_no_early_alu_shift_value_dep")
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232
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233 ;; Store instructions.
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234 ;; Writeback is again ignored.
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235
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236 (define_insn_reservation "cortex_a8_store1_2" 0
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237 (and (eq_attr "tune" "cortexa8")
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238 (eq_attr "type" "store1,store2"))
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239 "cortex_a8_load_store_1")
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240
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241 (define_insn_reservation "cortex_a8_store3_4" 0
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242 (and (eq_attr "tune" "cortexa8")
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243 (eq_attr "type" "store3,store4"))
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244 "cortex_a8_load_store_2")
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245
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246 ;; An ALU instruction acting as a producer for a store instruction
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247 ;; that only uses the result as the value to be stored (as opposed to
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248 ;; using it to calculate the address) has latency zero; the store
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249 ;; reads the value to be stored at the start of E3 and the ALU insn
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250 ;; writes it at the end of E2. Move instructions actually produce the
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251 ;; result at the end of E1, but since we don't have delay slots, the
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252 ;; scheduling behavior will be the same.
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253 (define_bypass 0 "cortex_a8_alu,cortex_a8_alu_shift,\
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254 cortex_a8_alu_shift_reg,cortex_a8_mov"
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255 "cortex_a8_store1_2,cortex_a8_store3_4"
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256 "arm_no_early_store_addr_dep")
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257
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258 ;; Branch instructions
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259
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260 (define_insn_reservation "cortex_a8_branch" 0
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261 (and (eq_attr "tune" "cortexa8")
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262 (eq_attr "type" "branch"))
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263 "cortex_a8_branch")
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264
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265 ;; Call latencies are not predictable. A semi-arbitrary very large
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266 ;; number is used as "positive infinity" so that everything should be
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267 ;; finished by the time of return.
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268 (define_insn_reservation "cortex_a8_call" 32
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269 (and (eq_attr "tune" "cortexa8")
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270 (eq_attr "type" "call"))
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271 "cortex_a8_issue_branch")
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272
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273 ;; NEON (including VFP) instructions.
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274
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275 (include "cortex-a8-neon.md")
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276
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