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1 ;; ARM Cortex-R4F VFP pipeline description
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2 ;; Copyright (C) 2007, 2008 Free Software Foundation, Inc.
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3 ;; Written by CodeSourcery.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but
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13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 ;; General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; With the exception of simple VMOV <freg>, <freg> instructions and
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22 ;; the accululate operand of a multiply-accumulate instruction, all
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23 ;; registers are early registers. Thus base latencies are 1 more than
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24 ;; those listed in the TRM.
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25
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26 ;; We use the A, B abd C units from the integer core, plus two additional
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27 ;; units to enforce VFP dual issue constraints.
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28
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29 ;; A B C V1 VMLA
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30 ;; fcpy 1 2
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31 ;; farith 1 2 1
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32 ;; fmrc 1 2
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33 ;; fconst 1 2 * *
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34 ;; ffarith 1 2 * *
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35 ;; fmac 1 2 1 2
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36 ;; fdiv 1 2 *
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37 ;; f_loads * * *
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38 ;; f_stores * * *
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39
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40 (define_cpu_unit "cortex_r4_v1" "cortex_r4")
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41
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42 (define_cpu_unit "cortex_r4_vmla" "cortex_r4")
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43
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44 (define_reservation "cortex_r4_issue_ab"
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45 "(cortex_r4_issue_a|cortex_r4_issue_b)")
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46 (define_reservation "cortex_r4_single_issue"
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47 "cortex_r4_issue_a+cortex_r4_issue_b")
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48
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49 (define_insn_reservation "cortex_r4_fcpys" 2
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50 (and (eq_attr "tune_cortexr4" "yes")
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51 (eq_attr "type" "fcpys"))
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52 "cortex_r4_issue_ab")
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53
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54 (define_insn_reservation "cortex_r4_ffariths" 2
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55 (and (eq_attr "tune_cortexr4" "yes")
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56 (eq_attr "type" "ffariths,fconsts,fcmps"))
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57 "cortex_r4_issue_ab+cortex_r4_issue_c+cortex_r4_v1")
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58
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59 (define_insn_reservation "cortex_r4_fariths" 3
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60 (and (eq_attr "tune_cortexr4" "yes")
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61 (eq_attr "type" "fadds,fmuls"))
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62 "(cortex_r4_issue_a+cortex_r4_v1)|cortex_r4_issue_b")
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63
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64 (define_insn_reservation "cortex_r4_fmacs" 6
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65 (and (eq_attr "tune_cortexr4" "yes")
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66 (eq_attr "type" "fmacs"))
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67 "(cortex_r4_issue_a+cortex_r4_v1)|(cortex_r4_issue_b+cortex_r4_vmla)")
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68
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69 (define_insn_reservation "cortex_r4_fdivs" 17
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70 (and (eq_attr "tune_cortexr4" "yes")
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71 (eq_attr "type" "fdivs"))
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72 "cortex_r4_issue_ab+cortex_r4_v1,cortex_r4_issue_a+cortex_r4_v1")
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73
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74 (define_insn_reservation "cortex_r4_floads" 2
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75 (and (eq_attr "tune_cortexr4" "yes")
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76 (eq_attr "type" "f_loads"))
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77 "cortex_r4_issue_a+cortex_r4_issue_c+cortex_r4_v1")
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78
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79 (define_insn_reservation "cortex_r4_fstores" 1
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80 (and (eq_attr "tune_cortexr4" "yes")
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81 (eq_attr "type" "f_stores"))
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82 "cortex_r4_issue_a+cortex_r4_issue_c+cortex_r4_vmla")
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83
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84 (define_insn_reservation "cortex_r4_mcr" 2
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85 (and (eq_attr "tune_cortexr4" "yes")
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86 (eq_attr "type" "r_2_f"))
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87 "cortex_r4_issue_ab")
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88
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89 (define_insn_reservation "cortex_r4_mrc" 3
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90 (and (eq_attr "tune_cortexr4" "yes")
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91 (eq_attr "type" "f_2_r"))
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92 "cortex_r4_issue_ab")
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93
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94 ;; Bypasses for normal (not early) regs.
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95 (define_bypass 1 "cortex_r4_ffariths,cortex_r4_fcpys,cortex_r4_mcr"
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96 "cortex_r4_fcpys")
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97 (define_bypass 2 "cortex_r4_fariths"
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98 "cortex_r4_fcpys")
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99 (define_bypass 5 "cortex_r4_fmacs"
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100 "cortex_r4_fcpys")
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101 (define_bypass 16 "cortex_r4_fdivs"
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102 "cortex_r4_fcpys")
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103
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104 (define_bypass 1 "cortex_r4_ffariths,cortex_r4_fcpys,cortex_r4_mcr"
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105 "cortex_r4_fmacs"
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106 "arm_no_early_mul_dep")
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107 (define_bypass 2 "cortex_r4_fariths"
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108 "cortex_r4_fmacs"
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109 "arm_no_early_mul_dep")
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110 ;; mac->mac has an extra forwarding path.
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111 (define_bypass 3 "cortex_r4_fmacs"
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112 "cortex_r4_fmacs"
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113 "arm_no_early_mul_dep")
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114 (define_bypass 16 "cortex_r4_fdivs"
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115 "cortex_r4_fmacs"
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116 "arm_no_early_mul_dep")
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117
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118 ;; Double precision operations. These can not dual issue.
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119
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120 (define_insn_reservation "cortex_r4_fmacd" 20
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121 (and (eq_attr "tune_cortexr4" "yes")
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122 (eq_attr "type" "fmacd"))
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123 "cortex_r4_single_issue*13")
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124
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125 (define_insn_reservation "cortex_r4_farith" 10
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126 (and (eq_attr "tune_cortexr4" "yes")
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127 (eq_attr "type" "faddd,fmuld"))
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128 "cortex_r4_single_issue*3")
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129
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130 ;; FIXME: The short cycle count suggests these instructions complete
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131 ;; out of order. Chances are this is not a pipelined operation.
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132 (define_insn_reservation "cortex_r4_fdivd" 97
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133 (and (eq_attr "tune_cortexr4" "yes")
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134 (eq_attr "type" "fdivd"))
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135 "cortex_r4_single_issue*3")
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136
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137 (define_insn_reservation "cortex_r4_ffarithd" 2
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138 (and (eq_attr "tune_cortexr4" "yes")
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139 (eq_attr "type" "ffarithd,fconstd"))
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140 "cortex_r4_single_issue")
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141
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142 (define_insn_reservation "cortex_r4_fcmpd" 2
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143 (and (eq_attr "tune_cortexr4" "yes")
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144 (eq_attr "type" "fcmpd"))
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145 "cortex_r4_single_issue*2")
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146
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147 (define_insn_reservation "cortex_r4_f_cvt" 8
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148 (and (eq_attr "tune_cortexr4" "yes")
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149 (eq_attr "type" "f_cvt"))
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150 "cortex_r4_single_issue*3")
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151
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152 (define_insn_reservation "cortex_r4_f_memd" 8
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153 (and (eq_attr "tune_cortexr4" "yes")
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154 (eq_attr "type" "f_loadd,f_stored"))
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155 "cortex_r4_single_issue")
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156
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157 (define_insn_reservation "cortex_r4_f_flag" 1
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158 (and (eq_attr "tune_cortexr4" "yes")
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159 (eq_attr "type" "f_stores"))
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160 "cortex_r4_single_issue")
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161
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