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1 ;; ARM VFP11 pipeline description
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2 ;; Copyright (C) 2003, 2005, 2007, 2008 Free Software Foundation, Inc.
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3 ;; Written by CodeSourcery.
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4 ;;
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_automaton "vfp11")
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22
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23 ;; There are 3 pipelines in the VFP11 unit.
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24 ;;
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25 ;; - A 8-stage FMAC pipeline (7 execute + writeback) with forward from
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26 ;; fourth stage for simple operations.
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27 ;;
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28 ;; - A 5-stage DS pipeline (4 execute + writeback) for divide/sqrt insns.
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29 ;; These insns also uses first execute stage of FMAC pipeline.
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30 ;;
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31 ;; - A 4-stage LS pipeline (execute + 2 memory + writeback) with forward from
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32 ;; second memory stage for loads.
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33
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34 ;; We do not model Write-After-Read hazards.
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35 ;; We do not do write scheduling with the arm core, so it is only necessary
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36 ;; to model the first stage of each pipeline
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37 ;; ??? Need to model LS pipeline properly for load/store multiple?
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38 ;; We do not model fmstat properly. This could be done by modeling pipelines
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39 ;; properly and defining an absence set between a dummy fmstat unit and all
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40 ;; other vfp units.
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41
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42 (define_cpu_unit "fmac" "vfp11")
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43
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44 (define_cpu_unit "ds" "vfp11")
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45
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46 (define_cpu_unit "vfp_ls" "vfp11")
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47
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48 (define_cpu_unit "fmstat" "vfp11")
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49
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50 (exclusion_set "fmac,ds" "fmstat")
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51
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52 (define_insn_reservation "vfp_ffarith" 4
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53 (and (eq_attr "generic_vfp" "yes")
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54 (eq_attr "type" "fcpys,ffariths,ffarithd,fcmps,fcmpd"))
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55 "fmac")
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56
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57 (define_insn_reservation "vfp_farith" 8
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58 (and (eq_attr "generic_vfp" "yes")
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59 (eq_attr "type" "fadds,faddd,fconsts,fconstd,f_cvt,fmuls,fmacs"))
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60 "fmac")
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61
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62 (define_insn_reservation "vfp_fmul" 9
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63 (and (eq_attr "generic_vfp" "yes")
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64 (eq_attr "type" "fmuld,fmacd"))
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65 "fmac*2")
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66
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67 (define_insn_reservation "vfp_fdivs" 19
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68 (and (eq_attr "generic_vfp" "yes")
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69 (eq_attr "type" "fdivs"))
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70 "ds*15")
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71
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72 (define_insn_reservation "vfp_fdivd" 33
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73 (and (eq_attr "generic_vfp" "yes")
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74 (eq_attr "type" "fdivd"))
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75 "fmac+ds*29")
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76
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77 ;; Moves to/from arm regs also use the load/store pipeline.
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78 (define_insn_reservation "vfp_fload" 4
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79 (and (eq_attr "generic_vfp" "yes")
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80 (eq_attr "type" "f_loads,f_loadd,r_2_f"))
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81 "vfp_ls")
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82
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83 (define_insn_reservation "vfp_fstore" 4
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84 (and (eq_attr "generic_vfp" "yes")
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85 (eq_attr "type" "f_stores,f_stored,f_2_r"))
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86 "vfp_ls")
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87
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88 (define_insn_reservation "vfp_to_cpsr" 4
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89 (and (eq_attr "generic_vfp" "yes")
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90 (eq_attr "type" "f_flag"))
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91 "fmstat,vfp_ls*3")
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92
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