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1 ;; -*- Mode: Scheme -*-
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2 ;; Machine description for GNU compiler,
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3 ;; for ATMEL AVR micro controllers.
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4 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007, 2008,
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5 ;; 2009 Free Software Foundation, Inc.
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6 ;; Contributed by Denis Chertykov (denisc@overta.ru)
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7
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8 ;; This file is part of GCC.
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9
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10 ;; GCC is free software; you can redistribute it and/or modify
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11 ;; it under the terms of the GNU General Public License as published by
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12 ;; the Free Software Foundation; either version 3, or (at your option)
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13 ;; any later version.
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14
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15 ;; GCC is distributed in the hope that it will be useful,
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16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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18 ;; GNU General Public License for more details.
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19
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20 ;; You should have received a copy of the GNU General Public License
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21 ;; along with GCC; see the file COPYING3. If not see
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22 ;; <http://www.gnu.org/licenses/>.
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23
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24 ;; Special characters after '%':
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25 ;; A No effect (add 0).
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26 ;; B Add 1 to REG number, MEM address or CONST_INT.
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27 ;; C Add 2.
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28 ;; D Add 3.
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29 ;; j Branch condition.
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30 ;; k Reverse branch condition.
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31 ;; o Displacement for (mem (plus (reg) (const_int))) operands.
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32 ;; p POST_INC or PRE_DEC address as a pointer (X, Y, Z)
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33 ;; r POST_INC or PRE_DEC address as a register (r26, r28, r30)
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34 ;; ~ Output 'r' if not AVR_HAVE_JMP_CALL.
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35 ;; ! Output 'e' if AVR_HAVE_EIJMP_EICALL.
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36
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37 ;; UNSPEC usage:
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38 ;; 0 Length of a string, see "strlenhi".
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39 ;; 1 Jump by register pair Z or by table addressed by Z, see "casesi".
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40
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41 (define_constants
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42 [(REG_X 26)
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43 (REG_Y 28)
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44 (REG_Z 30)
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45 (REG_W 24)
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46 (REG_SP 32)
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47 (TMP_REGNO 0) ; temporary register r0
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48 (ZERO_REGNO 1) ; zero register r1
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49
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50 (SREG_ADDR 0x5F)
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51 (RAMPZ_ADDR 0x5B)
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52
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53 (UNSPEC_STRLEN 0)
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54 (UNSPEC_INDEX_JMP 1)
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55 (UNSPEC_SEI 2)
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56 (UNSPEC_CLI 3)
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57
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58 (UNSPECV_PROLOGUE_SAVES 0)
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59 (UNSPECV_EPILOGUE_RESTORES 1)
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60 (UNSPECV_WRITE_SP_IRQ_ON 2)
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61 (UNSPECV_WRITE_SP_IRQ_OFF 3)
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62 (UNSPECV_GOTO_RECEIVER 4)])
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63
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64 (include "predicates.md")
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65 (include "constraints.md")
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66
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67 ;; Condition code settings.
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68 (define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber"
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69 (const_string "none"))
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70
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71 (define_attr "type" "branch,branch1,arith,xcall"
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72 (const_string "arith"))
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73
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74 (define_attr "mcu_have_movw" "yes,no"
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75 (const (if_then_else (symbol_ref "AVR_HAVE_MOVW")
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76 (const_string "yes")
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77 (const_string "no"))))
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78
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79 (define_attr "mcu_mega" "yes,no"
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80 (const (if_then_else (symbol_ref "AVR_HAVE_JMP_CALL")
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81 (const_string "yes")
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82 (const_string "no"))))
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83
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84
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85 ;; The size of instructions in bytes.
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86 ;; XXX may depend from "cc"
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87
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88 (define_attr "length" ""
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89 (cond [(eq_attr "type" "branch")
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90 (if_then_else (and (ge (minus (pc) (match_dup 0))
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91 (const_int -63))
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92 (le (minus (pc) (match_dup 0))
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93 (const_int 62)))
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94 (const_int 1)
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95 (if_then_else (and (ge (minus (pc) (match_dup 0))
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96 (const_int -2045))
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97 (le (minus (pc) (match_dup 0))
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98 (const_int 2045)))
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99 (const_int 2)
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100 (const_int 3)))
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101 (eq_attr "type" "branch1")
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102 (if_then_else (and (ge (minus (pc) (match_dup 0))
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103 (const_int -62))
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104 (le (minus (pc) (match_dup 0))
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105 (const_int 61)))
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106 (const_int 2)
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107 (if_then_else (and (ge (minus (pc) (match_dup 0))
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108 (const_int -2044))
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109 (le (minus (pc) (match_dup 0))
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110 (const_int 2043)))
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111 (const_int 3)
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112 (const_int 4)))
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113 (eq_attr "type" "xcall")
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114 (if_then_else (eq_attr "mcu_mega" "no")
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115 (const_int 1)
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116 (const_int 2))]
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117 (const_int 2)))
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118
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119 ;; Define mode iterator
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120 (define_mode_iterator QISI [(QI "") (HI "") (SI "")])
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121
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122 ;;========================================================================
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123 ;; The following is used by nonlocal_goto and setjmp.
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124 ;; The receiver pattern will create no instructions since internally
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125 ;; virtual_stack_vars = hard_frame_pointer + 1 so the RTL become R28=R28
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126 ;; This avoids creating add/sub offsets in frame_pointer save/resore.
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127 ;; The 'null' receiver also avoids problems with optimisation
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128 ;; not recognising incoming jmp and removing code that resets frame_pointer.
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129 ;; The code derived from builtins.c.
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130
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131 (define_expand "nonlocal_goto_receiver"
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132 [(set (reg:HI REG_Y)
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133 (unspec_volatile:HI [(const_int 0)] UNSPECV_GOTO_RECEIVER))]
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134 ""
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135 {
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136 emit_move_insn (virtual_stack_vars_rtx,
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137 gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx,
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138 gen_int_mode (STARTING_FRAME_OFFSET,
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139 Pmode)));
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140 /* This might change the hard frame pointer in ways that aren't
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141 apparent to early optimization passes, so force a clobber. */
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142 emit_clobber (hard_frame_pointer_rtx);
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143 DONE;
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144 })
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145
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146
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147 ;; Defining nonlocal_goto_receiver means we must also define this.
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148 ;; even though its function is identical to that in builtins.c
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149
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150 (define_expand "nonlocal_goto"
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151 [
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152 (use (match_operand 0 "general_operand"))
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153 (use (match_operand 1 "general_operand"))
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154 (use (match_operand 2 "general_operand"))
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155 (use (match_operand 3 "general_operand"))
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156 ]
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157 ""
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158 {
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159 rtx r_label = copy_to_reg (operands[1]);
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160 rtx r_fp = operands[3];
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161 rtx r_sp = operands[2];
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162
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163 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
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164
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165 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
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166
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167 emit_move_insn (hard_frame_pointer_rtx, r_fp);
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168 emit_stack_restore (SAVE_NONLOCAL, r_sp, NULL_RTX);
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169
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170 emit_use (hard_frame_pointer_rtx);
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171 emit_use (stack_pointer_rtx);
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172
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173 emit_indirect_jump (r_label);
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174
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175 DONE;
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176 })
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177
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178
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179 (define_insn "*pushqi"
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180 [(set (mem:QI (post_dec (reg:HI REG_SP)))
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181 (match_operand:QI 0 "reg_or_0_operand" "r,L"))]
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182 ""
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183 "@
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184 push %0
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185 push __zero_reg__"
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186 [(set_attr "length" "1,1")])
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187
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188
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189 (define_insn "*pushhi"
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190 [(set (mem:HI (post_dec (reg:HI REG_SP)))
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191 (match_operand:HI 0 "reg_or_0_operand" "r,L"))]
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192 ""
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193 "@
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194 push %B0\;push %A0
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195 push __zero_reg__\;push __zero_reg__"
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196 [(set_attr "length" "2,2")])
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197
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198 (define_insn "*pushsi"
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199 [(set (mem:SI (post_dec (reg:HI REG_SP)))
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200 (match_operand:SI 0 "reg_or_0_operand" "r,L"))]
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201 ""
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202 "@
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203 push %D0\;push %C0\;push %B0\;push %A0
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204 push __zero_reg__\;push __zero_reg__\;push __zero_reg__\;push __zero_reg__"
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205 [(set_attr "length" "4,4")])
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206
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207 (define_insn "*pushsf"
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208 [(set (mem:SF (post_dec (reg:HI REG_SP)))
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209 (match_operand:SF 0 "register_operand" "r"))]
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210 ""
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211 "push %D0
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212 push %C0
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213 push %B0
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214 push %A0"
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215 [(set_attr "length" "4")])
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216
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217 ;;========================================================================
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218 ;; move byte
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219 ;; The last alternative (any immediate constant to any register) is
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220 ;; very expensive. It should be optimized by peephole2 if a scratch
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221 ;; register is available, but then that register could just as well be
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222 ;; allocated for the variable we are loading. But, most of NO_LD_REGS
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223 ;; are call-saved registers, and most of LD_REGS are call-used registers,
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224 ;; so this may still be a win for registers live across function calls.
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225
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226 (define_expand "movqi"
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227 [(set (match_operand:QI 0 "nonimmediate_operand" "")
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228 (match_operand:QI 1 "general_operand" ""))]
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229 ""
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230 "/* One of the ops has to be in a register. */
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231 if (!register_operand(operand0, QImode)
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232 && ! (register_operand(operand1, QImode) || const0_rtx == operand1))
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233 operands[1] = copy_to_mode_reg(QImode, operand1);
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234 ")
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235
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236 (define_insn "*movqi"
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237 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,d,Qm,r,q,r,*r")
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238 (match_operand:QI 1 "general_operand" "r,i,rL,Qm,r,q,i"))]
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239 "(register_operand (operands[0],QImode)
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240 || register_operand (operands[1], QImode) || const0_rtx == operands[1])"
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241 "* return output_movqi (insn, operands, NULL);"
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242 [(set_attr "length" "1,1,5,5,1,1,4")
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243 (set_attr "cc" "none,none,clobber,clobber,none,none,clobber")])
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244
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245 ;; This is used in peephole2 to optimize loading immediate constants
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246 ;; if a scratch register from LD_REGS happens to be available.
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247
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248 (define_insn "*reload_inqi"
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249 [(set (match_operand:QI 0 "register_operand" "=l")
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250 (match_operand:QI 1 "immediate_operand" "i"))
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251 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
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252 "reload_completed"
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253 "ldi %2,lo8(%1)
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254 mov %0,%2"
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255 [(set_attr "length" "2")
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256 (set_attr "cc" "none")])
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257
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258 (define_peephole2
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259 [(match_scratch:QI 2 "d")
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260 (set (match_operand:QI 0 "l_register_operand" "")
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261 (match_operand:QI 1 "immediate_operand" ""))]
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262 "(operands[1] != const0_rtx
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263 && operands[1] != const1_rtx
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264 && operands[1] != constm1_rtx)"
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265 [(parallel [(set (match_dup 0) (match_dup 1))
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266 (clobber (match_dup 2))])]
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267 "")
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268
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269 ;;============================================================================
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270 ;; move word (16 bit)
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271
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272 (define_expand "movhi"
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273 [(set (match_operand:HI 0 "nonimmediate_operand" "")
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274 (match_operand:HI 1 "general_operand" ""))]
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275 ""
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276 "
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277 {
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278 /* One of the ops has to be in a register. */
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279 if (!register_operand(operand0, HImode)
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280 && !(register_operand(operand1, HImode) || const0_rtx == operands[1]))
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281 {
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282 operands[1] = copy_to_mode_reg(HImode, operand1);
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283 }
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284 }")
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285
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286 (define_insn "*movhi_sp"
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287 [(set (match_operand:HI 0 "register_operand" "=q,r")
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288 (match_operand:HI 1 "register_operand" "r,q"))]
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289 "((stack_register_operand(operands[0], HImode) && register_operand (operands[1], HImode))
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290 || (register_operand (operands[0], HImode) && stack_register_operand(operands[1], HImode)))"
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291 "* return output_movhi (insn, operands, NULL);"
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292 [(set_attr "length" "5,2")
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293 (set_attr "cc" "none,none")])
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294
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295 (define_insn "movhi_sp_r_irq_off"
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296 [(set (match_operand:HI 0 "stack_register_operand" "=q")
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297 (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r")]
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298 UNSPECV_WRITE_SP_IRQ_OFF))]
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299 ""
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300 "out __SP_H__, %B1
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301 out __SP_L__, %A1"
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302 [(set_attr "length" "2")
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303 (set_attr "cc" "none")])
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304
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305 (define_insn "movhi_sp_r_irq_on"
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306 [(set (match_operand:HI 0 "stack_register_operand" "=q")
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307 (unspec_volatile:HI [(match_operand:HI 1 "register_operand" "r")]
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308 UNSPECV_WRITE_SP_IRQ_ON))]
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309 ""
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310 "cli
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311 out __SP_H__, %B1
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312 sei
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313 out __SP_L__, %A1"
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314 [(set_attr "length" "4")
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315 (set_attr "cc" "none")])
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316
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317 (define_peephole2
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318 [(match_scratch:QI 2 "d")
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319 (set (match_operand:HI 0 "l_register_operand" "")
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320 (match_operand:HI 1 "immediate_operand" ""))]
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321 "(operands[1] != const0_rtx
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322 && operands[1] != constm1_rtx)"
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323 [(parallel [(set (match_dup 0) (match_dup 1))
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324 (clobber (match_dup 2))])]
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325 "")
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326
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327 ;; '*' because it is not used in rtl generation, only in above peephole
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328 (define_insn "*reload_inhi"
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329 [(set (match_operand:HI 0 "register_operand" "=r")
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330 (match_operand:HI 1 "immediate_operand" "i"))
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331 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
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332 "reload_completed"
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333 "* return output_reload_inhi (insn, operands, NULL);"
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334 [(set_attr "length" "4")
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335 (set_attr "cc" "none")])
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336
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337 (define_insn "*movhi"
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338 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,d,*r,q,r")
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339 (match_operand:HI 1 "general_operand" "r,m,rL,i,i,r,q"))]
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340 "(register_operand (operands[0],HImode)
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341 || register_operand (operands[1],HImode) || const0_rtx == operands[1])"
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342 "* return output_movhi (insn, operands, NULL);"
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343 [(set_attr "length" "2,6,7,2,6,5,2")
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344 (set_attr "cc" "none,clobber,clobber,none,clobber,none,none")])
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345
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346 (define_peephole2 ; movw
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347 [(set (match_operand:QI 0 "even_register_operand" "")
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348 (match_operand:QI 1 "even_register_operand" ""))
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349 (set (match_operand:QI 2 "odd_register_operand" "")
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350 (match_operand:QI 3 "odd_register_operand" ""))]
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351 "(AVR_HAVE_MOVW
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352 && REGNO (operands[0]) == REGNO (operands[2]) - 1
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353 && REGNO (operands[1]) == REGNO (operands[3]) - 1)"
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354 [(set (match_dup 4) (match_dup 5))]
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355 {
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356 operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
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357 operands[5] = gen_rtx_REG (HImode, REGNO (operands[1]));
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358 })
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359
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360 (define_peephole2 ; movw_r
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|
361 [(set (match_operand:QI 0 "odd_register_operand" "")
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|
362 (match_operand:QI 1 "odd_register_operand" ""))
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363 (set (match_operand:QI 2 "even_register_operand" "")
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364 (match_operand:QI 3 "even_register_operand" ""))]
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365 "(AVR_HAVE_MOVW
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366 && REGNO (operands[2]) == REGNO (operands[0]) - 1
|
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367 && REGNO (operands[3]) == REGNO (operands[1]) - 1)"
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368 [(set (match_dup 4) (match_dup 5))]
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369 {
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370 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
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371 operands[5] = gen_rtx_REG (HImode, REGNO (operands[3]));
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|
372 })
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373
|
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|
374 ;;==========================================================================
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375 ;; move double word (32 bit)
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376
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|
377 (define_expand "movsi"
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|
378 [(set (match_operand:SI 0 "nonimmediate_operand" "")
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|
379 (match_operand:SI 1 "general_operand" ""))]
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380 ""
|
|
|
381 "
|
|
|
382 {
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|
383 /* One of the ops has to be in a register. */
|
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|
384 if (!register_operand (operand0, SImode)
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385 && !(register_operand (operand1, SImode) || const0_rtx == operand1))
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386 {
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|
387 operands[1] = copy_to_mode_reg (SImode, operand1);
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|
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388 }
|
|
|
389 }")
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390
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391
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392
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|
393 (define_peephole2 ; movsi_lreg_const
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394 [(match_scratch:QI 2 "d")
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|
395 (set (match_operand:SI 0 "l_register_operand" "")
|
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396 (match_operand:SI 1 "immediate_operand" ""))
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|
|
397 (match_dup 2)]
|
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|
398 "(operands[1] != const0_rtx
|
|
|
399 && operands[1] != constm1_rtx)"
|
|
|
400 [(parallel [(set (match_dup 0) (match_dup 1))
|
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|
401 (clobber (match_dup 2))])]
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|
402 "")
|
|
|
403
|
|
|
404 ;; '*' because it is not used in rtl generation.
|
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|
405 (define_insn "*reload_insi"
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406 [(set (match_operand:SI 0 "register_operand" "=r")
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407 (match_operand:SI 1 "immediate_operand" "i"))
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|
408 (clobber (match_operand:QI 2 "register_operand" "=&d"))]
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|
409 "reload_completed"
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|
|
410 "* return output_reload_insisf (insn, operands, NULL);"
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|
|
411 [(set_attr "length" "8")
|
|
|
412 (set_attr "cc" "none")])
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|
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413
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414
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|
|
415 (define_insn "*movsi"
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416 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r")
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|
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417 (match_operand:SI 1 "general_operand" "r,L,Qm,rL,i,i"))]
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|
|
418 "(register_operand (operands[0],SImode)
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|
419 || register_operand (operands[1],SImode) || const0_rtx == operands[1])"
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|
|
420 "* return output_movsisf (insn, operands, NULL);"
|
|
|
421 [(set_attr "length" "4,4,8,9,4,10")
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|
|
422 (set_attr "cc" "none,set_zn,clobber,clobber,none,clobber")])
|
|
|
423
|
|
|
424 ;; fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
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|
|
425 ;; move floating point numbers (32 bit)
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|
|
426
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|
|
427 (define_expand "movsf"
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|
|
428 [(set (match_operand:SF 0 "nonimmediate_operand" "")
|
|
|
429 (match_operand:SF 1 "general_operand" ""))]
|
|
|
430 ""
|
|
|
431 "
|
|
|
432 {
|
|
|
433 /* One of the ops has to be in a register. */
|
|
|
434 if (!register_operand (operand1, SFmode)
|
|
|
435 && !register_operand (operand0, SFmode))
|
|
|
436 {
|
|
|
437 operands[1] = copy_to_mode_reg (SFmode, operand1);
|
|
|
438 }
|
|
|
439 }")
|
|
|
440
|
|
|
441 (define_insn "*movsf"
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|
|
442 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,Qm,!d,r")
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|
|
443 (match_operand:SF 1 "general_operand" "r,G,Qm,r,F,F"))]
|
|
|
444 "register_operand (operands[0], SFmode)
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|
|
445 || register_operand (operands[1], SFmode)"
|
|
|
446 "* return output_movsisf (insn, operands, NULL);"
|
|
|
447 [(set_attr "length" "4,4,8,9,4,10")
|
|
|
448 (set_attr "cc" "none,set_zn,clobber,clobber,none,clobber")])
|
|
|
449
|
|
|
450 ;;=========================================================================
|
|
|
451 ;; move string (like memcpy)
|
|
|
452 ;; implement as RTL loop
|
|
|
453
|
|
|
454 (define_expand "movmemhi"
|
|
|
455 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
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|
|
456 (match_operand:BLK 1 "memory_operand" ""))
|
|
|
457 (use (match_operand:HI 2 "const_int_operand" ""))
|
|
|
458 (use (match_operand:HI 3 "const_int_operand" ""))])]
|
|
|
459 ""
|
|
|
460 "{
|
|
|
461 int prob;
|
|
|
462 HOST_WIDE_INT count;
|
|
|
463 enum machine_mode mode;
|
|
|
464 rtx label = gen_label_rtx ();
|
|
|
465 rtx loop_reg;
|
|
|
466 rtx jump;
|
|
|
467
|
|
|
468 /* Copy pointers into new psuedos - they will be changed. */
|
|
|
469 rtx addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
|
|
|
470 rtx addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
|
|
|
471
|
|
|
472 /* Create rtx for tmp register - we use this as scratch. */
|
|
|
473 rtx tmp_reg_rtx = gen_rtx_REG (QImode, TMP_REGNO);
|
|
|
474
|
|
|
475 if (GET_CODE (operands[2]) != CONST_INT)
|
|
|
476 FAIL;
|
|
|
477
|
|
|
478 count = INTVAL (operands[2]);
|
|
|
479 if (count <= 0)
|
|
|
480 FAIL;
|
|
|
481
|
|
|
482 /* Work out branch probability for latter use. */
|
|
|
483 prob = REG_BR_PROB_BASE - REG_BR_PROB_BASE / count;
|
|
|
484
|
|
|
485 /* See if constant fit 8 bits. */
|
|
|
486 mode = (count < 0x100) ? QImode : HImode;
|
|
|
487 /* Create loop counter register. */
|
|
|
488 loop_reg = copy_to_mode_reg (mode, gen_int_mode (count, mode));
|
|
|
489
|
|
|
490 /* Now create RTL code for move loop. */
|
|
|
491 /* Label at top of loop. */
|
|
|
492 emit_label (label);
|
|
|
493
|
|
|
494 /* Move one byte into scratch and inc pointer. */
|
|
|
495 emit_move_insn (tmp_reg_rtx, gen_rtx_MEM (QImode, addr1));
|
|
|
496 emit_move_insn (addr1, gen_rtx_PLUS (Pmode, addr1, const1_rtx));
|
|
|
497
|
|
|
498 /* Move to mem and inc pointer. */
|
|
|
499 emit_move_insn (gen_rtx_MEM (QImode, addr0), tmp_reg_rtx);
|
|
|
500 emit_move_insn (addr0, gen_rtx_PLUS (Pmode, addr0, const1_rtx));
|
|
|
501
|
|
|
502 /* Decrement count. */
|
|
|
503 emit_move_insn (loop_reg, gen_rtx_PLUS (mode, loop_reg, constm1_rtx));
|
|
|
504
|
|
|
505 /* Compare with zero and jump if not equal. */
|
|
|
506 emit_cmp_and_jump_insns (loop_reg, const0_rtx, NE, NULL_RTX, mode, 1,
|
|
|
507 label);
|
|
|
508 /* Set jump probability based on loop count. */
|
|
|
509 jump = get_last_insn ();
|
|
|
510 REG_NOTES (jump) = gen_rtx_EXPR_LIST (REG_BR_PROB,
|
|
|
511 GEN_INT (prob),
|
|
|
512 REG_NOTES (jump));
|
|
|
513 DONE;
|
|
|
514 }")
|
|
|
515
|
|
|
516 ;; =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2
|
|
|
517 ;; memset (%0, %2, %1)
|
|
|
518
|
|
|
519 (define_expand "setmemhi"
|
|
|
520 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
|
|
|
521 (match_operand 2 "const_int_operand" ""))
|
|
|
522 (use (match_operand:HI 1 "const_int_operand" ""))
|
|
|
523 (use (match_operand:HI 3 "const_int_operand" "n"))
|
|
|
524 (clobber (match_scratch:HI 4 ""))
|
|
|
525 (clobber (match_dup 5))])]
|
|
|
526 ""
|
|
|
527 "{
|
|
|
528 rtx addr0;
|
|
|
529 int cnt8;
|
|
|
530 enum machine_mode mode;
|
|
|
531
|
|
|
532 /* If value to set is not zero, use the library routine. */
|
|
|
533 if (operands[2] != const0_rtx)
|
|
|
534 FAIL;
|
|
|
535
|
|
|
536 if (GET_CODE (operands[1]) != CONST_INT)
|
|
|
537 FAIL;
|
|
|
538
|
|
|
539 cnt8 = byte_immediate_operand (operands[1], GET_MODE (operands[1]));
|
|
|
540 mode = cnt8 ? QImode : HImode;
|
|
|
541 operands[5] = gen_rtx_SCRATCH (mode);
|
|
|
542 operands[1] = copy_to_mode_reg (mode,
|
|
|
543 gen_int_mode (INTVAL (operands[1]), mode));
|
|
|
544 addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
|
|
|
545 operands[0] = gen_rtx_MEM (BLKmode, addr0);
|
|
|
546 }")
|
|
|
547
|
|
|
548 (define_insn "*clrmemqi"
|
|
|
549 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
|
|
|
550 (const_int 0))
|
|
|
551 (use (match_operand:QI 1 "register_operand" "r"))
|
|
|
552 (use (match_operand:QI 2 "const_int_operand" "n"))
|
|
|
553 (clobber (match_scratch:HI 3 "=0"))
|
|
|
554 (clobber (match_scratch:QI 4 "=&1"))]
|
|
|
555 ""
|
|
|
556 "st %a0+,__zero_reg__
|
|
|
557 dec %1
|
|
|
558 brne .-6"
|
|
|
559 [(set_attr "length" "3")
|
|
|
560 (set_attr "cc" "clobber")])
|
|
|
561
|
|
|
562 (define_insn "*clrmemhi"
|
|
|
563 [(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
|
|
|
564 (const_int 0))
|
|
|
565 (use (match_operand:HI 1 "register_operand" "!w,d"))
|
|
|
566 (use (match_operand:HI 2 "const_int_operand" "n,n"))
|
|
|
567 (clobber (match_scratch:HI 3 "=0,0"))
|
|
|
568 (clobber (match_scratch:HI 4 "=&1,&1"))]
|
|
|
569 ""
|
|
|
570 "*{
|
|
|
571 if (which_alternative==0)
|
|
|
572 return (AS2 (st,%a0+,__zero_reg__) CR_TAB
|
|
|
573 AS2 (sbiw,%A1,1) CR_TAB
|
|
|
574 AS1 (brne,.-6));
|
|
|
575 else
|
|
|
576 return (AS2 (st,%a0+,__zero_reg__) CR_TAB
|
|
|
577 AS2 (subi,%A1,1) CR_TAB
|
|
|
578 AS2 (sbci,%B1,0) CR_TAB
|
|
|
579 AS1 (brne,.-8));
|
|
|
580 }"
|
|
|
581 [(set_attr "length" "3,4")
|
|
|
582 (set_attr "cc" "clobber,clobber")])
|
|
|
583
|
|
|
584 (define_expand "strlenhi"
|
|
|
585 [(set (match_dup 4)
|
|
|
586 (unspec:HI [(match_operand:BLK 1 "memory_operand" "")
|
|
|
587 (match_operand:QI 2 "const_int_operand" "")
|
|
|
588 (match_operand:HI 3 "immediate_operand" "")]
|
|
|
589 UNSPEC_STRLEN))
|
|
|
590 (set (match_dup 4) (plus:HI (match_dup 4)
|
|
|
591 (const_int -1)))
|
|
|
592 (set (match_operand:HI 0 "register_operand" "")
|
|
|
593 (minus:HI (match_dup 4)
|
|
|
594 (match_dup 5)))]
|
|
|
595 ""
|
|
|
596 "{
|
|
|
597 rtx addr;
|
|
|
598 if (! (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0))
|
|
|
599 FAIL;
|
|
|
600 addr = copy_to_mode_reg (Pmode, XEXP (operands[1],0));
|
|
|
601 operands[1] = gen_rtx_MEM (BLKmode, addr);
|
|
|
602 operands[5] = addr;
|
|
|
603 operands[4] = gen_reg_rtx (HImode);
|
|
|
604 }")
|
|
|
605
|
|
|
606 (define_insn "*strlenhi"
|
|
|
607 [(set (match_operand:HI 0 "register_operand" "=e")
|
|
|
608 (unspec:HI [(mem:BLK (match_operand:HI 1 "register_operand" "%0"))
|
|
|
609 (const_int 0)
|
|
|
610 (match_operand:HI 2 "immediate_operand" "i")]
|
|
|
611 UNSPEC_STRLEN))]
|
|
|
612 ""
|
|
|
613 "ld __tmp_reg__,%a0+
|
|
|
614 tst __tmp_reg__
|
|
|
615 brne .-6"
|
|
|
616 [(set_attr "length" "3")
|
|
|
617 (set_attr "cc" "clobber")])
|
|
|
618
|
|
|
619 ;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
|
|
620 ; add bytes
|
|
|
621
|
|
|
622 (define_insn "addqi3"
|
|
|
623 [(set (match_operand:QI 0 "register_operand" "=r,d,r,r")
|
|
|
624 (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0")
|
|
|
625 (match_operand:QI 2 "nonmemory_operand" "r,i,P,N")))]
|
|
|
626 ""
|
|
|
627 "@
|
|
|
628 add %0,%2
|
|
|
629 subi %0,lo8(-(%2))
|
|
|
630 inc %0
|
|
|
631 dec %0"
|
|
|
632 [(set_attr "length" "1,1,1,1")
|
|
|
633 (set_attr "cc" "set_czn,set_czn,set_zn,set_zn")])
|
|
|
634
|
|
|
635
|
|
|
636 (define_expand "addhi3"
|
|
|
637 [(set (match_operand:HI 0 "register_operand" "")
|
|
|
638 (plus:HI (match_operand:HI 1 "register_operand" "")
|
|
|
639 (match_operand:HI 2 "nonmemory_operand" "")))]
|
|
|
640 ""
|
|
|
641 "
|
|
|
642 {
|
|
|
643 if (GET_CODE (operands[2]) == CONST_INT)
|
|
|
644 {
|
|
|
645 short tmp = INTVAL (operands[2]);
|
|
|
646 operands[2] = GEN_INT(tmp);
|
|
|
647 }
|
|
|
648 }")
|
|
|
649
|
|
|
650
|
|
|
651 (define_insn "*addhi3_zero_extend"
|
|
|
652 [(set (match_operand:HI 0 "register_operand" "=r")
|
|
|
653 (plus:HI (zero_extend:HI
|
|
|
654 (match_operand:QI 1 "register_operand" "r"))
|
|
|
655 (match_operand:HI 2 "register_operand" "0")))]
|
|
|
656 ""
|
|
|
657 "add %A0,%1
|
|
|
658 adc %B0,__zero_reg__"
|
|
|
659 [(set_attr "length" "2")
|
|
|
660 (set_attr "cc" "set_n")])
|
|
|
661
|
|
|
662 (define_insn "*addhi3_zero_extend1"
|
|
|
663 [(set (match_operand:HI 0 "register_operand" "=r")
|
|
|
664 (plus:HI (match_operand:HI 1 "register_operand" "%0")
|
|
|
665 (zero_extend:HI
|
|
|
666 (match_operand:QI 2 "register_operand" "r"))))]
|
|
|
667 ""
|
|
|
668 "add %A0,%2
|
|
|
669 adc %B0,__zero_reg__"
|
|
|
670 [(set_attr "length" "2")
|
|
|
671 (set_attr "cc" "set_n")])
|
|
|
672
|
|
|
673 (define_insn "*addhi3_sp_R_pc2"
|
|
|
674 [(set (match_operand:HI 1 "stack_register_operand" "=q")
|
|
|
675 (plus:HI (match_operand:HI 2 "stack_register_operand" "q")
|
|
|
676 (match_operand:HI 0 "avr_sp_immediate_operand" "R")))]
|
|
|
677 "AVR_2_BYTE_PC"
|
|
|
678 "*{
|
|
|
679 if (CONST_INT_P (operands[0]))
|
|
|
680 {
|
|
|
681 switch(INTVAL (operands[0]))
|
|
|
682 {
|
|
|
683 case -6:
|
|
|
684 return \"rcall .\" CR_TAB
|
|
|
685 \"rcall .\" CR_TAB
|
|
|
686 \"rcall .\";
|
|
|
687 case -5:
|
|
|
688 return \"rcall .\" CR_TAB
|
|
|
689 \"rcall .\" CR_TAB
|
|
|
690 \"push __tmp_reg__\";
|
|
|
691 case -4:
|
|
|
692 return \"rcall .\" CR_TAB
|
|
|
693 \"rcall .\";
|
|
|
694 case -3:
|
|
|
695 return \"rcall .\" CR_TAB
|
|
|
696 \"push __tmp_reg__\";
|
|
|
697 case -2:
|
|
|
698 return \"rcall .\";
|
|
|
699 case -1:
|
|
|
700 return \"push __tmp_reg__\";
|
|
|
701 case 0:
|
|
|
702 return \"\";
|
|
|
703 case 1:
|
|
|
704 return \"pop __tmp_reg__\";
|
|
|
705 case 2:
|
|
|
706 return \"pop __tmp_reg__\" CR_TAB
|
|
|
707 \"pop __tmp_reg__\";
|
|
|
708 case 3:
|
|
|
709 return \"pop __tmp_reg__\" CR_TAB
|
|
|
710 \"pop __tmp_reg__\" CR_TAB
|
|
|
711 \"pop __tmp_reg__\";
|
|
|
712 case 4:
|
|
|
713 return \"pop __tmp_reg__\" CR_TAB
|
|
|
714 \"pop __tmp_reg__\" CR_TAB
|
|
|
715 \"pop __tmp_reg__\" CR_TAB
|
|
|
716 \"pop __tmp_reg__\";
|
|
|
717 case 5:
|
|
|
718 return \"pop __tmp_reg__\" CR_TAB
|
|
|
719 \"pop __tmp_reg__\" CR_TAB
|
|
|
720 \"pop __tmp_reg__\" CR_TAB
|
|
|
721 \"pop __tmp_reg__\" CR_TAB
|
|
|
722 \"pop __tmp_reg__\";
|
|
|
723 }
|
|
|
724 }
|
|
|
725 return \"bug\";
|
|
|
726 }"
|
|
|
727 [(set (attr "length")
|
|
|
728 (cond [(eq (const_int -6) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
|
|
|
729 (eq (const_int -5) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
|
|
|
730 (eq (const_int -4) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
|
|
|
731 (eq (const_int -3) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
|
|
|
732 (eq (const_int -2) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
|
|
|
733 (eq (const_int -1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
|
|
|
734 (eq (const_int 0) (symbol_ref "INTVAL (operands[0])")) (const_int 0)
|
|
|
735 (eq (const_int 1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
|
|
|
736 (eq (const_int 2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
|
|
|
737 (eq (const_int 3) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
|
|
|
738 (eq (const_int 4) (symbol_ref "INTVAL (operands[0])")) (const_int 4)
|
|
|
739 (eq (const_int 5) (symbol_ref "INTVAL (operands[0])")) (const_int 5)]
|
|
|
740 (const_int 0)))])
|
|
|
741
|
|
|
742 (define_insn "*addhi3_sp_R_pc3"
|
|
|
743 [(set (match_operand:HI 1 "stack_register_operand" "=q")
|
|
|
744 (plus:HI (match_operand:HI 2 "stack_register_operand" "q")
|
|
|
745 (match_operand:QI 0 "avr_sp_immediate_operand" "R")))]
|
|
|
746 "AVR_3_BYTE_PC"
|
|
|
747 "*{
|
|
|
748 if (CONST_INT_P (operands[0]))
|
|
|
749 {
|
|
|
750 switch(INTVAL (operands[0]))
|
|
|
751 {
|
|
|
752 case -6:
|
|
|
753 return \"rcall .\" CR_TAB
|
|
|
754 \"rcall .\";
|
|
|
755 case -5:
|
|
|
756 return \"rcall .\" CR_TAB
|
|
|
757 \"push __tmp_reg__\" CR_TAB
|
|
|
758 \"push __tmp_reg__\";
|
|
|
759 case -4:
|
|
|
760 return \"rcall .\" CR_TAB
|
|
|
761 \"push __tmp_reg__\";
|
|
|
762 case -3:
|
|
|
763 return \"rcall .\";
|
|
|
764 case -2:
|
|
|
765 return \"push __tmp_reg__\" CR_TAB
|
|
|
766 \"push __tmp_reg__\";
|
|
|
767 case -1:
|
|
|
768 return \"push __tmp_reg__\";
|
|
|
769 case 0:
|
|
|
770 return \"\";
|
|
|
771 case 1:
|
|
|
772 return \"pop __tmp_reg__\";
|
|
|
773 case 2:
|
|
|
774 return \"pop __tmp_reg__\" CR_TAB
|
|
|
775 \"pop __tmp_reg__\";
|
|
|
776 case 3:
|
|
|
777 return \"pop __tmp_reg__\" CR_TAB
|
|
|
778 \"pop __tmp_reg__\" CR_TAB
|
|
|
779 \"pop __tmp_reg__\";
|
|
|
780 case 4:
|
|
|
781 return \"pop __tmp_reg__\" CR_TAB
|
|
|
782 \"pop __tmp_reg__\" CR_TAB
|
|
|
783 \"pop __tmp_reg__\" CR_TAB
|
|
|
784 \"pop __tmp_reg__\";
|
|
|
785 case 5:
|
|
|
786 return \"pop __tmp_reg__\" CR_TAB
|
|
|
787 \"pop __tmp_reg__\" CR_TAB
|
|
|
788 \"pop __tmp_reg__\" CR_TAB
|
|
|
789 \"pop __tmp_reg__\" CR_TAB
|
|
|
790 \"pop __tmp_reg__\";
|
|
|
791 }
|
|
|
792 }
|
|
|
793 return \"bug\";
|
|
|
794 }"
|
|
|
795 [(set (attr "length")
|
|
|
796 (cond [(eq (const_int -6) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
|
|
|
797 (eq (const_int -5) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
|
|
|
798 (eq (const_int -4) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
|
|
|
799 (eq (const_int -3) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
|
|
|
800 (eq (const_int -2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
|
|
|
801 (eq (const_int -1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
|
|
|
802 (eq (const_int 0) (symbol_ref "INTVAL (operands[0])")) (const_int 0)
|
|
|
803 (eq (const_int 1) (symbol_ref "INTVAL (operands[0])")) (const_int 1)
|
|
|
804 (eq (const_int 2) (symbol_ref "INTVAL (operands[0])")) (const_int 2)
|
|
|
805 (eq (const_int 3) (symbol_ref "INTVAL (operands[0])")) (const_int 3)
|
|
|
806 (eq (const_int 4) (symbol_ref "INTVAL (operands[0])")) (const_int 4)
|
|
|
807 (eq (const_int 5) (symbol_ref "INTVAL (operands[0])")) (const_int 5)]
|
|
|
808 (const_int 0)))])
|
|
|
809
|
|
|
810 (define_insn "*addhi3"
|
|
|
811 [(set (match_operand:HI 0 "register_operand" "=r,!w,!w,d,r,r")
|
|
|
812 (plus:HI
|
|
|
813 (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
|
|
|
814 (match_operand:HI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
|
|
|
815 ""
|
|
|
816 "@
|
|
|
817 add %A0,%A2\;adc %B0,%B2
|
|
|
818 adiw %A0,%2
|
|
|
819 sbiw %A0,%n2
|
|
|
820 subi %A0,lo8(-(%2))\;sbci %B0,hi8(-(%2))
|
|
|
821 sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__
|
|
|
822 sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__"
|
|
|
823 [(set_attr "length" "2,1,1,2,3,3")
|
|
|
824 (set_attr "cc" "set_n,set_czn,set_czn,set_czn,set_n,set_n")])
|
|
|
825
|
|
|
826 (define_insn "addsi3"
|
|
|
827 [(set (match_operand:SI 0 "register_operand" "=r,!w,!w,d,r,r")
|
|
|
828 (plus:SI
|
|
|
829 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
|
|
|
830 (match_operand:SI 2 "nonmemory_operand" "r,I,J,i,P,N")))]
|
|
|
831 ""
|
|
|
832 "@
|
|
|
833 add %A0,%A2\;adc %B0,%B2\;adc %C0,%C2\;adc %D0,%D2
|
|
|
834 adiw %0,%2\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
|
|
|
835 sbiw %0,%n2\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__
|
|
|
836 subi %0,lo8(-(%2))\;sbci %B0,hi8(-(%2))\;sbci %C0,hlo8(-(%2))\;sbci %D0,hhi8(-(%2))
|
|
|
837 sec\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
|
|
|
838 sec\;sbc %A0,__zero_reg__\;sbc %B0,__zero_reg__\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__"
|
|
|
839 [(set_attr "length" "4,3,3,4,5,5")
|
|
|
840 (set_attr "cc" "set_n,set_n,set_czn,set_czn,set_n,set_n")])
|
|
|
841
|
|
|
842 (define_insn "*addsi3_zero_extend"
|
|
|
843 [(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
844 (plus:SI (zero_extend:SI
|
|
|
845 (match_operand:QI 1 "register_operand" "r"))
|
|
|
846 (match_operand:SI 2 "register_operand" "0")))]
|
|
|
847 ""
|
|
|
848 "add %A0,%1
|
|
|
849 adc %B0,__zero_reg__
|
|
|
850 adc %C0,__zero_reg__
|
|
|
851 adc %D0,__zero_reg__"
|
|
|
852 [(set_attr "length" "4")
|
|
|
853 (set_attr "cc" "set_n")])
|
|
|
854
|
|
|
855 ;-----------------------------------------------------------------------------
|
|
|
856 ; sub bytes
|
|
|
857 (define_insn "subqi3"
|
|
|
858 [(set (match_operand:QI 0 "register_operand" "=r,d")
|
|
|
859 (minus:QI (match_operand:QI 1 "register_operand" "0,0")
|
|
|
860 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
|
|
|
861 ""
|
|
|
862 "@
|
|
|
863 sub %0,%2
|
|
|
864 subi %0,lo8(%2)"
|
|
|
865 [(set_attr "length" "1,1")
|
|
|
866 (set_attr "cc" "set_czn,set_czn")])
|
|
|
867
|
|
|
868 (define_insn "subhi3"
|
|
|
869 [(set (match_operand:HI 0 "register_operand" "=r,d")
|
|
|
870 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
|
|
|
871 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
|
|
|
872 ""
|
|
|
873 "@
|
|
|
874 sub %A0,%A2\;sbc %B0,%B2
|
|
|
875 subi %A0,lo8(%2)\;sbci %B0,hi8(%2)"
|
|
|
876 [(set_attr "length" "2,2")
|
|
|
877 (set_attr "cc" "set_czn,set_czn")])
|
|
|
878
|
|
|
879 (define_insn "*subhi3_zero_extend1"
|
|
|
880 [(set (match_operand:HI 0 "register_operand" "=r")
|
|
|
881 (minus:HI (match_operand:HI 1 "register_operand" "0")
|
|
|
882 (zero_extend:HI
|
|
|
883 (match_operand:QI 2 "register_operand" "r"))))]
|
|
|
884 ""
|
|
|
885 "sub %A0,%2
|
|
|
886 sbc %B0,__zero_reg__"
|
|
|
887 [(set_attr "length" "2")
|
|
|
888 (set_attr "cc" "set_n")])
|
|
|
889
|
|
|
890 (define_insn "subsi3"
|
|
|
891 [(set (match_operand:SI 0 "register_operand" "=r,d")
|
|
|
892 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
|
|
|
893 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
|
|
|
894 ""
|
|
|
895 "@
|
|
|
896 sub %0,%2\;sbc %B0,%B2\;sbc %C0,%C2\;sbc %D0,%D2
|
|
|
897 subi %A0,lo8(%2)\;sbci %B0,hi8(%2)\;sbci %C0,hlo8(%2)\;sbci %D0,hhi8(%2)"
|
|
|
898 [(set_attr "length" "4,4")
|
|
|
899 (set_attr "cc" "set_czn,set_czn")])
|
|
|
900
|
|
|
901 (define_insn "*subsi3_zero_extend"
|
|
|
902 [(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
903 (minus:SI (match_operand:SI 1 "register_operand" "0")
|
|
|
904 (zero_extend:SI
|
|
|
905 (match_operand:QI 2 "register_operand" "r"))))]
|
|
|
906 ""
|
|
|
907 "sub %A0,%2
|
|
|
908 sbc %B0,__zero_reg__
|
|
|
909 sbc %C0,__zero_reg__
|
|
|
910 sbc %D0,__zero_reg__"
|
|
|
911 [(set_attr "length" "4")
|
|
|
912 (set_attr "cc" "set_n")])
|
|
|
913
|
|
|
914 ;******************************************************************************
|
|
|
915 ; mul
|
|
|
916
|
|
|
917 (define_expand "mulqi3"
|
|
|
918 [(set (match_operand:QI 0 "register_operand" "")
|
|
|
919 (mult:QI (match_operand:QI 1 "register_operand" "")
|
|
|
920 (match_operand:QI 2 "register_operand" "")))]
|
|
|
921 ""
|
|
|
922 "{
|
|
|
923 if (!AVR_HAVE_MUL)
|
|
|
924 {
|
|
|
925 emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
|
|
|
926 DONE;
|
|
|
927 }
|
|
|
928 }")
|
|
|
929
|
|
|
930 (define_insn "*mulqi3_enh"
|
|
|
931 [(set (match_operand:QI 0 "register_operand" "=r")
|
|
|
932 (mult:QI (match_operand:QI 1 "register_operand" "r")
|
|
|
933 (match_operand:QI 2 "register_operand" "r")))]
|
|
|
934 "AVR_HAVE_MUL"
|
|
|
935 "mul %1,%2
|
|
|
936 mov %0,r0
|
|
|
937 clr r1"
|
|
|
938 [(set_attr "length" "3")
|
|
|
939 (set_attr "cc" "clobber")])
|
|
|
940
|
|
|
941 (define_expand "mulqi3_call"
|
|
|
942 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
|
|
|
943 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
|
|
|
944 (parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
|
|
|
945 (clobber (reg:QI 22))])
|
|
|
946 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))]
|
|
|
947 ""
|
|
|
948 "")
|
|
|
949
|
|
|
950 (define_insn "*mulqi3_call"
|
|
|
951 [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
|
|
|
952 (clobber (reg:QI 22))]
|
|
|
953 "!AVR_HAVE_MUL"
|
|
|
954 "%~call __mulqi3"
|
|
|
955 [(set_attr "type" "xcall")
|
|
|
956 (set_attr "cc" "clobber")])
|
|
|
957
|
|
|
958 (define_insn "mulqihi3"
|
|
|
959 [(set (match_operand:HI 0 "register_operand" "=r")
|
|
|
960 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))
|
|
|
961 (sign_extend:HI (match_operand:QI 2 "register_operand" "d"))))]
|
|
|
962 "AVR_HAVE_MUL"
|
|
|
963 "muls %1,%2
|
|
|
964 movw %0,r0
|
|
|
965 clr r1"
|
|
|
966 [(set_attr "length" "3")
|
|
|
967 (set_attr "cc" "clobber")])
|
|
|
968
|
|
|
969 (define_insn "umulqihi3"
|
|
|
970 [(set (match_operand:HI 0 "register_operand" "=r")
|
|
|
971 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
|
|
|
972 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
|
|
|
973 "AVR_HAVE_MUL"
|
|
|
974 "mul %1,%2
|
|
|
975 movw %0,r0
|
|
|
976 clr r1"
|
|
|
977 [(set_attr "length" "3")
|
|
|
978 (set_attr "cc" "clobber")])
|
|
|
979
|
|
|
980 (define_expand "mulhi3"
|
|
|
981 [(set (match_operand:HI 0 "register_operand" "")
|
|
|
982 (mult:HI (match_operand:HI 1 "register_operand" "")
|
|
|
983 (match_operand:HI 2 "register_operand" "")))]
|
|
|
984 ""
|
|
|
985 "
|
|
|
986 {
|
|
|
987 if (!AVR_HAVE_MUL)
|
|
|
988 {
|
|
|
989 emit_insn (gen_mulhi3_call (operands[0], operands[1], operands[2]));
|
|
|
990 DONE;
|
|
|
991 }
|
|
|
992 }")
|
|
|
993
|
|
|
994 (define_insn "*mulhi3_enh"
|
|
|
995 [(set (match_operand:HI 0 "register_operand" "=&r")
|
|
|
996 (mult:HI (match_operand:HI 1 "register_operand" "r")
|
|
|
997 (match_operand:HI 2 "register_operand" "r")))]
|
|
|
998 "AVR_HAVE_MUL"
|
|
|
999 "mul %A1,%A2
|
|
|
1000 movw %0,r0
|
|
|
1001 mul %A1,%B2
|
|
|
1002 add %B0,r0
|
|
|
1003 mul %B1,%A2
|
|
|
1004 add %B0,r0
|
|
|
1005 clr r1"
|
|
|
1006 [(set_attr "length" "7")
|
|
|
1007 (set_attr "cc" "clobber")])
|
|
|
1008
|
|
|
1009 (define_expand "mulhi3_call"
|
|
|
1010 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
|
|
|
1011 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
|
|
|
1012 (parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
|
|
|
1013 (clobber (reg:HI 22))
|
|
|
1014 (clobber (reg:QI 21))])
|
|
|
1015 (set (match_operand:HI 0 "register_operand" "") (reg:HI 24))]
|
|
|
1016 ""
|
|
|
1017 "")
|
|
|
1018
|
|
|
1019 (define_insn "*mulhi3_call"
|
|
|
1020 [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
|
|
|
1021 (clobber (reg:HI 22))
|
|
|
1022 (clobber (reg:QI 21))]
|
|
|
1023 "!AVR_HAVE_MUL"
|
|
|
1024 "%~call __mulhi3"
|
|
|
1025 [(set_attr "type" "xcall")
|
|
|
1026 (set_attr "cc" "clobber")])
|
|
|
1027
|
|
|
1028 ;; Operand 2 (reg:SI 18) not clobbered on the enhanced core.
|
|
|
1029 ;; All call-used registers clobbered otherwise - normal library call.
|
|
|
1030 (define_expand "mulsi3"
|
|
|
1031 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
|
|
|
1032 (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
|
|
|
1033 (parallel [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
|
|
|
1034 (clobber (reg:HI 26))
|
|
|
1035 (clobber (reg:HI 30))])
|
|
|
1036 (set (match_operand:SI 0 "register_operand" "") (reg:SI 22))]
|
|
|
1037 "AVR_HAVE_MUL"
|
|
|
1038 "")
|
|
|
1039
|
|
|
1040 (define_insn "*mulsi3_call"
|
|
|
1041 [(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
|
|
|
1042 (clobber (reg:HI 26))
|
|
|
1043 (clobber (reg:HI 30))]
|
|
|
1044 "AVR_HAVE_MUL"
|
|
|
1045 "%~call __mulsi3"
|
|
|
1046 [(set_attr "type" "xcall")
|
|
|
1047 (set_attr "cc" "clobber")])
|
|
|
1048
|
|
|
1049 ; / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / %
|
|
|
1050 ; divmod
|
|
|
1051
|
|
|
1052 ;; Generate libgcc.S calls ourselves, because:
|
|
|
1053 ;; - we know exactly which registers are clobbered (for QI and HI
|
|
|
1054 ;; modes, some of the call-used registers are preserved)
|
|
|
1055 ;; - we get both the quotient and the remainder at no extra cost
|
|
|
1056
|
|
|
1057 (define_expand "divmodqi4"
|
|
|
1058 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
|
|
|
1059 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
|
|
|
1060 (parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
|
|
|
1061 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
|
|
|
1062 (clobber (reg:QI 22))
|
|
|
1063 (clobber (reg:QI 23))])
|
|
|
1064 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))
|
|
|
1065 (set (match_operand:QI 3 "register_operand" "") (reg:QI 25))]
|
|
|
1066 ""
|
|
|
1067 "")
|
|
|
1068
|
|
|
1069 (define_insn "*divmodqi4_call"
|
|
|
1070 [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
|
|
|
1071 (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
|
|
|
1072 (clobber (reg:QI 22))
|
|
|
1073 (clobber (reg:QI 23))]
|
|
|
1074 ""
|
|
|
1075 "%~call __divmodqi4"
|
|
|
1076 [(set_attr "type" "xcall")
|
|
|
1077 (set_attr "cc" "clobber")])
|
|
|
1078
|
|
|
1079 (define_expand "udivmodqi4"
|
|
|
1080 [(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
|
|
|
1081 (set (reg:QI 22) (match_operand:QI 2 "register_operand" ""))
|
|
|
1082 (parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
|
|
|
1083 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
|
|
|
1084 (clobber (reg:QI 23))])
|
|
|
1085 (set (match_operand:QI 0 "register_operand" "") (reg:QI 24))
|
|
|
1086 (set (match_operand:QI 3 "register_operand" "") (reg:QI 25))]
|
|
|
1087 ""
|
|
|
1088 "")
|
|
|
1089
|
|
|
1090 (define_insn "*udivmodqi4_call"
|
|
|
1091 [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
|
|
|
1092 (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
|
|
|
1093 (clobber (reg:QI 23))]
|
|
|
1094 ""
|
|
|
1095 "%~call __udivmodqi4"
|
|
|
1096 [(set_attr "type" "xcall")
|
|
|
1097 (set_attr "cc" "clobber")])
|
|
|
1098
|
|
|
1099 (define_expand "divmodhi4"
|
|
|
1100 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
|
|
|
1101 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
|
|
|
1102 (parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
|
|
|
1103 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
|
|
|
1104 (clobber (reg:HI 26))
|
|
|
1105 (clobber (reg:QI 21))])
|
|
|
1106 (set (match_operand:HI 0 "register_operand" "") (reg:HI 22))
|
|
|
1107 (set (match_operand:HI 3 "register_operand" "") (reg:HI 24))]
|
|
|
1108 ""
|
|
|
1109 "")
|
|
|
1110
|
|
|
1111 (define_insn "*divmodhi4_call"
|
|
|
1112 [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
|
|
|
1113 (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
|
|
|
1114 (clobber (reg:HI 26))
|
|
|
1115 (clobber (reg:QI 21))]
|
|
|
1116 ""
|
|
|
1117 "%~call __divmodhi4"
|
|
|
1118 [(set_attr "type" "xcall")
|
|
|
1119 (set_attr "cc" "clobber")])
|
|
|
1120
|
|
|
1121 (define_expand "udivmodhi4"
|
|
|
1122 [(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
|
|
|
1123 (set (reg:HI 22) (match_operand:HI 2 "register_operand" ""))
|
|
|
1124 (parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
|
|
|
1125 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
|
|
|
1126 (clobber (reg:HI 26))
|
|
|
1127 (clobber (reg:QI 21))])
|
|
|
1128 (set (match_operand:HI 0 "register_operand" "") (reg:HI 22))
|
|
|
1129 (set (match_operand:HI 3 "register_operand" "") (reg:HI 24))]
|
|
|
1130 ""
|
|
|
1131 "")
|
|
|
1132
|
|
|
1133 (define_insn "*udivmodhi4_call"
|
|
|
1134 [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
|
|
|
1135 (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
|
|
|
1136 (clobber (reg:HI 26))
|
|
|
1137 (clobber (reg:QI 21))]
|
|
|
1138 ""
|
|
|
1139 "%~call __udivmodhi4"
|
|
|
1140 [(set_attr "type" "xcall")
|
|
|
1141 (set_attr "cc" "clobber")])
|
|
|
1142
|
|
|
1143 (define_expand "divmodsi4"
|
|
|
1144 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
|
|
|
1145 (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
|
|
|
1146 (parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
|
|
|
1147 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
|
|
|
1148 (clobber (reg:HI 26))
|
|
|
1149 (clobber (reg:HI 30))])
|
|
|
1150 (set (match_operand:SI 0 "register_operand" "") (reg:SI 18))
|
|
|
1151 (set (match_operand:SI 3 "register_operand" "") (reg:SI 22))]
|
|
|
1152 ""
|
|
|
1153 "")
|
|
|
1154
|
|
|
1155 (define_insn "*divmodsi4_call"
|
|
|
1156 [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
|
|
|
1157 (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
|
|
|
1158 (clobber (reg:HI 26))
|
|
|
1159 (clobber (reg:HI 30))]
|
|
|
1160 ""
|
|
|
1161 "%~call __divmodsi4"
|
|
|
1162 [(set_attr "type" "xcall")
|
|
|
1163 (set_attr "cc" "clobber")])
|
|
|
1164
|
|
|
1165 (define_expand "udivmodsi4"
|
|
|
1166 [(set (reg:SI 22) (match_operand:SI 1 "register_operand" ""))
|
|
|
1167 (set (reg:SI 18) (match_operand:SI 2 "register_operand" ""))
|
|
|
1168 (parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
|
|
|
1169 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
|
|
|
1170 (clobber (reg:HI 26))
|
|
|
1171 (clobber (reg:HI 30))])
|
|
|
1172 (set (match_operand:SI 0 "register_operand" "") (reg:SI 18))
|
|
|
1173 (set (match_operand:SI 3 "register_operand" "") (reg:SI 22))]
|
|
|
1174 ""
|
|
|
1175 "")
|
|
|
1176
|
|
|
1177 (define_insn "*udivmodsi4_call"
|
|
|
1178 [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
|
|
|
1179 (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
|
|
|
1180 (clobber (reg:HI 26))
|
|
|
1181 (clobber (reg:HI 30))]
|
|
|
1182 ""
|
|
|
1183 "%~call __udivmodsi4"
|
|
|
1184 [(set_attr "type" "xcall")
|
|
|
1185 (set_attr "cc" "clobber")])
|
|
|
1186
|
|
|
1187 ;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
|
|
|
1188 ; and
|
|
|
1189
|
|
|
1190 (define_insn "andqi3"
|
|
|
1191 [(set (match_operand:QI 0 "register_operand" "=r,d")
|
|
|
1192 (and:QI (match_operand:QI 1 "register_operand" "%0,0")
|
|
|
1193 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
|
|
|
1194 ""
|
|
|
1195 "@
|
|
|
1196 and %0,%2
|
|
|
1197 andi %0,lo8(%2)"
|
|
|
1198 [(set_attr "length" "1,1")
|
|
|
1199 (set_attr "cc" "set_zn,set_zn")])
|
|
|
1200
|
|
|
1201 (define_insn "andhi3"
|
|
|
1202 [(set (match_operand:HI 0 "register_operand" "=r,d,r")
|
|
|
1203 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0")
|
|
|
1204 (match_operand:HI 2 "nonmemory_operand" "r,i,M")))
|
|
|
1205 (clobber (match_scratch:QI 3 "=X,X,&d"))]
|
|
|
1206 ""
|
|
|
1207 "*{
|
|
|
1208 if (which_alternative==0)
|
|
|
1209 return (AS2 (and,%A0,%A2) CR_TAB
|
|
|
1210 AS2 (and,%B0,%B2));
|
|
|
1211 else if (which_alternative==1)
|
|
|
1212 {
|
|
|
1213 if (GET_CODE (operands[2]) == CONST_INT)
|
|
|
1214 {
|
|
|
1215 int mask = INTVAL (operands[2]);
|
|
|
1216 if ((mask & 0xff) != 0xff)
|
|
|
1217 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
|
|
|
1218 if ((mask & 0xff00) != 0xff00)
|
|
|
1219 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
|
|
|
1220 return \"\";
|
|
|
1221 }
|
|
|
1222 return (AS2 (andi,%A0,lo8(%2)) CR_TAB
|
|
|
1223 AS2 (andi,%B0,hi8(%2)));
|
|
|
1224 }
|
|
|
1225 return (AS2 (ldi,%3,lo8(%2)) CR_TAB
|
|
|
1226 AS2 (and,%A0,%3) CR_TAB
|
|
|
1227 AS1 (clr,%B0));
|
|
|
1228 }"
|
|
|
1229 [(set_attr "length" "2,2,3")
|
|
|
1230 (set_attr "cc" "set_n,clobber,set_n")])
|
|
|
1231
|
|
|
1232 (define_insn "andsi3"
|
|
|
1233 [(set (match_operand:SI 0 "register_operand" "=r,d")
|
|
|
1234 (and:SI (match_operand:SI 1 "register_operand" "%0,0")
|
|
|
1235 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
|
|
|
1236 ""
|
|
|
1237 "*{
|
|
|
1238 if (which_alternative==0)
|
|
|
1239 return (AS2 (and, %0,%2) CR_TAB
|
|
|
1240 AS2 (and, %B0,%B2) CR_TAB
|
|
|
1241 AS2 (and, %C0,%C2) CR_TAB
|
|
|
1242 AS2 (and, %D0,%D2));
|
|
|
1243 else if (which_alternative==1)
|
|
|
1244 {
|
|
|
1245 if (GET_CODE (operands[2]) == CONST_INT)
|
|
|
1246 {
|
|
|
1247 HOST_WIDE_INT mask = INTVAL (operands[2]);
|
|
|
1248 if ((mask & 0xff) != 0xff)
|
|
|
1249 output_asm_insn (AS2 (andi,%A0,lo8(%2)), operands);
|
|
|
1250 if ((mask & 0xff00) != 0xff00)
|
|
|
1251 output_asm_insn (AS2 (andi,%B0,hi8(%2)), operands);
|
|
|
1252 if ((mask & 0xff0000L) != 0xff0000L)
|
|
|
1253 output_asm_insn (AS2 (andi,%C0,hlo8(%2)), operands);
|
|
|
1254 if ((mask & 0xff000000L) != 0xff000000L)
|
|
|
1255 output_asm_insn (AS2 (andi,%D0,hhi8(%2)), operands);
|
|
|
1256 return \"\";
|
|
|
1257 }
|
|
|
1258 return (AS2 (andi, %A0,lo8(%2)) CR_TAB
|
|
|
1259 AS2 (andi, %B0,hi8(%2)) CR_TAB
|
|
|
1260 AS2 (andi, %C0,hlo8(%2)) CR_TAB
|
|
|
1261 AS2 (andi, %D0,hhi8(%2)));
|
|
|
1262 }
|
|
|
1263 return \"bug\";
|
|
|
1264 }"
|
|
|
1265 [(set_attr "length" "4,4")
|
|
|
1266 (set_attr "cc" "set_n,clobber")])
|
|
|
1267
|
|
|
1268 (define_peephole2 ; andi
|
|
|
1269 [(set (match_operand:QI 0 "d_register_operand" "")
|
|
|
1270 (and:QI (match_dup 0)
|
|
|
1271 (match_operand:QI 1 "const_int_operand" "")))
|
|
|
1272 (set (match_dup 0)
|
|
|
1273 (and:QI (match_dup 0)
|
|
|
1274 (match_operand:QI 2 "const_int_operand" "")))]
|
|
|
1275 ""
|
|
|
1276 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
|
|
|
1277 {
|
|
|
1278 operands[1] = GEN_INT (INTVAL (operands[1]) & INTVAL (operands[2]));
|
|
|
1279 })
|
|
|
1280
|
|
|
1281 ;;|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
|
|
1282 ;; ior
|
|
|
1283
|
|
|
1284 (define_insn "iorqi3"
|
|
|
1285 [(set (match_operand:QI 0 "register_operand" "=r,d")
|
|
|
1286 (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
|
|
|
1287 (match_operand:QI 2 "nonmemory_operand" "r,i")))]
|
|
|
1288 ""
|
|
|
1289 "@
|
|
|
1290 or %0,%2
|
|
|
1291 ori %0,lo8(%2)"
|
|
|
1292 [(set_attr "length" "1,1")
|
|
|
1293 (set_attr "cc" "set_zn,set_zn")])
|
|
|
1294
|
|
|
1295 (define_insn "iorhi3"
|
|
|
1296 [(set (match_operand:HI 0 "register_operand" "=r,d")
|
|
|
1297 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
|
|
|
1298 (match_operand:HI 2 "nonmemory_operand" "r,i")))]
|
|
|
1299 ""
|
|
|
1300 "*{
|
|
|
1301 if (which_alternative==0)
|
|
|
1302 return (AS2 (or,%A0,%A2) CR_TAB
|
|
|
1303 AS2 (or,%B0,%B2));
|
|
|
1304 if (GET_CODE (operands[2]) == CONST_INT)
|
|
|
1305 {
|
|
|
1306 int mask = INTVAL (operands[2]);
|
|
|
1307 if (mask & 0xff)
|
|
|
1308 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
|
|
|
1309 if (mask & 0xff00)
|
|
|
1310 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
|
|
|
1311 return \"\";
|
|
|
1312 }
|
|
|
1313 return (AS2 (ori,%0,lo8(%2)) CR_TAB
|
|
|
1314 AS2 (ori,%B0,hi8(%2)));
|
|
|
1315 }"
|
|
|
1316 [(set_attr "length" "2,2")
|
|
|
1317 (set_attr "cc" "set_n,clobber")])
|
|
|
1318
|
|
|
1319 (define_insn "*iorhi3_clobber"
|
|
|
1320 [(set (match_operand:HI 0 "register_operand" "=r,r")
|
|
|
1321 (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
|
|
|
1322 (match_operand:HI 2 "immediate_operand" "M,i")))
|
|
|
1323 (clobber (match_scratch:QI 3 "=&d,&d"))]
|
|
|
1324 ""
|
|
|
1325 "@
|
|
|
1326 ldi %3,lo8(%2)\;or %A0,%3
|
|
|
1327 ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3"
|
|
|
1328 [(set_attr "length" "2,4")
|
|
|
1329 (set_attr "cc" "clobber,set_n")])
|
|
|
1330
|
|
|
1331 (define_insn "iorsi3"
|
|
|
1332 [(set (match_operand:SI 0 "register_operand" "=r,d")
|
|
|
1333 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
|
|
|
1334 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
|
|
|
1335 ""
|
|
|
1336 "*{
|
|
|
1337 if (which_alternative==0)
|
|
|
1338 return (AS2 (or, %0,%2) CR_TAB
|
|
|
1339 AS2 (or, %B0,%B2) CR_TAB
|
|
|
1340 AS2 (or, %C0,%C2) CR_TAB
|
|
|
1341 AS2 (or, %D0,%D2));
|
|
|
1342 if (GET_CODE (operands[2]) == CONST_INT)
|
|
|
1343 {
|
|
|
1344 HOST_WIDE_INT mask = INTVAL (operands[2]);
|
|
|
1345 if (mask & 0xff)
|
|
|
1346 output_asm_insn (AS2 (ori,%A0,lo8(%2)), operands);
|
|
|
1347 if (mask & 0xff00)
|
|
|
1348 output_asm_insn (AS2 (ori,%B0,hi8(%2)), operands);
|
|
|
1349 if (mask & 0xff0000L)
|
|
|
1350 output_asm_insn (AS2 (ori,%C0,hlo8(%2)), operands);
|
|
|
1351 if (mask & 0xff000000L)
|
|
|
1352 output_asm_insn (AS2 (ori,%D0,hhi8(%2)), operands);
|
|
|
1353 return \"\";
|
|
|
1354 }
|
|
|
1355 return (AS2 (ori, %A0,lo8(%2)) CR_TAB
|
|
|
1356 AS2 (ori, %B0,hi8(%2)) CR_TAB
|
|
|
1357 AS2 (ori, %C0,hlo8(%2)) CR_TAB
|
|
|
1358 AS2 (ori, %D0,hhi8(%2)));
|
|
|
1359 }"
|
|
|
1360 [(set_attr "length" "4,4")
|
|
|
1361 (set_attr "cc" "set_n,clobber")])
|
|
|
1362
|
|
|
1363 (define_insn "*iorsi3_clobber"
|
|
|
1364 [(set (match_operand:SI 0 "register_operand" "=r,r")
|
|
|
1365 (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
|
|
|
1366 (match_operand:SI 2 "immediate_operand" "M,i")))
|
|
|
1367 (clobber (match_scratch:QI 3 "=&d,&d"))]
|
|
|
1368 ""
|
|
|
1369 "@
|
|
|
1370 ldi %3,lo8(%2)\;or %A0,%3
|
|
|
1371 ldi %3,lo8(%2)\;or %A0,%3\;ldi %3,hi8(%2)\;or %B0,%3\;ldi %3,hlo8(%2)\;or %C0,%3\;ldi %3,hhi8(%2)\;or %D0,%3"
|
|
|
1372 [(set_attr "length" "2,8")
|
|
|
1373 (set_attr "cc" "clobber,set_n")])
|
|
|
1374
|
|
|
1375 ;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
1376 ;; xor
|
|
|
1377
|
|
|
1378 (define_insn "xorqi3"
|
|
|
1379 [(set (match_operand:QI 0 "register_operand" "=r")
|
|
|
1380 (xor:QI (match_operand:QI 1 "register_operand" "%0")
|
|
|
1381 (match_operand:QI 2 "register_operand" "r")))]
|
|
|
1382 ""
|
|
|
1383 "eor %0,%2"
|
|
|
1384 [(set_attr "length" "1")
|
|
|
1385 (set_attr "cc" "set_zn")])
|
|
|
1386
|
|
|
1387 (define_insn "xorhi3"
|
|
|
1388 [(set (match_operand:HI 0 "register_operand" "=r")
|
|
|
1389 (xor:HI (match_operand:HI 1 "register_operand" "%0")
|
|
|
1390 (match_operand:HI 2 "register_operand" "r")))]
|
|
|
1391 ""
|
|
|
1392 "eor %0,%2
|
|
|
1393 eor %B0,%B2"
|
|
|
1394 [(set_attr "length" "2")
|
|
|
1395 (set_attr "cc" "set_n")])
|
|
|
1396
|
|
|
1397 (define_insn "xorsi3"
|
|
|
1398 [(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
1399 (xor:SI (match_operand:SI 1 "register_operand" "%0")
|
|
|
1400 (match_operand:SI 2 "register_operand" "r")))]
|
|
|
1401 ""
|
|
|
1402 "eor %0,%2
|
|
|
1403 eor %B0,%B2
|
|
|
1404 eor %C0,%C2
|
|
|
1405 eor %D0,%D2"
|
|
|
1406 [(set_attr "length" "4")
|
|
|
1407 (set_attr "cc" "set_n")])
|
|
|
1408
|
|
|
1409 ;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap
|
|
|
1410 ;; swap
|
|
|
1411
|
|
|
1412 (define_expand "rotlqi3"
|
|
|
1413 [(set (match_operand:QI 0 "register_operand" "")
|
|
|
1414 (rotate:QI (match_operand:QI 1 "register_operand" "")
|
|
|
1415 (match_operand:QI 2 "const_int_operand" "")))]
|
|
|
1416 ""
|
|
|
1417 "
|
|
|
1418 {
|
|
|
1419 if (INTVAL (operands[2]) != 4)
|
|
|
1420 FAIL;
|
|
|
1421 }")
|
|
|
1422
|
|
|
1423 (define_insn "*rotlqi3_4"
|
|
|
1424 [(set (match_operand:QI 0 "register_operand" "=r")
|
|
|
1425 (rotate:QI (match_operand:QI 1 "register_operand" "0")
|
|
|
1426 (const_int 4)))]
|
|
|
1427 ""
|
|
|
1428 "swap %0"
|
|
|
1429 [(set_attr "length" "1")
|
|
|
1430 (set_attr "cc" "none")])
|
|
|
1431
|
|
|
1432 (define_expand "rotlhi3"
|
|
|
1433 [(set (match_operand:HI 0 "register_operand" "")
|
|
|
1434 (rotate:HI (match_operand:HI 1 "register_operand" "")
|
|
|
1435 (match_operand:HI 2 "const_int_operand" "")))]
|
|
|
1436 ""
|
|
|
1437 "
|
|
|
1438 {
|
|
|
1439 if (INTVAL (operands[2]) != 8)
|
|
|
1440 FAIL;
|
|
|
1441 }")
|
|
|
1442
|
|
|
1443 (define_insn_and_split "*rotlhi3_8"
|
|
|
1444 [(set (match_operand:HI 0 "register_operand" "=r")
|
|
|
1445 (rotate:HI (match_operand:HI 1 "register_operand" "r")
|
|
|
1446 (const_int 8)))]
|
|
|
1447 ""
|
|
|
1448 "mov __tmp_reg__,%A0
|
|
|
1449 mov %A0,%B0
|
|
|
1450 mov %B0, __tmp_reg__"
|
|
|
1451 "reload_completed
|
|
|
1452 && REGNO (operands[0]) != REGNO (operands[1])"
|
|
|
1453 [(set (match_dup 2) (match_dup 5))
|
|
|
1454 (set (match_dup 3) (match_dup 4))]
|
|
|
1455 "operands[2] = gen_lowpart (QImode, operands[0]);
|
|
|
1456 operands[3] = gen_highpart (QImode, operands[0]);
|
|
|
1457
|
|
|
1458 operands[4] = gen_lowpart (QImode, operands[1]);
|
|
|
1459 operands[5] = gen_highpart (QImode, operands[1]);"
|
|
|
1460 [(set_attr "length" "3")
|
|
|
1461 (set_attr "cc" "none")])
|
|
|
1462
|
|
|
1463 (define_expand "rotlsi3"
|
|
|
1464 [(set (match_operand:SI 0 "register_operand" "")
|
|
|
1465 (rotate:SI (match_operand:SI 1 "register_operand" "")
|
|
|
1466 (match_operand:SI 2 "const_int_operand" "")))]
|
|
|
1467 ""
|
|
|
1468 "
|
|
|
1469 {
|
|
|
1470 if (INTVAL (operands[2]) != 8
|
|
|
1471 || INTVAL (operands[2]) != 16
|
|
|
1472 || INTVAL (operands[2]) != 24)
|
|
|
1473 FAIL;
|
|
|
1474 }")
|
|
|
1475
|
|
|
1476 (define_insn_and_split "*rotlsi3_16"
|
|
|
1477 [(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
1478 (rotate:SI (match_operand:SI 1 "register_operand" "r")
|
|
|
1479 (const_int 16)))]
|
|
|
1480 ""
|
|
|
1481 "{mov __tmp_reg__,%A1\;mov %A0,%C1\;mov %C0, __tmp_reg__\;mov __tmp_reg__,%B1\;mov %B0,%D1\;mov %D0, __tmp_reg__|movw __tmp_reg__,%A1\;movw %A0,%C1\;movw %C0, __tmp_reg__\;clr __zero_reg__}"
|
|
|
1482 "reload_completed
|
|
|
1483 && REGNO (operands[0]) != REGNO (operands[1])"
|
|
|
1484 [(set (match_dup 2) (match_dup 5))
|
|
|
1485 (set (match_dup 3) (match_dup 4))]
|
|
|
1486 "unsigned int si_lo_off = subreg_lowpart_offset (HImode, SImode);
|
|
|
1487 unsigned int si_hi_off = subreg_highpart_offset (HImode, SImode);
|
|
|
1488
|
|
|
1489 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, si_lo_off);
|
|
|
1490 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, si_hi_off);
|
|
|
1491
|
|
|
1492 operands[4] = simplify_gen_subreg (HImode, operands[1], SImode, si_lo_off);
|
|
|
1493 operands[5] = simplify_gen_subreg (HImode, operands[1], SImode, si_hi_off);
|
|
|
1494
|
|
|
1495 if (REGNO (operands[0]) == REGNO(operands[1]) + 2)
|
|
|
1496 {
|
|
|
1497 emit_move_insn (operands[3], operands[4]);
|
|
|
1498 DONE;
|
|
|
1499 }
|
|
|
1500 else if (REGNO (operands[0]) == REGNO(operands[1]) - 2)
|
|
|
1501 {
|
|
|
1502 emit_move_insn (operands[2], operands[5]);
|
|
|
1503 DONE;
|
|
|
1504 }"
|
|
|
1505 [(set (attr "length") (if_then_else (eq_attr "mcu_have_movw" "yes")
|
|
|
1506 (const_int 4)
|
|
|
1507 (const_int 6)))
|
|
|
1508 (set (attr "cc") (if_then_else (eq_attr "mcu_have_movw" "yes")
|
|
|
1509 (const_string "clobber")
|
|
|
1510 (const_string "none")))])
|
|
|
1511
|
|
|
1512 (define_insn_and_split "*rotlsi3_8"
|
|
|
1513 [(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
1514 (rotate:SI (match_operand:SI 1 "register_operand" "r")
|
|
|
1515 (const_int 8)))]
|
|
|
1516 ""
|
|
|
1517 "mov __tmp_reg__,%D1
|
|
|
1518 mov %D0,%C1
|
|
|
1519 mov %C0,%B1
|
|
|
1520 mov %B0,%A1
|
|
|
1521 mov %A0, __tmp_reg__"
|
|
|
1522 "reload_completed
|
|
|
1523 && REGNO (operands[0]) != REGNO (operands[1])"
|
|
|
1524 [(const_int 0)]
|
|
|
1525 "unsigned int si_lo_off = subreg_lowpart_offset (HImode, SImode);
|
|
|
1526 unsigned int si_hi_off = subreg_highpart_offset (HImode, SImode);
|
|
|
1527 unsigned int hi_lo_off = subreg_lowpart_offset (QImode, HImode);
|
|
|
1528 unsigned int hi_hi_off = subreg_highpart_offset (QImode, HImode);
|
|
|
1529
|
|
|
1530 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, si_lo_off);
|
|
|
1531 operands[4] = simplify_gen_subreg (HImode, operands[0], SImode, si_hi_off);
|
|
|
1532 operands[3] = simplify_gen_subreg (QImode, operands[2], HImode, hi_hi_off);
|
|
|
1533 operands[2] = simplify_gen_subreg (QImode, operands[2], HImode, hi_lo_off);
|
|
|
1534 operands[5] = simplify_gen_subreg (QImode, operands[4], HImode, hi_hi_off);
|
|
|
1535 operands[4] = simplify_gen_subreg (QImode, operands[4], HImode, hi_lo_off);
|
|
|
1536
|
|
|
1537 operands[6] = simplify_gen_subreg (HImode, operands[1], SImode, si_lo_off);
|
|
|
1538 operands[8] = simplify_gen_subreg (HImode, operands[1], SImode, si_hi_off);
|
|
|
1539 operands[7] = simplify_gen_subreg (QImode, operands[6], HImode, hi_hi_off);
|
|
|
1540 operands[6] = simplify_gen_subreg (QImode, operands[6], HImode, hi_lo_off);
|
|
|
1541 operands[9] = simplify_gen_subreg (QImode, operands[8], HImode, hi_hi_off);
|
|
|
1542 operands[8] = simplify_gen_subreg (QImode, operands[8], HImode, hi_lo_off);
|
|
|
1543
|
|
|
1544 if (REGNO (operands[0]) < REGNO(operands[1]))
|
|
|
1545 {
|
|
|
1546 emit_move_insn (operands[2], operands[9]);
|
|
|
1547 emit_move_insn (operands[3], operands[6]);
|
|
|
1548 emit_move_insn (operands[4], operands[7]);
|
|
|
1549 emit_move_insn (operands[5], operands[8]);
|
|
|
1550 }
|
|
|
1551 else
|
|
|
1552 {
|
|
|
1553 emit_move_insn (operands[5], operands[8]);
|
|
|
1554 emit_move_insn (operands[2], operands[9]);
|
|
|
1555 emit_move_insn (operands[4], operands[7]);
|
|
|
1556 emit_move_insn (operands[3], operands[6]);
|
|
|
1557 }
|
|
|
1558 DONE;"
|
|
|
1559 [(set_attr "length" "5")
|
|
|
1560 (set_attr "cc" "none")])
|
|
|
1561
|
|
|
1562 (define_insn_and_split "*rotlsi3_24"
|
|
|
1563 [(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
1564 (rotate:SI (match_operand:SI 1 "register_operand" "r")
|
|
|
1565 (const_int 24)))]
|
|
|
1566 ""
|
|
|
1567 "mov __tmp_reg__,%A1
|
|
|
1568 mov %A0,%B1
|
|
|
1569 mov %B0,%C1
|
|
|
1570 mov %C0,%D1
|
|
|
1571 mov %D0, __tmp_reg__"
|
|
|
1572 "reload_completed
|
|
|
1573 && REGNO (operands[0]) != REGNO (operands[1])"
|
|
|
1574 [(const_int 0)]
|
|
|
1575 "unsigned int si_lo_off = subreg_lowpart_offset (HImode, SImode);
|
|
|
1576 unsigned int si_hi_off = subreg_highpart_offset (HImode, SImode);
|
|
|
1577 unsigned int hi_lo_off = subreg_lowpart_offset (QImode, HImode);
|
|
|
1578 unsigned int hi_hi_off = subreg_highpart_offset (QImode, HImode);
|
|
|
1579
|
|
|
1580 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, si_lo_off);
|
|
|
1581 operands[4] = simplify_gen_subreg (HImode, operands[0], SImode, si_hi_off);
|
|
|
1582 operands[3] = simplify_gen_subreg (QImode, operands[2], HImode, hi_hi_off);
|
|
|
1583 operands[2] = simplify_gen_subreg (QImode, operands[2], HImode, hi_lo_off);
|
|
|
1584 operands[5] = simplify_gen_subreg (QImode, operands[4], HImode, hi_hi_off);
|
|
|
1585 operands[4] = simplify_gen_subreg (QImode, operands[4], HImode, hi_lo_off);
|
|
|
1586
|
|
|
1587 operands[6] = simplify_gen_subreg (HImode, operands[1], SImode, si_lo_off);
|
|
|
1588 operands[8] = simplify_gen_subreg (HImode, operands[1], SImode, si_hi_off);
|
|
|
1589 operands[7] = simplify_gen_subreg (QImode, operands[6], HImode, hi_hi_off);
|
|
|
1590 operands[6] = simplify_gen_subreg (QImode, operands[6], HImode, hi_lo_off);
|
|
|
1591 operands[9] = simplify_gen_subreg (QImode, operands[8], HImode, hi_hi_off);
|
|
|
1592 operands[8] = simplify_gen_subreg (QImode, operands[8], HImode, hi_lo_off);
|
|
|
1593
|
|
|
1594 if (REGNO (operands[0]) < REGNO(operands[1]))
|
|
|
1595 {
|
|
|
1596 emit_move_insn (operands[2], operands[7]);
|
|
|
1597 emit_move_insn (operands[5], operands[6]);
|
|
|
1598 emit_move_insn (operands[3], operands[8]);
|
|
|
1599 emit_move_insn (operands[4], operands[9]);
|
|
|
1600 }
|
|
|
1601 else
|
|
|
1602 {
|
|
|
1603 emit_move_insn (operands[5], operands[6]);
|
|
|
1604 emit_move_insn (operands[4], operands[9]);
|
|
|
1605 emit_move_insn (operands[3], operands[8]);
|
|
|
1606 emit_move_insn (operands[2], operands[7]);
|
|
|
1607 }
|
|
|
1608 DONE;"
|
|
|
1609 [(set_attr "length" "5")
|
|
|
1610 (set_attr "cc" "none")])
|
|
|
1611
|
|
|
1612 ;;<< << << << << << << << << << << << << << << << << << << << << << << << << <<
|
|
|
1613 ;; arithmetic shift left
|
|
|
1614
|
|
|
1615 (define_expand "ashlqi3"
|
|
|
1616 [(set (match_operand:QI 0 "register_operand" "")
|
|
|
1617 (ashift:QI (match_operand:QI 1 "register_operand" "")
|
|
|
1618 (match_operand:QI 2 "general_operand" "")))]
|
|
|
1619 ""
|
|
|
1620 "")
|
|
|
1621
|
|
|
1622 (define_split ; ashlqi3_const4
|
|
|
1623 [(set (match_operand:QI 0 "d_register_operand" "")
|
|
|
1624 (ashift:QI (match_dup 0)
|
|
|
1625 (const_int 4)))]
|
|
|
1626 ""
|
|
|
1627 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
|
|
|
1628 (set (match_dup 0) (and:QI (match_dup 0) (const_int -16)))]
|
|
|
1629 "")
|
|
|
1630
|
|
|
1631 (define_split ; ashlqi3_const5
|
|
|
1632 [(set (match_operand:QI 0 "d_register_operand" "")
|
|
|
1633 (ashift:QI (match_dup 0)
|
|
|
1634 (const_int 5)))]
|
|
|
1635 ""
|
|
|
1636 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
|
|
|
1637 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
|
|
|
1638 (set (match_dup 0) (and:QI (match_dup 0) (const_int -32)))]
|
|
|
1639 "")
|
|
|
1640
|
|
|
1641 (define_split ; ashlqi3_const6
|
|
|
1642 [(set (match_operand:QI 0 "d_register_operand" "")
|
|
|
1643 (ashift:QI (match_dup 0)
|
|
|
1644 (const_int 6)))]
|
|
|
1645 ""
|
|
|
1646 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
|
|
|
1647 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
|
|
|
1648 (set (match_dup 0) (and:QI (match_dup 0) (const_int -64)))]
|
|
|
1649 "")
|
|
|
1650
|
|
|
1651 (define_insn "*ashlqi3"
|
|
|
1652 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
|
|
|
1653 (ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
|
|
|
1654 (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
|
|
|
1655 ""
|
|
|
1656 "* return ashlqi3_out (insn, operands, NULL);"
|
|
|
1657 [(set_attr "length" "5,0,1,2,4,6,9")
|
|
|
1658 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
|
|
|
1659
|
|
|
1660 (define_insn "ashlhi3"
|
|
|
1661 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
|
|
|
1662 (ashift:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
|
|
|
1663 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
|
|
|
1664 ""
|
|
|
1665 "* return ashlhi3_out (insn, operands, NULL);"
|
|
|
1666 [(set_attr "length" "6,0,2,2,4,10,10")
|
|
|
1667 (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
|
|
|
1668
|
|
|
1669 (define_insn "ashlsi3"
|
|
|
1670 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
|
|
|
1671 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
|
|
|
1672 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
|
|
|
1673 ""
|
|
|
1674 "* return ashlsi3_out (insn, operands, NULL);"
|
|
|
1675 [(set_attr "length" "8,0,4,4,8,10,12")
|
|
|
1676 (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
|
|
|
1677
|
|
|
1678 ;; Optimize if a scratch register from LD_REGS happens to be available.
|
|
|
1679
|
|
|
1680 (define_peephole2 ; ashlqi3_l_const4
|
|
|
1681 [(set (match_operand:QI 0 "l_register_operand" "")
|
|
|
1682 (ashift:QI (match_dup 0)
|
|
|
1683 (const_int 4)))
|
|
|
1684 (match_scratch:QI 1 "d")]
|
|
|
1685 ""
|
|
|
1686 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
|
|
|
1687 (set (match_dup 1) (const_int -16))
|
|
|
1688 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
|
|
|
1689 "")
|
|
|
1690
|
|
|
1691 (define_peephole2 ; ashlqi3_l_const5
|
|
|
1692 [(set (match_operand:QI 0 "l_register_operand" "")
|
|
|
1693 (ashift:QI (match_dup 0)
|
|
|
1694 (const_int 5)))
|
|
|
1695 (match_scratch:QI 1 "d")]
|
|
|
1696 ""
|
|
|
1697 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
|
|
|
1698 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 1)))
|
|
|
1699 (set (match_dup 1) (const_int -32))
|
|
|
1700 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
|
|
|
1701 "")
|
|
|
1702
|
|
|
1703 (define_peephole2 ; ashlqi3_l_const6
|
|
|
1704 [(set (match_operand:QI 0 "l_register_operand" "")
|
|
|
1705 (ashift:QI (match_dup 0)
|
|
|
1706 (const_int 6)))
|
|
|
1707 (match_scratch:QI 1 "d")]
|
|
|
1708 ""
|
|
|
1709 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
|
|
|
1710 (set (match_dup 0) (ashift:QI (match_dup 0) (const_int 2)))
|
|
|
1711 (set (match_dup 1) (const_int -64))
|
|
|
1712 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
|
|
|
1713 "")
|
|
|
1714
|
|
|
1715 (define_peephole2
|
|
|
1716 [(match_scratch:QI 3 "d")
|
|
|
1717 (set (match_operand:HI 0 "register_operand" "")
|
|
|
1718 (ashift:HI (match_operand:HI 1 "register_operand" "")
|
|
|
1719 (match_operand:QI 2 "const_int_operand" "")))]
|
|
|
1720 ""
|
|
|
1721 [(parallel [(set (match_dup 0) (ashift:HI (match_dup 1) (match_dup 2)))
|
|
|
1722 (clobber (match_dup 3))])]
|
|
|
1723 "")
|
|
|
1724
|
|
|
1725 (define_insn "*ashlhi3_const"
|
|
|
1726 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
|
|
|
1727 (ashift:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
|
|
|
1728 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
|
|
|
1729 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
|
|
|
1730 "reload_completed"
|
|
|
1731 "* return ashlhi3_out (insn, operands, NULL);"
|
|
|
1732 [(set_attr "length" "0,2,2,4,10")
|
|
|
1733 (set_attr "cc" "none,set_n,clobber,set_n,clobber")])
|
|
|
1734
|
|
|
1735 (define_peephole2
|
|
|
1736 [(match_scratch:QI 3 "d")
|
|
|
1737 (set (match_operand:SI 0 "register_operand" "")
|
|
|
1738 (ashift:SI (match_operand:SI 1 "register_operand" "")
|
|
|
1739 (match_operand:QI 2 "const_int_operand" "")))]
|
|
|
1740 ""
|
|
|
1741 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
|
|
|
1742 (clobber (match_dup 3))])]
|
|
|
1743 "")
|
|
|
1744
|
|
|
1745 (define_insn "*ashlsi3_const"
|
|
|
1746 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
|
|
|
1747 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
|
|
|
1748 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
|
|
|
1749 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
|
|
|
1750 "reload_completed"
|
|
|
1751 "* return ashlsi3_out (insn, operands, NULL);"
|
|
|
1752 [(set_attr "length" "0,4,4,10")
|
|
|
1753 (set_attr "cc" "none,set_n,clobber,clobber")])
|
|
|
1754
|
|
|
1755 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
|
|
|
1756 ;; arithmetic shift right
|
|
|
1757
|
|
|
1758 (define_insn "ashrqi3"
|
|
|
1759 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
|
|
|
1760 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
|
|
|
1761 (match_operand:QI 2 "general_operand" "r,L,P,K,n,Qm")))]
|
|
|
1762 ""
|
|
|
1763 "* return ashrqi3_out (insn, operands, NULL);"
|
|
|
1764 [(set_attr "length" "5,0,1,2,5,9")
|
|
|
1765 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber")])
|
|
|
1766
|
|
|
1767 (define_insn "ashrhi3"
|
|
|
1768 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
|
|
|
1769 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
|
|
|
1770 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
|
|
|
1771 ""
|
|
|
1772 "* return ashrhi3_out (insn, operands, NULL);"
|
|
|
1773 [(set_attr "length" "6,0,2,4,4,10,10")
|
|
|
1774 (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
|
|
|
1775
|
|
|
1776 (define_insn "ashrsi3"
|
|
|
1777 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
|
|
|
1778 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
|
|
|
1779 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
|
|
|
1780 ""
|
|
|
1781 "* return ashrsi3_out (insn, operands, NULL);"
|
|
|
1782 [(set_attr "length" "8,0,4,6,8,10,12")
|
|
|
1783 (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
|
|
|
1784
|
|
|
1785 ;; Optimize if a scratch register from LD_REGS happens to be available.
|
|
|
1786
|
|
|
1787 (define_peephole2
|
|
|
1788 [(match_scratch:QI 3 "d")
|
|
|
1789 (set (match_operand:HI 0 "register_operand" "")
|
|
|
1790 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
|
|
|
1791 (match_operand:QI 2 "const_int_operand" "")))]
|
|
|
1792 ""
|
|
|
1793 [(parallel [(set (match_dup 0) (ashiftrt:HI (match_dup 1) (match_dup 2)))
|
|
|
1794 (clobber (match_dup 3))])]
|
|
|
1795 "")
|
|
|
1796
|
|
|
1797 (define_insn "*ashrhi3_const"
|
|
|
1798 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
|
|
|
1799 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
|
|
|
1800 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
|
|
|
1801 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
|
|
|
1802 "reload_completed"
|
|
|
1803 "* return ashrhi3_out (insn, operands, NULL);"
|
|
|
1804 [(set_attr "length" "0,2,4,4,10")
|
|
|
1805 (set_attr "cc" "none,clobber,set_n,clobber,clobber")])
|
|
|
1806
|
|
|
1807 (define_peephole2
|
|
|
1808 [(match_scratch:QI 3 "d")
|
|
|
1809 (set (match_operand:SI 0 "register_operand" "")
|
|
|
1810 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
|
|
|
1811 (match_operand:QI 2 "const_int_operand" "")))]
|
|
|
1812 ""
|
|
|
1813 [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (match_dup 2)))
|
|
|
1814 (clobber (match_dup 3))])]
|
|
|
1815 "")
|
|
|
1816
|
|
|
1817 (define_insn "*ashrsi3_const"
|
|
|
1818 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
|
|
|
1819 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
|
|
|
1820 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
|
|
|
1821 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
|
|
|
1822 "reload_completed"
|
|
|
1823 "* return ashrsi3_out (insn, operands, NULL);"
|
|
|
1824 [(set_attr "length" "0,4,4,10")
|
|
|
1825 (set_attr "cc" "none,clobber,set_n,clobber")])
|
|
|
1826
|
|
|
1827 ;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
|
|
|
1828 ;; logical shift right
|
|
|
1829
|
|
|
1830 (define_expand "lshrqi3"
|
|
|
1831 [(set (match_operand:QI 0 "register_operand" "")
|
|
|
1832 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
|
|
|
1833 (match_operand:QI 2 "general_operand" "")))]
|
|
|
1834 ""
|
|
|
1835 "")
|
|
|
1836
|
|
|
1837 (define_split ; lshrqi3_const4
|
|
|
1838 [(set (match_operand:QI 0 "d_register_operand" "")
|
|
|
1839 (lshiftrt:QI (match_dup 0)
|
|
|
1840 (const_int 4)))]
|
|
|
1841 ""
|
|
|
1842 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
|
|
|
1843 (set (match_dup 0) (and:QI (match_dup 0) (const_int 15)))]
|
|
|
1844 "")
|
|
|
1845
|
|
|
1846 (define_split ; lshrqi3_const5
|
|
|
1847 [(set (match_operand:QI 0 "d_register_operand" "")
|
|
|
1848 (lshiftrt:QI (match_dup 0)
|
|
|
1849 (const_int 5)))]
|
|
|
1850 ""
|
|
|
1851 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
|
|
|
1852 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
|
|
|
1853 (set (match_dup 0) (and:QI (match_dup 0) (const_int 7)))]
|
|
|
1854 "")
|
|
|
1855
|
|
|
1856 (define_split ; lshrqi3_const6
|
|
|
1857 [(set (match_operand:QI 0 "d_register_operand" "")
|
|
|
1858 (lshiftrt:QI (match_dup 0)
|
|
|
1859 (const_int 6)))]
|
|
|
1860 ""
|
|
|
1861 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
|
|
|
1862 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
|
|
|
1863 (set (match_dup 0) (and:QI (match_dup 0) (const_int 3)))]
|
|
|
1864 "")
|
|
|
1865
|
|
|
1866 (define_insn "*lshrqi3"
|
|
|
1867 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
|
|
|
1868 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
|
|
|
1869 (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
|
|
|
1870 ""
|
|
|
1871 "* return lshrqi3_out (insn, operands, NULL);"
|
|
|
1872 [(set_attr "length" "5,0,1,2,4,6,9")
|
|
|
1873 (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
|
|
|
1874
|
|
|
1875 (define_insn "lshrhi3"
|
|
|
1876 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
|
|
|
1877 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
|
|
|
1878 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
|
|
|
1879 ""
|
|
|
1880 "* return lshrhi3_out (insn, operands, NULL);"
|
|
|
1881 [(set_attr "length" "6,0,2,2,4,10,10")
|
|
|
1882 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
|
|
|
1883
|
|
|
1884 (define_insn "lshrsi3"
|
|
|
1885 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
|
|
|
1886 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
|
|
|
1887 (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
|
|
|
1888 ""
|
|
|
1889 "* return lshrsi3_out (insn, operands, NULL);"
|
|
|
1890 [(set_attr "length" "8,0,4,4,8,10,12")
|
|
|
1891 (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
|
|
|
1892
|
|
|
1893 ;; Optimize if a scratch register from LD_REGS happens to be available.
|
|
|
1894
|
|
|
1895 (define_peephole2 ; lshrqi3_l_const4
|
|
|
1896 [(set (match_operand:QI 0 "l_register_operand" "")
|
|
|
1897 (lshiftrt:QI (match_dup 0)
|
|
|
1898 (const_int 4)))
|
|
|
1899 (match_scratch:QI 1 "d")]
|
|
|
1900 ""
|
|
|
1901 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
|
|
|
1902 (set (match_dup 1) (const_int 15))
|
|
|
1903 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
|
|
|
1904 "")
|
|
|
1905
|
|
|
1906 (define_peephole2 ; lshrqi3_l_const5
|
|
|
1907 [(set (match_operand:QI 0 "l_register_operand" "")
|
|
|
1908 (lshiftrt:QI (match_dup 0)
|
|
|
1909 (const_int 5)))
|
|
|
1910 (match_scratch:QI 1 "d")]
|
|
|
1911 ""
|
|
|
1912 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
|
|
|
1913 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 1)))
|
|
|
1914 (set (match_dup 1) (const_int 7))
|
|
|
1915 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
|
|
|
1916 "")
|
|
|
1917
|
|
|
1918 (define_peephole2 ; lshrqi3_l_const6
|
|
|
1919 [(set (match_operand:QI 0 "l_register_operand" "")
|
|
|
1920 (lshiftrt:QI (match_dup 0)
|
|
|
1921 (const_int 6)))
|
|
|
1922 (match_scratch:QI 1 "d")]
|
|
|
1923 ""
|
|
|
1924 [(set (match_dup 0) (rotate:QI (match_dup 0) (const_int 4)))
|
|
|
1925 (set (match_dup 0) (lshiftrt:QI (match_dup 0) (const_int 2)))
|
|
|
1926 (set (match_dup 1) (const_int 3))
|
|
|
1927 (set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))]
|
|
|
1928 "")
|
|
|
1929
|
|
|
1930 (define_peephole2
|
|
|
1931 [(match_scratch:QI 3 "d")
|
|
|
1932 (set (match_operand:HI 0 "register_operand" "")
|
|
|
1933 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
|
|
|
1934 (match_operand:QI 2 "const_int_operand" "")))]
|
|
|
1935 ""
|
|
|
1936 [(parallel [(set (match_dup 0) (lshiftrt:HI (match_dup 1) (match_dup 2)))
|
|
|
1937 (clobber (match_dup 3))])]
|
|
|
1938 "")
|
|
|
1939
|
|
|
1940 (define_insn "*lshrhi3_const"
|
|
|
1941 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
|
|
|
1942 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
|
|
|
1943 (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
|
|
|
1944 (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
|
|
|
1945 "reload_completed"
|
|
|
1946 "* return lshrhi3_out (insn, operands, NULL);"
|
|
|
1947 [(set_attr "length" "0,2,2,4,10")
|
|
|
1948 (set_attr "cc" "none,clobber,clobber,clobber,clobber")])
|
|
|
1949
|
|
|
1950 (define_peephole2
|
|
|
1951 [(match_scratch:QI 3 "d")
|
|
|
1952 (set (match_operand:SI 0 "register_operand" "")
|
|
|
1953 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
|
|
|
1954 (match_operand:QI 2 "const_int_operand" "")))]
|
|
|
1955 ""
|
|
|
1956 [(parallel [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (match_dup 2)))
|
|
|
1957 (clobber (match_dup 3))])]
|
|
|
1958 "")
|
|
|
1959
|
|
|
1960 (define_insn "*lshrsi3_const"
|
|
|
1961 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
|
|
|
1962 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
|
|
|
1963 (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
|
|
|
1964 (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
|
|
|
1965 "reload_completed"
|
|
|
1966 "* return lshrsi3_out (insn, operands, NULL);"
|
|
|
1967 [(set_attr "length" "0,4,4,10")
|
|
|
1968 (set_attr "cc" "none,clobber,clobber,clobber")])
|
|
|
1969
|
|
|
1970 ;; abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x)
|
|
|
1971 ;; abs
|
|
|
1972
|
|
|
1973 (define_insn "absqi2"
|
|
|
1974 [(set (match_operand:QI 0 "register_operand" "=r")
|
|
|
1975 (abs:QI (match_operand:QI 1 "register_operand" "0")))]
|
|
|
1976 ""
|
|
|
1977 "sbrc %0,7
|
|
|
1978 neg %0"
|
|
|
1979 [(set_attr "length" "2")
|
|
|
1980 (set_attr "cc" "clobber")])
|
|
|
1981
|
|
|
1982
|
|
|
1983 (define_insn "abssf2"
|
|
|
1984 [(set (match_operand:SF 0 "register_operand" "=d,r")
|
|
|
1985 (abs:SF (match_operand:SF 1 "register_operand" "0,0")))]
|
|
|
1986 ""
|
|
|
1987 "@
|
|
|
1988 andi %D0,0x7f
|
|
|
1989 clt\;bld %D0,7"
|
|
|
1990 [(set_attr "length" "1,2")
|
|
|
1991 (set_attr "cc" "set_n,clobber")])
|
|
|
1992
|
|
|
1993 ;; 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x
|
|
|
1994 ;; neg
|
|
|
1995
|
|
|
1996 (define_insn "negqi2"
|
|
|
1997 [(set (match_operand:QI 0 "register_operand" "=r")
|
|
|
1998 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
|
|
|
1999 ""
|
|
|
2000 "neg %0"
|
|
|
2001 [(set_attr "length" "1")
|
|
|
2002 (set_attr "cc" "set_zn")])
|
|
|
2003
|
|
|
2004 (define_insn "neghi2"
|
|
|
2005 [(set (match_operand:HI 0 "register_operand" "=!d,r,&r")
|
|
|
2006 (neg:HI (match_operand:HI 1 "register_operand" "0,0,r")))]
|
|
|
2007 ""
|
|
|
2008 "@
|
|
|
2009 com %B0\;neg %A0\;sbci %B0,lo8(-1)
|
|
|
2010 com %B0\;neg %A0\;sbc %B0,__zero_reg__\;inc %B0
|
|
|
2011 clr %A0\;clr %B0\;sub %A0,%A1\;sbc %B0,%B1"
|
|
|
2012 [(set_attr "length" "3,4,4")
|
|
|
2013 (set_attr "cc" "set_czn,set_n,set_czn")])
|
|
|
2014
|
|
|
2015 (define_insn "negsi2"
|
|
|
2016 [(set (match_operand:SI 0 "register_operand" "=!d,r,&r")
|
|
|
2017 (neg:SI (match_operand:SI 1 "register_operand" "0,0,r")))]
|
|
|
2018 ""
|
|
|
2019 "@
|
|
|
2020 com %D0\;com %C0\;com %B0\;neg %A0\;sbci %B0,lo8(-1)\;sbci %C0,lo8(-1)\;sbci %D0,lo8(-1)
|
|
|
2021 com %D0\;com %C0\;com %B0\;com %A0\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
|
|
|
2022 clr %A0\;clr %B0\;{clr %C0\;clr %D0|movw %C0,%A0}\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1"
|
|
|
2023 [(set_attr_alternative "length"
|
|
|
2024 [(const_int 7)
|
|
|
2025 (const_int 8)
|
|
|
2026 (if_then_else (eq_attr "mcu_have_movw" "yes")
|
|
|
2027 (const_int 7)
|
|
|
2028 (const_int 8))])
|
|
|
2029 (set_attr "cc" "set_czn,set_n,set_czn")])
|
|
|
2030
|
|
|
2031 (define_insn "negsf2"
|
|
|
2032 [(set (match_operand:SF 0 "register_operand" "=d,r")
|
|
|
2033 (neg:SF (match_operand:SF 1 "register_operand" "0,0")))]
|
|
|
2034 ""
|
|
|
2035 "@
|
|
|
2036 subi %D0,0x80
|
|
|
2037 bst %D0,7\;com %D0\;bld %D0,7\;com %D0"
|
|
|
2038 [(set_attr "length" "1,4")
|
|
|
2039 (set_attr "cc" "set_n,set_n")])
|
|
|
2040
|
|
|
2041 ;; !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
|
|
2042 ;; not
|
|
|
2043
|
|
|
2044 (define_insn "one_cmplqi2"
|
|
|
2045 [(set (match_operand:QI 0 "register_operand" "=r")
|
|
|
2046 (not:QI (match_operand:QI 1 "register_operand" "0")))]
|
|
|
2047 ""
|
|
|
2048 "com %0"
|
|
|
2049 [(set_attr "length" "1")
|
|
|
2050 (set_attr "cc" "set_czn")])
|
|
|
2051
|
|
|
2052 (define_insn "one_cmplhi2"
|
|
|
2053 [(set (match_operand:HI 0 "register_operand" "=r")
|
|
|
2054 (not:HI (match_operand:HI 1 "register_operand" "0")))]
|
|
|
2055 ""
|
|
|
2056 "com %0
|
|
|
2057 com %B0"
|
|
|
2058 [(set_attr "length" "2")
|
|
|
2059 (set_attr "cc" "set_n")])
|
|
|
2060
|
|
|
2061 (define_insn "one_cmplsi2"
|
|
|
2062 [(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
2063 (not:SI (match_operand:SI 1 "register_operand" "0")))]
|
|
|
2064 ""
|
|
|
2065 "com %0
|
|
|
2066 com %B0
|
|
|
2067 com %C0
|
|
|
2068 com %D0"
|
|
|
2069 [(set_attr "length" "4")
|
|
|
2070 (set_attr "cc" "set_n")])
|
|
|
2071
|
|
|
2072 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
|
|
|
2073 ;; sign extend
|
|
|
2074
|
|
|
2075 (define_insn "extendqihi2"
|
|
|
2076 [(set (match_operand:HI 0 "register_operand" "=r,r")
|
|
|
2077 (sign_extend:HI (match_operand:QI 1 "register_operand" "0,*r")))]
|
|
|
2078 ""
|
|
|
2079 "@
|
|
|
2080 clr %B0\;sbrc %0,7\;com %B0
|
|
|
2081 mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0"
|
|
|
2082 [(set_attr "length" "3,4")
|
|
|
2083 (set_attr "cc" "set_n,set_n")])
|
|
|
2084
|
|
|
2085 (define_insn "extendqisi2"
|
|
|
2086 [(set (match_operand:SI 0 "register_operand" "=r,r")
|
|
|
2087 (sign_extend:SI (match_operand:QI 1 "register_operand" "0,*r")))]
|
|
|
2088 ""
|
|
|
2089 "@
|
|
|
2090 clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0
|
|
|
2091 mov %A0,%A1\;clr %B0\;sbrc %A0,7\;com %B0\;mov %C0,%B0\;mov %D0,%B0"
|
|
|
2092 [(set_attr "length" "5,6")
|
|
|
2093 (set_attr "cc" "set_n,set_n")])
|
|
|
2094
|
|
|
2095 (define_insn "extendhisi2"
|
|
|
2096 [(set (match_operand:SI 0 "register_operand" "=r,&r")
|
|
|
2097 (sign_extend:SI (match_operand:HI 1 "register_operand" "0,*r")))]
|
|
|
2098 ""
|
|
|
2099 "@
|
|
|
2100 clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0
|
|
|
2101 {mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0"
|
|
|
2102 [(set_attr_alternative "length"
|
|
|
2103 [(const_int 4)
|
|
|
2104 (if_then_else (eq_attr "mcu_have_movw" "yes")
|
|
|
2105 (const_int 5)
|
|
|
2106 (const_int 6))])
|
|
|
2107 (set_attr "cc" "set_n,set_n")])
|
|
|
2108
|
|
|
2109 ;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
|
|
|
2110 ;; zero extend
|
|
|
2111
|
|
|
2112 (define_insn_and_split "zero_extendqihi2"
|
|
|
2113 [(set (match_operand:HI 0 "register_operand" "=r")
|
|
|
2114 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
|
|
|
2115 ""
|
|
|
2116 "#"
|
|
|
2117 "reload_completed"
|
|
|
2118 [(set (match_dup 2) (match_dup 1))
|
|
|
2119 (set (match_dup 3) (const_int 0))]
|
|
|
2120 "unsigned int low_off = subreg_lowpart_offset (QImode, HImode);
|
|
|
2121 unsigned int high_off = subreg_highpart_offset (QImode, HImode);
|
|
|
2122
|
|
|
2123 operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, low_off);
|
|
|
2124 operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, high_off);
|
|
|
2125 ")
|
|
|
2126
|
|
|
2127 (define_insn_and_split "zero_extendqisi2"
|
|
|
2128 [(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
2129 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
|
|
|
2130 ""
|
|
|
2131 "#"
|
|
|
2132 "reload_completed"
|
|
|
2133 [(set (match_dup 2) (zero_extend:HI (match_dup 1)))
|
|
|
2134 (set (match_dup 3) (const_int 0))]
|
|
|
2135 "unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
|
|
|
2136 unsigned int high_off = subreg_highpart_offset (HImode, SImode);
|
|
|
2137
|
|
|
2138 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
|
|
|
2139 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
|
|
|
2140 ")
|
|
|
2141
|
|
|
2142 (define_insn_and_split "zero_extendhisi2"
|
|
|
2143 [(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
2144 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
|
|
|
2145 ""
|
|
|
2146 "#"
|
|
|
2147 "reload_completed"
|
|
|
2148 [(set (match_dup 2) (match_dup 1))
|
|
|
2149 (set (match_dup 3) (const_int 0))]
|
|
|
2150 "unsigned int low_off = subreg_lowpart_offset (HImode, SImode);
|
|
|
2151 unsigned int high_off = subreg_highpart_offset (HImode, SImode);
|
|
|
2152
|
|
|
2153 operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off);
|
|
|
2154 operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off);
|
|
|
2155 ")
|
|
|
2156
|
|
|
2157 (define_insn_and_split "zero_extendqidi2"
|
|
|
2158 [(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
2159 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
|
|
|
2160 ""
|
|
|
2161 "#"
|
|
|
2162 "reload_completed"
|
|
|
2163 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
|
|
|
2164 (set (match_dup 3) (const_int 0))]
|
|
|
2165 "unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
|
|
|
2166 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
|
|
|
2167
|
|
|
2168 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
|
|
|
2169 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
|
|
|
2170 ")
|
|
|
2171
|
|
|
2172 (define_insn_and_split "zero_extendhidi2"
|
|
|
2173 [(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
2174 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
|
|
|
2175 ""
|
|
|
2176 "#"
|
|
|
2177 "reload_completed"
|
|
|
2178 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
|
|
|
2179 (set (match_dup 3) (const_int 0))]
|
|
|
2180 "unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
|
|
|
2181 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
|
|
|
2182
|
|
|
2183 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
|
|
|
2184 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
|
|
|
2185 ")
|
|
|
2186
|
|
|
2187 (define_insn_and_split "zero_extendsidi2"
|
|
|
2188 [(set (match_operand:DI 0 "register_operand" "=r")
|
|
|
2189 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
|
|
|
2190 ""
|
|
|
2191 "#"
|
|
|
2192 "reload_completed"
|
|
|
2193 [(set (match_dup 2) (match_dup 1))
|
|
|
2194 (set (match_dup 3) (const_int 0))]
|
|
|
2195 "unsigned int low_off = subreg_lowpart_offset (SImode, DImode);
|
|
|
2196 unsigned int high_off = subreg_highpart_offset (SImode, DImode);
|
|
|
2197
|
|
|
2198 operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off);
|
|
|
2199 operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off);
|
|
|
2200 ")
|
|
|
2201
|
|
|
2202 ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=>
|
|
|
2203 ;; compare
|
|
|
2204
|
|
|
2205 (define_insn "tstqi"
|
|
|
2206 [(set (cc0)
|
|
|
2207 (match_operand:QI 0 "register_operand" "r"))]
|
|
|
2208 ""
|
|
|
2209 "tst %0"
|
|
|
2210 [(set_attr "cc" "compare")
|
|
|
2211 (set_attr "length" "1")])
|
|
|
2212
|
|
|
2213 (define_insn "*reversed_tstqi"
|
|
|
2214 [(set (cc0)
|
|
|
2215 (compare (const_int 0)
|
|
|
2216 (match_operand:QI 0 "register_operand" "r")))]
|
|
|
2217 ""
|
|
|
2218 "cp __zero_reg__,%0"
|
|
|
2219 [(set_attr "cc" "compare")
|
|
|
2220 (set_attr "length" "1")])
|
|
|
2221
|
|
|
2222 (define_insn "tsthi"
|
|
|
2223 [(set (cc0)
|
|
|
2224 (match_operand:HI 0 "register_operand" "!w,r"))]
|
|
|
2225 ""
|
|
|
2226 "* return out_tsthi (insn,NULL);"
|
|
|
2227 [(set_attr "cc" "compare,compare")
|
|
|
2228 (set_attr "length" "1,2")])
|
|
|
2229
|
|
|
2230 (define_insn "*reversed_tsthi"
|
|
|
2231 [(set (cc0)
|
|
|
2232 (compare (const_int 0)
|
|
|
2233 (match_operand:HI 0 "register_operand" "r")))]
|
|
|
2234 ""
|
|
|
2235 "cp __zero_reg__,%A0
|
|
|
2236 cpc __zero_reg__,%B0"
|
|
|
2237 [(set_attr "cc" "compare")
|
|
|
2238 (set_attr "length" "2")])
|
|
|
2239
|
|
|
2240 (define_insn "tstsi"
|
|
|
2241 [(set (cc0)
|
|
|
2242 (match_operand:SI 0 "register_operand" "r"))]
|
|
|
2243 ""
|
|
|
2244 "* return out_tstsi (insn,NULL);"
|
|
|
2245 [(set_attr "cc" "compare")
|
|
|
2246 (set_attr "length" "4")])
|
|
|
2247
|
|
|
2248 (define_insn "*reversed_tstsi"
|
|
|
2249 [(set (cc0)
|
|
|
2250 (compare (const_int 0)
|
|
|
2251 (match_operand:SI 0 "register_operand" "r")))]
|
|
|
2252 ""
|
|
|
2253 "cp __zero_reg__,%A0
|
|
|
2254 cpc __zero_reg__,%B0
|
|
|
2255 cpc __zero_reg__,%C0
|
|
|
2256 cpc __zero_reg__,%D0"
|
|
|
2257 [(set_attr "cc" "compare")
|
|
|
2258 (set_attr "length" "4")])
|
|
|
2259
|
|
|
2260
|
|
|
2261 (define_insn "cmpqi"
|
|
|
2262 [(set (cc0)
|
|
|
2263 (compare (match_operand:QI 0 "register_operand" "r,d")
|
|
|
2264 (match_operand:QI 1 "nonmemory_operand" "r,i")))]
|
|
|
2265 ""
|
|
|
2266 "@
|
|
|
2267 cp %0,%1
|
|
|
2268 cpi %0,lo8(%1)"
|
|
|
2269 [(set_attr "cc" "compare,compare")
|
|
|
2270 (set_attr "length" "1,1")])
|
|
|
2271
|
|
|
2272 (define_insn "*cmpqi_sign_extend"
|
|
|
2273 [(set (cc0)
|
|
|
2274 (compare (sign_extend:HI
|
|
|
2275 (match_operand:QI 0 "register_operand" "d"))
|
|
|
2276 (match_operand:HI 1 "const_int_operand" "n")))]
|
|
|
2277 "INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) <= 127"
|
|
|
2278 "cpi %0,lo8(%1)"
|
|
|
2279 [(set_attr "cc" "compare")
|
|
|
2280 (set_attr "length" "1")])
|
|
|
2281
|
|
|
2282 (define_insn "cmphi"
|
|
|
2283 [(set (cc0)
|
|
|
2284 (compare (match_operand:HI 0 "register_operand" "r,d,d,r,r")
|
|
|
2285 (match_operand:HI 1 "nonmemory_operand" "r,M,i,M,i")))
|
|
|
2286 (clobber (match_scratch:QI 2 "=X,X,&d,&d,&d"))]
|
|
|
2287 ""
|
|
|
2288 "*{
|
|
|
2289 switch (which_alternative)
|
|
|
2290 {
|
|
|
2291 case 0:
|
|
|
2292 return (AS2 (cp,%A0,%A1) CR_TAB
|
|
|
2293 AS2 (cpc,%B0,%B1));
|
|
|
2294 case 1:
|
|
|
2295 if (reg_unused_after (insn, operands[0])
|
|
|
2296 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63
|
|
|
2297 && test_hard_reg_class (ADDW_REGS, operands[0]))
|
|
|
2298 return AS2 (sbiw,%0,%1);
|
|
|
2299 else
|
|
|
2300 return (AS2 (cpi,%0,%1) CR_TAB
|
|
|
2301 AS2 (cpc,%B0,__zero_reg__));
|
|
|
2302 case 2:
|
|
|
2303 if (reg_unused_after (insn, operands[0]))
|
|
|
2304 return (AS2 (subi,%0,lo8(%1)) CR_TAB
|
|
|
2305 AS2 (sbci,%B0,hi8(%1)));
|
|
|
2306 else
|
|
|
2307 return (AS2 (ldi, %2,hi8(%1)) CR_TAB
|
|
|
2308 AS2 (cpi, %A0,lo8(%1)) CR_TAB
|
|
|
2309 AS2 (cpc, %B0,%2));
|
|
|
2310 case 3:
|
|
|
2311 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
|
|
|
2312 AS2 (cp, %A0,%2) CR_TAB
|
|
|
2313 AS2 (cpc, %B0,__zero_reg__));
|
|
|
2314
|
|
|
2315 case 4:
|
|
|
2316 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
|
|
|
2317 AS2 (cp, %A0,%2) CR_TAB
|
|
|
2318 AS2 (ldi, %2,hi8(%1)) CR_TAB
|
|
|
2319 AS2 (cpc, %B0,%2));
|
|
|
2320 }
|
|
|
2321 return \"bug\";
|
|
|
2322 }"
|
|
|
2323 [(set_attr "cc" "compare,compare,compare,compare,compare")
|
|
|
2324 (set_attr "length" "2,2,3,3,4")])
|
|
|
2325
|
|
|
2326
|
|
|
2327 (define_insn "cmpsi"
|
|
|
2328 [(set (cc0)
|
|
|
2329 (compare (match_operand:SI 0 "register_operand" "r,d,d,r,r")
|
|
|
2330 (match_operand:SI 1 "nonmemory_operand" "r,M,i,M,i")))
|
|
|
2331 (clobber (match_scratch:QI 2 "=X,X,&d,&d,&d"))]
|
|
|
2332 ""
|
|
|
2333 "*{
|
|
|
2334 switch (which_alternative)
|
|
|
2335 {
|
|
|
2336 case 0:
|
|
|
2337 return (AS2 (cp,%A0,%A1) CR_TAB
|
|
|
2338 AS2 (cpc,%B0,%B1) CR_TAB
|
|
|
2339 AS2 (cpc,%C0,%C1) CR_TAB
|
|
|
2340 AS2 (cpc,%D0,%D1));
|
|
|
2341 case 1:
|
|
|
2342 if (reg_unused_after (insn, operands[0])
|
|
|
2343 && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63
|
|
|
2344 && test_hard_reg_class (ADDW_REGS, operands[0]))
|
|
|
2345 return (AS2 (sbiw,%0,%1) CR_TAB
|
|
|
2346 AS2 (cpc,%C0,__zero_reg__) CR_TAB
|
|
|
2347 AS2 (cpc,%D0,__zero_reg__));
|
|
|
2348 else
|
|
|
2349 return (AS2 (cpi,%A0,lo8(%1)) CR_TAB
|
|
|
2350 AS2 (cpc,%B0,__zero_reg__) CR_TAB
|
|
|
2351 AS2 (cpc,%C0,__zero_reg__) CR_TAB
|
|
|
2352 AS2 (cpc,%D0,__zero_reg__));
|
|
|
2353 case 2:
|
|
|
2354 if (reg_unused_after (insn, operands[0]))
|
|
|
2355 return (AS2 (subi,%A0,lo8(%1)) CR_TAB
|
|
|
2356 AS2 (sbci,%B0,hi8(%1)) CR_TAB
|
|
|
2357 AS2 (sbci,%C0,hlo8(%1)) CR_TAB
|
|
|
2358 AS2 (sbci,%D0,hhi8(%1)));
|
|
|
2359 else
|
|
|
2360 return (AS2 (cpi, %A0,lo8(%1)) CR_TAB
|
|
|
2361 AS2 (ldi, %2,hi8(%1)) CR_TAB
|
|
|
2362 AS2 (cpc, %B0,%2) CR_TAB
|
|
|
2363 AS2 (ldi, %2,hlo8(%1)) CR_TAB
|
|
|
2364 AS2 (cpc, %C0,%2) CR_TAB
|
|
|
2365 AS2 (ldi, %2,hhi8(%1)) CR_TAB
|
|
|
2366 AS2 (cpc, %D0,%2));
|
|
|
2367 case 3:
|
|
|
2368 return (AS2 (ldi,%2,lo8(%1)) CR_TAB
|
|
|
2369 AS2 (cp,%A0,%2) CR_TAB
|
|
|
2370 AS2 (cpc,%B0,__zero_reg__) CR_TAB
|
|
|
2371 AS2 (cpc,%C0,__zero_reg__) CR_TAB
|
|
|
2372 AS2 (cpc,%D0,__zero_reg__));
|
|
|
2373 case 4:
|
|
|
2374 return (AS2 (ldi, %2,lo8(%1)) CR_TAB
|
|
|
2375 AS2 (cp, %A0,%2) CR_TAB
|
|
|
2376 AS2 (ldi, %2,hi8(%1)) CR_TAB
|
|
|
2377 AS2 (cpc, %B0,%2) CR_TAB
|
|
|
2378 AS2 (ldi, %2,hlo8(%1)) CR_TAB
|
|
|
2379 AS2 (cpc, %C0,%2) CR_TAB
|
|
|
2380 AS2 (ldi, %2,hhi8(%1)) CR_TAB
|
|
|
2381 AS2 (cpc, %D0,%2));
|
|
|
2382 }
|
|
|
2383 return \"bug\";
|
|
|
2384 }"
|
|
|
2385 [(set_attr "cc" "compare,compare,compare,compare,compare")
|
|
|
2386 (set_attr "length" "4,4,7,5,8")])
|
|
|
2387
|
|
|
2388 ; Optimize negated tests into reverse compare if overflow is undefined.
|
|
|
2389 (define_insn_and_split "negated_tst<mode>"
|
|
|
2390 [(set (cc0)
|
|
|
2391 (neg:QISI (match_operand:QISI 0 "register_operand")))]
|
|
|
2392
|
|
|
2393 "(!flag_wrapv && !flag_trapv && flag_strict_overflow)"
|
|
|
2394 "#"
|
|
|
2395 ""
|
|
|
2396 [(set (cc0)
|
|
|
2397 (compare (const_int 0)
|
|
|
2398 (match_dup 0)))]
|
|
|
2399 "")
|
|
|
2400
|
|
|
2401 ;; ----------------------------------------------------------------------
|
|
|
2402 ;; JUMP INSTRUCTIONS
|
|
|
2403 ;; ----------------------------------------------------------------------
|
|
|
2404 ;; Conditional jump instructions
|
|
|
2405
|
|
|
2406 (define_expand "beq"
|
|
|
2407 [(set (pc)
|
|
|
2408 (if_then_else (eq (cc0) (const_int 0))
|
|
|
2409 (label_ref (match_operand 0 "" ""))
|
|
|
2410 (pc)))]
|
|
|
2411 ""
|
|
|
2412 "")
|
|
|
2413
|
|
|
2414 (define_expand "bne"
|
|
|
2415 [(set (pc)
|
|
|
2416 (if_then_else (ne (cc0) (const_int 0))
|
|
|
2417 (label_ref (match_operand 0 "" ""))
|
|
|
2418 (pc)))]
|
|
|
2419 ""
|
|
|
2420 "")
|
|
|
2421
|
|
|
2422 (define_expand "bge"
|
|
|
2423 [(set (pc)
|
|
|
2424 (if_then_else (ge (cc0) (const_int 0))
|
|
|
2425 (label_ref (match_operand 0 "" ""))
|
|
|
2426 (pc)))]
|
|
|
2427 ""
|
|
|
2428 "")
|
|
|
2429
|
|
|
2430 (define_expand "bgeu"
|
|
|
2431 [(set (pc)
|
|
|
2432 (if_then_else (geu (cc0) (const_int 0))
|
|
|
2433 (label_ref (match_operand 0 "" ""))
|
|
|
2434 (pc)))]
|
|
|
2435 ""
|
|
|
2436 "")
|
|
|
2437
|
|
|
2438 (define_expand "blt"
|
|
|
2439 [(set (pc)
|
|
|
2440 (if_then_else (lt (cc0) (const_int 0))
|
|
|
2441 (label_ref (match_operand 0 "" ""))
|
|
|
2442 (pc)))]
|
|
|
2443 ""
|
|
|
2444 "")
|
|
|
2445
|
|
|
2446 (define_expand "bltu"
|
|
|
2447 [(set (pc)
|
|
|
2448 (if_then_else (ltu (cc0) (const_int 0))
|
|
|
2449 (label_ref (match_operand 0 "" ""))
|
|
|
2450 (pc)))]
|
|
|
2451 ""
|
|
|
2452 "")
|
|
|
2453
|
|
|
2454
|
|
|
2455
|
|
|
2456 /****************************************************************
|
|
|
2457 AVR not have following conditional jumps: LE,LEU,GT,GTU.
|
|
|
2458 Convert them all to proper jumps.
|
|
|
2459 *****************************************************************/
|
|
|
2460
|
|
|
2461 (define_expand "ble"
|
|
|
2462 [(set (pc)
|
|
|
2463 (if_then_else (le (cc0) (const_int 0))
|
|
|
2464 (label_ref (match_operand 0 "" ""))
|
|
|
2465 (pc)))]
|
|
|
2466 ""
|
|
|
2467 "")
|
|
|
2468
|
|
|
2469 (define_expand "bleu"
|
|
|
2470 [(set (pc)
|
|
|
2471 (if_then_else (leu (cc0) (const_int 0))
|
|
|
2472 (label_ref (match_operand 0 "" ""))
|
|
|
2473 (pc)))]
|
|
|
2474 ""
|
|
|
2475 "")
|
|
|
2476
|
|
|
2477 (define_expand "bgt"
|
|
|
2478 [(set (pc)
|
|
|
2479 (if_then_else (gt (cc0) (const_int 0))
|
|
|
2480 (label_ref (match_operand 0 "" ""))
|
|
|
2481 (pc)))]
|
|
|
2482 ""
|
|
|
2483 "")
|
|
|
2484
|
|
|
2485 (define_expand "bgtu"
|
|
|
2486 [(set (pc)
|
|
|
2487 (if_then_else (gtu (cc0) (const_int 0))
|
|
|
2488 (label_ref (match_operand 0 "" ""))
|
|
|
2489 (pc)))]
|
|
|
2490 ""
|
|
|
2491 "")
|
|
|
2492
|
|
|
2493 ;; Test a single bit in a QI/HI/SImode register.
|
|
|
2494 (define_insn "*sbrx_branch"
|
|
|
2495 [(set (pc)
|
|
|
2496 (if_then_else
|
|
|
2497 (match_operator 0 "eqne_operator"
|
|
|
2498 [(zero_extract:HI
|
|
|
2499 (match_operand:QI 1 "register_operand" "r")
|
|
|
2500 (const_int 1)
|
|
|
2501 (match_operand 2 "const_int_operand" "n"))
|
|
|
2502 (const_int 0)])
|
|
|
2503 (label_ref (match_operand 3 "" ""))
|
|
|
2504 (pc)))]
|
|
|
2505 ""
|
|
|
2506 "* return avr_out_sbxx_branch (insn, operands);"
|
|
|
2507 [(set (attr "length")
|
|
|
2508 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
|
|
|
2509 (le (minus (pc) (match_dup 3)) (const_int 2046)))
|
|
|
2510 (const_int 2)
|
|
|
2511 (if_then_else (eq_attr "mcu_mega" "no")
|
|
|
2512 (const_int 2)
|
|
|
2513 (const_int 4))))
|
|
|
2514 (set_attr "cc" "clobber")])
|
|
|
2515
|
|
|
2516 (define_insn "*sbrx_and_branchhi"
|
|
|
2517 [(set (pc)
|
|
|
2518 (if_then_else
|
|
|
2519 (match_operator 0 "eqne_operator"
|
|
|
2520 [(and:HI
|
|
|
2521 (match_operand:HI 1 "register_operand" "r")
|
|
|
2522 (match_operand:HI 2 "single_one_operand" "n"))
|
|
|
2523 (const_int 0)])
|
|
|
2524 (label_ref (match_operand 3 "" ""))
|
|
|
2525 (pc)))]
|
|
|
2526 ""
|
|
|
2527 "* return avr_out_sbxx_branch (insn, operands);"
|
|
|
2528 [(set (attr "length")
|
|
|
2529 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
|
|
|
2530 (le (minus (pc) (match_dup 3)) (const_int 2046)))
|
|
|
2531 (const_int 2)
|
|
|
2532 (if_then_else (eq_attr "mcu_mega" "no")
|
|
|
2533 (const_int 2)
|
|
|
2534 (const_int 4))))
|
|
|
2535 (set_attr "cc" "clobber")])
|
|
|
2536
|
|
|
2537 (define_insn "*sbrx_and_branchsi"
|
|
|
2538 [(set (pc)
|
|
|
2539 (if_then_else
|
|
|
2540 (match_operator 0 "eqne_operator"
|
|
|
2541 [(and:SI
|
|
|
2542 (match_operand:SI 1 "register_operand" "r")
|
|
|
2543 (match_operand:SI 2 "single_one_operand" "n"))
|
|
|
2544 (const_int 0)])
|
|
|
2545 (label_ref (match_operand 3 "" ""))
|
|
|
2546 (pc)))]
|
|
|
2547 ""
|
|
|
2548 "* return avr_out_sbxx_branch (insn, operands);"
|
|
|
2549 [(set (attr "length")
|
|
|
2550 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
|
|
|
2551 (le (minus (pc) (match_dup 3)) (const_int 2046)))
|
|
|
2552 (const_int 2)
|
|
|
2553 (if_then_else (eq_attr "mcu_mega" "no")
|
|
|
2554 (const_int 2)
|
|
|
2555 (const_int 4))))
|
|
|
2556 (set_attr "cc" "clobber")])
|
|
|
2557
|
|
|
2558 ;; Convert sign tests to bit 7/15/31 tests that match the above insns.
|
|
|
2559 (define_peephole2
|
|
|
2560 [(set (cc0) (match_operand:QI 0 "register_operand" ""))
|
|
|
2561 (set (pc) (if_then_else (ge (cc0) (const_int 0))
|
|
|
2562 (label_ref (match_operand 1 "" ""))
|
|
|
2563 (pc)))]
|
|
|
2564 ""
|
|
|
2565 [(set (pc) (if_then_else (eq (zero_extract:HI (match_dup 0)
|
|
|
2566 (const_int 1)
|
|
|
2567 (const_int 7))
|
|
|
2568 (const_int 0))
|
|
|
2569 (label_ref (match_dup 1))
|
|
|
2570 (pc)))]
|
|
|
2571 "")
|
|
|
2572
|
|
|
2573 (define_peephole2
|
|
|
2574 [(set (cc0) (match_operand:QI 0 "register_operand" ""))
|
|
|
2575 (set (pc) (if_then_else (lt (cc0) (const_int 0))
|
|
|
2576 (label_ref (match_operand 1 "" ""))
|
|
|
2577 (pc)))]
|
|
|
2578 ""
|
|
|
2579 [(set (pc) (if_then_else (ne (zero_extract:HI (match_dup 0)
|
|
|
2580 (const_int 1)
|
|
|
2581 (const_int 7))
|
|
|
2582 (const_int 0))
|
|
|
2583 (label_ref (match_dup 1))
|
|
|
2584 (pc)))]
|
|
|
2585 "")
|
|
|
2586
|
|
|
2587 (define_peephole2
|
|
|
2588 [(set (cc0) (match_operand:HI 0 "register_operand" ""))
|
|
|
2589 (set (pc) (if_then_else (ge (cc0) (const_int 0))
|
|
|
2590 (label_ref (match_operand 1 "" ""))
|
|
|
2591 (pc)))]
|
|
|
2592 ""
|
|
|
2593 [(set (pc) (if_then_else (eq (and:HI (match_dup 0) (const_int -32768))
|
|
|
2594 (const_int 0))
|
|
|
2595 (label_ref (match_dup 1))
|
|
|
2596 (pc)))]
|
|
|
2597 "")
|
|
|
2598
|
|
|
2599 (define_peephole2
|
|
|
2600 [(set (cc0) (match_operand:HI 0 "register_operand" ""))
|
|
|
2601 (set (pc) (if_then_else (lt (cc0) (const_int 0))
|
|
|
2602 (label_ref (match_operand 1 "" ""))
|
|
|
2603 (pc)))]
|
|
|
2604 ""
|
|
|
2605 [(set (pc) (if_then_else (ne (and:HI (match_dup 0) (const_int -32768))
|
|
|
2606 (const_int 0))
|
|
|
2607 (label_ref (match_dup 1))
|
|
|
2608 (pc)))]
|
|
|
2609 "")
|
|
|
2610
|
|
|
2611 (define_peephole2
|
|
|
2612 [(set (cc0) (match_operand:SI 0 "register_operand" ""))
|
|
|
2613 (set (pc) (if_then_else (ge (cc0) (const_int 0))
|
|
|
2614 (label_ref (match_operand 1 "" ""))
|
|
|
2615 (pc)))]
|
|
|
2616 ""
|
|
|
2617 [(set (pc) (if_then_else (eq (and:SI (match_dup 0) (match_dup 2))
|
|
|
2618 (const_int 0))
|
|
|
2619 (label_ref (match_dup 1))
|
|
|
2620 (pc)))]
|
|
|
2621 "operands[2] = GEN_INT (-2147483647 - 1);")
|
|
|
2622
|
|
|
2623 (define_peephole2
|
|
|
2624 [(set (cc0) (match_operand:SI 0 "register_operand" ""))
|
|
|
2625 (set (pc) (if_then_else (lt (cc0) (const_int 0))
|
|
|
2626 (label_ref (match_operand 1 "" ""))
|
|
|
2627 (pc)))]
|
|
|
2628 ""
|
|
|
2629 [(set (pc) (if_then_else (ne (and:SI (match_dup 0) (match_dup 2))
|
|
|
2630 (const_int 0))
|
|
|
2631 (label_ref (match_dup 1))
|
|
|
2632 (pc)))]
|
|
|
2633 "operands[2] = GEN_INT (-2147483647 - 1);")
|
|
|
2634
|
|
|
2635 ;; ************************************************************************
|
|
|
2636 ;; Implementation of conditional jumps here.
|
|
|
2637 ;; Compare with 0 (test) jumps
|
|
|
2638 ;; ************************************************************************
|
|
|
2639
|
|
|
2640 (define_insn "branch"
|
|
|
2641 [(set (pc)
|
|
|
2642 (if_then_else (match_operator 1 "simple_comparison_operator"
|
|
|
2643 [(cc0)
|
|
|
2644 (const_int 0)])
|
|
|
2645 (label_ref (match_operand 0 "" ""))
|
|
|
2646 (pc)))]
|
|
|
2647 ""
|
|
|
2648 "*
|
|
|
2649 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
|
|
|
2650 [(set_attr "type" "branch")
|
|
|
2651 (set_attr "cc" "clobber")])
|
|
|
2652
|
|
|
2653 (define_insn "difficult_branch"
|
|
|
2654 [(set (pc)
|
|
|
2655 (if_then_else (match_operator 1 "difficult_comparison_operator"
|
|
|
2656 [(cc0)
|
|
|
2657 (const_int 0)])
|
|
|
2658 (label_ref (match_operand 0 "" ""))
|
|
|
2659 (pc)))]
|
|
|
2660 ""
|
|
|
2661 "*
|
|
|
2662 return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
|
|
|
2663 [(set_attr "type" "branch1")
|
|
|
2664 (set_attr "cc" "clobber")])
|
|
|
2665
|
|
|
2666 ;; revers branch
|
|
|
2667
|
|
|
2668 (define_insn "rvbranch"
|
|
|
2669 [(set (pc)
|
|
|
2670 (if_then_else (match_operator 1 "simple_comparison_operator"
|
|
|
2671 [(cc0)
|
|
|
2672 (const_int 0)])
|
|
|
2673 (pc)
|
|
|
2674 (label_ref (match_operand 0 "" ""))))]
|
|
|
2675 ""
|
|
|
2676 "*
|
|
|
2677 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
|
|
|
2678 [(set_attr "type" "branch1")
|
|
|
2679 (set_attr "cc" "clobber")])
|
|
|
2680
|
|
|
2681 (define_insn "difficult_rvbranch"
|
|
|
2682 [(set (pc)
|
|
|
2683 (if_then_else (match_operator 1 "difficult_comparison_operator"
|
|
|
2684 [(cc0)
|
|
|
2685 (const_int 0)])
|
|
|
2686 (pc)
|
|
|
2687 (label_ref (match_operand 0 "" ""))))]
|
|
|
2688 ""
|
|
|
2689 "*
|
|
|
2690 return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
|
|
|
2691 [(set_attr "type" "branch")
|
|
|
2692 (set_attr "cc" "clobber")])
|
|
|
2693
|
|
|
2694 ;; **************************************************************************
|
|
|
2695 ;; Unconditional and other jump instructions.
|
|
|
2696
|
|
|
2697 (define_insn "jump"
|
|
|
2698 [(set (pc)
|
|
|
2699 (label_ref (match_operand 0 "" "")))]
|
|
|
2700 ""
|
|
|
2701 "*{
|
|
|
2702 if (AVR_HAVE_JMP_CALL && get_attr_length (insn) != 1)
|
|
|
2703 return AS1 (jmp,%0);
|
|
|
2704 return AS1 (rjmp,%0);
|
|
|
2705 }"
|
|
|
2706 [(set (attr "length")
|
|
|
2707 (if_then_else (match_operand 0 "symbol_ref_operand" "")
|
|
|
2708 (if_then_else (eq_attr "mcu_mega" "no")
|
|
|
2709 (const_int 1)
|
|
|
2710 (const_int 2))
|
|
|
2711 (if_then_else (and (ge (minus (pc) (match_dup 0)) (const_int -2047))
|
|
|
2712 (le (minus (pc) (match_dup 0)) (const_int 2047)))
|
|
|
2713 (const_int 1)
|
|
|
2714 (const_int 2))))
|
|
|
2715 (set_attr "cc" "none")])
|
|
|
2716
|
|
|
2717 ;; call
|
|
|
2718
|
|
|
2719 (define_expand "call"
|
|
|
2720 [(call (match_operand:HI 0 "call_insn_operand" "")
|
|
|
2721 (match_operand:HI 1 "general_operand" ""))]
|
|
|
2722 ;; Operand 1 not used on the AVR.
|
|
|
2723 ""
|
|
|
2724 "")
|
|
|
2725
|
|
|
2726 ;; call value
|
|
|
2727
|
|
|
2728 (define_expand "call_value"
|
|
|
2729 [(set (match_operand 0 "register_operand" "")
|
|
|
2730 (call (match_operand:HI 1 "call_insn_operand" "")
|
|
|
2731 (match_operand:HI 2 "general_operand" "")))]
|
|
|
2732 ;; Operand 2 not used on the AVR.
|
|
|
2733 ""
|
|
|
2734 "")
|
|
|
2735
|
|
|
2736 (define_insn "call_insn"
|
|
|
2737 [(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "!z,*r,s,n"))
|
|
|
2738 (match_operand:HI 1 "general_operand" "X,X,X,X"))]
|
|
|
2739 ;; We don't need in saving Z register because r30,r31 is a call used registers
|
|
|
2740 ;; Operand 1 not used on the AVR.
|
|
|
2741 "(register_operand (operands[0], HImode) || CONSTANT_P (operands[0]))"
|
|
|
2742 "*{
|
|
|
2743 if (which_alternative==0)
|
|
|
2744 return \"%!icall\";
|
|
|
2745 else if (which_alternative==1)
|
|
|
2746 {
|
|
|
2747 if (AVR_HAVE_MOVW)
|
|
|
2748 return (AS2 (movw, r30, %0) CR_TAB
|
|
|
2749 \"%!icall\");
|
|
|
2750 else
|
|
|
2751 return (AS2 (mov, r30, %A0) CR_TAB
|
|
|
2752 AS2 (mov, r31, %B0) CR_TAB
|
|
|
2753 \"%!icall\");
|
|
|
2754 }
|
|
|
2755 else if (which_alternative==2)
|
|
|
2756 return AS1(%~call,%c0);
|
|
|
2757 return (AS2 (ldi,r30,lo8(%0)) CR_TAB
|
|
|
2758 AS2 (ldi,r31,hi8(%0)) CR_TAB
|
|
|
2759 \"%!icall\");
|
|
|
2760 }"
|
|
|
2761 [(set_attr "cc" "clobber,clobber,clobber,clobber")
|
|
|
2762 (set_attr_alternative "length"
|
|
|
2763 [(const_int 1)
|
|
|
2764 (if_then_else (eq_attr "mcu_have_movw" "yes")
|
|
|
2765 (const_int 2)
|
|
|
2766 (const_int 3))
|
|
|
2767 (if_then_else (eq_attr "mcu_mega" "yes")
|
|
|
2768 (const_int 2)
|
|
|
2769 (const_int 1))
|
|
|
2770 (const_int 3)])])
|
|
|
2771
|
|
|
2772 (define_insn "call_value_insn"
|
|
|
2773 [(set (match_operand 0 "register_operand" "=r,r,r,r")
|
|
|
2774 (call (mem:HI (match_operand:HI 1 "nonmemory_operand" "!z,*r,s,n"))
|
|
|
2775 ;; We don't need in saving Z register because r30,r31 is a call used registers
|
|
|
2776 (match_operand:HI 2 "general_operand" "X,X,X,X")))]
|
|
|
2777 ;; Operand 2 not used on the AVR.
|
|
|
2778 "(register_operand (operands[0], VOIDmode) || CONSTANT_P (operands[0]))"
|
|
|
2779 "*{
|
|
|
2780 if (which_alternative==0)
|
|
|
2781 return \"%!icall\";
|
|
|
2782 else if (which_alternative==1)
|
|
|
2783 {
|
|
|
2784 if (AVR_HAVE_MOVW)
|
|
|
2785 return (AS2 (movw, r30, %1) CR_TAB
|
|
|
2786 \"%!icall\");
|
|
|
2787 else
|
|
|
2788 return (AS2 (mov, r30, %A1) CR_TAB
|
|
|
2789 AS2 (mov, r31, %B1) CR_TAB
|
|
|
2790 \"%!icall\");
|
|
|
2791 }
|
|
|
2792 else if (which_alternative==2)
|
|
|
2793 return AS1(%~call,%c1);
|
|
|
2794 return (AS2 (ldi, r30, lo8(%1)) CR_TAB
|
|
|
2795 AS2 (ldi, r31, hi8(%1)) CR_TAB
|
|
|
2796 \"%!icall\");
|
|
|
2797 }"
|
|
|
2798 [(set_attr "cc" "clobber,clobber,clobber,clobber")
|
|
|
2799 (set_attr_alternative "length"
|
|
|
2800 [(const_int 1)
|
|
|
2801 (if_then_else (eq_attr "mcu_have_movw" "yes")
|
|
|
2802 (const_int 2)
|
|
|
2803 (const_int 3))
|
|
|
2804 (if_then_else (eq_attr "mcu_mega" "yes")
|
|
|
2805 (const_int 2)
|
|
|
2806 (const_int 1))
|
|
|
2807 (const_int 3)])])
|
|
|
2808
|
|
|
2809 (define_insn "nop"
|
|
|
2810 [(const_int 0)]
|
|
|
2811 ""
|
|
|
2812 "nop"
|
|
|
2813 [(set_attr "cc" "none")
|
|
|
2814 (set_attr "length" "1")])
|
|
|
2815
|
|
|
2816 ; indirect jump
|
|
|
2817 (define_insn "indirect_jump"
|
|
|
2818 [(set (pc) (match_operand:HI 0 "register_operand" "!z,*r"))]
|
|
|
2819 "!AVR_HAVE_EIJMP_EICALL"
|
|
|
2820 "@
|
|
|
2821 ijmp
|
|
|
2822 push %A0\;push %B0\;ret"
|
|
|
2823 [(set_attr "length" "1,3")
|
|
|
2824 (set_attr "cc" "none,none")])
|
|
|
2825
|
|
|
2826 (define_insn "*indirect_jump_avr6"
|
|
|
2827 [(set (pc) (match_operand:HI 0 "register_operand" "z"))]
|
|
|
2828 "AVR_HAVE_EIJMP_EICALL"
|
|
|
2829 "eijmp"
|
|
|
2830 [(set_attr "length" "1")
|
|
|
2831 (set_attr "cc" "none")])
|
|
|
2832
|
|
|
2833 ;; table jump
|
|
|
2834
|
|
|
2835 ;; Table made from "rjmp" instructions for <=8K devices.
|
|
|
2836 (define_insn "*tablejump_rjmp"
|
|
|
2837 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r")]
|
|
|
2838 UNSPEC_INDEX_JMP))
|
|
|
2839 (use (label_ref (match_operand 1 "" "")))
|
|
|
2840 (clobber (match_dup 0))]
|
|
|
2841 "(!AVR_HAVE_JMP_CALL) && (!AVR_HAVE_EIJMP_EICALL)"
|
|
|
2842 "@
|
|
|
2843 ijmp
|
|
|
2844 push %A0\;push %B0\;ret"
|
|
|
2845 [(set_attr "length" "1,3")
|
|
|
2846 (set_attr "cc" "none,none")])
|
|
|
2847
|
|
|
2848 ;; Not a prologue, but similar idea - move the common piece of code to libgcc.
|
|
|
2849 (define_insn "*tablejump_lib"
|
|
|
2850 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
|
|
|
2851 UNSPEC_INDEX_JMP))
|
|
|
2852 (use (label_ref (match_operand 1 "" "")))
|
|
|
2853 (clobber (match_dup 0))]
|
|
|
2854 "AVR_HAVE_JMP_CALL && TARGET_CALL_PROLOGUES"
|
|
|
2855 "jmp __tablejump2__"
|
|
|
2856 [(set_attr "length" "2")
|
|
|
2857 (set_attr "cc" "clobber")])
|
|
|
2858
|
|
|
2859 (define_insn "*tablejump_enh"
|
|
|
2860 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
|
|
|
2861 UNSPEC_INDEX_JMP))
|
|
|
2862 (use (label_ref (match_operand 1 "" "")))
|
|
|
2863 (clobber (match_dup 0))]
|
|
|
2864 "AVR_HAVE_JMP_CALL && AVR_HAVE_LPMX"
|
|
|
2865 "lsl r30
|
|
|
2866 rol r31
|
|
|
2867 lpm __tmp_reg__,Z+
|
|
|
2868 lpm r31,Z
|
|
|
2869 mov r30,__tmp_reg__
|
|
|
2870 %!ijmp"
|
|
|
2871 [(set_attr "length" "6")
|
|
|
2872 (set_attr "cc" "clobber")])
|
|
|
2873
|
|
|
2874 (define_insn "*tablejump"
|
|
|
2875 [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
|
|
|
2876 UNSPEC_INDEX_JMP))
|
|
|
2877 (use (label_ref (match_operand 1 "" "")))
|
|
|
2878 (clobber (match_dup 0))]
|
|
|
2879 "AVR_HAVE_JMP_CALL && !AVR_HAVE_EIJMP_EICALL"
|
|
|
2880 "lsl r30
|
|
|
2881 rol r31
|
|
|
2882 lpm
|
|
|
2883 inc r30
|
|
|
2884 push r0
|
|
|
2885 lpm
|
|
|
2886 push r0
|
|
|
2887 ret"
|
|
|
2888 [(set_attr "length" "8")
|
|
|
2889 (set_attr "cc" "clobber")])
|
|
|
2890
|
|
|
2891 (define_expand "casesi"
|
|
|
2892 [(set (match_dup 6)
|
|
|
2893 (minus:HI (subreg:HI (match_operand:SI 0 "register_operand" "") 0)
|
|
|
2894 (match_operand:HI 1 "register_operand" "")))
|
|
|
2895 (parallel [(set (cc0)
|
|
|
2896 (compare (match_dup 6)
|
|
|
2897 (match_operand:HI 2 "register_operand" "")))
|
|
|
2898 (clobber (match_scratch:QI 9 ""))])
|
|
|
2899
|
|
|
2900 (set (pc)
|
|
|
2901 (if_then_else (gtu (cc0)
|
|
|
2902 (const_int 0))
|
|
|
2903 (label_ref (match_operand 4 "" ""))
|
|
|
2904 (pc)))
|
|
|
2905
|
|
|
2906 (set (match_dup 6)
|
|
|
2907 (plus:HI (match_dup 6) (label_ref (match_operand:HI 3 "" ""))))
|
|
|
2908
|
|
|
2909 (parallel [(set (pc) (unspec:HI [(match_dup 6)] UNSPEC_INDEX_JMP))
|
|
|
2910 (use (label_ref (match_dup 3)))
|
|
|
2911 (clobber (match_dup 6))])]
|
|
|
2912 ""
|
|
|
2913 "
|
|
|
2914 {
|
|
|
2915 operands[6] = gen_reg_rtx (HImode);
|
|
|
2916 }")
|
|
|
2917
|
|
|
2918
|
|
|
2919 ;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
2920 ;; This instruction sets Z flag
|
|
|
2921
|
|
|
2922 (define_insn "sez"
|
|
|
2923 [(set (cc0) (const_int 0))]
|
|
|
2924 ""
|
|
|
2925 "sez"
|
|
|
2926 [(set_attr "length" "1")
|
|
|
2927 (set_attr "cc" "compare")])
|
|
|
2928
|
|
|
2929 ;; Clear/set/test a single bit in I/O address space.
|
|
|
2930
|
|
|
2931 (define_insn "*cbi"
|
|
|
2932 [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
|
|
|
2933 (and:QI (mem:QI (match_dup 0))
|
|
|
2934 (match_operand:QI 1 "single_zero_operand" "n")))]
|
|
|
2935 "(optimize > 0)"
|
|
|
2936 {
|
|
|
2937 operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
|
|
|
2938 return AS2 (cbi,%0-0x20,%2);
|
|
|
2939 }
|
|
|
2940 [(set_attr "length" "1")
|
|
|
2941 (set_attr "cc" "none")])
|
|
|
2942
|
|
|
2943 (define_insn "*sbi"
|
|
|
2944 [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
|
|
|
2945 (ior:QI (mem:QI (match_dup 0))
|
|
|
2946 (match_operand:QI 1 "single_one_operand" "n")))]
|
|
|
2947 "(optimize > 0)"
|
|
|
2948 {
|
|
|
2949 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
|
|
|
2950 return AS2 (sbi,%0-0x20,%2);
|
|
|
2951 }
|
|
|
2952 [(set_attr "length" "1")
|
|
|
2953 (set_attr "cc" "none")])
|
|
|
2954
|
|
|
2955 ;; Lower half of the I/O space - use sbic/sbis directly.
|
|
|
2956 (define_insn "*sbix_branch"
|
|
|
2957 [(set (pc)
|
|
|
2958 (if_then_else
|
|
|
2959 (match_operator 0 "eqne_operator"
|
|
|
2960 [(zero_extract:HI
|
|
|
2961 (mem:QI (match_operand 1 "low_io_address_operand" "n"))
|
|
|
2962 (const_int 1)
|
|
|
2963 (match_operand 2 "const_int_operand" "n"))
|
|
|
2964 (const_int 0)])
|
|
|
2965 (label_ref (match_operand 3 "" ""))
|
|
|
2966 (pc)))]
|
|
|
2967 "(optimize > 0)"
|
|
|
2968 "* return avr_out_sbxx_branch (insn, operands);"
|
|
|
2969 [(set (attr "length")
|
|
|
2970 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
|
|
|
2971 (le (minus (pc) (match_dup 3)) (const_int 2046)))
|
|
|
2972 (const_int 2)
|
|
|
2973 (if_then_else (eq_attr "mcu_mega" "no")
|
|
|
2974 (const_int 2)
|
|
|
2975 (const_int 4))))
|
|
|
2976 (set_attr "cc" "clobber")])
|
|
|
2977
|
|
|
2978 ;; Tests of bit 7 are pessimized to sign tests, so we need this too...
|
|
|
2979 (define_insn "*sbix_branch_bit7"
|
|
|
2980 [(set (pc)
|
|
|
2981 (if_then_else
|
|
|
2982 (match_operator 0 "gelt_operator"
|
|
|
2983 [(mem:QI (match_operand 1 "low_io_address_operand" "n"))
|
|
|
2984 (const_int 0)])
|
|
|
2985 (label_ref (match_operand 2 "" ""))
|
|
|
2986 (pc)))]
|
|
|
2987 "(optimize > 0)"
|
|
|
2988 {
|
|
|
2989 operands[3] = operands[2];
|
|
|
2990 operands[2] = GEN_INT (7);
|
|
|
2991 return avr_out_sbxx_branch (insn, operands);
|
|
|
2992 }
|
|
|
2993 [(set (attr "length")
|
|
|
2994 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
|
|
|
2995 (le (minus (pc) (match_dup 2)) (const_int 2046)))
|
|
|
2996 (const_int 2)
|
|
|
2997 (if_then_else (eq_attr "mcu_mega" "no")
|
|
|
2998 (const_int 2)
|
|
|
2999 (const_int 4))))
|
|
|
3000 (set_attr "cc" "clobber")])
|
|
|
3001
|
|
|
3002 ;; Upper half of the I/O space - read port to __tmp_reg__ and use sbrc/sbrs.
|
|
|
3003 (define_insn "*sbix_branch_tmp"
|
|
|
3004 [(set (pc)
|
|
|
3005 (if_then_else
|
|
|
3006 (match_operator 0 "eqne_operator"
|
|
|
3007 [(zero_extract:HI
|
|
|
3008 (mem:QI (match_operand 1 "high_io_address_operand" "n"))
|
|
|
3009 (const_int 1)
|
|
|
3010 (match_operand 2 "const_int_operand" "n"))
|
|
|
3011 (const_int 0)])
|
|
|
3012 (label_ref (match_operand 3 "" ""))
|
|
|
3013 (pc)))]
|
|
|
3014 "(optimize > 0)"
|
|
|
3015 "* return avr_out_sbxx_branch (insn, operands);"
|
|
|
3016 [(set (attr "length")
|
|
|
3017 (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
|
|
|
3018 (le (minus (pc) (match_dup 3)) (const_int 2045)))
|
|
|
3019 (const_int 3)
|
|
|
3020 (if_then_else (eq_attr "mcu_mega" "no")
|
|
|
3021 (const_int 3)
|
|
|
3022 (const_int 5))))
|
|
|
3023 (set_attr "cc" "clobber")])
|
|
|
3024
|
|
|
3025 (define_insn "*sbix_branch_tmp_bit7"
|
|
|
3026 [(set (pc)
|
|
|
3027 (if_then_else
|
|
|
3028 (match_operator 0 "gelt_operator"
|
|
|
3029 [(mem:QI (match_operand 1 "high_io_address_operand" "n"))
|
|
|
3030 (const_int 0)])
|
|
|
3031 (label_ref (match_operand 2 "" ""))
|
|
|
3032 (pc)))]
|
|
|
3033 "(optimize > 0)"
|
|
|
3034 {
|
|
|
3035 operands[3] = operands[2];
|
|
|
3036 operands[2] = GEN_INT (7);
|
|
|
3037 return avr_out_sbxx_branch (insn, operands);
|
|
|
3038 }
|
|
|
3039 [(set (attr "length")
|
|
|
3040 (if_then_else (and (ge (minus (pc) (match_dup 2)) (const_int -2046))
|
|
|
3041 (le (minus (pc) (match_dup 2)) (const_int 2045)))
|
|
|
3042 (const_int 3)
|
|
|
3043 (if_then_else (eq_attr "mcu_mega" "no")
|
|
|
3044 (const_int 3)
|
|
|
3045 (const_int 5))))
|
|
|
3046 (set_attr "cc" "clobber")])
|
|
|
3047
|
|
|
3048 ;; ************************* Peepholes ********************************
|
|
|
3049
|
|
|
3050 (define_peephole
|
|
|
3051 [(set (match_operand:SI 0 "d_register_operand" "")
|
|
|
3052 (plus:SI (match_dup 0)
|
|
|
3053 (const_int -1)))
|
|
|
3054 (parallel
|
|
|
3055 [(set (cc0)
|
|
|
3056 (compare (match_dup 0)
|
|
|
3057 (const_int -1)))
|
|
|
3058 (clobber (match_operand:QI 1 "d_register_operand" ""))])
|
|
|
3059 (set (pc)
|
|
|
3060 (if_then_else (ne (cc0) (const_int 0))
|
|
|
3061 (label_ref (match_operand 2 "" ""))
|
|
|
3062 (pc)))]
|
|
|
3063 ""
|
|
|
3064 "*
|
|
|
3065 {
|
|
|
3066 CC_STATUS_INIT;
|
|
|
3067 if (test_hard_reg_class (ADDW_REGS, operands[0]))
|
|
|
3068 output_asm_insn (AS2 (sbiw,%0,1) CR_TAB
|
|
|
3069 AS2 (sbc,%C0,__zero_reg__) CR_TAB
|
|
|
3070 AS2 (sbc,%D0,__zero_reg__) \"\\n\", operands);
|
|
|
3071 else
|
|
|
3072 output_asm_insn (AS2 (subi,%A0,1) CR_TAB
|
|
|
3073 AS2 (sbc,%B0,__zero_reg__) CR_TAB
|
|
|
3074 AS2 (sbc,%C0,__zero_reg__) CR_TAB
|
|
|
3075 AS2 (sbc,%D0,__zero_reg__) \"\\n\", operands);
|
|
|
3076 switch (avr_jump_mode (operands[2],insn))
|
|
|
3077 {
|
|
|
3078 case 1:
|
|
|
3079 return AS1 (brcc,%2);
|
|
|
3080 case 2:
|
|
|
3081 return (AS1 (brcs,.+2) CR_TAB
|
|
|
3082 AS1 (rjmp,%2));
|
|
|
3083 }
|
|
|
3084 return (AS1 (brcs,.+4) CR_TAB
|
|
|
3085 AS1 (jmp,%2));
|
|
|
3086 }")
|
|
|
3087
|
|
|
3088 (define_peephole
|
|
|
3089 [(set (match_operand:HI 0 "d_register_operand" "")
|
|
|
3090 (plus:HI (match_dup 0)
|
|
|
3091 (const_int -1)))
|
|
|
3092 (parallel
|
|
|
3093 [(set (cc0)
|
|
|
3094 (compare (match_dup 0)
|
|
|
3095 (const_int 65535)))
|
|
|
3096 (clobber (match_operand:QI 1 "d_register_operand" ""))])
|
|
|
3097 (set (pc)
|
|
|
3098 (if_then_else (ne (cc0) (const_int 0))
|
|
|
3099 (label_ref (match_operand 2 "" ""))
|
|
|
3100 (pc)))]
|
|
|
3101 ""
|
|
|
3102 "*
|
|
|
3103 {
|
|
|
3104 CC_STATUS_INIT;
|
|
|
3105 if (test_hard_reg_class (ADDW_REGS, operands[0]))
|
|
|
3106 output_asm_insn (AS2 (sbiw,%0,1), operands);
|
|
|
3107 else
|
|
|
3108 output_asm_insn (AS2 (subi,%A0,1) CR_TAB
|
|
|
3109 AS2 (sbc,%B0,__zero_reg__) \"\\n\", operands);
|
|
|
3110 switch (avr_jump_mode (operands[2],insn))
|
|
|
3111 {
|
|
|
3112 case 1:
|
|
|
3113 return AS1 (brcc,%2);
|
|
|
3114 case 2:
|
|
|
3115 return (AS1 (brcs,.+2) CR_TAB
|
|
|
3116 AS1 (rjmp,%2));
|
|
|
3117 }
|
|
|
3118 return (AS1 (brcs,.+4) CR_TAB
|
|
|
3119 AS1 (jmp,%2));
|
|
|
3120 }")
|
|
|
3121
|
|
|
3122 (define_peephole
|
|
|
3123 [(set (match_operand:QI 0 "d_register_operand" "")
|
|
|
3124 (plus:QI (match_dup 0)
|
|
|
3125 (const_int -1)))
|
|
|
3126 (set (cc0)
|
|
|
3127 (compare (match_dup 0)
|
|
|
3128 (const_int -1)))
|
|
|
3129 (set (pc)
|
|
|
3130 (if_then_else (ne (cc0) (const_int 0))
|
|
|
3131 (label_ref (match_operand 1 "" ""))
|
|
|
3132 (pc)))]
|
|
|
3133 ""
|
|
|
3134 "*
|
|
|
3135 {
|
|
|
3136 CC_STATUS_INIT;
|
|
|
3137 cc_status.value1 = operands[0];
|
|
|
3138 cc_status.flags |= CC_OVERFLOW_UNUSABLE;
|
|
|
3139 output_asm_insn (AS2 (subi,%A0,1), operands);
|
|
|
3140 switch (avr_jump_mode (operands[1],insn))
|
|
|
3141 {
|
|
|
3142 case 1:
|
|
|
3143 return AS1 (brcc,%1);
|
|
|
3144 case 2:
|
|
|
3145 return (AS1 (brcs,.+2) CR_TAB
|
|
|
3146 AS1 (rjmp,%1));
|
|
|
3147 }
|
|
|
3148 return (AS1 (brcs,.+4) CR_TAB
|
|
|
3149 AS1 (jmp,%1));
|
|
|
3150 }")
|
|
|
3151
|
|
|
3152 (define_peephole
|
|
|
3153 [(set (cc0) (match_operand:QI 0 "register_operand" ""))
|
|
|
3154 (set (pc)
|
|
|
3155 (if_then_else (eq (cc0) (const_int 0))
|
|
|
3156 (label_ref (match_operand 1 "" ""))
|
|
|
3157 (pc)))]
|
|
|
3158 "jump_over_one_insn_p (insn, operands[1])"
|
|
|
3159 "cpse %0,__zero_reg__")
|
|
|
3160
|
|
|
3161 (define_peephole
|
|
|
3162 [(set (cc0)
|
|
|
3163 (compare (match_operand:QI 0 "register_operand" "")
|
|
|
3164 (match_operand:QI 1 "register_operand" "")))
|
|
|
3165 (set (pc)
|
|
|
3166 (if_then_else (eq (cc0) (const_int 0))
|
|
|
3167 (label_ref (match_operand 2 "" ""))
|
|
|
3168 (pc)))]
|
|
|
3169 "jump_over_one_insn_p (insn, operands[2])"
|
|
|
3170 "cpse %0,%1")
|
|
|
3171
|
|
|
3172 ;;pppppppppppppppppppppppppppppppppppppppppppppppppppp
|
|
|
3173 ;;prologue/epilogue support instructions
|
|
|
3174
|
|
|
3175 (define_insn "popqi"
|
|
|
3176 [(set (match_operand:QI 0 "register_operand" "=r")
|
|
|
3177 (mem:QI (post_inc (reg:HI REG_SP))))]
|
|
|
3178 ""
|
|
|
3179 "pop %0"
|
|
|
3180 [(set_attr "cc" "none")
|
|
|
3181 (set_attr "length" "1")])
|
|
|
3182
|
|
|
3183 (define_insn "pophi"
|
|
|
3184 [(set (match_operand:HI 0 "register_operand" "=r")
|
|
|
3185 (mem:HI (post_inc (reg:HI REG_SP))))]
|
|
|
3186 ""
|
|
|
3187 "pop %A0\;pop %B0"
|
|
|
3188 [(set_attr "cc" "none")
|
|
|
3189 (set_attr "length" "2")])
|
|
|
3190
|
|
|
3191 ;; Enable Interrupts
|
|
|
3192 (define_insn "enable_interrupt"
|
|
|
3193 [(unspec [(const_int 0)] UNSPEC_SEI)]
|
|
|
3194 ""
|
|
|
3195 "sei"
|
|
|
3196 [(set_attr "length" "1")
|
|
|
3197 (set_attr "cc" "none")
|
|
|
3198 ])
|
|
|
3199
|
|
|
3200 ;; Disable Interrupts
|
|
|
3201 (define_insn "disable_interrupt"
|
|
|
3202 [(unspec [(const_int 0)] UNSPEC_CLI)]
|
|
|
3203 ""
|
|
|
3204 "cli"
|
|
|
3205 [(set_attr "length" "1")
|
|
|
3206 (set_attr "cc" "none")
|
|
|
3207 ])
|
|
|
3208
|
|
|
3209 ;; Library prologue saves
|
|
|
3210 (define_insn "call_prologue_saves"
|
|
|
3211 [(unspec_volatile:HI [(const_int 0)] UNSPECV_PROLOGUE_SAVES)
|
|
|
3212 (match_operand:HI 0 "immediate_operand" "")
|
|
|
3213 (set (reg:HI REG_SP) (minus:HI
|
|
|
3214 (reg:HI REG_SP)
|
|
|
3215 (match_operand:HI 1 "immediate_operand" "")))
|
|
|
3216 (use (reg:HI REG_X))
|
|
|
3217 (clobber (reg:HI REG_Z))]
|
|
|
3218 ""
|
|
|
3219 "ldi r30,lo8(gs(1f))
|
|
|
3220 ldi r31,hi8(gs(1f))
|
|
|
3221 %~jmp __prologue_saves__+((18 - %0) * 2)
|
|
|
3222 1:"
|
|
|
3223 [(set_attr_alternative "length"
|
|
|
3224 [(if_then_else (eq_attr "mcu_mega" "yes")
|
|
|
3225 (const_int 6)
|
|
|
3226 (const_int 5))])
|
|
|
3227 (set_attr "cc" "clobber")
|
|
|
3228 ])
|
|
|
3229
|
|
|
3230 ; epilogue restores using library
|
|
|
3231 (define_insn "epilogue_restores"
|
|
|
3232 [(unspec_volatile:QI [(const_int 0)] UNSPECV_EPILOGUE_RESTORES)
|
|
|
3233 (set (reg:HI REG_Y ) (plus:HI
|
|
|
3234 (reg:HI REG_Y)
|
|
|
3235 (match_operand:HI 0 "immediate_operand" "")))
|
|
|
3236 (set (reg:HI REG_SP) (reg:HI REG_Y))
|
|
|
3237 (clobber (reg:QI REG_Z))]
|
|
|
3238 ""
|
|
|
3239 "ldi r30, lo8(%0)
|
|
|
3240 %~jmp __epilogue_restores__ + ((18 - %0) * 2)"
|
|
|
3241 [(set_attr_alternative "length"
|
|
|
3242 [(if_then_else (eq_attr "mcu_mega" "yes")
|
|
|
3243 (const_int 3)
|
|
|
3244 (const_int 2))])
|
|
|
3245 (set_attr "cc" "clobber")
|
|
|
3246 ])
|
|
|
3247
|
|
|
3248 ; return
|
|
|
3249 (define_insn "return"
|
|
|
3250 [(return)]
|
|
|
3251 "reload_completed && avr_simple_epilogue ()"
|
|
|
3252 "ret"
|
|
|
3253 [(set_attr "cc" "none")
|
|
|
3254 (set_attr "length" "1")])
|
|
|
3255
|
|
|
3256 (define_insn "return_from_epilogue"
|
|
|
3257 [(return)]
|
|
|
3258 "(reload_completed
|
|
|
3259 && cfun->machine
|
|
|
3260 && !(cfun->machine->is_interrupt || cfun->machine->is_signal)
|
|
|
3261 && !cfun->machine->is_naked)"
|
|
|
3262 "ret"
|
|
|
3263 [(set_attr "cc" "none")
|
|
|
3264 (set_attr "length" "1")])
|
|
|
3265
|
|
|
3266 (define_insn "return_from_interrupt_epilogue"
|
|
|
3267 [(return)]
|
|
|
3268 "(reload_completed
|
|
|
3269 && cfun->machine
|
|
|
3270 && (cfun->machine->is_interrupt || cfun->machine->is_signal)
|
|
|
3271 && !cfun->machine->is_naked)"
|
|
|
3272 "reti"
|
|
|
3273 [(set_attr "cc" "none")
|
|
|
3274 (set_attr "length" "1")])
|
|
|
3275
|
|
|
3276 (define_insn "return_from_naked_epilogue"
|
|
|
3277 [(return)]
|
|
|
3278 "(reload_completed
|
|
|
3279 && cfun->machine
|
|
|
3280 && cfun->machine->is_naked)"
|
|
|
3281 ""
|
|
|
3282 [(set_attr "cc" "none")
|
|
|
3283 (set_attr "length" "0")])
|
|
|
3284
|
|
|
3285 (define_expand "prologue"
|
|
|
3286 [(const_int 0)]
|
|
|
3287 ""
|
|
|
3288 "
|
|
|
3289 {
|
|
|
3290 expand_prologue ();
|
|
|
3291 DONE;
|
|
|
3292 }")
|
|
|
3293
|
|
|
3294 (define_expand "epilogue"
|
|
|
3295 [(const_int 0)]
|
|
|
3296 ""
|
|
|
3297 "
|
|
|
3298 {
|
|
|
3299 expand_epilogue ();
|
|
|
3300 DONE;
|
|
|
3301 }")
|
