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1 /* Definitions of target machine for GNU compiler.
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2 Vitesse IQ2000 processors
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3 Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008
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4 Free Software Foundation, Inc.
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5
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6 This file is part of GCC.
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7
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8 GCC is free software; you can redistribute it and/or modify it
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9 under the terms of the GNU General Public License as published
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10 by the Free Software Foundation; either version 3, or (at your
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11 option) any later version.
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12
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13 GCC is distributed in the hope that it will be useful, but WITHOUT
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14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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16 License for more details.
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17
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18 You should have received a copy of the GNU General Public License
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19 along with GCC; see the file COPYING3. If not see
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20 <http://www.gnu.org/licenses/>. */
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21
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22 /* Driver configuration. */
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23
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24 #undef SWITCH_TAKES_ARG
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25 #define SWITCH_TAKES_ARG(CHAR) \
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26 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
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27
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28 /* The svr4.h LIB_SPEC with -leval and --*group tacked on */
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29 #undef LIB_SPEC
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30 #define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}"
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31
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32 #undef STARTFILE_SPEC
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33 #undef ENDFILE_SPEC
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34
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35
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36 /* Run-time target specifications. */
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37
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38 #define TARGET_CPU_CPP_BUILTINS() \
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39 do \
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40 { \
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41 builtin_define ("__iq2000__"); \
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42 builtin_assert ("cpu=iq2000"); \
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43 builtin_assert ("machine=iq2000"); \
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44 } \
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45 while (0)
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46
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47 /* Macros used in the machine description to test the flags. */
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48
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49 #define TARGET_STATS 0
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50
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51 #define TARGET_DEBUG_MODE 0
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52 #define TARGET_DEBUG_A_MODE 0
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53 #define TARGET_DEBUG_B_MODE 0
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54 #define TARGET_DEBUG_C_MODE 0
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55 #define TARGET_DEBUG_D_MODE 0
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56
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57 #ifndef IQ2000_ISA_DEFAULT
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58 #define IQ2000_ISA_DEFAULT 1
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59 #endif
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60
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61 #define IQ2000_VERSION "[1.0]"
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62
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63 #ifndef MACHINE_TYPE
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64 #define MACHINE_TYPE "IQ2000"
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65 #endif
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66
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67 #ifndef TARGET_VERSION_INTERNAL
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68 #define TARGET_VERSION_INTERNAL(STREAM) \
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69 fprintf (STREAM, " %s %s", IQ2000_VERSION, MACHINE_TYPE)
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70 #endif
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71
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72 #ifndef TARGET_VERSION
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73 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
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74 #endif
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75
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76 #define OVERRIDE_OPTIONS override_options ()
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77
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78 #define CAN_DEBUG_WITHOUT_FP
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79
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80 /* Storage Layout. */
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81
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82 #define BITS_BIG_ENDIAN 0
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83 #define BYTES_BIG_ENDIAN 1
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84 #define WORDS_BIG_ENDIAN 1
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85 #define LIBGCC2_WORDS_BIG_ENDIAN 1
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86 #define BITS_PER_WORD 32
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87 #define MAX_BITS_PER_WORD 64
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88 #define UNITS_PER_WORD 4
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89 #define MIN_UNITS_PER_WORD 4
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90 #define POINTER_SIZE 32
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91
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92 /* Define this macro if it is advisable to hold scalars in registers
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93 in a wider mode than that declared by the program. In such cases,
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94 the value is constrained to be within the bounds of the declared
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95 type, but kept valid in the wider mode. The signedness of the
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96 extension may differ from that of the type.
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97
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98 We promote any value smaller than SImode up to SImode. */
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99
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100 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
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101 if (GET_MODE_CLASS (MODE) == MODE_INT \
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102 && GET_MODE_SIZE (MODE) < 4) \
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103 (MODE) = SImode;
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104
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105 #define PARM_BOUNDARY 32
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106
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107 #define STACK_BOUNDARY 64
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108
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109 #define FUNCTION_BOUNDARY 32
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110
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111 #define BIGGEST_ALIGNMENT 64
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112
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113 #undef DATA_ALIGNMENT
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114 #define DATA_ALIGNMENT(TYPE, ALIGN) \
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115 ((((ALIGN) < BITS_PER_WORD) \
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116 && (TREE_CODE (TYPE) == ARRAY_TYPE \
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117 || TREE_CODE (TYPE) == UNION_TYPE \
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118 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
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119
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120 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
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121 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
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122 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
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123
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124 #define EMPTY_FIELD_BOUNDARY 32
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125
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126 #define STRUCTURE_SIZE_BOUNDARY 8
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127
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128 #define STRICT_ALIGNMENT 1
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129
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130 #define PCC_BITFIELD_TYPE_MATTERS 1
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131
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132
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133 /* Layout of Source Language Data Types. */
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134
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135 #define INT_TYPE_SIZE 32
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136 #define SHORT_TYPE_SIZE 16
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137 #define LONG_TYPE_SIZE 32
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138 #define LONG_LONG_TYPE_SIZE 64
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139 #define CHAR_TYPE_SIZE BITS_PER_UNIT
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140 #define FLOAT_TYPE_SIZE 32
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141 #define DOUBLE_TYPE_SIZE 64
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142 #define LONG_DOUBLE_TYPE_SIZE 64
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143 #define DEFAULT_SIGNED_CHAR 1
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144
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145
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146 /* Register Basics. */
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147
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148 /* On the IQ2000, we have 32 integer registers. */
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149 #define FIRST_PSEUDO_REGISTER 33
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150
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151 #define FIXED_REGISTERS \
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152 { \
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153 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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154 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1 \
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155 }
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156
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157 #define CALL_USED_REGISTERS \
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158 { \
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159 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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160 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1 \
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161 }
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162
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163
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164 /* Order of allocation of registers. */
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165
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166 #define REG_ALLOC_ORDER \
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167 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
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168 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 \
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169 }
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170
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171
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172 /* How Values Fit in Registers. */
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173
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174 #define HARD_REGNO_NREGS(REGNO, MODE) \
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175 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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176
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177 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
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178 ((REGNO_REG_CLASS (REGNO) == GR_REGS) \
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179 ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4 \
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180 : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
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181
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182 #define MODES_TIEABLE_P(MODE1, MODE2) \
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183 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
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184 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
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185 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
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186 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
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187
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188 #define AVOID_CCMODE_COPIES
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189
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190
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191 /* Register Classes. */
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192
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193 enum reg_class
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194 {
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195 NO_REGS, /* No registers in set. */
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196 GR_REGS, /* Integer registers. */
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197 ALL_REGS, /* All registers. */
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198 LIM_REG_CLASSES /* Max value + 1. */
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199 };
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200
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201 #define GENERAL_REGS GR_REGS
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202
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203 #define N_REG_CLASSES (int) LIM_REG_CLASSES
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204
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205 #define IRA_COVER_CLASSES \
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206 { \
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207 GR_REGS, LIM_REG_CLASSES \
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208 }
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209
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210 #define REG_CLASS_NAMES \
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211 { \
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212 "NO_REGS", \
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213 "GR_REGS", \
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214 "ALL_REGS" \
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215 }
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216
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217 #define REG_CLASS_CONTENTS \
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218 { \
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219 { 0x00000000, 0x00000000 }, /* No registers, */ \
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220 { 0xffffffff, 0x00000000 }, /* Integer registers. */ \
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221 { 0xffffffff, 0x00000001 } /* All registers. */ \
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222 }
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223
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224 #define REGNO_REG_CLASS(REGNO) \
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225 ((REGNO) <= GP_REG_LAST + 1 ? GR_REGS : NO_REGS)
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226
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227 #define BASE_REG_CLASS (GR_REGS)
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228
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229 #define INDEX_REG_CLASS NO_REGS
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230
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231 #define REG_CLASS_FROM_LETTER(C) \
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232 ((C) == 'd' ? GR_REGS : \
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233 (C) == 'b' ? ALL_REGS : \
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234 (C) == 'y' ? GR_REGS : \
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235 NO_REGS)
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236
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237 #define REGNO_OK_FOR_INDEX_P(regno) 0
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238
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239 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
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240 ((CLASS) != ALL_REGS \
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241 ? (CLASS) \
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242 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
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243 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
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244 ? (GR_REGS) \
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245 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
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246 || GET_MODE (X) == VOIDmode) \
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247 ? (GR_REGS) \
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248 : (CLASS))))
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249
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250 #define SMALL_REGISTER_CLASSES 0
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251
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252 #define CLASS_MAX_NREGS(CLASS, MODE) \
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253 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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254
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255 /* For IQ2000:
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256
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257 `I' is used for the range of constants an arithmetic insn can
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258 actually contain (16-bits signed integers).
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259
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260 `J' is used for the range which is just zero (i.e., $r0).
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261
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262 `K' is used for the range of constants a logical insn can actually
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263 contain (16-bit zero-extended integers).
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264
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265 `L' is used for the range of constants that be loaded with lui
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266 (i.e., the bottom 16 bits are zero).
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267
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268 `M' is used for the range of constants that take two words to load
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269 (i.e., not matched by `I', `K', and `L').
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270
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271 `N' is used for constants 0xffffnnnn or 0xnnnnffff
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272
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273 `O' is a 5-bit zero-extended integer. */
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274
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275 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
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276 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
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277 : (C) == 'J' ? ((VALUE) == 0) \
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278 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
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279 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
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280 && (((VALUE) & ~2147483647) == 0 \
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281 || ((VALUE) & ~2147483647) == ~2147483647)) \
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282 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
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283 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
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284 && (((VALUE) & 0x0000ffff) != 0 \
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285 || (((VALUE) & ~2147483647) != 0 \
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286 && ((VALUE) & ~2147483647) != ~2147483647))) \
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287 : (C) == 'N' ? ((((VALUE) & 0xffff) == 0xffff) \
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288 || (((VALUE) & 0xffff0000) == 0xffff0000)) \
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289 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x20) < 0x40) \
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290 : 0)
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291
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292 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
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293 ((C) == 'G' \
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294 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
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295
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296 /* `R' is for memory references which take 1 word for the instruction. */
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297
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298 #define EXTRA_CONSTRAINT(OP,CODE) \
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299 (((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
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300 : FALSE)
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301
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302
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303 /* Basic Stack Layout. */
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304
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305 #define STACK_GROWS_DOWNWARD
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306
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307 #define FRAME_GROWS_DOWNWARD 0
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308
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309 #define STARTING_FRAME_OFFSET \
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310 (crtl->outgoing_args_size)
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311
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312 /* Use the default value zero. */
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313 /* #define STACK_POINTER_OFFSET 0 */
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314
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315 #define FIRST_PARM_OFFSET(FNDECL) 0
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316
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317 /* The return address for the current frame is in r31 if this is a leaf
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318 function. Otherwise, it is on the stack. It is at a variable offset
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319 from sp/fp/ap, so we define a fake hard register rap which is a
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320 pointer to the return address on the stack. This always gets eliminated
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321 during reload to be either the frame pointer or the stack pointer plus
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322 an offset. */
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323
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324 #define RETURN_ADDR_RTX(count, frame) \
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325 (((count) == 0) \
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326 ? (leaf_function_p () \
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327 ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \
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328 : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \
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329 RETURN_ADDRESS_POINTER_REGNUM))) \
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330 : (rtx) 0)
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331
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332 /* Before the prologue, RA lives in r31. */
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333 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
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334
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335
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336 /* Register That Address the Stack Frame. */
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337
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338 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
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339 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
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340 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 27)
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341 #define ARG_POINTER_REGNUM GP_REG_FIRST
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342 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
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343 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
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344
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345
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346 /* Eliminating the Frame Pointer and the Arg Pointer. */
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347
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348 #define FRAME_POINTER_REQUIRED 0
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349
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350 #define ELIMINABLE_REGS \
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351 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
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352 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
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353 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
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354 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
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355 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
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356 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
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357 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
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358
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359
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360 /* We can always eliminate to the frame pointer. We can eliminate to the
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361 stack pointer unless a frame pointer is needed. */
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362
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363 #define CAN_ELIMINATE(FROM, TO) \
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364 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
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365 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
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366 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
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367 && ((TO) == HARD_FRAME_POINTER_REGNUM \
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368 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed))))
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369
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370 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
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371 (OFFSET) = iq2000_initial_elimination_offset ((FROM), (TO))
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372
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373 /* Passing Function Arguments on the Stack. */
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374
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375 /* #define PUSH_ROUNDING(BYTES) 0 */
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376
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377 #define ACCUMULATE_OUTGOING_ARGS 1
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378
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379 #define REG_PARM_STACK_SPACE(FNDECL) 0
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380
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381 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
|
|
|
382
|
|
|
383 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
|
|
|
384
|
|
|
385
|
|
|
386 /* Function Arguments in Registers. */
|
|
|
387
|
|
|
388 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
|
|
|
389 function_arg (& CUM, MODE, TYPE, NAMED)
|
|
|
390
|
|
|
391 #define MAX_ARGS_IN_REGISTERS 8
|
|
|
392
|
|
|
393 typedef struct iq2000_args
|
|
|
394 {
|
|
|
395 int gp_reg_found; /* Whether a gp register was found yet. */
|
|
|
396 unsigned int arg_number; /* Argument number. */
|
|
|
397 unsigned int arg_words; /* # total words the arguments take. */
|
|
|
398 unsigned int fp_arg_words; /* # words for FP args (IQ2000_EABI only). */
|
|
|
399 int last_arg_fp; /* Nonzero if last arg was FP (EABI only). */
|
|
|
400 int fp_code; /* Mode of FP arguments. */
|
|
|
401 unsigned int num_adjusts; /* Number of adjustments made. */
|
|
|
402 /* Adjustments made to args pass in regs. */
|
|
|
403 struct rtx_def * adjust[MAX_ARGS_IN_REGISTERS * 2];
|
|
|
404 } CUMULATIVE_ARGS;
|
|
|
405
|
|
|
406 /* Initialize a variable CUM of type CUMULATIVE_ARGS
|
|
|
407 for a call to a function whose data type is FNTYPE.
|
|
|
408 For a library call, FNTYPE is 0. */
|
|
|
409 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
|
|
|
410 init_cumulative_args (& CUM, FNTYPE, LIBNAME) \
|
|
|
411
|
|
|
412 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
|
|
|
413 function_arg_advance (& CUM, MODE, TYPE, NAMED)
|
|
|
414
|
|
|
415 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
|
|
|
416 (! BYTES_BIG_ENDIAN \
|
|
|
417 ? upward \
|
|
|
418 : (((MODE) == BLKmode \
|
|
|
419 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
|
|
|
420 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
|
|
|
421 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
|
|
|
422 && (GET_MODE_CLASS (MODE) == MODE_INT))) \
|
|
|
423 ? downward : upward))
|
|
|
424
|
|
|
425 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
|
|
|
426 (((TYPE) != 0) \
|
|
|
427 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
|
|
|
428 ? PARM_BOUNDARY \
|
|
|
429 : TYPE_ALIGN(TYPE)) \
|
|
|
430 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
|
|
|
431 ? PARM_BOUNDARY \
|
|
|
432 : GET_MODE_ALIGNMENT(MODE)))
|
|
|
433
|
|
|
434 #define FUNCTION_ARG_REGNO_P(N) \
|
|
|
435 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
|
|
|
436
|
|
|
437
|
|
|
438 /* How Scalar Function Values are Returned. */
|
|
|
439
|
|
|
440 #define FUNCTION_VALUE(VALTYPE, FUNC) iq2000_function_value (VALTYPE, FUNC)
|
|
|
441
|
|
|
442 #define LIBCALL_VALUE(MODE) \
|
|
|
443 gen_rtx_REG (((GET_MODE_CLASS (MODE) != MODE_INT \
|
|
|
444 || GET_MODE_SIZE (MODE) >= 4) \
|
|
|
445 ? (MODE) \
|
|
|
446 : SImode), \
|
|
|
447 GP_RETURN)
|
|
|
448
|
|
|
449 /* On the IQ2000, R2 and R3 are the only register thus used. */
|
|
|
450
|
|
|
451 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN)
|
|
|
452
|
|
|
453
|
|
|
454 /* How Large Values are Returned. */
|
|
|
455
|
|
|
456 #define DEFAULT_PCC_STRUCT_RETURN 0
|
|
|
457
|
|
|
458 /* Function Entry and Exit. */
|
|
|
459
|
|
|
460 #define EXIT_IGNORE_STACK 1
|
|
|
461
|
|
|
462
|
|
|
463 /* Generating Code for Profiling. */
|
|
|
464
|
|
|
465 #define FUNCTION_PROFILER(FILE, LABELNO) \
|
|
|
466 { \
|
|
|
467 fprintf (FILE, "\t.set\tnoreorder\n"); \
|
|
|
468 fprintf (FILE, "\t.set\tnoat\n"); \
|
|
|
469 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
|
|
|
470 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
|
|
|
471 fprintf (FILE, "\tjal\t_mcount\n"); \
|
|
|
472 fprintf (FILE, \
|
|
|
473 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
|
|
|
474 "subu", \
|
|
|
475 reg_names[STACK_POINTER_REGNUM], \
|
|
|
476 reg_names[STACK_POINTER_REGNUM], \
|
|
|
477 Pmode == DImode ? 16 : 8); \
|
|
|
478 fprintf (FILE, "\t.set\treorder\n"); \
|
|
|
479 fprintf (FILE, "\t.set\tat\n"); \
|
|
|
480 }
|
|
|
481
|
|
|
482
|
|
|
483 /* Trampolines for Nested Functions. */
|
|
|
484
|
|
|
485 /* A C statement to output, on the stream FILE, assembler code for a
|
|
|
486 block of data that contains the constant parts of a trampoline.
|
|
|
487 This code should not include a label--the label is taken care of
|
|
|
488 automatically. */
|
|
|
489
|
|
|
490 #define TRAMPOLINE_TEMPLATE(STREAM) \
|
|
|
491 { \
|
|
|
492 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
|
|
|
493 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
|
|
|
494 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
|
|
|
495 if (Pmode == DImode) \
|
|
|
496 { \
|
|
|
497 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
|
|
|
498 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
|
|
|
499 } \
|
|
|
500 else \
|
|
|
501 { \
|
|
|
502 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
|
|
|
503 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
|
|
|
504 } \
|
|
|
505 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
|
|
|
506 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
|
|
|
507 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
|
|
|
508 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
|
|
|
509 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
|
|
|
510 }
|
|
|
511
|
|
|
512 #define TRAMPOLINE_SIZE (40)
|
|
|
513
|
|
|
514 #define TRAMPOLINE_ALIGNMENT 32
|
|
|
515
|
|
|
516 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
|
|
|
517 { \
|
|
|
518 rtx addr = ADDR; \
|
|
|
519 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
|
|
|
520 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
|
|
|
521 }
|
|
|
522
|
|
|
523
|
|
|
524 /* Addressing Modes. */
|
|
|
525
|
|
|
526 #define CONSTANT_ADDRESS_P(X) \
|
|
|
527 ( (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
|
|
|
528 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
|
|
|
529 || (GET_CODE (X) == CONST)))
|
|
|
530
|
|
|
531 #define MAX_REGS_PER_ADDRESS 1
|
|
|
532
|
|
|
533 #ifdef REG_OK_STRICT
|
|
|
534 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
|
|
|
535 { \
|
|
|
536 if (iq2000_legitimate_address_p (MODE, X, 1)) \
|
|
|
537 goto ADDR; \
|
|
|
538 }
|
|
|
539 #else
|
|
|
540 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
|
|
|
541 { \
|
|
|
542 if (iq2000_legitimate_address_p (MODE, X, 0)) \
|
|
|
543 goto ADDR; \
|
|
|
544 }
|
|
|
545 #endif
|
|
|
546
|
|
|
547 #define REG_OK_FOR_INDEX_P(X) 0
|
|
|
548
|
|
|
549
|
|
|
550 /* For the IQ2000, transform:
|
|
|
551
|
|
|
552 memory(X + <large int>)
|
|
|
553 into:
|
|
|
554 Y = <large int> & ~0x7fff;
|
|
|
555 Z = X + Y
|
|
|
556 memory (Z + (<large int> & 0x7fff));
|
|
|
557 */
|
|
|
558
|
|
|
559 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
|
|
|
560 { \
|
|
|
561 rtx xinsn = (X); \
|
|
|
562 \
|
|
|
563 if (TARGET_DEBUG_B_MODE) \
|
|
|
564 { \
|
|
|
565 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
|
|
|
566 GO_DEBUG_RTX (xinsn); \
|
|
|
567 } \
|
|
|
568 \
|
|
|
569 if (iq2000_check_split (X, MODE)) \
|
|
|
570 { \
|
|
|
571 X = gen_rtx_LO_SUM (Pmode, \
|
|
|
572 copy_to_mode_reg (Pmode, \
|
|
|
573 gen_rtx_HIGH (Pmode, X)), \
|
|
|
574 X); \
|
|
|
575 goto WIN; \
|
|
|
576 } \
|
|
|
577 \
|
|
|
578 if (GET_CODE (xinsn) == PLUS) \
|
|
|
579 { \
|
|
|
580 rtx xplus0 = XEXP (xinsn, 0); \
|
|
|
581 rtx xplus1 = XEXP (xinsn, 1); \
|
|
|
582 enum rtx_code code0 = GET_CODE (xplus0); \
|
|
|
583 enum rtx_code code1 = GET_CODE (xplus1); \
|
|
|
584 \
|
|
|
585 if (code0 != REG && code1 == REG) \
|
|
|
586 { \
|
|
|
587 xplus0 = XEXP (xinsn, 1); \
|
|
|
588 xplus1 = XEXP (xinsn, 0); \
|
|
|
589 code0 = GET_CODE (xplus0); \
|
|
|
590 code1 = GET_CODE (xplus1); \
|
|
|
591 } \
|
|
|
592 \
|
|
|
593 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
|
|
|
594 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
|
|
|
595 { \
|
|
|
596 rtx int_reg = gen_reg_rtx (Pmode); \
|
|
|
597 rtx ptr_reg = gen_reg_rtx (Pmode); \
|
|
|
598 \
|
|
|
599 emit_move_insn (int_reg, \
|
|
|
600 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
|
|
|
601 \
|
|
|
602 emit_insn (gen_rtx_SET (VOIDmode, \
|
|
|
603 ptr_reg, \
|
|
|
604 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
|
|
|
605 \
|
|
|
606 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
|
|
|
607 goto WIN; \
|
|
|
608 } \
|
|
|
609 } \
|
|
|
610 \
|
|
|
611 if (TARGET_DEBUG_B_MODE) \
|
|
|
612 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
|
|
|
613 }
|
|
|
614
|
|
|
615 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
|
|
|
616
|
|
|
617 #define LEGITIMATE_CONSTANT_P(X) (1)
|
|
|
618
|
|
|
619
|
|
|
620 /* Describing Relative Costs of Operations. */
|
|
|
621
|
|
|
622 #define REGISTER_MOVE_COST(MODE, FROM, TO) 2
|
|
|
623
|
|
|
624 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
|
|
|
625 (TO_P ? 2 : 16)
|
|
|
626
|
|
|
627 #define BRANCH_COST(speed_p, predictable_p) 2
|
|
|
628
|
|
|
629 #define SLOW_BYTE_ACCESS 1
|
|
|
630
|
|
|
631 #define NO_FUNCTION_CSE 1
|
|
|
632
|
|
|
633 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
|
|
|
634 if (REG_NOTE_KIND (LINK) != 0) \
|
|
|
635 (COST) = 0; /* Anti or output dependence. */
|
|
|
636
|
|
|
637
|
|
|
638 /* Dividing the output into sections. */
|
|
|
639
|
|
|
640 #define TEXT_SECTION_ASM_OP "\t.text" /* Instructions. */
|
|
|
641
|
|
|
642 #define DATA_SECTION_ASM_OP "\t.data" /* Large data. */
|
|
|
643
|
|
|
644
|
|
|
645 /* The Overall Framework of an Assembler File. */
|
|
|
646
|
|
|
647 #define ASM_COMMENT_START " #"
|
|
|
648
|
|
|
649 #define ASM_APP_ON "#APP\n"
|
|
|
650
|
|
|
651 #define ASM_APP_OFF "#NO_APP\n"
|
|
|
652
|
|
|
653
|
|
|
654 /* Output and Generation of Labels. */
|
|
|
655
|
|
|
656 #undef ASM_GENERATE_INTERNAL_LABEL
|
|
|
657 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
|
|
|
658 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM))
|
|
|
659
|
|
|
660 #define GLOBAL_ASM_OP "\t.globl\t"
|
|
|
661
|
|
|
662
|
|
|
663 /* Output of Assembler Instructions. */
|
|
|
664
|
|
|
665 #define REGISTER_NAMES \
|
|
|
666 { \
|
|
|
667 "%0", "%1", "%2", "%3", "%4", "%5", "%6", "%7", \
|
|
|
668 "%8", "%9", "%10", "%11", "%12", "%13", "%14", "%15", \
|
|
|
669 "%16", "%17", "%18", "%19", "%20", "%21", "%22", "%23", \
|
|
|
670 "%24", "%25", "%26", "%27", "%28", "%29", "%30", "%31", "%rap" \
|
|
|
671 };
|
|
|
672
|
|
|
673 #define ADDITIONAL_REGISTER_NAMES \
|
|
|
674 { \
|
|
|
675 { "%0", 0 + GP_REG_FIRST }, \
|
|
|
676 { "%1", 1 + GP_REG_FIRST }, \
|
|
|
677 { "%2", 2 + GP_REG_FIRST }, \
|
|
|
678 { "%3", 3 + GP_REG_FIRST }, \
|
|
|
679 { "%4", 4 + GP_REG_FIRST }, \
|
|
|
680 { "%5", 5 + GP_REG_FIRST }, \
|
|
|
681 { "%6", 6 + GP_REG_FIRST }, \
|
|
|
682 { "%7", 7 + GP_REG_FIRST }, \
|
|
|
683 { "%8", 8 + GP_REG_FIRST }, \
|
|
|
684 { "%9", 9 + GP_REG_FIRST }, \
|
|
|
685 { "%10", 10 + GP_REG_FIRST }, \
|
|
|
686 { "%11", 11 + GP_REG_FIRST }, \
|
|
|
687 { "%12", 12 + GP_REG_FIRST }, \
|
|
|
688 { "%13", 13 + GP_REG_FIRST }, \
|
|
|
689 { "%14", 14 + GP_REG_FIRST }, \
|
|
|
690 { "%15", 15 + GP_REG_FIRST }, \
|
|
|
691 { "%16", 16 + GP_REG_FIRST }, \
|
|
|
692 { "%17", 17 + GP_REG_FIRST }, \
|
|
|
693 { "%18", 18 + GP_REG_FIRST }, \
|
|
|
694 { "%19", 19 + GP_REG_FIRST }, \
|
|
|
695 { "%20", 20 + GP_REG_FIRST }, \
|
|
|
696 { "%21", 21 + GP_REG_FIRST }, \
|
|
|
697 { "%22", 22 + GP_REG_FIRST }, \
|
|
|
698 { "%23", 23 + GP_REG_FIRST }, \
|
|
|
699 { "%24", 24 + GP_REG_FIRST }, \
|
|
|
700 { "%25", 25 + GP_REG_FIRST }, \
|
|
|
701 { "%26", 26 + GP_REG_FIRST }, \
|
|
|
702 { "%27", 27 + GP_REG_FIRST }, \
|
|
|
703 { "%28", 28 + GP_REG_FIRST }, \
|
|
|
704 { "%29", 29 + GP_REG_FIRST }, \
|
|
|
705 { "%30", 27 + GP_REG_FIRST }, \
|
|
|
706 { "%31", 31 + GP_REG_FIRST }, \
|
|
|
707 { "%rap", 32 + GP_REG_FIRST }, \
|
|
|
708 }
|
|
|
709
|
|
|
710 /* Check if the current insn needs a nop in front of it
|
|
|
711 because of load delays, and also update the delay slot statistics. */
|
|
|
712
|
|
|
713 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
|
|
|
714 final_prescan_insn (INSN, OPVEC, NOPERANDS)
|
|
|
715
|
|
|
716 /* See iq2000.c for the IQ2000 specific codes. */
|
|
|
717 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
|
|
|
718
|
|
|
719 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) iq2000_print_operand_punct[CODE]
|
|
|
720
|
|
|
721 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
|
|
|
722
|
|
|
723 #define DBR_OUTPUT_SEQEND(STREAM) \
|
|
|
724 do \
|
|
|
725 { \
|
|
|
726 fputs ("\n", STREAM); \
|
|
|
727 } \
|
|
|
728 while (0)
|
|
|
729
|
|
|
730 #define LOCAL_LABEL_PREFIX "$"
|
|
|
731
|
|
|
732 #define USER_LABEL_PREFIX ""
|
|
|
733
|
|
|
734
|
|
|
735 /* Output of dispatch tables. */
|
|
|
736
|
|
|
737 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
|
|
|
738 do \
|
|
|
739 { \
|
|
|
740 fprintf (STREAM, "\t%s\t%sL%d\n", \
|
|
|
741 Pmode == DImode ? ".dword" : ".word", \
|
|
|
742 LOCAL_LABEL_PREFIX, VALUE); \
|
|
|
743 } \
|
|
|
744 while (0)
|
|
|
745
|
|
|
746 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
|
|
|
747 fprintf (STREAM, "\t%s\t%sL%d\n", \
|
|
|
748 Pmode == DImode ? ".dword" : ".word", \
|
|
|
749 LOCAL_LABEL_PREFIX, \
|
|
|
750 VALUE)
|
|
|
751
|
|
|
752
|
|
|
753 /* Assembler Commands for Alignment. */
|
|
|
754
|
|
|
755 #undef ASM_OUTPUT_SKIP
|
|
|
756 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
|
|
|
757 fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n", \
|
|
|
758 (unsigned HOST_WIDE_INT)(SIZE))
|
|
|
759
|
|
|
760 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
|
|
|
761 if ((LOG) != 0) \
|
|
|
762 fprintf (STREAM, "\t.balign %d\n", 1<<(LOG))
|
|
|
763
|
|
|
764
|
|
|
765 /* Macros Affecting all Debug Formats. */
|
|
|
766
|
|
|
767 #define DEBUGGER_AUTO_OFFSET(X) \
|
|
|
768 iq2000_debugger_offset (X, (HOST_WIDE_INT) 0)
|
|
|
769
|
|
|
770 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
|
|
|
771 iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
|
|
|
772
|
|
|
773 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
|
|
|
774
|
|
|
775 #define DWARF2_DEBUGGING_INFO 1
|
|
|
776
|
|
|
777
|
|
|
778 /* Miscellaneous Parameters. */
|
|
|
779
|
|
|
780 #define CASE_VECTOR_MODE SImode
|
|
|
781
|
|
|
782 #define WORD_REGISTER_OPERATIONS
|
|
|
783
|
|
|
784 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
|
|
|
785
|
|
|
786 #define MOVE_MAX 4
|
|
|
787
|
|
|
788 #define MAX_MOVE_MAX 8
|
|
|
789
|
|
|
790 #define SHIFT_COUNT_TRUNCATED 1
|
|
|
791
|
|
|
792 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
|
|
|
793
|
|
|
794 #define STORE_FLAG_VALUE 1
|
|
|
795
|
|
|
796 #define Pmode SImode
|
|
|
797
|
|
|
798 #define FUNCTION_MODE SImode
|
|
|
799
|
|
|
800 /* Standard GCC variables that we reference. */
|
|
|
801
|
|
|
802 extern char call_used_regs[];
|
|
|
803
|
|
|
804 /* IQ2000 external variables defined in iq2000.c. */
|
|
|
805
|
|
|
806 /* Comparison type. */
|
|
|
807 enum cmp_type
|
|
|
808 {
|
|
|
809 CMP_SI, /* Compare four byte integers. */
|
|
|
810 CMP_DI, /* Compare eight byte integers. */
|
|
|
811 CMP_SF, /* Compare single precision floats. */
|
|
|
812 CMP_DF, /* Compare double precision floats. */
|
|
|
813 CMP_MAX /* Max comparison type. */
|
|
|
814 };
|
|
|
815
|
|
|
816 /* Types of delay slot. */
|
|
|
817 enum delay_type
|
|
|
818 {
|
|
|
819 DELAY_NONE, /* No delay slot. */
|
|
|
820 DELAY_LOAD, /* Load from memory delay. */
|
|
|
821 DELAY_FCMP /* Delay after doing c.<xx>.{d,s}. */
|
|
|
822 };
|
|
|
823
|
|
|
824 /* Which processor to schedule for. */
|
|
|
825
|
|
|
826 enum processor_type
|
|
|
827 {
|
|
|
828 PROCESSOR_DEFAULT,
|
|
|
829 PROCESSOR_IQ2000,
|
|
|
830 PROCESSOR_IQ10
|
|
|
831 };
|
|
|
832
|
|
|
833 /* Recast the cpu class to be the cpu attribute. */
|
|
|
834 #define iq2000_cpu_attr ((enum attr_cpu) iq2000_tune)
|
|
|
835
|
|
|
836 #define BITMASK_UPPER16 ((unsigned long) 0xffff << 16) /* 0xffff0000 */
|
|
|
837 #define BITMASK_LOWER16 ((unsigned long) 0xffff) /* 0x0000ffff */
|
|
|
838
|
|
|
839
|
|
|
840 #define GENERATE_BRANCHLIKELY (ISA_HAS_BRANCHLIKELY)
|
|
|
841
|
|
|
842 /* Macros to decide whether certain features are available or not,
|
|
|
843 depending on the instruction set architecture level. */
|
|
|
844
|
|
|
845 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
|
|
|
846
|
|
|
847 /* ISA has branch likely instructions. */
|
|
|
848 #define ISA_HAS_BRANCHLIKELY (iq2000_isa == 1)
|
|
|
849
|
|
|
850
|
|
|
851 #undef ASM_SPEC
|
|
|
852
|
|
|
853
|
|
|
854 /* The mapping from gcc register number to DWARF 2 CFA column number. */
|
|
|
855 #define DWARF_FRAME_REGNUM(REG) (REG)
|
|
|
856
|
|
|
857 /* The DWARF 2 CFA column which tracks the return address. */
|
|
|
858 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
|
|
|
859
|
|
|
860 /* Describe how we implement __builtin_eh_return. */
|
|
|
861 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
|
|
|
862
|
|
|
863 /* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the
|
|
|
864 location used to store the amount to adjust the stack. This is
|
|
|
865 usually a register that is available from end of the function's body
|
|
|
866 to the end of the epilogue. Thus, this cannot be a register used as a
|
|
|
867 temporary by the epilogue.
|
|
|
868
|
|
|
869 This must be an integer register. */
|
|
|
870 #define EH_RETURN_STACKADJ_REGNO 3
|
|
|
871 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
|
|
|
872
|
|
|
873 /* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the
|
|
|
874 location used to store the address the processor should jump to
|
|
|
875 catch exception. This is usually a registers that is available from
|
|
|
876 end of the function's body to the end of the epilogue. Thus, this
|
|
|
877 cannot be a register used as a temporary by the epilogue.
|
|
|
878
|
|
|
879 This must be an address register. */
|
|
|
880 #define EH_RETURN_HANDLER_REGNO 26
|
|
|
881 #define EH_RETURN_HANDLER_RTX \
|
|
|
882 gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO)
|
|
|
883
|
|
|
884 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
|
|
|
885 #define DWARF_CIE_DATA_ALIGNMENT 4
|
|
|
886
|
|
|
887 /* For IQ2000, width of a floating point register. */
|
|
|
888 #define UNITS_PER_FPREG 4
|
|
|
889
|
|
|
890 /* Force right-alignment for small varargs in 32 bit little_endian mode */
|
|
|
891
|
|
|
892 #define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN
|
|
|
893
|
|
|
894 /* Internal macros to classify a register number as to whether it's a
|
|
|
895 general purpose register, a floating point register, a
|
|
|
896 multiply/divide register, or a status register. */
|
|
|
897
|
|
|
898 #define GP_REG_FIRST 0
|
|
|
899 #define GP_REG_LAST 31
|
|
|
900 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
|
|
|
901
|
|
|
902 #define RAP_REG_NUM 32
|
|
|
903 #define AT_REGNUM (GP_REG_FIRST + 1)
|
|
|
904
|
|
|
905 #define GP_REG_P(REGNO) \
|
|
|
906 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
|
|
|
907
|
|
|
908 /* IQ2000 registers used in prologue/epilogue code when the stack frame
|
|
|
909 is larger than 32K bytes. These registers must come from the
|
|
|
910 scratch register set, and not used for passing and returning
|
|
|
911 arguments and any other information used in the calling sequence. */
|
|
|
912
|
|
|
913 #define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12)
|
|
|
914 #define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13)
|
|
|
915
|
|
|
916 /* This macro is used later on in the file. */
|
|
|
917 #define GR_REG_CLASS_P(CLASS) \
|
|
|
918 ((CLASS) == GR_REGS)
|
|
|
919
|
|
|
920 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
|
|
|
921 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
|
|
|
922
|
|
|
923 /* Certain machines have the property that some registers cannot be
|
|
|
924 copied to some other registers without using memory. Define this
|
|
|
925 macro on those machines to be a C expression that is nonzero if
|
|
|
926 objects of mode MODE in registers of CLASS1 can only be copied to
|
|
|
927 registers of class CLASS2 by storing a register of CLASS1 into
|
|
|
928 memory and loading that memory location into a register of CLASS2.
|
|
|
929
|
|
|
930 Do not define this macro if its value would always be zero. */
|
|
|
931
|
|
|
932 /* Return the maximum number of consecutive registers
|
|
|
933 needed to represent mode MODE in a register of class CLASS. */
|
|
|
934
|
|
|
935 #define CLASS_UNITS(mode, size) \
|
|
|
936 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
|
|
|
937
|
|
|
938 /* If defined, gives a class of registers that cannot be used as the
|
|
|
939 operand of a SUBREG that changes the mode of the object illegally. */
|
|
|
940
|
|
|
941 #define CLASS_CANNOT_CHANGE_MODE 0
|
|
|
942
|
|
|
943 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
|
|
|
944
|
|
|
945 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
|
|
|
946 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
|
|
|
947
|
|
|
948 /* Make sure 4 words are always allocated on the stack. */
|
|
|
949
|
|
|
950 #ifndef STACK_ARGS_ADJUST
|
|
|
951 #define STACK_ARGS_ADJUST(SIZE) \
|
|
|
952 { \
|
|
|
953 if (SIZE.constant < 4 * UNITS_PER_WORD) \
|
|
|
954 SIZE.constant = 4 * UNITS_PER_WORD; \
|
|
|
955 }
|
|
|
956 #endif
|
|
|
957
|
|
|
958
|
|
|
959 /* Symbolic macros for the registers used to return integer and floating
|
|
|
960 point values. */
|
|
|
961
|
|
|
962 #define GP_RETURN (GP_REG_FIRST + 2)
|
|
|
963
|
|
|
964 /* Symbolic macros for the first/last argument registers. */
|
|
|
965
|
|
|
966 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
|
|
|
967 #define GP_ARG_LAST (GP_REG_FIRST + 11)
|
|
|
968
|
|
|
969 #define MAX_ARGS_IN_REGISTERS 8
|
|
|
970
|
|
|
971
|
|
|
972 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
|
|
|
973
|
|
|
974 #define MUST_SAVE_REGISTER(regno) \
|
|
|
975 ((df_regs_ever_live_p (regno) && !call_used_regs[regno]) \
|
|
|
976 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
|
|
|
977 || (regno == (GP_REG_FIRST + 31) && df_regs_ever_live_p (GP_REG_FIRST + 31)))
|
|
|
978
|
|
|
979 /* ALIGN FRAMES on double word boundaries */
|
|
|
980 #ifndef IQ2000_STACK_ALIGN
|
|
|
981 #define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
|
|
|
982 #endif
|
|
|
983
|
|
|
984
|
|
|
985 /* These assume that REGNO is a hard or pseudo reg number.
|
|
|
986 They give nonzero only if REGNO is a hard reg of the suitable class
|
|
|
987 or a pseudo reg currently allocated to a suitable hard reg.
|
|
|
988 These definitions are NOT overridden anywhere. */
|
|
|
989
|
|
|
990 #define BASE_REG_P(regno, mode) \
|
|
|
991 (GP_REG_P (regno))
|
|
|
992
|
|
|
993 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
|
|
|
994 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
|
|
|
995 (mode))
|
|
|
996
|
|
|
997 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
|
|
|
998 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
|
|
|
999
|
|
|
1000 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
|
|
|
1001 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
|
|
|
1002
|
|
|
1003 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
|
|
|
1004 and check its validity for a certain class.
|
|
|
1005 We have two alternate definitions for each of them.
|
|
|
1006 The usual definition accepts all pseudo regs; the other rejects them all.
|
|
|
1007 The symbol REG_OK_STRICT causes the latter definition to be used.
|
|
|
1008
|
|
|
1009 Most source files want to accept pseudo regs in the hope that
|
|
|
1010 they will get allocated to the class that the insn wants them to be in.
|
|
|
1011 Some source files that are used after register allocation
|
|
|
1012 need to be strict. */
|
|
|
1013
|
|
|
1014 #ifndef REG_OK_STRICT
|
|
|
1015 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
|
|
|
1016 iq2000_reg_mode_ok_for_base_p (X, MODE, 0)
|
|
|
1017 #else
|
|
|
1018 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
|
|
|
1019 iq2000_reg_mode_ok_for_base_p (X, MODE, 1)
|
|
|
1020 #endif
|
|
|
1021
|
|
|
1022 #if 1
|
|
|
1023 #define GO_PRINTF(x) fprintf (stderr, (x))
|
|
|
1024 #define GO_PRINTF2(x,y) fprintf (stderr, (x), (y))
|
|
|
1025 #define GO_DEBUG_RTX(x) debug_rtx (x)
|
|
|
1026
|
|
|
1027 #else
|
|
|
1028 #define GO_PRINTF(x)
|
|
|
1029 #define GO_PRINTF2(x,y)
|
|
|
1030 #define GO_DEBUG_RTX(x)
|
|
|
1031 #endif
|
|
|
1032
|
|
|
1033 /* If defined, modifies the length assigned to instruction INSN as a
|
|
|
1034 function of the context in which it is used. LENGTH is an lvalue
|
|
|
1035 that contains the initially computed length of the insn and should
|
|
|
1036 be updated with the correct length of the insn. */
|
|
|
1037 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
|
|
|
1038 ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH)))
|
|
|
1039
|
|
|
1040
|
|
|
1041
|
|
|
1042
|
|
|
1043 /* How to tell the debugger about changes of source files. */
|
|
|
1044
|
|
|
1045 #ifndef SET_FILE_NUMBER
|
|
|
1046 #define SET_FILE_NUMBER() ++ num_source_filenames
|
|
|
1047 #endif
|
|
|
1048
|
|
|
1049 /* This is how to output a note the debugger telling it the line number
|
|
|
1050 to which the following sequence of instructions corresponds. */
|
|
|
1051
|
|
|
1052 #ifndef LABEL_AFTER_LOC
|
|
|
1053 #define LABEL_AFTER_LOC(STREAM)
|
|
|
1054 #endif
|
|
|
1055
|
|
|
1056
|
|
|
1057 /* Default to -G 8 */
|
|
|
1058 #ifndef IQ2000_DEFAULT_GVALUE
|
|
|
1059 #define IQ2000_DEFAULT_GVALUE 8
|
|
|
1060 #endif
|
|
|
1061
|
|
|
1062 #define SDATA_SECTION_ASM_OP "\t.sdata" /* Small data. */
|
|
|
1063
|
|
|
1064
|
|
|
1065 /* List of all IQ2000 punctuation characters used by print_operand. */
|
|
|
1066 extern char iq2000_print_operand_punct[256];
|
|
|
1067
|
|
|
1068 /* The target cpu for optimization and scheduling. */
|
|
|
1069 extern enum processor_type iq2000_tune;
|
|
|
1070
|
|
|
1071 /* Which instruction set architecture to use. */
|
|
|
1072 extern int iq2000_isa;
|
|
|
1073
|
|
|
1074 /* Cached operands, and operator to compare for use in set/branch/trap
|
|
|
1075 on condition codes. */
|
|
|
1076 extern rtx branch_cmp[2];
|
|
|
1077
|
|
|
1078 /* What type of branch to use. */
|
|
|
1079 extern enum cmp_type branch_type;
|
|
|
1080
|
|
|
1081 enum iq2000_builtins
|
|
|
1082 {
|
|
|
1083 IQ2000_BUILTIN_ADO16,
|
|
|
1084 IQ2000_BUILTIN_CFC0,
|
|
|
1085 IQ2000_BUILTIN_CFC1,
|
|
|
1086 IQ2000_BUILTIN_CFC2,
|
|
|
1087 IQ2000_BUILTIN_CFC3,
|
|
|
1088 IQ2000_BUILTIN_CHKHDR,
|
|
|
1089 IQ2000_BUILTIN_CTC0,
|
|
|
1090 IQ2000_BUILTIN_CTC1,
|
|
|
1091 IQ2000_BUILTIN_CTC2,
|
|
|
1092 IQ2000_BUILTIN_CTC3,
|
|
|
1093 IQ2000_BUILTIN_LU,
|
|
|
1094 IQ2000_BUILTIN_LUC32L,
|
|
|
1095 IQ2000_BUILTIN_LUC64,
|
|
|
1096 IQ2000_BUILTIN_LUC64L,
|
|
|
1097 IQ2000_BUILTIN_LUK,
|
|
|
1098 IQ2000_BUILTIN_LULCK,
|
|
|
1099 IQ2000_BUILTIN_LUM32,
|
|
|
1100 IQ2000_BUILTIN_LUM32L,
|
|
|
1101 IQ2000_BUILTIN_LUM64,
|
|
|
1102 IQ2000_BUILTIN_LUM64L,
|
|
|
1103 IQ2000_BUILTIN_LUR,
|
|
|
1104 IQ2000_BUILTIN_LURL,
|
|
|
1105 IQ2000_BUILTIN_MFC0,
|
|
|
1106 IQ2000_BUILTIN_MFC1,
|
|
|
1107 IQ2000_BUILTIN_MFC2,
|
|
|
1108 IQ2000_BUILTIN_MFC3,
|
|
|
1109 IQ2000_BUILTIN_MRGB,
|
|
|
1110 IQ2000_BUILTIN_MTC0,
|
|
|
1111 IQ2000_BUILTIN_MTC1,
|
|
|
1112 IQ2000_BUILTIN_MTC2,
|
|
|
1113 IQ2000_BUILTIN_MTC3,
|
|
|
1114 IQ2000_BUILTIN_PKRL,
|
|
|
1115 IQ2000_BUILTIN_RAM,
|
|
|
1116 IQ2000_BUILTIN_RB,
|
|
|
1117 IQ2000_BUILTIN_RX,
|
|
|
1118 IQ2000_BUILTIN_SRRD,
|
|
|
1119 IQ2000_BUILTIN_SRRDL,
|
|
|
1120 IQ2000_BUILTIN_SRULC,
|
|
|
1121 IQ2000_BUILTIN_SRULCK,
|
|
|
1122 IQ2000_BUILTIN_SRWR,
|
|
|
1123 IQ2000_BUILTIN_SRWRU,
|
|
|
1124 IQ2000_BUILTIN_TRAPQF,
|
|
|
1125 IQ2000_BUILTIN_TRAPQFL,
|
|
|
1126 IQ2000_BUILTIN_TRAPQN,
|
|
|
1127 IQ2000_BUILTIN_TRAPQNE,
|
|
|
1128 IQ2000_BUILTIN_TRAPRE,
|
|
|
1129 IQ2000_BUILTIN_TRAPREL,
|
|
|
1130 IQ2000_BUILTIN_WB,
|
|
|
1131 IQ2000_BUILTIN_WBR,
|
|
|
1132 IQ2000_BUILTIN_WBU,
|
|
|
1133 IQ2000_BUILTIN_WX,
|
|
|
1134 IQ2000_BUILTIN_SYSCALL
|
|
|
1135 };
|
