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1 ;; VR4300 pipeline description.
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2 ;; Copyright (C) 2004, 2005, 2007 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published
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8 ;; by the Free Software Foundation; either version 3, or (at your
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9 ;; option) any later version.
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10
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11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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14 ;; License for more details.
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15
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20
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21 ;; This file overrides parts of generic.md. It is derived from the
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22 ;; old define_function_unit description.
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23
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24 (define_insn_reservation "r4300_load" 2
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25 (and (eq_attr "cpu" "r4300")
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26 (eq_attr "type" "load,fpload,fpidxload,mfc,mtc"))
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27 "alu")
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28
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29 (define_insn_reservation "r4300_imul_si" 5
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30 (and (eq_attr "cpu" "r4300")
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31 (and (eq_attr "type" "imul,imul3,imadd")
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32 (eq_attr "mode" "SI")))
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33 "imuldiv*5")
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34
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35 (define_insn_reservation "r4300_imul_di" 8
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36 (and (eq_attr "cpu" "r4300")
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37 (and (eq_attr "type" "imul,imul3,imadd")
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38 (eq_attr "mode" "DI")))
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39 "imuldiv*8")
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40
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41 (define_insn_reservation "r4300_idiv_si" 37
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42 (and (eq_attr "cpu" "r4300")
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43 (and (eq_attr "type" "idiv")
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44 (eq_attr "mode" "SI")))
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45 "imuldiv*37")
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46
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47 (define_insn_reservation "r4300_idiv_di" 69
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48 (and (eq_attr "cpu" "r4300")
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49 (and (eq_attr "type" "idiv")
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50 (eq_attr "mode" "DI")))
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51 "imuldiv*69")
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52
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53 (define_insn_reservation "r4300_fmove" 1
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54 (and (eq_attr "cpu" "r4300")
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55 (eq_attr "type" "fcmp,fabs,fneg,fmove"))
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56 "imuldiv")
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57
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58 (define_insn_reservation "r4300_fadd" 3
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59 (and (eq_attr "cpu" "r4300")
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60 (eq_attr "type" "fadd"))
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61 "imuldiv*3")
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62
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63 (define_insn_reservation "r4300_fmul_single" 5
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64 (and (eq_attr "cpu" "r4300")
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65 (and (eq_attr "type" "fmul,fmadd")
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66 (eq_attr "mode" "SF")))
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67 "imuldiv*5")
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68
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69 (define_insn_reservation "r4300_fmul_double" 8
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70 (and (eq_attr "cpu" "r4300")
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71 (and (eq_attr "type" "fmul,fmadd")
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72 (eq_attr "mode" "DF")))
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73 "imuldiv*8")
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74
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75 (define_insn_reservation "r4300_fdiv_single" 29
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76 (and (eq_attr "cpu" "r4300")
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77 (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
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78 (eq_attr "mode" "SF")))
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79 "imuldiv*29")
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80
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81 (define_insn_reservation "r4300_fdiv_double" 58
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82 (and (eq_attr "cpu" "r4300")
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83 (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
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84 (eq_attr "mode" "DF")))
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85 "imuldiv*58")
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