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1 ;; DFA-based pipeline description for the RM7000.
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2 ;; Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published
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8 ;; by the Free Software Foundation; either version 3, or (at your
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9 ;; option) any later version.
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10
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11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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14 ;; License for more details.
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15
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; .........................
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21 ;;
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22 ;; The RM7000 is a dual-issue processor that can bundle instructions as:
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23 ;; {arith|load|store}{arith|imul|idiv|branch|float}
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24 ;;
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25 ;; Reference:
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26 ;; "RM7000 Family User Manual, PMC-2002296"
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27 ;;
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28 ;; .........................
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29
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30 ;; Use three automata to isolate long latency operations, reducing space.
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31 (define_automaton "rm7000_other, rm7000_fdiv, rm7000_idiv")
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32
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33 ;;
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34 ;; Describe the resources.
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35 ;;
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36
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37 ;; Global
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38 (define_cpu_unit "rm7_iss0,rm7_iss1" "rm7000_other")
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39
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40 ;; Integer execution unit (M-Pipe).
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41 (define_cpu_unit "ixum_addsub_agen" "rm7000_other")
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42
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43 ;; Integer execution unit (F-Pipe).
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44 (define_cpu_unit "ixuf_addsub" "rm7000_other")
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45 (define_cpu_unit "ixuf_branch" "rm7000_other")
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46 (define_cpu_unit "ixuf_mpydiv" "rm7000_other")
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47 (define_cpu_unit "ixuf_mpydiv_iter" "rm7000_idiv")
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48 ;; Floating-point unit (F-Pipe).
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49 (define_cpu_unit "fxuf_add" "rm7000_other")
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50 (define_cpu_unit "fxuf_mpy" "rm7000_other")
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51 (define_cpu_unit "fxuf_mpy_iter" "rm7000_fdiv")
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52 (define_cpu_unit "fxuf_divsqrt" "rm7000_other")
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53 (define_cpu_unit "fxuf_divsqrt_iter" "rm7000_fdiv")
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54
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55 (exclusion_set "ixuf_addsub"
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56 "ixuf_branch,ixuf_mpydiv,fxuf_add,fxuf_mpy,fxuf_divsqrt")
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57 (exclusion_set "ixuf_branch" "ixuf_mpydiv,fxuf_add,fxuf_mpy,fxuf_divsqrt")
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58 (exclusion_set "ixuf_mpydiv" "fxuf_add,fxuf_mpy,fxuf_divsqrt")
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59 (exclusion_set "fxuf_add" "fxuf_mpy,fxuf_divsqrt")
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60 (exclusion_set "fxuf_mpy" "fxuf_divsqrt")
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61
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62 ;; After branch any insn cannot be issued.
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63 (absence_set "rm7_iss0,rm7_iss1" "ixuf_branch")
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64
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65 ;;
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66 ;; Define reservations for unit name mnemonics or combinations.
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67 ;;
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68
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69 (define_reservation "rm7_iss" "rm7_iss0|rm7_iss1")
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70 (define_reservation "rm7_single_dispatch" "rm7_iss0+rm7_iss1")
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71
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72 (define_reservation "rm7_iaddsub" "rm7_iss+(ixum_addsub_agen|ixuf_addsub)")
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73 (define_reservation "rm7_imem" "rm7_iss+ixum_addsub_agen")
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74 (define_reservation "rm7_impydiv" "rm7_iss+ixuf_mpydiv")
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75 (define_reservation "rm7_impydiv_iter" "ixuf_mpydiv_iter")
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76 (define_reservation "rm7_branch" "rm7_iss+ixuf_branch")
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77
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78 (define_reservation "rm7_fpadd" "rm7_iss+fxuf_add")
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79 (define_reservation "rm7_fpmpy" "rm7_iss+fxuf_mpy")
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80 (define_reservation "rm7_fpmpy_iter" "fxuf_mpy_iter")
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81 (define_reservation "rm7_fpdivsqr" "rm7_iss+fxuf_divsqrt")
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82 (define_reservation "rm7_fpdivsqr_iter" "fxuf_divsqrt_iter")
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83
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84 ;;
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85 ;; Describe instruction reservations for integer operations.
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86 ;;
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87
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88 (define_insn_reservation "rm7_int_other" 1
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89 (and (eq_attr "cpu" "r7000")
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90 (eq_attr "type" "arith,shift,signext,slt,clz,const,condmove,logical,move,nop,trap"))
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91 "rm7_iaddsub")
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92
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93 (define_insn_reservation "rm7_ld" 2
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94 (and (eq_attr "cpu" "r7000")
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95 (eq_attr "type" "load,fpload,fpidxload"))
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96 "rm7_imem")
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97
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98 (define_insn_reservation "rm7_st" 1
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99 (and (eq_attr "cpu" "r7000")
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100 (eq_attr "type" "store,fpstore,fpidxstore"))
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101 "rm7_imem")
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102
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103 (define_insn_reservation "rm7_idiv_si" 36
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104 (and (eq_attr "cpu" "r7000")
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105 (and (eq_attr "type" "idiv")
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106 (eq_attr "mode" "SI")))
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107 "rm7_impydiv+(rm7_impydiv_iter*36)")
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108
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109 (define_insn_reservation "rm7_idiv_di" 68
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110 (and (eq_attr "cpu" "r7000")
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111 (and (eq_attr "type" "idiv")
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112 (eq_attr "mode" "DI")))
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113 "rm7_impydiv+(rm7_impydiv_iter*68)")
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114
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115 (define_insn_reservation "rm7_impy_si_mult" 5
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116 (and (eq_attr "cpu" "r7000")
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117 (and (eq_attr "type" "imul,imadd")
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118 (eq_attr "mode" "SI")))
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119 "rm7_impydiv+(rm7_impydiv_iter*3)")
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120
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121 ;; There are an additional 2 stall cycles.
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122 (define_insn_reservation "rm7_impy_si_mul" 2
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123 (and (eq_attr "cpu" "r7000")
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124 (and (eq_attr "type" "imul3")
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125 (eq_attr "mode" "SI")))
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126 "rm7_impydiv")
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127
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128 (define_insn_reservation "rm7_impy_di" 9
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129 (and (eq_attr "cpu" "r7000")
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130 (and (eq_attr "type" "imul,imul3")
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131 (eq_attr "mode" "DI")))
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132 "rm7_impydiv+(rm7_impydiv_iter*8)")
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133
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134 ;; Move to/from HI/LO.
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135 (define_insn_reservation "rm7_mthilo" 3
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136 (and (eq_attr "cpu" "r7000")
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137 (eq_attr "type" "mthilo"))
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138 "rm7_impydiv")
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139
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140 (define_insn_reservation "rm7_mfhilo" 1
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141 (and (eq_attr "cpu" "r7000")
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142 (eq_attr "type" "mfhilo"))
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143 "rm7_impydiv")
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144
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145 ;; Move to/from fp coprocessor.
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146 (define_insn_reservation "rm7_ixfer" 2
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147 (and (eq_attr "cpu" "r7000")
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148 (eq_attr "type" "mfc,mtc"))
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149 "rm7_iaddsub")
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150
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151 (define_insn_reservation "rm7_ibr" 3
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152 (and (eq_attr "cpu" "r7000")
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153 (eq_attr "type" "branch,jump,call"))
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154 "rm7_branch")
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155
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156 ;;
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157 ;; Describe instruction reservations for the floating-point operations.
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158 ;;
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159 (define_insn_reservation "rm7_fp_quick" 4
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160 (and (eq_attr "cpu" "r7000")
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161 (eq_attr "type" "fneg,fcmp,fabs,fmove"))
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162 "rm7_fpadd")
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163
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164 (define_insn_reservation "rm7_fp_other" 4
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165 (and (eq_attr "cpu" "r7000")
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166 (eq_attr "type" "fadd"))
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167 "rm7_fpadd")
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168
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169 (define_insn_reservation "rm7_fp_cvt" 4
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170 (and (eq_attr "cpu" "r7000")
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171 (eq_attr "type" "fcvt"))
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172 "rm7_fpadd")
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173
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174 (define_insn_reservation "rm7_fp_divsqrt_df" 36
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175 (and (eq_attr "cpu" "r7000")
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176 (and (eq_attr "type" "fdiv,frdiv,fsqrt")
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177 (eq_attr "mode" "DF")))
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178 "rm7_fpdivsqr+(rm7_fpdivsqr_iter*36)")
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179
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180 (define_insn_reservation "rm7_fp_divsqrt_sf" 21
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181 (and (eq_attr "cpu" "r7000")
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182 (and (eq_attr "type" "fdiv,frdiv,fsqrt")
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183 (eq_attr "mode" "SF")))
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184 "rm7_fpdivsqr+(rm7_fpdivsqr_iter*21)")
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185
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186 (define_insn_reservation "rm7_fp_rsqrt_df" 68
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187 (and (eq_attr "cpu" "r7000")
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188 (and (eq_attr "type" "frsqrt")
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189 (eq_attr "mode" "DF")))
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190 "rm7_fpdivsqr+(rm7_fpdivsqr_iter*68)")
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191
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192 (define_insn_reservation "rm7_fp_rsqrt_sf" 38
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193 (and (eq_attr "cpu" "r7000")
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194 (and (eq_attr "type" "frsqrt")
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195 (eq_attr "mode" "SF")))
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196 "rm7_fpdivsqr+(rm7_fpdivsqr_iter*38)")
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197
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198 (define_insn_reservation "rm7_fp_mpy_sf" 4
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199 (and (eq_attr "cpu" "r7000")
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200 (and (eq_attr "type" "fmul,fmadd")
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201 (eq_attr "mode" "SF")))
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202 "rm7_fpmpy+rm7_fpmpy_iter")
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203
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204 (define_insn_reservation "rm7_fp_mpy_df" 5
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205 (and (eq_attr "cpu" "r7000")
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206 (and (eq_attr "type" "fmul,fmadd")
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207 (eq_attr "mode" "DF")))
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208 "rm7_fpmpy+(rm7_fpmpy_iter*2)")
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209
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210 ;; Force single-dispatch for unknown or multi.
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211 (define_insn_reservation "rm7_unknown" 1
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212 (and (eq_attr "cpu" "r7000")
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213 (eq_attr "type" "unknown,multi"))
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214 "rm7_single_dispatch")
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