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1 ;; MIPS Paired-Single Floating and MIPS-3D Instructions.
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2 ;; Copyright (C) 2004, 2007 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_insn "*movcc_v2sf_<mode>"
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21 [(set (match_operand:V2SF 0 "register_operand" "=f,f")
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22 (if_then_else:V2SF
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23 (match_operator:GPR 4 "equality_operator"
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24 [(match_operand:GPR 1 "register_operand" "d,d")
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25 (const_int 0)])
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26 (match_operand:V2SF 2 "register_operand" "f,0")
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27 (match_operand:V2SF 3 "register_operand" "0,f")))]
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28 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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29 "@
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30 mov%T4.ps\t%0,%2,%1
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31 mov%t4.ps\t%0,%3,%1"
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32 [(set_attr "type" "condmove")
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33 (set_attr "mode" "SF")])
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34
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35 (define_insn "mips_cond_move_tf_ps"
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36 [(set (match_operand:V2SF 0 "register_operand" "=f,f")
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37 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f,0")
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38 (match_operand:V2SF 2 "register_operand" "0,f")
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39 (match_operand:CCV2 3 "register_operand" "z,z")]
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40 UNSPEC_MOVE_TF_PS))]
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41 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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42 "@
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43 movt.ps\t%0,%1,%3
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44 movf.ps\t%0,%2,%3"
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45 [(set_attr "type" "condmove")
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46 (set_attr "mode" "SF")])
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47
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48 (define_expand "movv2sfcc"
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49 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
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50 (set (match_operand:V2SF 0 "register_operand")
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51 (if_then_else:V2SF (match_dup 5)
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52 (match_operand:V2SF 2 "register_operand")
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53 (match_operand:V2SF 3 "register_operand")))]
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54 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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55 {
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56 /* We can only support MOVN.PS and MOVZ.PS.
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57 NOTE: MOVT.PS and MOVF.PS have different semantics from MOVN.PS and
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58 MOVZ.PS. MOVT.PS and MOVF.PS depend on two CC values and move
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59 each item independently. */
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60
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61 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
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62 FAIL;
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63
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64 mips_expand_conditional_move (operands);
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65 DONE;
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66 })
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67
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68 ; pul.ps - Pair Upper Lower
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69 (define_insn "mips_pul_ps"
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70 [(set (match_operand:V2SF 0 "register_operand" "=f")
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71 (vec_merge:V2SF
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72 (match_operand:V2SF 1 "register_operand" "f")
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73 (match_operand:V2SF 2 "register_operand" "f")
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74 (const_int 2)))]
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75 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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76 "pul.ps\t%0,%1,%2"
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77 [(set_attr "type" "fmove")
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78 (set_attr "mode" "SF")])
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79
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80 ; puu.ps - Pair upper upper
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81 (define_insn "mips_puu_ps"
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82 [(set (match_operand:V2SF 0 "register_operand" "=f")
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83 (vec_merge:V2SF
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84 (match_operand:V2SF 1 "register_operand" "f")
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85 (vec_select:V2SF (match_operand:V2SF 2 "register_operand" "f")
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86 (parallel [(const_int 1)
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87 (const_int 0)]))
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88 (const_int 2)))]
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89 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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90 "puu.ps\t%0,%1,%2"
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91 [(set_attr "type" "fmove")
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92 (set_attr "mode" "SF")])
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93
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94 ; pll.ps - Pair Lower Lower
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95 (define_insn "mips_pll_ps"
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96 [(set (match_operand:V2SF 0 "register_operand" "=f")
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97 (vec_merge:V2SF
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98 (vec_select:V2SF (match_operand:V2SF 1 "register_operand" "f")
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99 (parallel [(const_int 1)
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100 (const_int 0)]))
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101 (match_operand:V2SF 2 "register_operand" "f")
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102 (const_int 2)))]
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103 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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104 "pll.ps\t%0,%1,%2"
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105 [(set_attr "type" "fmove")
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106 (set_attr "mode" "SF")])
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107
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108 ; plu.ps - Pair Lower Upper
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109 (define_insn "mips_plu_ps"
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110 [(set (match_operand:V2SF 0 "register_operand" "=f")
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111 (vec_merge:V2SF
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112 (vec_select:V2SF (match_operand:V2SF 1 "register_operand" "f")
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113 (parallel [(const_int 1)
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114 (const_int 0)]))
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115 (vec_select:V2SF (match_operand:V2SF 2 "register_operand" "f")
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116 (parallel [(const_int 1)
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117 (const_int 0)]))
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118 (const_int 2)))]
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119 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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120 "plu.ps\t%0,%1,%2"
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121 [(set_attr "type" "fmove")
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122 (set_attr "mode" "SF")])
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123
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124 ; vec_init
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125 (define_expand "vec_initv2sf"
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126 [(match_operand:V2SF 0 "register_operand")
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127 (match_operand:V2SF 1 "")]
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128 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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129 {
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130 rtx op0 = force_reg (SFmode, XVECEXP (operands[1], 0, 0));
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131 rtx op1 = force_reg (SFmode, XVECEXP (operands[1], 0, 1));
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132 emit_insn (gen_vec_initv2sf_internal (operands[0], op0, op1));
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133 DONE;
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134 })
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135
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136 (define_insn "vec_initv2sf_internal"
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137 [(set (match_operand:V2SF 0 "register_operand" "=f")
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138 (vec_concat:V2SF
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139 (match_operand:SF 1 "register_operand" "f")
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140 (match_operand:SF 2 "register_operand" "f")))]
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141 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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142 {
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143 if (BYTES_BIG_ENDIAN)
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144 return "cvt.ps.s\t%0,%1,%2";
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145 else
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146 return "cvt.ps.s\t%0,%2,%1";
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147 }
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148 [(set_attr "type" "fcvt")
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149 (set_attr "mode" "SF")])
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150
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151 ;; ??? This is only generated if we perform a vector operation that has to be
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152 ;; emulated. There is no other way to get a vector mode bitfield extract
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153 ;; currently.
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154
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155 (define_insn "vec_extractv2sf"
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156 [(set (match_operand:SF 0 "register_operand" "=f")
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157 (vec_select:SF (match_operand:V2SF 1 "register_operand" "f")
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158 (parallel
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159 [(match_operand 2 "const_0_or_1_operand" "")])))]
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160 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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161 {
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162 if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN)
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163 return "cvt.s.pu\t%0,%1";
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164 else
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165 return "cvt.s.pl\t%0,%1";
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166 }
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167 [(set_attr "type" "fcvt")
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168 (set_attr "mode" "SF")])
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169
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170 ;; ??? This is only generated if we disable the vec_init pattern. There is
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171 ;; no other way to get a vector mode bitfield store currently.
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172
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173 (define_expand "vec_setv2sf"
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174 [(match_operand:V2SF 0 "register_operand")
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175 (match_operand:SF 1 "register_operand")
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176 (match_operand 2 "const_0_or_1_operand")]
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177 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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178 {
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179 rtx temp;
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180
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181 /* We don't have an insert instruction, so we duplicate the float, and
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182 then use a PUL instruction. */
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183 temp = gen_reg_rtx (V2SFmode);
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184 emit_insn (gen_mips_cvt_ps_s (temp, operands[1], operands[1]));
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185 if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN)
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186 emit_insn (gen_mips_pul_ps (operands[0], temp, operands[0]));
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187 else
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188 emit_insn (gen_mips_pul_ps (operands[0], operands[0], temp));
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189 DONE;
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190 })
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191
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192 ; cvt.ps.s - Floating Point Convert Pair to Paired Single
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193 (define_expand "mips_cvt_ps_s"
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194 [(match_operand:V2SF 0 "register_operand")
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195 (match_operand:SF 1 "register_operand")
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196 (match_operand:SF 2 "register_operand")]
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197 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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198 {
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199 if (BYTES_BIG_ENDIAN)
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200 emit_insn (gen_vec_initv2sf_internal (operands[0], operands[1],
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201 operands[2]));
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202 else
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203 emit_insn (gen_vec_initv2sf_internal (operands[0], operands[2],
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204 operands[1]));
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205 DONE;
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206 })
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207
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208 ; cvt.s.pl - Floating Point Convert Pair Lower to Single Floating Point
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209 (define_expand "mips_cvt_s_pl"
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210 [(set (match_operand:SF 0 "register_operand")
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211 (vec_select:SF (match_operand:V2SF 1 "register_operand")
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212 (parallel [(match_dup 2)])))]
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213 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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214 { operands[2] = GEN_INT (BYTES_BIG_ENDIAN); })
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215
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216 ; cvt.s.pu - Floating Point Convert Pair Upper to Single Floating Point
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217 (define_expand "mips_cvt_s_pu"
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218 [(set (match_operand:SF 0 "register_operand")
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219 (vec_select:SF (match_operand:V2SF 1 "register_operand")
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220 (parallel [(match_dup 2)])))]
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221 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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222 { operands[2] = GEN_INT (!BYTES_BIG_ENDIAN); })
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223
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224 ; alnv.ps - Floating Point Align Variable
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225 (define_insn "mips_alnv_ps"
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226 [(set (match_operand:V2SF 0 "register_operand" "=f")
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227 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
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228 (match_operand:V2SF 2 "register_operand" "f")
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229 (match_operand:SI 3 "register_operand" "d")]
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230 UNSPEC_ALNV_PS))]
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231 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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232 "alnv.ps\t%0,%1,%2,%3"
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233 [(set_attr "type" "fmove")
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234 (set_attr "mode" "SF")])
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235
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236 ; addr.ps - Floating Point Reduction Add
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237 (define_insn "mips_addr_ps"
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238 [(set (match_operand:V2SF 0 "register_operand" "=f")
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239 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
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240 (match_operand:V2SF 2 "register_operand" "f")]
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241 UNSPEC_ADDR_PS))]
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242 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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243 "addr.ps\t%0,%1,%2"
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244 [(set_attr "type" "fadd")
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245 (set_attr "mode" "SF")])
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246
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247 ; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word
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248 (define_insn "mips_cvt_pw_ps"
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249 [(set (match_operand:V2SF 0 "register_operand" "=f")
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250 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
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251 UNSPEC_CVT_PW_PS))]
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252 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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253 "cvt.pw.ps\t%0,%1"
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254 [(set_attr "type" "fcvt")
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255 (set_attr "mode" "SF")])
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256
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257 ; cvt.ps.pw - Floating Point Convert Paired Word to Paired Single
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258 (define_insn "mips_cvt_ps_pw"
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259 [(set (match_operand:V2SF 0 "register_operand" "=f")
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260 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
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261 UNSPEC_CVT_PS_PW))]
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262 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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263 "cvt.ps.pw\t%0,%1"
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264 [(set_attr "type" "fcvt")
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265 (set_attr "mode" "SF")])
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266
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267 ; mulr.ps - Floating Point Reduction Multiply
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268 (define_insn "mips_mulr_ps"
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269 [(set (match_operand:V2SF 0 "register_operand" "=f")
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270 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
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271 (match_operand:V2SF 2 "register_operand" "f")]
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272 UNSPEC_MULR_PS))]
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273 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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274 "mulr.ps\t%0,%1,%2"
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275 [(set_attr "type" "fmul")
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276 (set_attr "mode" "SF")])
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277
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278 ; abs.ps
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279 (define_expand "mips_abs_ps"
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280 [(set (match_operand:V2SF 0 "register_operand")
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281 (unspec:V2SF [(match_operand:V2SF 1 "register_operand")]
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282 UNSPEC_ABS_PS))]
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283 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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284 {
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285 /* If we can ignore NaNs, this operation is equivalent to the
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286 rtl ABS code. */
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287 if (!HONOR_NANS (V2SFmode))
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288 {
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289 emit_insn (gen_absv2sf2 (operands[0], operands[1]));
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290 DONE;
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291 }
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292 })
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293
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294 (define_insn "*mips_abs_ps"
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295 [(set (match_operand:V2SF 0 "register_operand" "=f")
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296 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
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297 UNSPEC_ABS_PS))]
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298 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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299 "abs.ps\t%0,%1"
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300 [(set_attr "type" "fabs")
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301 (set_attr "mode" "SF")])
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302
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303 ;----------------------------------------------------------------------------
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304 ; Floating Point Comparisons for Scalars
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305 ;----------------------------------------------------------------------------
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306
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307 (define_insn "mips_cabs_cond_<fmt>"
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308 [(set (match_operand:CC 0 "register_operand" "=z")
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309 (unspec:CC [(match_operand:SCALARF 1 "register_operand" "f")
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310 (match_operand:SCALARF 2 "register_operand" "f")
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311 (match_operand 3 "const_int_operand" "")]
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312 UNSPEC_CABS))]
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313 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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314 "cabs.%Y3.<fmt>\t%0,%1,%2"
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315 [(set_attr "type" "fcmp")
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316 (set_attr "mode" "FPSW")])
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317
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318
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319 ;----------------------------------------------------------------------------
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320 ; Floating Point Comparisons for Four Singles
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321 ;----------------------------------------------------------------------------
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322
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323 (define_insn_and_split "mips_c_cond_4s"
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324 [(set (match_operand:CCV4 0 "register_operand" "=z")
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325 (unspec:CCV4 [(match_operand:V2SF 1 "register_operand" "f")
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326 (match_operand:V2SF 2 "register_operand" "f")
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327 (match_operand:V2SF 3 "register_operand" "f")
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328 (match_operand:V2SF 4 "register_operand" "f")
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329 (match_operand 5 "const_int_operand" "")]
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330 UNSPEC_C))]
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331 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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332 "#"
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333 "&& reload_completed"
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334 [(set (match_dup 6)
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335 (unspec:CCV2 [(match_dup 1)
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336 (match_dup 2)
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337 (match_dup 5)]
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338 UNSPEC_C))
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339 (set (match_dup 7)
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340 (unspec:CCV2 [(match_dup 3)
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341 (match_dup 4)
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342 (match_dup 5)]
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343 UNSPEC_C))]
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344 {
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345 operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0);
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346 operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8);
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347 }
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348 [(set_attr "type" "fcmp")
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349 (set_attr "length" "8")
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350 (set_attr "mode" "FPSW")])
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351
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352 (define_insn_and_split "mips_cabs_cond_4s"
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353 [(set (match_operand:CCV4 0 "register_operand" "=z")
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354 (unspec:CCV4 [(match_operand:V2SF 1 "register_operand" "f")
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355 (match_operand:V2SF 2 "register_operand" "f")
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356 (match_operand:V2SF 3 "register_operand" "f")
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357 (match_operand:V2SF 4 "register_operand" "f")
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358 (match_operand 5 "const_int_operand" "")]
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359 UNSPEC_CABS))]
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360 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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361 "#"
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362 "&& reload_completed"
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363 [(set (match_dup 6)
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364 (unspec:CCV2 [(match_dup 1)
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365 (match_dup 2)
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366 (match_dup 5)]
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367 UNSPEC_CABS))
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368 (set (match_dup 7)
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369 (unspec:CCV2 [(match_dup 3)
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370 (match_dup 4)
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371 (match_dup 5)]
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372 UNSPEC_CABS))]
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373 {
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374 operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0);
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375 operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8);
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376 }
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377 [(set_attr "type" "fcmp")
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378 (set_attr "length" "8")
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379 (set_attr "mode" "FPSW")])
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380
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381
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382 ;----------------------------------------------------------------------------
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383 ; Floating Point Comparisons for Paired Singles
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384 ;----------------------------------------------------------------------------
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385
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386 (define_insn "mips_c_cond_ps"
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387 [(set (match_operand:CCV2 0 "register_operand" "=z")
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388 (unspec:CCV2 [(match_operand:V2SF 1 "register_operand" "f")
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389 (match_operand:V2SF 2 "register_operand" "f")
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390 (match_operand 3 "const_int_operand" "")]
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391 UNSPEC_C))]
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392 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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393 "c.%Y3.ps\t%0,%1,%2"
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394 [(set_attr "type" "fcmp")
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395 (set_attr "mode" "FPSW")])
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396
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397 (define_insn "mips_cabs_cond_ps"
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398 [(set (match_operand:CCV2 0 "register_operand" "=z")
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399 (unspec:CCV2 [(match_operand:V2SF 1 "register_operand" "f")
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400 (match_operand:V2SF 2 "register_operand" "f")
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401 (match_operand 3 "const_int_operand" "")]
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|
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402 UNSPEC_CABS))]
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|
403 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
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|
|
404 "cabs.%Y3.ps\t%0,%1,%2"
|
|
|
405 [(set_attr "type" "fcmp")
|
|
|
406 (set_attr "mode" "FPSW")])
|
|
|
407
|
|
|
408 ;; An expander for generating an scc operation.
|
|
|
409 (define_expand "scc_ps"
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|
|
410 [(set (match_operand:CCV2 0)
|
|
|
411 (unspec:CCV2 [(match_operand 1)] UNSPEC_SCC))])
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|
|
412
|
|
|
413 (define_insn "s<code>_ps"
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|
|
414 [(set (match_operand:CCV2 0 "register_operand" "=z")
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|
|
415 (unspec:CCV2
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|
|
416 [(fcond (match_operand:V2SF 1 "register_operand" "f")
|
|
|
417 (match_operand:V2SF 2 "register_operand" "f"))]
|
|
|
418 UNSPEC_SCC))]
|
|
|
419 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
|
|
420 "c.<fcond>.ps\t%0,%1,%2"
|
|
|
421 [(set_attr "type" "fcmp")
|
|
|
422 (set_attr "mode" "FPSW")])
|
|
|
423
|
|
|
424 (define_insn "s<code>_ps"
|
|
|
425 [(set (match_operand:CCV2 0 "register_operand" "=z")
|
|
|
426 (unspec:CCV2
|
|
|
427 [(swapped_fcond (match_operand:V2SF 1 "register_operand" "f")
|
|
|
428 (match_operand:V2SF 2 "register_operand" "f"))]
|
|
|
429 UNSPEC_SCC))]
|
|
|
430 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
|
|
431 "c.<swapped_fcond>.ps\t%0,%2,%1"
|
|
|
432 [(set_attr "type" "fcmp")
|
|
|
433 (set_attr "mode" "FPSW")])
|
|
|
434
|
|
|
435 ;----------------------------------------------------------------------------
|
|
|
436 ; Floating Point Branch Instructions.
|
|
|
437 ;----------------------------------------------------------------------------
|
|
|
438
|
|
|
439 ; Branch on Any of Four Floating Point Condition Codes True
|
|
|
440 (define_insn "bc1any4t"
|
|
|
441 [(set (pc)
|
|
|
442 (if_then_else (ne (match_operand:CCV4 0 "register_operand" "z")
|
|
|
443 (const_int 0))
|
|
|
444 (label_ref (match_operand 1 "" ""))
|
|
|
445 (pc)))]
|
|
|
446 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
|
|
447 "%*bc1any4t\t%0,%1%/"
|
|
|
448 [(set_attr "type" "branch")
|
|
|
449 (set_attr "mode" "none")])
|
|
|
450
|
|
|
451 ; Branch on Any of Four Floating Point Condition Codes False
|
|
|
452 (define_insn "bc1any4f"
|
|
|
453 [(set (pc)
|
|
|
454 (if_then_else (ne (match_operand:CCV4 0 "register_operand" "z")
|
|
|
455 (const_int -1))
|
|
|
456 (label_ref (match_operand 1 "" ""))
|
|
|
457 (pc)))]
|
|
|
458 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
|
|
459 "%*bc1any4f\t%0,%1%/"
|
|
|
460 [(set_attr "type" "branch")
|
|
|
461 (set_attr "mode" "none")])
|
|
|
462
|
|
|
463 ; Branch on Any of Two Floating Point Condition Codes True
|
|
|
464 (define_insn "bc1any2t"
|
|
|
465 [(set (pc)
|
|
|
466 (if_then_else (ne (match_operand:CCV2 0 "register_operand" "z")
|
|
|
467 (const_int 0))
|
|
|
468 (label_ref (match_operand 1 "" ""))
|
|
|
469 (pc)))]
|
|
|
470 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
|
|
471 "%*bc1any2t\t%0,%1%/"
|
|
|
472 [(set_attr "type" "branch")
|
|
|
473 (set_attr "mode" "none")])
|
|
|
474
|
|
|
475 ; Branch on Any of Two Floating Point Condition Codes False
|
|
|
476 (define_insn "bc1any2f"
|
|
|
477 [(set (pc)
|
|
|
478 (if_then_else (ne (match_operand:CCV2 0 "register_operand" "z")
|
|
|
479 (const_int -1))
|
|
|
480 (label_ref (match_operand 1 "" ""))
|
|
|
481 (pc)))]
|
|
|
482 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
|
|
483 "%*bc1any2f\t%0,%1%/"
|
|
|
484 [(set_attr "type" "branch")
|
|
|
485 (set_attr "mode" "none")])
|
|
|
486
|
|
|
487 ; Used to access one register in a CCV2 pair. Operand 0 is the register
|
|
|
488 ; pair and operand 1 is the index of the register we want (a CONST_INT).
|
|
|
489 (define_expand "single_cc"
|
|
|
490 [(ne (unspec:CC [(match_operand 0) (match_operand 1)] UNSPEC_SINGLE_CC)
|
|
|
491 (const_int 0))])
|
|
|
492
|
|
|
493 ; This is a normal floating-point branch pattern, but rather than check
|
|
|
494 ; a single CCmode register, it checks one register in a CCV2 pair.
|
|
|
495 ; Operand 2 is the register pair and operand 3 is the index of the
|
|
|
496 ; register we want.
|
|
|
497 (define_insn "*branch_upper_lower"
|
|
|
498 [(set (pc)
|
|
|
499 (if_then_else
|
|
|
500 (match_operator 0 "equality_operator"
|
|
|
501 [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z")
|
|
|
502 (match_operand 3 "const_int_operand")]
|
|
|
503 UNSPEC_SINGLE_CC)
|
|
|
504 (const_int 0)])
|
|
|
505 (label_ref (match_operand 1 "" ""))
|
|
|
506 (pc)))]
|
|
|
507 "TARGET_HARD_FLOAT"
|
|
|
508 {
|
|
|
509 operands[2]
|
|
|
510 = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3]));
|
|
|
511 return mips_output_conditional_branch (insn, operands,
|
|
|
512 MIPS_BRANCH ("b%F0", "%2,%1"),
|
|
|
513 MIPS_BRANCH ("b%W0", "%2,%1"));
|
|
|
514 }
|
|
|
515 [(set_attr "type" "branch")
|
|
|
516 (set_attr "mode" "none")])
|
|
|
517
|
|
|
518 ; As above, but with the sense of the condition reversed.
|
|
|
519 (define_insn "*branch_upper_lower_inverted"
|
|
|
520 [(set (pc)
|
|
|
521 (if_then_else
|
|
|
522 (match_operator 0 "equality_operator"
|
|
|
523 [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z")
|
|
|
524 (match_operand 3 "const_int_operand")]
|
|
|
525 UNSPEC_SINGLE_CC)
|
|
|
526 (const_int 0)])
|
|
|
527 (pc)
|
|
|
528 (label_ref (match_operand 1 "" ""))))]
|
|
|
529 "TARGET_HARD_FLOAT"
|
|
|
530 {
|
|
|
531 operands[2]
|
|
|
532 = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3]));
|
|
|
533 return mips_output_conditional_branch (insn, operands,
|
|
|
534 MIPS_BRANCH ("b%W0", "%2,%1"),
|
|
|
535 MIPS_BRANCH ("b%F0", "%2,%1"));
|
|
|
536 }
|
|
|
537 [(set_attr "type" "branch")
|
|
|
538 (set_attr "mode" "none")])
|
|
|
539
|
|
|
540 ;----------------------------------------------------------------------------
|
|
|
541 ; Floating Point Reduced Precision Reciprocal Square Root Instructions.
|
|
|
542 ;----------------------------------------------------------------------------
|
|
|
543
|
|
|
544 (define_insn "mips_rsqrt1_<fmt>"
|
|
|
545 [(set (match_operand:ANYF 0 "register_operand" "=f")
|
|
|
546 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
|
|
|
547 UNSPEC_RSQRT1))]
|
|
|
548 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
|
|
549 "rsqrt1.<fmt>\t%0,%1"
|
|
|
550 [(set_attr "type" "frsqrt1")
|
|
|
551 (set_attr "mode" "<UNITMODE>")])
|
|
|
552
|
|
|
553 (define_insn "mips_rsqrt2_<fmt>"
|
|
|
554 [(set (match_operand:ANYF 0 "register_operand" "=f")
|
|
|
555 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")
|
|
|
556 (match_operand:ANYF 2 "register_operand" "f")]
|
|
|
557 UNSPEC_RSQRT2))]
|
|
|
558 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
|
|
559 "rsqrt2.<fmt>\t%0,%1,%2"
|
|
|
560 [(set_attr "type" "frsqrt2")
|
|
|
561 (set_attr "mode" "<UNITMODE>")])
|
|
|
562
|
|
|
563 (define_insn "mips_recip1_<fmt>"
|
|
|
564 [(set (match_operand:ANYF 0 "register_operand" "=f")
|
|
|
565 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
|
|
|
566 UNSPEC_RECIP1))]
|
|
|
567 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
|
|
568 "recip1.<fmt>\t%0,%1"
|
|
|
569 [(set_attr "type" "frdiv1")
|
|
|
570 (set_attr "mode" "<UNITMODE>")])
|
|
|
571
|
|
|
572 (define_insn "mips_recip2_<fmt>"
|
|
|
573 [(set (match_operand:ANYF 0 "register_operand" "=f")
|
|
|
574 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")
|
|
|
575 (match_operand:ANYF 2 "register_operand" "f")]
|
|
|
576 UNSPEC_RECIP2))]
|
|
|
577 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
|
|
578 "recip2.<fmt>\t%0,%1,%2"
|
|
|
579 [(set_attr "type" "frdiv2")
|
|
|
580 (set_attr "mode" "<UNITMODE>")])
|
|
|
581
|
|
|
582 (define_expand "vcondv2sf"
|
|
|
583 [(set (match_operand:V2SF 0 "register_operand")
|
|
|
584 (if_then_else:V2SF
|
|
|
585 (match_operator 3 ""
|
|
|
586 [(match_operand:V2SF 4 "register_operand")
|
|
|
587 (match_operand:V2SF 5 "register_operand")])
|
|
|
588 (match_operand:V2SF 1 "register_operand")
|
|
|
589 (match_operand:V2SF 2 "register_operand")))]
|
|
|
590 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
|
|
591 {
|
|
|
592 mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
|
|
|
593 GET_CODE (operands[3]), operands[4], operands[5]);
|
|
|
594 DONE;
|
|
|
595 })
|
|
|
596
|
|
|
597 (define_expand "sminv2sf3"
|
|
|
598 [(set (match_operand:V2SF 0 "register_operand")
|
|
|
599 (smin:V2SF (match_operand:V2SF 1 "register_operand")
|
|
|
600 (match_operand:V2SF 2 "register_operand")))]
|
|
|
601 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
|
|
602 {
|
|
|
603 mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
|
|
|
604 LE, operands[1], operands[2]);
|
|
|
605 DONE;
|
|
|
606 })
|
|
|
607
|
|
|
608 (define_expand "smaxv2sf3"
|
|
|
609 [(set (match_operand:V2SF 0 "register_operand")
|
|
|
610 (smax:V2SF (match_operand:V2SF 1 "register_operand")
|
|
|
611 (match_operand:V2SF 2 "register_operand")))]
|
|
|
612 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
|
|
|
613 {
|
|
|
614 mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
|
|
|
615 LE, operands[2], operands[1]);
|
|
|
616 DONE;
|
|
|
617 })
|
