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1 ;; Octeon pipeline description.
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2 ;; Copyright (C) 2008
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3 ;; Free Software Foundation, Inc.
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4
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify
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8 ;; it under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful,
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13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 ;; GNU General Public License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20 ;; Copyright (C) 2004, 2005, 2006 Cavium Networks.
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21
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22
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23 ;; Octeon is a dual-issue processor that can issue all instructions on
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24 ;; pipe0 and a subset on pipe1.
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25
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26 (define_automaton "octeon_main, octeon_mult")
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27
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28 (define_cpu_unit "octeon_pipe0" "octeon_main")
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29 (define_cpu_unit "octeon_pipe1" "octeon_main")
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30 (define_cpu_unit "octeon_mult" "octeon_mult")
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31
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32 (define_insn_reservation "octeon_arith" 1
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33 (and (eq_attr "cpu" "octeon")
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34 (eq_attr "type" "arith,const,logical,move,shift,signext,slt,nop"))
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35 "octeon_pipe0 | octeon_pipe1")
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36
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37 (define_insn_reservation "octeon_condmove" 2
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38 (and (eq_attr "cpu" "octeon")
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39 (eq_attr "type" "condmove"))
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40 "octeon_pipe0 | octeon_pipe1")
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41
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42 (define_insn_reservation "octeon_load" 2
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43 (and (eq_attr "cpu" "octeon")
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44 (eq_attr "type" "load,prefetch,mtc,mfc"))
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45 "octeon_pipe0")
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46
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47 (define_insn_reservation "octeon_store" 1
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48 (and (eq_attr "cpu" "octeon")
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49 (eq_attr "type" "store"))
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50 "octeon_pipe0")
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51
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52 (define_insn_reservation "octeon_brj" 1
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53 (and (eq_attr "cpu" "octeon")
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54 (eq_attr "type" "branch,jump,call,trap"))
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55 "octeon_pipe0")
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56
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57 (define_insn_reservation "octeon_imul3" 5
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58 (and (eq_attr "cpu" "octeon")
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59 (eq_attr "type" "imul3,pop,clz"))
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60 "(octeon_pipe0 | octeon_pipe1) + octeon_mult")
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61
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62 (define_insn_reservation "octeon_imul" 2
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63 (and (eq_attr "cpu" "octeon")
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64 (eq_attr "type" "imul,mthilo"))
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65 "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult")
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66
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67 (define_insn_reservation "octeon_mfhilo" 5
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68 (and (eq_attr "cpu" "octeon")
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69 (eq_attr "type" "mfhilo"))
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70 "(octeon_pipe0 | octeon_pipe1) + octeon_mult")
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71
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72 (define_insn_reservation "octeon_imadd" 4
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73 (and (eq_attr "cpu" "octeon")
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74 (eq_attr "type" "imadd"))
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75 "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*3")
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76
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77 (define_insn_reservation "octeon_idiv" 72
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78 (and (eq_attr "cpu" "octeon")
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79 (eq_attr "type" "idiv"))
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80 "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*71")
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81
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82 ;; Assume both pipes are needed for unknown and multiple-instruction
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83 ;; patterns.
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84
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85 (define_insn_reservation "octeon_unknown" 1
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86 (and (eq_attr "cpu" "octeon")
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87 (eq_attr "type" "unknown,multi"))
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88 "octeon_pipe0 + octeon_pipe1")
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