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1 ;;
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2 ;; DFA-based pipeline description for Broadcom SB-1
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3 ;;
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4
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5 ;; The Broadcom SB-1 core is 4-way superscalar, in-order. It has 2 load/store
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6 ;; pipes (one of which can support some ALU operations), 2 alu pipes, 2 FP
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7 ;; pipes, and 1 MDMX pipes. It can issue 2 ls insns and 2 exe/fpu/mdmx insns
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8 ;; each cycle.
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9
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10 ;; We model the 4-way issue by ordering unit choices. The possible choices are
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11 ;; {ex1,fp1}|{ex0,fp0}|ls1|ls0. Instructions issue to the first eligible unit
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12 ;; in the list in most cases. Non-indexed load/stores issue to ls0 first.
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13 ;; simple alu operations issue to ls1 if it is still available, and their
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14 ;; operands are ready (no co-issue with loads), otherwise to the first
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15 ;; available ex unit.
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16
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17 ;; When exceptions are enabled, can only issue FP insns to fp1. This is
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18 ;; to ensure that instructions complete in order. The -mfp-exceptions option
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19 ;; can be used to specify whether the system has FP exceptions enabled or not.
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20
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21 ;; In 32-bit mode, dependent FP can't co-issue with load, and only one FP exe
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22 ;; insn can issue per cycle (fp1).
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23
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24 ;; The A1 MDMX pipe is separate from the FP pipes, but uses the same register
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25 ;; file. As a result, once an MDMX insn is issued, no FP insns can be issued
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26 ;; for 3 cycles. When an FP insn is issued, no MDMX insn can be issued for
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27 ;; 5 cycles. This is currently not handled because there is no MDMX insn
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28 ;; support as yet.
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29
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30 ;;
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31 ;; We use two automata. sb1_cpu_div is for the integer divides, which are
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32 ;; not pipelined. sb1_cpu is for everything else.
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33 ;;
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34 (define_automaton "sb1_cpu, sb1_cpu_div")
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35
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36 ;; Load/store function units.
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37 (define_cpu_unit "sb1_ls0" "sb1_cpu")
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38 (define_cpu_unit "sb1_ls1" "sb1_cpu")
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39
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40 ;; CPU function units.
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41 (define_cpu_unit "sb1_ex0" "sb1_cpu")
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42 (define_cpu_unit "sb1_ex1" "sb1_cpu")
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43
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44 ;; The divide unit is not pipelined, and blocks hi/lo reads and writes.
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45 (define_cpu_unit "sb1_div" "sb1_cpu_div")
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46 ;; DMULT block any multiply from issuing in the next cycle.
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47 (define_cpu_unit "sb1_mul" "sb1_cpu")
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48
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49 ;; Floating-point units.
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50 (define_cpu_unit "sb1_fp0" "sb1_cpu")
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51 (define_cpu_unit "sb1_fp1" "sb1_cpu")
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52
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53 ;; Can only issue to one of the ex and fp pipes at a time.
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54 (exclusion_set "sb1_ex0" "sb1_fp0")
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55 (exclusion_set "sb1_ex1" "sb1_fp1")
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56
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57 ;; Define an SB-1 specific attribute to simplify some FP descriptions.
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58 ;; We can use 2 FP pipes only if we have 64-bit FP code, and exceptions are
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59 ;; disabled.
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60
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61 (define_attr "sb1_fp_pipes" "one,two"
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62 (cond [(and (ne (symbol_ref "TARGET_FLOAT64") (const_int 0))
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63 (eq (symbol_ref "TARGET_FP_EXCEPTIONS") (const_int 0)))
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64 (const_string "two")]
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65 (const_string "one")))
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66
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67 ;; Define reservations for common combinations.
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68
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69 ;; For long cycle operations, the FPU has a 4 cycle pipeline that repeats,
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70 ;; effectively re-issuing the operation every 4 cycles. This means that we
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71 ;; can have at most 4 long-cycle operations per pipe.
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72
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73 ;; ??? The fdiv operations should be e.g.
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74 ;; sb1_fp1_4cycles*7" | "sb1_fp0_4cycle*7
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75 ;; but the DFA is too large when we do that. Perhaps have to use scheduler
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76 ;; hooks here.
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77
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78 ;; ??? Try limiting scheduler to 2 long latency operations, and see if this
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79 ;; results in a usable DFA, and whether it helps code performance.
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80
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81 ;;(define_reservation "sb1_fp0_4cycles" "sb1_fp0, nothing*3")
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82 ;;(define_reservation "sb1_fp1_4cycles" "sb1_fp1, nothing*3")
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83
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84 ;;
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85 ;; The ordering of the instruction-execution-path/resource-usage
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86 ;; descriptions (also known as reservation RTL) is roughly ordered
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87 ;; based on the define attribute RTL for the "type" classification.
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88 ;; When modifying, remember that the first test that matches is the
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89 ;; reservation used!
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90 ;;
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91
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92 (define_insn_reservation "ir_sb1_unknown" 1
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93 (and (eq_attr "cpu" "sb1,sb1a")
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94 (eq_attr "type" "unknown,multi"))
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95 "sb1_ls0+sb1_ls1+sb1_ex0+sb1_ex1+sb1_fp0+sb1_fp1")
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96
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97 ;; predicted taken branch causes 2 cycle ifetch bubble. predicted not
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98 ;; taken branch causes 0 cycle ifetch bubble. mispredicted branch causes 8
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99 ;; cycle ifetch bubble. We assume all branches predicted not taken.
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100
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101 ;; ??? This assumption that branches are predicated not taken should be
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102 ;; investigated. Maybe using 2 here will give better results.
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103
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104 (define_insn_reservation "ir_sb1_branch" 0
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105 (and (eq_attr "cpu" "sb1,sb1a")
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106 (eq_attr "type" "branch,jump,call"))
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107 "sb1_ex0")
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108
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109 ;; ??? This is 1 cycle for ldl/ldr to ldl/ldr when they use the same data
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110 ;; register as destination.
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111
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112 ;; ??? SB-1 can co-issue a load with a dependent arith insn if it executes on
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113 ;; an EX unit. Can not co-issue if the dependent insn executes on an LS unit.
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114 ;; SB-1A can always co-issue here.
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115
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116 ;; A load normally has a latency of zero cycles. In some cases, dependent
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117 ;; insns can be issued in the same cycle. However, a value of 1 gives
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118 ;; better performance in empirical testing.
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119
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120 (define_insn_reservation "ir_sb1_load" 1
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121 (and (eq_attr "cpu" "sb1")
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122 (eq_attr "type" "load,prefetch"))
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123 "sb1_ls0 | sb1_ls1")
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124
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125 (define_insn_reservation "ir_sb1a_load" 0
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126 (and (eq_attr "cpu" "sb1a")
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127 (eq_attr "type" "load,prefetch"))
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128 "sb1_ls0 | sb1_ls1")
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129
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130 ;; Can not co-issue fpload with fp exe when in 32-bit mode.
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131
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132 (define_insn_reservation "ir_sb1_fpload" 0
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133 (and (eq_attr "cpu" "sb1,sb1a")
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134 (and (eq_attr "type" "fpload")
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135 (ne (symbol_ref "TARGET_FLOAT64")
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136 (const_int 0))))
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137 "sb1_ls0 | sb1_ls1")
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138
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139 (define_insn_reservation "ir_sb1_fpload_32bitfp" 1
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140 (and (eq_attr "cpu" "sb1,sb1a")
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141 (and (eq_attr "type" "fpload")
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142 (eq (symbol_ref "TARGET_FLOAT64")
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143 (const_int 0))))
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144 "sb1_ls0 | sb1_ls1")
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145
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146 ;; Indexed loads can only execute on LS1 pipe.
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147
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148 (define_insn_reservation "ir_sb1_fpidxload" 0
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149 (and (eq_attr "cpu" "sb1,sb1a")
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150 (and (eq_attr "type" "fpidxload")
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151 (ne (symbol_ref "TARGET_FLOAT64")
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152 (const_int 0))))
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153 "sb1_ls1")
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154
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155 (define_insn_reservation "ir_sb1_fpidxload_32bitfp" 1
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156 (and (eq_attr "cpu" "sb1,sb1a")
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157 (and (eq_attr "type" "fpidxload")
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158 (eq (symbol_ref "TARGET_FLOAT64")
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159 (const_int 0))))
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160 "sb1_ls1")
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161
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162 ;; prefx can only execute on the ls1 pipe.
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163
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164 (define_insn_reservation "ir_sb1_prefetchx" 0
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165 (and (eq_attr "cpu" "sb1,sb1a")
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166 (eq_attr "type" "prefetchx"))
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167 "sb1_ls1")
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168
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169 ;; ??? There is a 4.5 cycle latency if a store is followed by a load, and
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170 ;; there is a RAW dependency.
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171
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172 (define_insn_reservation "ir_sb1_store" 1
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173 (and (eq_attr "cpu" "sb1,sb1a")
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174 (eq_attr "type" "store"))
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175 "sb1_ls0+sb1_ex1 | sb1_ls0+sb1_ex0 | sb1_ls1+sb1_ex1 | sb1_ls1+sb1_ex0")
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176
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177 (define_insn_reservation "ir_sb1_fpstore" 1
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178 (and (eq_attr "cpu" "sb1,sb1a")
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179 (eq_attr "type" "fpstore"))
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180 "sb1_ls0+sb1_fp1 | sb1_ls0+sb1_fp0 | sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0")
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181
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182 ;; Indexed stores can only execute on LS1 pipe.
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183
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184 (define_insn_reservation "ir_sb1_fpidxstore" 1
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185 (and (eq_attr "cpu" "sb1,sb1a")
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186 (eq_attr "type" "fpidxstore"))
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187 "sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0")
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188
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189 ;; Load latencies are 3 cycles for one load to another load or store (address
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190 ;; only). This is 0 cycles for one load to a store using it as the data
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191 ;; written.
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192
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193 ;; This assumes that if a load is dependent on a previous insn, then it must
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194 ;; be an address dependence.
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195
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196 (define_bypass 3
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197 "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
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198 ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp"
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199 "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
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200 ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
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201
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202 (define_bypass 3
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203 "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
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204 ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp"
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205 "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
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206 "mips_store_data_bypass_p")
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207
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208 ;; On SB-1, simple alu instructions can execute on the LS1 unit.
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209
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210 ;; ??? A simple alu insn issued on an LS unit has 0 cycle latency to an EX
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211 ;; insn, to a store (for data), and to an xfer insn. It has 1 cycle latency to
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212 ;; another LS insn (excluding store data). A simple alu insn issued on an EX
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213 ;; unit has a latency of 5 cycles when the results goes to a LS unit (excluding
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214 ;; store data), otherwise a latency of 1 cycle.
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215
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216 ;; ??? We cannot handle latencies properly for simple alu instructions
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217 ;; within the DFA pipeline model. Latencies can be defined only from one
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218 ;; insn reservation to another. We can't make them depend on which function
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219 ;; unit was used. This isn't a DFA flaw. There is a conflict here, as we
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220 ;; need to know the latency before we can determine which unit will be
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221 ;; available, but we need to know which unit it is issued to before we can
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222 ;; compute the latency. Perhaps this can be handled via scheduler hooks.
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223 ;; This needs to be investigated.
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224
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225 ;; ??? Optimal scheduling taking the LS units into account seems to require
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226 ;; a pre-scheduling pass. We need to determine which instructions feed results
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227 ;; into store/load addresses, and thus benefit most from being issued to the
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228 ;; LS unit. Also, we need to prune the list to ensure we don't overschedule
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229 ;; insns to the LS unit, and that we don't conflict with insns that need LS1
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230 ;; such as indexed loads. We then need to emit nops to ensure that simple
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231 ;; alu instructions that are not supposed to be scheduled to LS1 don't
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232 ;; accidentally end up there because LS1 is free when they are issued. This
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233 ;; will be a lot of work, and it isn't clear how useful it will be.
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234
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235 ;; Empirical testing shows that 2 gives the best result.
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236
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237 (define_insn_reservation "ir_sb1_simple_alu" 2
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238 (and (eq_attr "cpu" "sb1")
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239 (eq_attr "type" "const,arith,logical,move,signext"))
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240 "sb1_ls1 | sb1_ex1 | sb1_ex0")
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241
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242 ;; On SB-1A, simple alu instructions can not execute on the LS1 unit, and we
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243 ;; have none of the above problems.
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244
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245 (define_insn_reservation "ir_sb1a_simple_alu" 1
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246 (and (eq_attr "cpu" "sb1a")
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247 (eq_attr "type" "const,arith,logical,move,signext"))
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248 "sb1_ex1 | sb1_ex0")
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249
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250 ;; ??? condmove also includes some FP instructions that execute on the FP
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251 ;; units. This needs to be clarified.
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252
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253 (define_insn_reservation "ir_sb1_alu" 1
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254 (and (eq_attr "cpu" "sb1,sb1a")
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255 (eq_attr "type" "condmove,nop,shift"))
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256 "sb1_ex1 | sb1_ex0")
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257
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258 ;; These are type arith/darith that only execute on the EX0 unit.
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259
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260 (define_insn_reservation "ir_sb1_alu_0" 1
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261 (and (eq_attr "cpu" "sb1,sb1a")
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262 (eq_attr "type" "slt,clz,trap"))
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263 "sb1_ex0")
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264
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265 ;; An alu insn issued on an EX unit has a latency of 5 cycles when the
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266 ;; result goes to a LS unit (excluding store data).
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267
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268 ;; This assumes that if a load is dependent on a previous insn, then it must
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269 ;; be an address dependence.
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270
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271 (define_bypass 5
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272 "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo"
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273 "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
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274 ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
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275
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276 (define_bypass 5
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277 "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo"
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278 "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
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279 "mips_store_data_bypass_p")
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280
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281 ;; mf{hi,lo} is 1 cycle.
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282
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283 (define_insn_reservation "ir_sb1_mfhi" 1
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284 (and (eq_attr "cpu" "sb1,sb1a")
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285 (and (eq_attr "type" "mfhilo")
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286 (not (match_operand 1 "lo_operand"))))
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287 "sb1_ex1")
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288
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289 (define_insn_reservation "ir_sb1_mflo" 1
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290 (and (eq_attr "cpu" "sb1,sb1a")
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291 (and (eq_attr "type" "mfhilo")
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292 (match_operand 1 "lo_operand")))
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293 "sb1_ex1")
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294
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295 ;; mt{hi,lo} to mul/div is 4 cycles.
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296
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297 (define_insn_reservation "ir_sb1_mthilo" 4
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298 (and (eq_attr "cpu" "sb1,sb1a")
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299 (eq_attr "type" "mthilo"))
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300 "sb1_ex1")
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301
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302 ;; mt{hi,lo} to mf{hi,lo} is 3 cycles.
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303
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304 (define_bypass 3 "ir_sb1_mthilo" "ir_sb1_mfhi,ir_sb1_mflo")
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305
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306 ;; multiply latency to an EX operation is 3 cycles.
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307
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308 ;; ??? Should check whether we need to make multiply conflict with moves
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309 ;; to/from hilo registers.
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310
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311 (define_insn_reservation "ir_sb1_mulsi" 3
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312 (and (eq_attr "cpu" "sb1,sb1a")
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313 (and (eq_attr "type" "imul,imul3,imadd")
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314 (eq_attr "mode" "SI")))
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315 "sb1_ex1+sb1_mul")
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316
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317 ;; muldi to mfhi is 4 cycles.
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318 ;; Blocks any other multiply insn issue for 1 cycle.
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319
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320 (define_insn_reservation "ir_sb1_muldi" 4
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321 (and (eq_attr "cpu" "sb1,sb1a")
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322 (and (eq_attr "type" "imul,imul3")
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323 (eq_attr "mode" "DI")))
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324 "sb1_ex1+sb1_mul, sb1_mul")
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325
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326 ;; muldi to mflo is 3 cycles.
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327
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328 (define_bypass 3 "ir_sb1_muldi" "ir_sb1_mflo")
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329
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330 ;; mul latency is 7 cycles if the result is used by any LS insn.
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331
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332 ;; This assumes that if a load is dependent on a previous insn, then it must
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333 ;; be an address dependence.
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334
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335 (define_bypass 7
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336 "ir_sb1_mulsi,ir_sb1_muldi"
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337 "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
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338 ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
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339
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340 (define_bypass 7
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341 "ir_sb1_mulsi,ir_sb1_muldi"
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342 "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
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343 "mips_store_data_bypass_p")
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344
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345 ;; The divide unit is not pipelined. Divide busy is asserted in the 4th
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346 ;; cycle, and then deasserted on the latency cycle. So only one divide at
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347 ;; a time, but the first/last 4 cycles can overlap.
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348
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349 ;; ??? All divides block writes to hi/lo regs. hi/lo regs are written 4 cycles
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350 ;; after the latency cycle for divides (e.g. 40/72). dmult writes lo in
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351 ;; cycle 7, and hi in cycle 8. All other insns write hi/lo regs in cycle 7.
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352 ;; Default for output dependencies is the difference in latencies, which is
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353 ;; only 1 cycle off here, e.g. div to mtlo stalls for 32 cycles, but should
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354 ;; stall for 33 cycles. This does not seem significant enough to worry about.
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355
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356 (define_insn_reservation "ir_sb1_divsi" 36
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357 (and (eq_attr "cpu" "sb1,sb1a")
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358 (and (eq_attr "type" "idiv")
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359 (eq_attr "mode" "SI")))
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360 "sb1_ex1, nothing*3, sb1_div*32")
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361
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362 (define_insn_reservation "ir_sb1_divdi" 68
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363 (and (eq_attr "cpu" "sb1,sb1a")
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364 (and (eq_attr "type" "idiv")
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365 (eq_attr "mode" "DI")))
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366 "sb1_ex1, nothing*3, sb1_div*64")
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367
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368 (define_insn_reservation "ir_sb1_fpu_2pipes" 4
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369 (and (eq_attr "cpu" "sb1,sb1a")
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370 (and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1")
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371 (eq_attr "sb1_fp_pipes" "two")))
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372 "sb1_fp1 | sb1_fp0")
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373
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374 (define_insn_reservation "ir_sb1_fpu_1pipe" 4
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375 (and (eq_attr "cpu" "sb1,sb1a")
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376 (and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1")
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377 (eq_attr "sb1_fp_pipes" "one")))
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378 "sb1_fp1")
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379
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380 (define_insn_reservation "ir_sb1_fpu_step2_2pipes" 8
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381 (and (eq_attr "cpu" "sb1,sb1a")
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382 (and (eq_attr "type" "frdiv2,frsqrt2")
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383 (eq_attr "sb1_fp_pipes" "two")))
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384 "sb1_fp1 | sb1_fp0")
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385
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386 (define_insn_reservation "ir_sb1_fpu_step2_1pipe" 8
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387 (and (eq_attr "cpu" "sb1,sb1a")
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388 (and (eq_attr "type" "frdiv2,frsqrt2")
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389 (eq_attr "sb1_fp_pipes" "one")))
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390 "sb1_fp1")
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391
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392 ;; ??? madd/msub 4-cycle latency to itself (same fr?), but 8 cycle latency
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393 ;; otherwise.
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394
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395 ;; ??? Blocks issue of another non-madd/msub after 4 cycles.
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396
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397 (define_insn_reservation "ir_sb1_fmadd_2pipes" 8
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398 (and (eq_attr "cpu" "sb1,sb1a")
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399 (and (eq_attr "type" "fmadd")
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400 (eq_attr "sb1_fp_pipes" "two")))
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401 "sb1_fp1 | sb1_fp0")
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402
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403 (define_insn_reservation "ir_sb1_fmadd_1pipe" 8
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404 (and (eq_attr "cpu" "sb1,sb1a")
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405 (and (eq_attr "type" "fmadd")
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406 (eq_attr "sb1_fp_pipes" "one")))
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407 "sb1_fp1")
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408
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409 (define_insn_reservation "ir_sb1_fcmp" 4
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410 (and (eq_attr "cpu" "sb1,sb1a")
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411 (eq_attr "type" "fcmp"))
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412 "sb1_fp1")
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413
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414 ;; mtc1 latency 5 cycles.
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415
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416 (define_insn_reservation "ir_sb1_mtxfer" 5
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417 (and (eq_attr "cpu" "sb1,sb1a")
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418 (eq_attr "type" "mtc"))
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419 "sb1_fp0")
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420
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421 ;; mfc1 latency 1 cycle.
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422
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423 (define_insn_reservation "ir_sb1_mfxfer" 1
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424 (and (eq_attr "cpu" "sb1,sb1a")
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425 (eq_attr "type" "mfc"))
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426 "sb1_fp0")
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427
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428 ;; ??? Can deliver at most 1 result per every 6 cycles because of issue
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429 ;; restrictions.
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430
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431 (define_insn_reservation "ir_sb1_divsf_2pipes" 24
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432 (and (eq_attr "cpu" "sb1,sb1a")
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433 (and (eq_attr "type" "fdiv")
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434 (and (eq_attr "mode" "SF")
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435 (eq_attr "sb1_fp_pipes" "two"))))
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436 "sb1_fp1 | sb1_fp0")
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437
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438 (define_insn_reservation "ir_sb1_divsf_1pipe" 24
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439 (and (eq_attr "cpu" "sb1,sb1a")
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440 (and (eq_attr "type" "fdiv")
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441 (and (eq_attr "mode" "SF")
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442 (eq_attr "sb1_fp_pipes" "one"))))
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443 "sb1_fp1")
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444
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445 ;; ??? Can deliver at most 1 result per every 8 cycles because of issue
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446 ;; restrictions.
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447
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448 (define_insn_reservation "ir_sb1_divdf_2pipes" 32
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449 (and (eq_attr "cpu" "sb1,sb1a")
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450 (and (eq_attr "type" "fdiv")
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451 (and (eq_attr "mode" "DF")
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452 (eq_attr "sb1_fp_pipes" "two"))))
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453 "sb1_fp1 | sb1_fp0")
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454
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455 (define_insn_reservation "ir_sb1_divdf_1pipe" 32
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456 (and (eq_attr "cpu" "sb1,sb1a")
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457 (and (eq_attr "type" "fdiv")
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458 (and (eq_attr "mode" "DF")
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459 (eq_attr "sb1_fp_pipes" "one"))))
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460 "sb1_fp1")
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461
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462 ;; ??? Can deliver at most 1 result per every 3 cycles because of issue
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463 ;; restrictions.
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464
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465 (define_insn_reservation "ir_sb1_recipsf_2pipes" 12
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466 (and (eq_attr "cpu" "sb1,sb1a")
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467 (and (eq_attr "type" "frdiv")
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468 (and (eq_attr "mode" "SF")
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469 (eq_attr "sb1_fp_pipes" "two"))))
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470 "sb1_fp1 | sb1_fp0")
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471
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472 (define_insn_reservation "ir_sb1_recipsf_1pipe" 12
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473 (and (eq_attr "cpu" "sb1,sb1a")
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474 (and (eq_attr "type" "frdiv")
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475 (and (eq_attr "mode" "SF")
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476 (eq_attr "sb1_fp_pipes" "one"))))
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477 "sb1_fp1")
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478
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479 ;; ??? Can deliver at most 1 result per every 5 cycles because of issue
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480 ;; restrictions.
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481
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482 (define_insn_reservation "ir_sb1_recipdf_2pipes" 20
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483 (and (eq_attr "cpu" "sb1,sb1a")
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484 (and (eq_attr "type" "frdiv")
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485 (and (eq_attr "mode" "DF")
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486 (eq_attr "sb1_fp_pipes" "two"))))
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487 "sb1_fp1 | sb1_fp0")
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488
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489 (define_insn_reservation "ir_sb1_recipdf_1pipe" 20
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490 (and (eq_attr "cpu" "sb1,sb1a")
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491 (and (eq_attr "type" "frdiv")
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492 (and (eq_attr "mode" "DF")
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493 (eq_attr "sb1_fp_pipes" "one"))))
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494 "sb1_fp1")
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495
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496 ;; ??? Can deliver at most 1 result per every 7 cycles because of issue
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497 ;; restrictions.
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498
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499 (define_insn_reservation "ir_sb1_sqrtsf_2pipes" 28
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500 (and (eq_attr "cpu" "sb1,sb1a")
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501 (and (eq_attr "type" "fsqrt")
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502 (and (eq_attr "mode" "SF")
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503 (eq_attr "sb1_fp_pipes" "two"))))
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504 "sb1_fp1 | sb1_fp0")
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505
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506 (define_insn_reservation "ir_sb1_sqrtsf_1pipe" 28
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507 (and (eq_attr "cpu" "sb1,sb1a")
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508 (and (eq_attr "type" "fsqrt")
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509 (and (eq_attr "mode" "SF")
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510 (eq_attr "sb1_fp_pipes" "one"))))
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511 "sb1_fp1")
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512
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513 ;; ??? Can deliver at most 1 result per every 10 cycles because of issue
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514 ;; restrictions.
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515
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516 (define_insn_reservation "ir_sb1_sqrtdf_2pipes" 40
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517 (and (eq_attr "cpu" "sb1,sb1a")
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518 (and (eq_attr "type" "fsqrt")
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519 (and (eq_attr "mode" "DF")
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520 (eq_attr "sb1_fp_pipes" "two"))))
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521 "sb1_fp1 | sb1_fp0")
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522
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523 (define_insn_reservation "ir_sb1_sqrtdf_1pipe" 40
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524 (and (eq_attr "cpu" "sb1,sb1a")
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525 (and (eq_attr "type" "fsqrt")
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526 (and (eq_attr "mode" "DF")
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527 (eq_attr "sb1_fp_pipes" "one"))))
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528 "sb1_fp1")
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529
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530 ;; ??? Can deliver at most 1 result per every 4 cycles because of issue
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531 ;; restrictions.
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532
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533 (define_insn_reservation "ir_sb1_rsqrtsf_2pipes" 16
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534 (and (eq_attr "cpu" "sb1,sb1a")
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535 (and (eq_attr "type" "frsqrt")
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536 (and (eq_attr "mode" "SF")
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537 (eq_attr "sb1_fp_pipes" "two"))))
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538 "sb1_fp1 | sb1_fp0")
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539
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540 (define_insn_reservation "ir_sb1_rsqrtsf_1pipe" 16
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541 (and (eq_attr "cpu" "sb1,sb1a")
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542 (and (eq_attr "type" "frsqrt")
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543 (and (eq_attr "mode" "SF")
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544 (eq_attr "sb1_fp_pipes" "one"))))
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545 "sb1_fp1")
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546
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547 ;; ??? Can deliver at most 1 result per every 7 cycles because of issue
|
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548 ;; restrictions.
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549
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550 (define_insn_reservation "ir_sb1_rsqrtdf_2pipes" 28
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551 (and (eq_attr "cpu" "sb1,sb1a")
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552 (and (eq_attr "type" "frsqrt")
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553 (and (eq_attr "mode" "DF")
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554 (eq_attr "sb1_fp_pipes" "two"))))
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555 "sb1_fp1 | sb1_fp0")
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556
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557 (define_insn_reservation "ir_sb1_rsqrtdf_1pipe" 28
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558 (and (eq_attr "cpu" "sb1,sb1a")
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559 (and (eq_attr "type" "frsqrt")
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560 (and (eq_attr "mode" "DF")
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561 (eq_attr "sb1_fp_pipes" "one"))))
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562 "sb1_fp1")
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