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1 ;; Scheduling description for PowerPC 603 processor.
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2 ;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published
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8 ;; by the Free Software Foundation; either version 3, or (at your
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9 ;; option) any later version.
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10
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11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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14 ;; License for more details.
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15
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_automaton "ppc603,ppc603fp")
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21 (define_cpu_unit "iu_603" "ppc603")
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22 (define_cpu_unit "fpu_603" "ppc603fp")
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23 (define_cpu_unit "lsu_603,bpu_603,sru_603" "ppc603")
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24
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25 ;; PPC603/PPC603e 32-bit IU, LSU, FPU, BPU, SRU
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26 ;; Max issue 3 insns/clock cycle (includes 1 branch)
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27
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28 ;; Branches go straight to the BPU. All other insns are handled
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29 ;; by a dispatch unit which can issue a max of 2 insns per cycle.
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30
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31 ;; The PPC603e user's manual recommends that to reduce branch mispredictions,
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32 ;; the insn that sets CR bits should be separated from the branch insn
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33 ;; that evaluates them; separation by more than 9 insns ensures that the CR
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34 ;; bits will be immediately available for execution.
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35 ;; This could be artificially achieved by exaggerating the latency of
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36 ;; compare insns but at the expense of a poorer schedule.
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37
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38 ;; CR insns get executed in the SRU. Not modelled.
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39
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40 (define_insn_reservation "ppc603-load" 2
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41 (and (eq_attr "type" "load,load_ext,load_ux,load_u,load_l")
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42 (eq_attr "cpu" "ppc603"))
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43 "lsu_603")
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44
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45 (define_insn_reservation "ppc603-store" 2
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46 (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
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47 (eq_attr "cpu" "ppc603"))
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48 "lsu_603*2")
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49
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50 (define_insn_reservation "ppc603-fpload" 2
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51 (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
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52 (eq_attr "cpu" "ppc603"))
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53 "lsu_603")
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54
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55 (define_insn_reservation "ppc603-storec" 8
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56 (and (eq_attr "type" "store_c")
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57 (eq_attr "cpu" "ppc603"))
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58 "lsu_603")
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59
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60 (define_insn_reservation "ppc603-integer" 1
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61 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\
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62 var_shift_rotate,cntlz,exts")
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63 (eq_attr "cpu" "ppc603"))
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64 "iu_603")
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65
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66 (define_insn_reservation "ppc603-two" 1
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67 (and (eq_attr "type" "two")
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68 (eq_attr "cpu" "ppc603"))
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69 "iu_603,iu_603")
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70
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71 (define_insn_reservation "ppc603-three" 1
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72 (and (eq_attr "type" "three")
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73 (eq_attr "cpu" "ppc603"))
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74 "iu_603,iu_603,iu_603")
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75
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76 ; This takes 2 or 3 cycles
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77 (define_insn_reservation "ppc603-imul" 3
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78 (and (eq_attr "type" "imul,imul_compare")
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79 (eq_attr "cpu" "ppc603"))
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80 "iu_603*2")
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81
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82 (define_insn_reservation "ppc603-imul2" 2
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83 (and (eq_attr "type" "imul2,imul3")
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84 (eq_attr "cpu" "ppc603"))
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85 "iu_603*2")
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86
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87 (define_insn_reservation "ppc603-idiv" 37
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88 (and (eq_attr "type" "idiv")
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89 (eq_attr "cpu" "ppc603"))
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90 "iu_603*37")
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91
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92 (define_insn_reservation "ppc603-compare" 3
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93 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\
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94 var_delayed_compare")
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95 (eq_attr "cpu" "ppc603"))
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96 "iu_603,nothing,bpu_603")
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97
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98 (define_insn_reservation "ppc603-fpcompare" 3
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99 (and (eq_attr "type" "fpcompare")
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100 (eq_attr "cpu" "ppc603"))
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101 "(fpu_603+iu_603*2),bpu_603")
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102
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103 (define_insn_reservation "ppc603-fp" 3
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104 (and (eq_attr "type" "fp")
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105 (eq_attr "cpu" "ppc603"))
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106 "fpu_603")
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107
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108 (define_insn_reservation "ppc603-dmul" 4
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109 (and (eq_attr "type" "dmul")
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110 (eq_attr "cpu" "ppc603"))
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111 "fpu_603*2")
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112
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113 ; Divides are not pipelined
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114 (define_insn_reservation "ppc603-sdiv" 18
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115 (and (eq_attr "type" "sdiv")
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116 (eq_attr "cpu" "ppc603"))
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117 "fpu_603*18")
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118
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119 (define_insn_reservation "ppc603-ddiv" 33
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120 (and (eq_attr "type" "ddiv")
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121 (eq_attr "cpu" "ppc603"))
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122 "fpu_603*33")
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123
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124 (define_insn_reservation "ppc603-crlogical" 2
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125 (and (eq_attr "type" "cr_logical,delayed_cr,mfcr,mtcr")
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126 (eq_attr "cpu" "ppc603"))
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127 "sru_603")
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128
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129 (define_insn_reservation "ppc603-mtjmpr" 4
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130 (and (eq_attr "type" "mtjmpr")
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131 (eq_attr "cpu" "ppc603"))
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132 "sru_603")
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133
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134 (define_insn_reservation "ppc603-mfjmpr" 2
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135 (and (eq_attr "type" "mfjmpr,isync,sync")
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136 (eq_attr "cpu" "ppc603"))
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137 "sru_603")
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138
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139 (define_insn_reservation "ppc603-jmpreg" 1
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140 (and (eq_attr "type" "jmpreg,branch")
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141 (eq_attr "cpu" "ppc603"))
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142 "bpu_603")
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143
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