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1 ;; Scheduling description for cell processor.
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2 ;; Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
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3 ;; Free Software Foundation, Inc.
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4 ;; Contributed by Sony Computer Entertainment, Inc.,
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5
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6
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7 ;; This file is free software; you can redistribute it and/or modify it under
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8 ;; the terms of the GNU General Public License as published by the Free
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9 ;; Software Foundation; either version 3 of the License, or (at your option)
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10 ;; any later version.
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11
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12 ;; This file is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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14 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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15 ;; for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; Sources: BE BOOK4 (/sfs/enc/doc/PPU_BookIV_DD3.0_latest.pdf)
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22
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23 ;; BE Architecture *DD3.0 and DD3.1*
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24 ;; This file simulate PPU processor unit backend of pipeline, maualP24.
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25 ;; manual P27, stall and flush points
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26 ;; IU, XU, VSU, dispatcher decodes and dispatch 2 insns per cycle in program
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27 ;; order, the grouped address are aligned by 8
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28 ;; This file only simulate one thread situation
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29 ;; XU executes all fixed point insns(3 units, a simple alu, a complex unit,
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30 ;; and load/store unit)
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31 ;; VSU executes all scalar floating points insn(a float unit),
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32 ;; VMX insns(VMX unit, 4 sub units, simple, permute, complex, floating point)
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33
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34 ;; Dual issue combination
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35
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36 ;; FXU LSU BR VMX VMX
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37 ;; (sx,cx,vsu_fp,fp_arith) (perm,vsu_ls,fp_ls)
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38 ;;FXU X
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39 ;;LSU X X X
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40 ;;BR X
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41 ;;VMX(sx,cx,vsu_fp,fp_arth) X
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42 ;;VMX(perm,vsu_ls, fp_ls) X
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43 ;; X are illegal combination.
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44
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45 ;; Dual issue exceptions:
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46 ;;(1) nop-pipelined FXU instr in slot 0
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47 ;;(2) non-pipelined FPU inst in slot 0
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48 ;; CSI instr(contex-synchronizing insn)
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49 ;; Microcode insn
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50
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51 ;; BRU unit: bru(none register stall), bru_cr(cr register stall)
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52 ;; VSU unit: vus(vmx simple), vup(vmx permute), vuc(vmx complex),
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53 ;; vuf(vmx float), fpu(floats). fpu_div is hypothetical, it is for
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54 ;; nonpipelined simulation
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55 ;; micr insns will stall at least 7 cycles to get the first instr from ROM,
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56 ;; micro instructions are not dual issued.
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57
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58 ;; slot0 is older than slot1
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59 ;; non-pipelined insn need to be in slot1 to avoid 1cycle stall
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60
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61 ;; There different stall point
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62 ;; IB2, only stall one thread if stall here, so try to stall here as much as
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63 ;; we can
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64 ;; condition(1) insert nop, OR and ORI instruction form
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65 ;; condition(2) flush happens, in case of: RAW, WAW, D-ERAT miss, or
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66 ;; CR0-access while stdcx, or stwcx
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67 ;; IS2 stall ;; Page91 for details
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68 ;; VQ8 stall
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69 ;; IS2 stall can be activated by VQ8 stall and trying to issue a vsu instr to
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70 ;; the vsu issue queue
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71
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72 ;;(define_automaton "cellxu")
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73
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74 ;;(define_cpu_unit "fxu_cell,lsu_cell,bru_cell,vsu1_cell,vsu2_cell" "cellxu")
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75
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76 ;; ndfa
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77 (define_automaton "cellxu,cellvsu,cellbru,cell_mis")
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78
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79 (define_cpu_unit "fxu_cell,lsu_cell" "cellxu")
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80 (define_cpu_unit "bru_cell" "cellbru")
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81 (define_cpu_unit "vsu1_cell,vsu2_cell" "cellvsu")
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82
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83 (define_cpu_unit "slot0,slot1" "cell_mis")
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84
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85 (absence_set "slot0" "slot1")
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86
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87 (define_reservation "nonpipeline" "fxu_cell+lsu_cell+vsu1_cell+vsu2_cell")
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88 (define_reservation "slot01" "slot0|slot1")
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89
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90
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91 ;; Load/store
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92 ;; lmw, lswi, lswx are only generated for optimize for space, MC,
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93 ;; these instr are not simulated
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94 (define_insn_reservation "cell-load" 2
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95 (and (eq_attr "type" "load")
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96 (eq_attr "cpu" "cell"))
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97 "slot01,lsu_cell")
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98
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99 ;; ldux, ldu, lbzux, lbzu, hardware breaks it down to two instrs,
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100 ;; if with 32bytes alignment, CMC
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101 (define_insn_reservation "cell-load-ux" 2
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102 (and (eq_attr "type" "load_ux,load_u")
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103 (eq_attr "cpu" "cell"))
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104 "slot01,fxu_cell+lsu_cell")
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105
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106 ;; lha, lhax, lhau, lhaux, lwa, lwax, lwaux, MC, latency unknown
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107 ;; 11/7, 11/8, 11/12
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108 (define_insn_reservation "cell-load-ext" 2
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109 (and (eq_attr "type" "load_ext,load_ext_u,load_ext_ux")
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110 (eq_attr "cpu" "cell"))
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111 "slot01,fxu_cell+lsu_cell")
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112
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113 ;;lfs,lfsx,lfd,lfdx, 1 cycle
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114 (define_insn_reservation "cell-fpload" 1
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115 (and (eq_attr "type" "fpload")
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116 (eq_attr "cpu" "cell"))
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117 "vsu2_cell+lsu_cell+slot01")
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118
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119 ;; lfsu,lfsux,lfdu,lfdux 1cycle(fpr) 2 cycle(gpr)
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120 (define_insn_reservation "cell-fpload-update" 1
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121 (and (eq_attr "type" "fpload,fpload_u,fpload_ux")
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122 (eq_attr "cpu" "cell"))
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123 "fxu_cell+vsu2_cell+lsu_cell+slot01")
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124
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125 (define_insn_reservation "cell-vecload" 2
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126 (and (eq_attr "type" "vecload")
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127 (eq_attr "cpu" "cell"))
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128 "slot01,vsu2_cell+lsu_cell")
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129
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130 ;;st? stw(MC)
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131 (define_insn_reservation "cell-store" 1
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132 (and (eq_attr "type" "store")
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133 (eq_attr "cpu" "cell"))
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134 "lsu_cell+slot01")
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135
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136 ;;stdux, stdu, (hardware breaks into store and add) 2 for update reg
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137 (define_insn_reservation "cell-store-update" 1
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138 (and (eq_attr "type" "store_ux,store_u")
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139 (eq_attr "cpu" "cell"))
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140 "fxu_cell+lsu_cell+slot01")
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141
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142 (define_insn_reservation "cell-fpstore" 1
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143 (and (eq_attr "type" "fpstore")
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144 (eq_attr "cpu" "cell"))
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145 "vsu2_cell+lsu_cell+slot01")
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146
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147 (define_insn_reservation "cell-fpstore-update" 1
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148 (and (eq_attr "type" "fpstore_ux,fpstore_u")
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149 (eq_attr "cpu" "cell"))
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150 "vsu2_cell+fxu_cell+lsu_cell+slot01")
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151
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152 (define_insn_reservation "cell-vecstore" 1
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153 (and (eq_attr "type" "vecstore")
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154 (eq_attr "cpu" "cell"))
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155 "vsu2_cell+lsu_cell+slot01")
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156
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157 ;; Integer latency is 2 cycles
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158 (define_insn_reservation "cell-integer" 2
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159 (and (eq_attr "type" "integer,insert_dword,shift,trap,\
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160 var_shift_rotate,cntlz,exts")
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161 (eq_attr "cpu" "cell"))
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162 "slot01,fxu_cell")
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163
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164 ;; Two integer latency is 4 cycles
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165 (define_insn_reservation "cell-two" 4
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166 (and (eq_attr "type" "two")
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167 (eq_attr "cpu" "cell"))
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168 "slot01,fxu_cell,fxu_cell*2")
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169
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170 ;; Three integer latency is 6 cycles
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171 (define_insn_reservation "cell-three" 6
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172 (and (eq_attr "type" "three")
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173 (eq_attr "cpu" "cell"))
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174 "slot01,fxu_cell,fxu_cell*4")
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175
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176 ;; rlwimi, alter cr0
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177 (define_insn_reservation "cell-insert" 2
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178 (and (eq_attr "type" "insert_word")
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179 (eq_attr "cpu" "cell"))
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180 "slot01,fxu_cell")
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181
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182 ;; cmpi, cmpli, cmpla, add, addo, sub, subo, alter cr0
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183 (define_insn_reservation "cell-cmp" 1
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184 (and (eq_attr "type" "cmp")
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185 (eq_attr "cpu" "cell"))
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186 "fxu_cell+slot01")
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187
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188 ;; add, addo, sub, subo, alter cr0, rldcli, rlwinm
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189 (define_insn_reservation "cell-fast-cmp" 2
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190 (and (and (eq_attr "type" "fast_compare,delayed_compare,compare,\
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191 var_delayed_compare")
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192 (eq_attr "cpu" "cell"))
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193 (eq_attr "cell_micro" "not"))
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194 "slot01,fxu_cell")
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195
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196 (define_insn_reservation "cell-cmp-microcoded" 9
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197 (and (and (eq_attr "type" "fast_compare,delayed_compare,compare,\
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198 var_delayed_compare")
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199 (eq_attr "cpu" "cell"))
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200 (eq_attr "cell_micro" "always"))
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201 "slot0+slot1,fxu_cell,fxu_cell*7")
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202
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203 ;; mulld
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204 (define_insn_reservation "cell-lmul" 15
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205 (and (eq_attr "type" "lmul")
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206 (eq_attr "cpu" "cell"))
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207 "slot1,nonpipeline,nonpipeline*13")
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208
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209 ;; mulld. is microcoded
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210 (define_insn_reservation "cell-lmul-cmp" 22
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211 (and (eq_attr "type" "lmul_compare")
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212 (eq_attr "cpu" "cell"))
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213 "slot0+slot1,nonpipeline,nonpipeline*20")
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214
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215 ;; mulli, 6 cycles
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216 (define_insn_reservation "cell-imul23" 6
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217 (and (eq_attr "type" "imul2,imul3")
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218 (eq_attr "cpu" "cell"))
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219 "slot1,nonpipeline,nonpipeline*4")
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220
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221 ;; mullw, 9
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222 (define_insn_reservation "cell-imul" 9
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223 (and (eq_attr "type" "imul")
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224 (eq_attr "cpu" "cell"))
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225 "slot1,nonpipeline,nonpipeline*7")
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226
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227 ;; divide
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228 (define_insn_reservation "cell-idiv" 32
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229 (and (eq_attr "type" "idiv")
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230 (eq_attr "cpu" "cell"))
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231 "slot1,nonpipeline,nonpipeline*30")
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232
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233 (define_insn_reservation "cell-ldiv" 64
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234 (and (eq_attr "type" "ldiv")
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235 (eq_attr "cpu" "cell"))
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236 "slot1,nonpipeline,nonpipeline*62")
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237
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238 ;;mflr and mfctr are pipelined
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239 (define_insn_reservation "cell-mfjmpr" 1
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240 (and (eq_attr "type" "mfjmpr")
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241 (eq_attr "cpu" "cell"))
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242 "slot01+bru_cell")
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243
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244 ;;mtlr and mtctr,
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245 ;;mtspr fully pipelined
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246 (define_insn_reservation "cell-mtjmpr" 1
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247 (and (eq_attr "type" "mtjmpr")
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248 (eq_attr "cpu" "cell"))
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249 "bru_cell+slot01")
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250
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251 ;; Branches
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252 ;; b, ba, bl, bla, unconditional branch always predicts correctly n/a latency
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253 ;; bcctr, bcctrl, latency 2, actually adjust by be to 4
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254 (define_insn_reservation "cell-branch" 1
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255 (and (eq_attr "type" "branch")
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256 (eq_attr "cpu" "cell"))
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257 "bru_cell+slot1")
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258
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259 (define_insn_reservation "cell-branchreg" 1
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260 (and (eq_attr "type" "jmpreg")
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261 (eq_attr "cpu" "cell"))
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262 "bru_cell+slot1")
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263
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264 ;; cr hazard
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265 ;; page 90, special cases for CR hazard, only one instr can access cr per cycle
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266 ;; if insn reads CR following a stwcx, pipeline stall till stwcx finish
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267 (define_insn_reservation "cell-crlogical" 1
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268 (and (eq_attr "type" "cr_logical,delayed_cr")
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269 (eq_attr "cpu" "cell"))
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270 "bru_cell+slot01")
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271
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272 ;; mfcrf and mfcr is about 34 cycles and nonpipelined
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273 (define_insn_reservation "cell-mfcr" 34
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274 (and (eq_attr "type" "mfcrf,mfcr")
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275 (eq_attr "cpu" "cell"))
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276 "slot1,nonpipeline,nonpipeline*32")
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277
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278 ;; mtcrf (1 field)
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279 (define_insn_reservation "cell-mtcrf" 1
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280 (and (eq_attr "type" "mtcr")
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281 (eq_attr "cpu" "cell"))
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282 "fxu_cell+slot01")
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283
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284 ; Basic FP latency is 10 cycles, thoughput is 1/cycle
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285 (define_insn_reservation "cell-fp" 10
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286 (and (eq_attr "type" "fp,dmul")
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287 (eq_attr "cpu" "cell"))
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288 "slot01,vsu1_cell,vsu1_cell*8")
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289
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290 (define_insn_reservation "cell-fpcompare" 1
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291 (and (eq_attr "type" "fpcompare")
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292 (eq_attr "cpu" "cell"))
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293 "vsu1_cell+slot01")
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294
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295 ;; sdiv thoughput 1/74, not pipelined but only in the FPU
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296 (define_insn_reservation "cell-sdiv" 74
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297 (and (eq_attr "type" "sdiv,ddiv")
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298 (eq_attr "cpu" "cell"))
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299 "slot1,nonpipeline,nonpipeline*72")
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300
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301 ;; fsqrt thoughput 1/84, not pipelined but only in the FPU
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302 (define_insn_reservation "cell-sqrt" 84
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303 (and (eq_attr "type" "ssqrt,dsqrt")
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304 (eq_attr "cpu" "cell"))
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305 "slot1,nonpipeline,nonpipeline*82")
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306
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307 ; VMX
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308 (define_insn_reservation "cell-vecsimple" 4
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309 (and (eq_attr "type" "vecsimple")
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310 (eq_attr "cpu" "cell"))
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311 "slot01,vsu1_cell,vsu1_cell*2")
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312
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313 ;; mult, div, madd
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314 (define_insn_reservation "cell-veccomplex" 10
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315 (and (eq_attr "type" "veccomplex")
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316 (eq_attr "cpu" "cell"))
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317 "slot01,vsu1_cell,vsu1_cell*8")
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318
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319 ;; TODO: add support for recording instructions
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320 (define_insn_reservation "cell-veccmp" 4
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321 (and (eq_attr "type" "veccmp")
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322 (eq_attr "cpu" "cell"))
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323 "slot01,vsu1_cell,vsu1_cell*2")
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324
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325 (define_insn_reservation "cell-vecfloat" 12
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326 (and (eq_attr "type" "vecfloat")
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327 (eq_attr "cpu" "cell"))
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328 "slot01,vsu1_cell,vsu1_cell*10")
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329
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330 (define_insn_reservation "cell-vecperm" 4
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331 (and (eq_attr "type" "vecperm")
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332 (eq_attr "cpu" "cell"))
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333 "slot01,vsu2_cell,vsu2_cell*2")
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334
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335 ;; New for 4.2, syncs
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336
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337 (define_insn_reservation "cell-sync" 11
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338 (and (eq_attr "type" "sync")
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339 (eq_attr "cpu" "cell"))
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340 "slot01,lsu_cell,lsu_cell*9")
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341
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342 (define_insn_reservation "cell-isync" 11
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343 (and (eq_attr "type" "isync")
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344 (eq_attr "cpu" "cell"))
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345 "slot01,lsu_cell,lsu_cell*9")
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346
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347 (define_insn_reservation "cell-load_l" 11
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348 (and (eq_attr "type" "load_l")
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349 (eq_attr "cpu" "cell"))
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350 "slot01,lsu_cell,lsu_cell*9")
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351
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352 (define_insn_reservation "cell-store_c" 11
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353 (and (eq_attr "type" "store_c")
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354 (eq_attr "cpu" "cell"))
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355 "slot01,lsu_cell,lsu_cell*9")
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356
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357 ;; RAW register dependency
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358
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359 ;; addi r3, r3, 1
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360 ;; lw r4,offset(r3)
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361 ;; there are 5 cycle deplay for r3 bypassing
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362 ;; there are 5 cycle delay for a dependent load after a load
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363 (define_bypass 5 "cell-integer" "cell-load")
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364 (define_bypass 5 "cell-integer" "cell-load-ext")
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365 (define_bypass 5 "cell-load,cell-load-ext" "cell-load,cell-load-ext")
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366
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367 ;; there is a 6 cycle delay after a fp compare until you can use the cr.
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368 (define_bypass 6 "cell-fpcompare" "cell-branch,cell-branchreg,cell-mfcr,cell-crlogical")
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369
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370 ;; VXU float RAW
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371 (define_bypass 11 "cell-vecfloat" "cell-vecfloat")
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372
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373 ;; VXU and FPU
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374 (define_bypass 6 "cell-veccomplex" "cell-vecsimple")
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375 ;;(define_bypass 6 "cell-veccompare" "cell-branch,cell-branchreg")
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376 (define_bypass 3 "cell-vecfloat" "cell-veccomplex")
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377 ; this is not correct,
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378 ;; this is a stall in general and not dependent on result
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379 (define_bypass 13 "cell-vecstore" "cell-fpstore")
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380 ; this is not correct, this can never be true, not dependent on result
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381 (define_bypass 7 "cell-fp" "cell-fpload")
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382 ;; vsu1 should avoid writing to the same target register as vsu2 insn
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383 ;; within 12 cycles.
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384
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385 ;; WAW hazard
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386
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387 ;; the target of VSU estimate should not be reused within 10 dispatch groups
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388 ;; the target of VSU float should not be reused within 8 dispatch groups
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389 ;; the target of VSU complex should not be reused within 5 dispatch groups
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390 ;; FP LOAD should not reuse an FPU Arithmetic target with 6 dispatch gropus
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391
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392 ;; mtctr-bcctr/bcctrl, branch target ctr register shadow update at
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393 ;; ex4 stage(10 cycles)
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394 (define_bypass 10 "cell-mtjmpr" "cell-branchreg")
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395
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396 ;;Things are not simulated:
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397 ;; update instruction, update address gpr are not simulated
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398 ;; vrefp, vrsqrtefp have latency(14), currently simulated as 12 cycle float
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399 ;; insns
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400
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