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1 ;; Scheduling description for IBM POWER5 processor.
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2 ;; Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published
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8 ;; by the Free Software Foundation; either version 3, or (at your
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9 ;; option) any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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14 ;; License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; Sources: IBM Red Book and White Paper on POWER5
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21
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22 ;; The POWER5 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip).
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23 ;; Instructions that update more than one register get broken into two
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24 ;; (split) or more internal ops. The chip can issue up to 5
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25 ;; internal ops per cycle.
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26
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27 (define_automaton "power5iu,power5fpu,power5misc")
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28
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29 (define_cpu_unit "iu1_power5,iu2_power5" "power5iu")
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30 (define_cpu_unit "lsu1_power5,lsu2_power5" "power5misc")
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31 (define_cpu_unit "fpu1_power5,fpu2_power5" "power5fpu")
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32 (define_cpu_unit "bpu_power5,cru_power5" "power5misc")
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33 (define_cpu_unit "du1_power5,du2_power5,du3_power5,du4_power5,du5_power5"
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34 "power5misc")
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35
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36 (define_reservation "lsq_power5"
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37 "(du1_power5,lsu1_power5)\
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38 |(du2_power5,lsu2_power5)\
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39 |(du3_power5,lsu2_power5)\
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40 |(du4_power5,lsu1_power5)")
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41
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42 (define_reservation "iq_power5"
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43 "(du1_power5,iu1_power5)\
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44 |(du2_power5,iu2_power5)\
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45 |(du3_power5,iu2_power5)\
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46 |(du4_power5,iu1_power5)")
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47
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48 (define_reservation "fpq_power5"
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49 "(du1_power5,fpu1_power5)\
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50 |(du2_power5,fpu2_power5)\
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51 |(du3_power5,fpu2_power5)\
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52 |(du4_power5,fpu1_power5)")
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53
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54 ; Dispatch slots are allocated in order conforming to program order.
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55 (absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5")
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56 (absence_set "du2_power5" "du3_power5,du4_power5,du5_power5")
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57 (absence_set "du3_power5" "du4_power5,du5_power5")
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58 (absence_set "du4_power5" "du5_power5")
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59
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60
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61 ; Load/store
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62 (define_insn_reservation "power5-load" 4 ; 3
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63 (and (eq_attr "type" "load")
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64 (eq_attr "cpu" "power5"))
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65 "lsq_power5")
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66
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67 (define_insn_reservation "power5-load-ext" 5
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68 (and (eq_attr "type" "load_ext")
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69 (eq_attr "cpu" "power5"))
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70 "du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5")
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71
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72 (define_insn_reservation "power5-load-ext-update" 5
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73 (and (eq_attr "type" "load_ext_u")
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74 (eq_attr "cpu" "power5"))
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75 "du1_power5+du2_power5+du3_power5+du4_power5,\
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76 lsu1_power5+iu2_power5,nothing,nothing,iu2_power5")
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77
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78 (define_insn_reservation "power5-load-ext-update-indexed" 5
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79 (and (eq_attr "type" "load_ext_ux")
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80 (eq_attr "cpu" "power5"))
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81 "du1_power5+du2_power5+du3_power5+du4_power5,\
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82 iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5")
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83
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84 (define_insn_reservation "power5-load-update-indexed" 3
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85 (and (eq_attr "type" "load_ux")
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86 (eq_attr "cpu" "power5"))
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87 "du1_power5+du2_power5+du3_power5+du4_power5,\
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88 iu1_power5,lsu2_power5+iu2_power5")
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89
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90 (define_insn_reservation "power5-load-update" 4 ; 3
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91 (and (eq_attr "type" "load_u")
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92 (eq_attr "cpu" "power5"))
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93 "du1_power5+du2_power5,lsu1_power5+iu2_power5")
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94
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95 (define_insn_reservation "power5-fpload" 6 ; 5
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96 (and (eq_attr "type" "fpload")
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97 (eq_attr "cpu" "power5"))
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98 "lsq_power5")
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99
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100 (define_insn_reservation "power5-fpload-update" 6 ; 5
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101 (and (eq_attr "type" "fpload_u,fpload_ux")
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102 (eq_attr "cpu" "power5"))
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103 "du1_power5+du2_power5,lsu1_power5+iu2_power5")
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104
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105 (define_insn_reservation "power5-store" 12
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106 (and (eq_attr "type" "store")
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107 (eq_attr "cpu" "power5"))
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108 "(du1_power5,lsu1_power5,iu1_power5)\
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109 |(du2_power5,lsu2_power5,iu2_power5)\
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110 |(du3_power5,lsu2_power5,iu2_power5)\
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111 |(du4_power5,lsu1_power5,iu1_power5)")
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112
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113 (define_insn_reservation "power5-store-update" 12
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114 (and (eq_attr "type" "store_u")
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115 (eq_attr "cpu" "power5"))
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116 "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5")
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117
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118 (define_insn_reservation "power5-store-update-indexed" 12
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119 (and (eq_attr "type" "store_ux")
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120 (eq_attr "cpu" "power5"))
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121 "du1_power5+du2_power5+du3_power5+du4_power5,\
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122 iu1_power5,lsu2_power5+iu2_power5,iu2_power5")
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123
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124 (define_insn_reservation "power5-fpstore" 12
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125 (and (eq_attr "type" "fpstore")
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126 (eq_attr "cpu" "power5"))
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127 "(du1_power5,lsu1_power5,fpu1_power5)\
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128 |(du2_power5,lsu2_power5,fpu2_power5)\
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129 |(du3_power5,lsu2_power5,fpu2_power5)\
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130 |(du4_power5,lsu1_power5,fpu1_power5)")
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131
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132 (define_insn_reservation "power5-fpstore-update" 12
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133 (and (eq_attr "type" "fpstore_u,fpstore_ux")
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134 (eq_attr "cpu" "power5"))
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135 "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5")
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136
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137 (define_insn_reservation "power5-llsc" 11
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138 (and (eq_attr "type" "load_l,store_c,sync")
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139 (eq_attr "cpu" "power5"))
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140 "du1_power5+du2_power5+du3_power5+du4_power5,\
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141 lsu1_power5")
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142
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143
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144 ; Integer latency is 2 cycles
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145 (define_insn_reservation "power5-integer" 2
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146 (and (eq_attr "type" "integer,insert_dword,shift,trap,\
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147 var_shift_rotate,cntlz,exts")
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148 (eq_attr "cpu" "power5"))
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149 "iq_power5")
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150
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151 (define_insn_reservation "power5-two" 2
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152 (and (eq_attr "type" "two")
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153 (eq_attr "cpu" "power5"))
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154 "(du1_power5+du2_power5,iu1_power5,nothing,iu2_power5)\
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155 |(du2_power5+du3_power5,iu2_power5,nothing,iu2_power5)\
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156 |(du3_power5+du4_power5,iu2_power5,nothing,iu1_power5)\
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157 |(du4_power5+du1_power5,iu1_power5,nothing,iu1_power5)")
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158
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159 (define_insn_reservation "power5-three" 2
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160 (and (eq_attr "type" "three")
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161 (eq_attr "cpu" "power5"))
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162 "(du1_power5+du2_power5+du3_power5,\
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163 iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\
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164 |(du2_power5+du3_power5+du4_power5,\
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165 iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\
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166 |(du3_power5+du4_power5+du1_power5,\
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167 iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\
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168 |(du4_power5+du1_power5+du2_power5,\
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169 iu1_power5,nothing,iu2_power5,nothing,iu2_power5)")
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170
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171 (define_insn_reservation "power5-insert" 4
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172 (and (eq_attr "type" "insert_word")
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173 (eq_attr "cpu" "power5"))
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174 "du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")
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175
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176 (define_insn_reservation "power5-cmp" 3
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177 (and (eq_attr "type" "cmp,fast_compare")
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178 (eq_attr "cpu" "power5"))
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179 "iq_power5")
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180
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181 (define_insn_reservation "power5-compare" 2
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182 (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare")
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183 (eq_attr "cpu" "power5"))
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184 "du1_power5+du2_power5,iu1_power5,iu2_power5")
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185
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186 (define_bypass 4 "power5-compare" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
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187
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188 (define_insn_reservation "power5-lmul-cmp" 7
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189 (and (eq_attr "type" "lmul_compare")
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190 (eq_attr "cpu" "power5"))
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191 "du1_power5+du2_power5,iu1_power5*6,iu2_power5")
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192
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193 (define_bypass 10 "power5-lmul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
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194
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195 (define_insn_reservation "power5-imul-cmp" 5
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196 (and (eq_attr "type" "imul_compare")
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197 (eq_attr "cpu" "power5"))
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198 "du1_power5+du2_power5,iu1_power5*4,iu2_power5")
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199
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200 (define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
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201
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202 (define_insn_reservation "power5-lmul" 7
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203 (and (eq_attr "type" "lmul")
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204 (eq_attr "cpu" "power5"))
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205 "(du1_power5,iu1_power5*6)\
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206 |(du2_power5,iu2_power5*6)\
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207 |(du3_power5,iu2_power5*6)\
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208 |(du4_power5,iu1_power5*6)")
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209
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210 (define_insn_reservation "power5-imul" 5
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211 (and (eq_attr "type" "imul")
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212 (eq_attr "cpu" "power5"))
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213 "(du1_power5,iu1_power5*4)\
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214 |(du2_power5,iu2_power5*4)\
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215 |(du3_power5,iu2_power5*4)\
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216 |(du4_power5,iu1_power5*4)")
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217
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218 (define_insn_reservation "power5-imul3" 4
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219 (and (eq_attr "type" "imul2,imul3")
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220 (eq_attr "cpu" "power5"))
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221 "(du1_power5,iu1_power5*3)\
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222 |(du2_power5,iu2_power5*3)\
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223 |(du3_power5,iu2_power5*3)\
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224 |(du4_power5,iu1_power5*3)")
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225
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226
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227 ; SPR move only executes in first IU.
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228 ; Integer division only executes in second IU.
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229 (define_insn_reservation "power5-idiv" 36
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230 (and (eq_attr "type" "idiv")
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231 (eq_attr "cpu" "power5"))
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232 "du1_power5+du2_power5,iu2_power5*35")
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233
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234 (define_insn_reservation "power5-ldiv" 68
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235 (and (eq_attr "type" "ldiv")
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236 (eq_attr "cpu" "power5"))
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237 "du1_power5+du2_power5,iu2_power5*67")
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238
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239
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240 (define_insn_reservation "power5-mtjmpr" 3
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241 (and (eq_attr "type" "mtjmpr,mfjmpr")
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242 (eq_attr "cpu" "power5"))
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243 "du1_power5,bpu_power5")
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244
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245
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246 ; Branches take dispatch Slot 4. The presence_sets prevent other insn from
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247 ; grabbing previous dispatch slots once this is assigned.
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248 (define_insn_reservation "power5-branch" 2
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249 (and (eq_attr "type" "jmpreg,branch")
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250 (eq_attr "cpu" "power5"))
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251 "(du5_power5\
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252 |du4_power5+du5_power5\
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253 |du3_power5+du4_power5+du5_power5\
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254 |du2_power5+du3_power5+du4_power5+du5_power5\
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255 |du1_power5+du2_power5+du3_power5+du4_power5+du5_power5),bpu_power5")
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256
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257
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258 ; Condition Register logical ops are split if non-destructive (RT != RB)
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259 (define_insn_reservation "power5-crlogical" 2
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260 (and (eq_attr "type" "cr_logical")
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261 (eq_attr "cpu" "power5"))
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262 "du1_power5,cru_power5")
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263
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264 (define_insn_reservation "power5-delayedcr" 4
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265 (and (eq_attr "type" "delayed_cr")
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266 (eq_attr "cpu" "power5"))
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267 "du1_power5+du2_power5,cru_power5,cru_power5")
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268
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269 ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu
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270 (define_insn_reservation "power5-mfcr" 6
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271 (and (eq_attr "type" "mfcr")
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272 (eq_attr "cpu" "power5"))
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273 "du1_power5+du2_power5+du3_power5+du4_power5,\
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274 du1_power5+du2_power5+du3_power5+du4_power5+cru_power5,\
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275 cru_power5,cru_power5,cru_power5")
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276
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277 ; mfcrf (1 field)
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278 (define_insn_reservation "power5-mfcrf" 3
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279 (and (eq_attr "type" "mfcrf")
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280 (eq_attr "cpu" "power5"))
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281 "du1_power5,cru_power5")
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282
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283 ; mtcrf (1 field)
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284 (define_insn_reservation "power5-mtcr" 4
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285 (and (eq_attr "type" "mtcr")
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286 (eq_attr "cpu" "power5"))
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287 "du1_power5,iu1_power5")
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288
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289 ; Basic FP latency is 6 cycles
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290 (define_insn_reservation "power5-fp" 6
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291 (and (eq_attr "type" "fp,dmul")
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292 (eq_attr "cpu" "power5"))
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293 "fpq_power5")
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294
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295 (define_insn_reservation "power5-fpcompare" 5
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296 (and (eq_attr "type" "fpcompare")
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297 (eq_attr "cpu" "power5"))
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298 "fpq_power5")
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299
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300 (define_insn_reservation "power5-sdiv" 33
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301 (and (eq_attr "type" "sdiv,ddiv")
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302 (eq_attr "cpu" "power5"))
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303 "(du1_power5,fpu1_power5*28)\
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304 |(du2_power5,fpu2_power5*28)\
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305 |(du3_power5,fpu2_power5*28)\
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306 |(du4_power5,fpu1_power5*28)")
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307
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308 (define_insn_reservation "power5-sqrt" 40
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309 (and (eq_attr "type" "ssqrt,dsqrt")
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310 (eq_attr "cpu" "power5"))
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311 "(du1_power5,fpu1_power5*35)\
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312 |(du2_power5,fpu2_power5*35)\
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313 |(du3_power5,fpu2_power5*35)\
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314 |(du4_power5,fpu2_power5*35)")
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315
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316 (define_insn_reservation "power5-isync" 2
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317 (and (eq_attr "type" "isync")
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318 (eq_attr "cpu" "power5"))
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319 "du1_power5+du2_power5+du3_power5+du4_power5,\
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320 lsu1_power5")
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321
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