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1 ;; Scheduling description for z10 (cpu 2097).
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2 ;; Copyright (C) 2008 Free Software Foundation, Inc.
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3 ;; Contributed by Wolfgang Gellerich (gellerich@de.ibm.com).
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4
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5
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6 ; General naming conventions used in this file:
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7 ; - The two pipelines are called S and T, respectively.
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8 ; - A name ending "_S" or "_T" indicates that something happens in
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9 ; (or belongs to) this pipeline.
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10 ; - A name ending "_ANY" indicates that something happens in (or belongs
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11 ; to) either of the two pipelines.
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12 ; - A name ending "_BOTH" indicates that something happens in (or belongs
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13 ; to) both pipelines.
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14
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15
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16 ;; Automaton and components.
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17
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18 (define_automaton "z10_cpu")
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19
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20 (define_cpu_unit "z10_e1_S, z10_e1_T" "z10_cpu")
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21 (define_reservation "z10_e1_ANY" "(z10_e1_S | z10_e1_T)")
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22 (define_reservation "z10_e1_BOTH" "(z10_e1_S + z10_e1_T)")
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23
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24
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25 ; Both pipelines can execute a branch instruction, and branch
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26 ; instructions can be grouped with all other groupable instructions
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27 ; but not with a second branch instruction.
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28
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29 (define_cpu_unit "z10_branch_ANY" "z10_cpu")
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30
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31 (define_insn_reservation "z10_branch" 4
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32 (and (eq_attr "cpu" "z10")
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33 (eq_attr "type" "branch"))
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34 "z10_branch_ANY + z10_e1_ANY, z10_Gate_ANY")
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35
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36
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37 ; Z10 operand and result forwarding.
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38
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39 ; Instructions marked with the attributes as z10_fwd or z10_fr can
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40 ; forward a value they load from one of their operants into a register
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41 ; if the instruction in the second pipeline reads the same register.
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42 ; The second operation must be superscalar. Instructions marked as
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43 ; z10_rec or z10_fr can receive a value they read from a register is
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44 ; this register gets updated by an instruction in the first pipeline.
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45 ; The first instruction must be superscalar.
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46
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47
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48 ; Forwarding from z10_fwd and z10_fr to z10_super.
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49
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50 (define_bypass 0 "z10_la_fwd, z10_la_fwd_A1, z10_larl_fwd, z10_larl_fwd_A3, \
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51 z10_load_fwd, z10_load_fwd_A3, \
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52 z10_other_fwd, z10_other_fwd_A1, z10_other_fwd_A3, \
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53 z10_other_fr, z10_other_fr_A3, z10_other_fr_E1, \
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54 z10_other_fwd_E1, z10_lr_fr, z10_lr_fr_E1, \
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55 z10_int_fwd, z10_int_fwd_A1, z10_int_fwd_A3, \
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56 z10_int_fwd_E1, z10_int_fr, z10_int_fr_E1, \
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57 z10_int_fr_A3"
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58 "z10_other_super, z10_other_super_c_E1, z10_other_super_E1, \
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59 z10_int_super, z10_int_super_E1, \
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60 z10_lr, z10_store_super")
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61
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62
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63 ; Forwarding from z10_super to frz10_ and z10_rec.
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64
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65 (define_bypass 0 "z10_other_super, z10_other_super_E1, z10_other_super_c_E1, \
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66 z10_int_super, z10_int_super_E1, \
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67 z10_larl_super_E1, z10_larl_super, \
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68 z10_store_super"
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69 "z10_int_fr, z10_int_fr_E1, z10_int_fr_A3, \
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70 z10_other_fr, z10_other_fr_A3, z10_lr_fr, z10_lr_fr_E1, \
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71 z10_other_fr_E1, z10_store_rec")
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72
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73
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74 ; Forwarding from z10_fwd and z10_fr to z10_rec and z10_fr.
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75
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76 (define_bypass 0 "z10_la_fwd, z10_la_fwd_A1, z10_larl_fwd, z10_larl_fwd_A3, \
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77 z10_load_fwd, z10_load_fwd_A3, \
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78 z10_other_fwd, z10_other_fwd_A1, z10_other_fwd_A3, \
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79 z10_other_fr, z10_other_fr_A3, z10_other_fr_E1, \
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80 z10_other_fwd_E1, \
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81 z10_lr_fr, z10_lr_fr_E1, \
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82 z10_int_fwd, z10_int_fwd_A1, z10_int_fwd_A3, \
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83 z10_int_fwd_E1, z10_int_fr, z10_int_fr_E1, \
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84 z10_int_fr_A3"
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85 "z10_int_fr, z10_int_fr_E1, z10_int_fr_A3, \
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86 z10_other_fr, z10_other_fr_A3, z10_lr_fr, z10_lr_fr_E1, \
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87 z10_other_fr_E1, z10_store_rec")
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88
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89
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90 ;
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91 ; Simple insns
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92 ;
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93
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94 ; Here is the cycle diagram for FXU-executed instructions:
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95 ; ... A1 A2 A3 E1 P1 P2 P3 R0 ...
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96 ; ^ ^ ^
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97 ; | | updated GPR is available
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98 ; | write to GPR
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99 ; instruction reads GPR during this cycle
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100
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101
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102 ; Variants of z10_int follow.
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103
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104 (define_insn_reservation "z10_int" 6
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105 (and (and (eq_attr "cpu" "z10")
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106 (eq_attr "type" "integer"))
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107 (and (eq_attr "atype" "reg")
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108 (and (and (eq_attr "z10prop" "!z10_super")
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109 (eq_attr "z10prop" "!z10_super_c"))
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110 (and (and (and (and (eq_attr "z10prop" "!z10_super_E1")
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111 (eq_attr "z10prop" "!z10_super_c_E1"))
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112 (eq_attr "z10prop" "!z10_fwd"))
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113 (and (eq_attr "z10prop" "!z10_fwd_A1")
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114 (eq_attr "z10prop" "!z10_fwd_A3")))
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115 (and (and (eq_attr "z10prop" "!z10_fwd_E1")
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116 (eq_attr "z10prop" "!z10_fr"))
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117 (and (eq_attr "z10prop" "!z10_fr_E1")
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118 (eq_attr "z10prop" "!z10_fr_A3")))))))
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119 "z10_e1_ANY, z10_Gate_ANY")
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120
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121 (define_insn_reservation "z10_int_super" 6
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122 (and (eq_attr "cpu" "z10")
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123 (and (eq_attr "type" "integer")
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124 (and (eq_attr "atype" "reg")
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125 (ior (eq_attr "z10prop" "z10_super")
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126 (eq_attr "z10prop" "z10_super_c")))))
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127 "z10_e1_ANY, z10_Gate_ANY")
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128
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129 (define_insn_reservation "z10_int_super_E1" 6
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130 (and (eq_attr "cpu" "z10")
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131 (and (eq_attr "type" "integer")
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132 (and (eq_attr "atype" "reg")
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133 (ior (eq_attr "z10prop" "z10_super_E1")
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134 (eq_attr "z10prop" "z10_super_c_E1")))))
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135 "z10_e1_ANY, z10_Gate_ANY")
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136
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137 (define_insn_reservation "z10_int_fwd" 6
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138 (and (eq_attr "cpu" "z10")
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139 (and (eq_attr "type" "integer")
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140 (and (eq_attr "atype" "reg")
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141 (eq_attr "z10prop" "z10_fwd"))))
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142 "z10_e1_ANY, z10_Gate_ANY")
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143
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144 (define_insn_reservation "z10_int_fwd_A1" 6
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145 (and (eq_attr "cpu" "z10")
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146 (and (eq_attr "type" "integer")
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147 (and (eq_attr "atype" "reg")
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148 (eq_attr "z10prop" "z10_fwd_A1"))))
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149 "z10_e1_ANY, z10_Gate_ANY")
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150
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151 (define_insn_reservation "z10_int_fwd_A3" 6
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152 (and (eq_attr "cpu" "z10")
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153 (and (eq_attr "type" "integer")
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154 (and (eq_attr "atype" "reg")
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155 (eq_attr "z10prop" "z10_fwd_A3"))))
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156 "z10_e1_ANY, z10_Gate_ANY")
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157
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158 (define_insn_reservation "z10_int_fwd_E1" 6
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159 (and (eq_attr "cpu" "z10")
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160 (and (eq_attr "type" "integer")
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161 (and (eq_attr "atype" "reg")
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162 (eq_attr "z10prop" "z10_fwd_E1"))))
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163 "z10_e1_ANY, z10_Gate_ANY")
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164
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165 (define_insn_reservation "z10_int_fr" 6
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166 (and (eq_attr "cpu" "z10")
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167 (and (eq_attr "type" "integer")
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168 (and (eq_attr "atype" "reg")
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169 (eq_attr "z10prop" "z10_fr"))))
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170 "z10_e1_ANY, z10_Gate_ANY")
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171
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172 (define_insn_reservation "z10_int_fr_E1" 6
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173 (and (eq_attr "cpu" "z10")
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174 (and (eq_attr "type" "integer")
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175 (and (eq_attr "atype" "reg")
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176 (eq_attr "z10prop" "z10_fr_E1"))))
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177 "z10_e1_ANY, z10_Gate_ANY")
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178
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179 (define_insn_reservation "z10_int_fr_A3" 6
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180 (and (eq_attr "cpu" "z10")
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181 (and (eq_attr "type" "integer")
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182 (and (eq_attr "atype" "reg")
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183 (eq_attr "z10prop" "z10_fr_A3"))))
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184 "z10_e1_ANY, z10_Gate_ANY")
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185
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186 ; END of z10_int variants
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187
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188
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189 (define_insn_reservation "z10_agen" 6
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190 (and (eq_attr "cpu" "z10")
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191 (and (eq_attr "type" "integer")
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192 (eq_attr "atype" "agen")))
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193 "z10_e1_ANY, z10_Gate_ANY")
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194
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195
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196 (define_insn_reservation "z10_lr" 6
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197 (and (eq_attr "cpu" "z10")
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198 (and (eq_attr "type" "lr")
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199 (and (eq_attr "z10prop" "!z10_fr")
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200 (eq_attr "z10prop" "!z10_fr_E1"))))
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201 "z10_e1_ANY, z10_Gate_ANY")
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202
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203 (define_insn_reservation "z10_lr_fr" 6
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204 (and (eq_attr "cpu" "z10")
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205 (and (eq_attr "type" "lr")
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206 (eq_attr "z10prop" "z10_fr")))
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207 "z10_e1_ANY, z10_Gate_ANY")
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208 ; "z10_e1_ANY")
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209
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210 (define_insn_reservation "z10_lr_fr_E1" 6
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211 (and (eq_attr "cpu" "z10")
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212 (and (eq_attr "type" "lr")
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213 (eq_attr "z10prop" "z10_fr_E1")))
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214 "z10_e1_ANY, z10_Gate_ANY")
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215 ; "z10_e1_ANY")
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216
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217
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218 (define_insn_reservation "z10_la" 6
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219 (and (eq_attr "cpu" "z10")
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220 (and (eq_attr "type" "la")
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221 (and (eq_attr "z10prop" "!z10_fwd")
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222 (eq_attr "z10prop" "!z10_fwd_A1"))))
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223 "z10_e1_ANY, z10_Gate_ANY")
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224
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225 (define_insn_reservation "z10_la_fwd" 6
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226 (and (eq_attr "cpu" "z10")
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227 (and (eq_attr "type" "la")
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228 (eq_attr "z10prop" "z10_fwd")))
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229 "z10_e1_ANY, z10_Gate_ANY")
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230 ; "z10_e1_ANY")
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231
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232 (define_insn_reservation "z10_la_fwd_A1" 6
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233 (and (eq_attr "cpu" "z10")
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234 (and (eq_attr "type" "la")
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235 (eq_attr "z10prop" "z10_fwd_A1")))
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236 "z10_e1_ANY, z10_Gate_ANY")
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237 ; "z10_e1_ANY")
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238
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239
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240 ; larl-type instructions
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241
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242 (define_insn_reservation "z10_larl" 6
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243 (and (eq_attr "cpu" "z10")
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244 (and (eq_attr "type" "larl")
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245 (and (eq_attr "z10prop" "!z10_super_A1")
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246 (and (eq_attr "z10prop" "!z10_fwd")
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247 (and (eq_attr "z10prop" "!z10_fwd_A3")
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248 (and (eq_attr "z10prop" "!z10_super")
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249 (eq_attr "z10prop" "!z10_super_c"))
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250 (and (eq_attr "z10prop" "!z10_super_E1")
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251 (eq_attr "z10prop" "!z10_super_c_E1")))))))
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252 "z10_e1_ANY, z10_Gate_ANY")
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253
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254 (define_insn_reservation "z10_larl_super" 6
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255 (and (eq_attr "cpu" "z10")
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256 (and (eq_attr "type" "larl")
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257 (and (eq_attr "z10prop" "z10_super")
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258 (eq_attr "z10prop" "z10_super_c"))))
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259 "z10_e1_ANY, z10_Gate_ANY")
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260
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261 (define_insn_reservation "z10_larl_fwd" 6
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262 (and (eq_attr "cpu" "z10")
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263 (and (eq_attr "type" "larl")
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264 (eq_attr "z10prop" "z10_fwd")))
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265 "z10_e1_ANY, z10_Gate_ANY")
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266
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267 (define_insn_reservation "z10_larl_fwd_A3" 6
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268 (and (eq_attr "cpu" "z10")
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269 (and (eq_attr "type" "larl")
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270 (eq_attr "z10prop" "z10_fwd_A3")))
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271 "z10_e1_ANY, z10_Gate_ANY")
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272
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273
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274 (define_insn_reservation "z10_larl_A1" 6
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275 (and (eq_attr "cpu" "z10")
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276 (and (eq_attr "type" "larl")
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277 (eq_attr "z10prop" "z10_super_A1")))
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278 "z10_e1_ANY, z10_Gate_ANY")
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279 ; "z10_e1_ANY")
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280
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281 (define_insn_reservation "z10_larl_super_E1" 6
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282 (and (eq_attr "cpu" "z10")
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283 (and (eq_attr "type" "larl")
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284 (ior (eq_attr "z10prop" "z10_super_E1")
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285 (eq_attr "z10prop" "z10_super_c_E1"))))
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286 "z10_e1_ANY, z10_Gate_ANY")
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287 ; "z10_e1_ANY")
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288
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289
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290 (define_insn_reservation "z10_load" 6
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291 (and (eq_attr "cpu" "z10")
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292 (and (eq_attr "type" "load")
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293 (and (eq_attr "z10prop" "!z10_fwd")
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294 (eq_attr "z10prop" "!z10_fwd_A3"))))
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295 "z10_e1_ANY, z10_Gate_ANY")
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296
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297 (define_insn_reservation "z10_load_fwd" 6
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298 (and (eq_attr "cpu" "z10")
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299 (and (eq_attr "type" "load")
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300 (eq_attr "z10prop" "z10_fwd")))
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301 "z10_e1_ANY, z10_Gate_ANY")
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302 ; "z10_e1_ANY")
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303
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304 (define_insn_reservation "z10_load_fwd_A3" 6
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305 (and (eq_attr "cpu" "z10")
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306 (and (eq_attr "type" "load")
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307 (eq_attr "z10prop" "z10_fwd_A3")))
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308 "z10_e1_ANY, z10_Gate_ANY")
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309 ; "z10_e1_ANY")
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310
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311 (define_insn_reservation "z10_store" 6
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312 (and (eq_attr "cpu" "z10")
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313 (and (eq_attr "type" "store")
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314 (and (eq_attr "z10prop" "!z10_rec")
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315 (and (eq_attr "z10prop" "!z10_super")
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316 (eq_attr "z10prop" "!z10_super_c")))))
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317 "z10_e1_ANY, z10_Gate_ANY")
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318
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319 (define_insn_reservation "z10_store_super" 6
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320 (and (eq_attr "cpu" "z10")
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321 (and (eq_attr "type" "store")
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322 (ior (eq_attr "z10prop" "z10_super")
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323 (eq_attr "z10prop" "z10_super_c"))))
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324 "z10_e1_ANY, z10_Gate_ANY")
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325
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326 (define_insn_reservation "z10_store_rec" 6
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327 (and (eq_attr "cpu" "z10")
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328 (and (eq_attr "type" "store")
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329 (eq_attr "z10prop" "z10_rec")))
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330 "z10_e1_ANY, z10_Gate_ANY")
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331
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332 ; The default_latency is chosen to drain off the pipeline.
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333 (define_insn_reservation "z10_call" 14
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334 (and (eq_attr "cpu" "z10")
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335 (eq_attr "type" "jsr"))
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336 "z10_e1_BOTH*4, z10_Gate_BOTH")
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337
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338 ; The default latency is for worst case. CS and CSG take one
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339 ; cycle only (i.e. latency would be 6).
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340 (define_insn_reservation "z10_sem" 9
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341 (and (eq_attr "cpu" "z10")
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342 (eq_attr "type" "sem"))
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343 "z10_e1_BOTH*5, z10_Gate_ANY")
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344
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345 (define_insn_reservation "z10_cs" 6
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346 (and (eq_attr "cpu" "z10")
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347 (eq_attr "type" "cs"))
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348 "z10_e1_BOTH, z10_Gate_BOTH")
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349
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350 (define_insn_reservation "z10_vs" 6
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351 (and (eq_attr "cpu" "z10")
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352 (eq_attr "type" "vs"))
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353 "z10_e1_BOTH*4, z10_Gate_BOTH")
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354
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355 ; Load and store multiple. Actual number of cycles
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356 ; in unknown at compile.time.
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357 (define_insn_reservation "z10_stm" 10
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358 (and (eq_attr "cpu" "z10")
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359 (ior (eq_attr "type" "stm")
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360 (eq_attr "type" "lm")))
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361 "z10_e1_BOTH*4, z10_Gate_BOTH")
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362
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363
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364 ; Subsets of z10_other follow.
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365
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366 (define_insn_reservation "z10_other" 6
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367 (and (and (eq_attr "cpu" "z10")
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368 (eq_attr "type" "other"))
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369 (and (and (eq_attr "z10prop" "!z10_fwd")
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370 (eq_attr "z10prop" "!z10_fwd_A1"))
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371 (and (and (and (eq_attr "z10prop" "!z10_fr_A3")
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372 (eq_attr "z10prop" "!z10_fwd_A3"))
|
|
373 (and (eq_attr "z10prop" "!z10_fr")
|
|
374 (eq_attr "z10prop" "!z10_fr_E1")))
|
|
375 (and (and (and (eq_attr "z10prop" "!z10_super")
|
|
376 (eq_attr "z10prop" "!z10_super_c"))
|
|
377 (eq_attr "z10prop" "!z10_super_c_E1"))
|
|
378 (and (eq_attr "z10prop" "!z10_super_E1")
|
|
379 (eq_attr "z10prop" "!z10_fwd_E1"))))))
|
|
380 "z10_e1_BOTH, z10_Gate_BOTH")
|
|
381
|
|
382 (define_insn_reservation "z10_other_fr_E1" 6
|
|
383 (and (eq_attr "cpu" "z10")
|
|
384 (and (eq_attr "type" "other")
|
|
385 (eq_attr "z10prop" "z10_fr_E1")))
|
|
386 "z10_e1_BOTH, z10_Gate_BOTH")
|
|
387
|
|
388 (define_insn_reservation "z10_other_super_c_E1" 6
|
|
389 (and (eq_attr "cpu" "z10")
|
|
390 (and (eq_attr "type" "other")
|
|
391 (eq_attr "z10prop" "z10_super_c_E1")))
|
|
392 "z10_e1_BOTH, z10_Gate_BOTH")
|
|
393
|
|
394 (define_insn_reservation "z10_other_super_E1" 6
|
|
395 (and (eq_attr "cpu" "z10")
|
|
396 (and (eq_attr "type" "other")
|
|
397 (eq_attr "z10prop" "z10_super_E1")))
|
|
398 "z10_e1_BOTH, z10_Gate_BOTH")
|
|
399
|
|
400 (define_insn_reservation "z10_other_fwd_E1" 6
|
|
401 (and (eq_attr "cpu" "z10")
|
|
402 (and (eq_attr "type" "other")
|
|
403 (eq_attr "z10prop" "z10_fwd_E1")))
|
|
404 "z10_e1_BOTH, z10_Gate_BOTH")
|
|
405
|
|
406 (define_insn_reservation "z10_other_fwd" 6
|
|
407 (and (eq_attr "cpu" "z10")
|
|
408 (and (eq_attr "type" "other")
|
|
409 (eq_attr "z10prop" "z10_fwd")))
|
|
410 "z10_e1_BOTH, z10_Gate_BOTH")
|
|
411
|
|
412 (define_insn_reservation "z10_other_fwd_A3" 6
|
|
413 (and (eq_attr "cpu" "z10")
|
|
414 (and (eq_attr "type" "other")
|
|
415 (eq_attr "z10prop" "z10_fwd_A3")))
|
|
416 "z10_e1_BOTH, z10_Gate_BOTH")
|
|
417
|
|
418 (define_insn_reservation "z10_other_fwd_A1" 6
|
|
419 (and (eq_attr "cpu" "z10")
|
|
420 (and (eq_attr "type" "other")
|
|
421 (eq_attr "z10prop" "z10_fwd_A1")))
|
|
422 "z10_e1_BOTH, z10_Gate_BOTH")
|
|
423
|
|
424 (define_insn_reservation "z10_other_fr" 6
|
|
425 (and (eq_attr "cpu" "z10")
|
|
426 (and (eq_attr "type" "other")
|
|
427 (eq_attr "z10prop" "z10_fr")))
|
|
428 "z10_e1_BOTH, z10_Gate_BOTH")
|
|
429
|
|
430 (define_insn_reservation "z10_other_fr_A3" 6
|
|
431 (and (eq_attr "cpu" "z10")
|
|
432 (and (eq_attr "type" "other")
|
|
433 (eq_attr "z10prop" "z10_fr_A3")))
|
|
434 "z10_e1_BOTH, z10_Gate_BOTH")
|
|
435
|
|
436 (define_insn_reservation "z10_other_super" 6
|
|
437 (and (eq_attr "cpu" "z10")
|
|
438 (and (eq_attr "type" "other")
|
|
439 (ior (eq_attr "z10prop" "z10_super")
|
|
440 (eq_attr "z10prop" "z10_super_c"))))
|
|
441 "z10_e1_BOTH, z10_Gate_BOTH")
|
|
442
|
|
443 ; END of z10_other subsets.
|
|
444
|
|
445
|
|
446 ;
|
|
447 ; Floating point insns
|
|
448 ;
|
|
449
|
|
450 ; Z10 executes the following integer operations in the BFU pipeline.
|
|
451
|
|
452 (define_insn_reservation "z10_mul_sidi" 12
|
|
453 (and (eq_attr "cpu" "z10")
|
|
454 (eq_attr "type" "imulsi,imuldi,imulhi"))
|
|
455 "z10_e1_BOTH, z10_Gate_FP")
|
|
456
|
|
457 ; Some variants take fewer cycles, but that is not relevant here.
|
|
458 (define_insn_reservation "z10_div" 162
|
|
459 (and (eq_attr "cpu" "z10")
|
|
460 (eq_attr "type" "idiv"))
|
|
461 "z10_e1_BOTH*4, z10_Gate_FP")
|
|
462
|
|
463
|
|
464 ; BFP multiplication and general instructions
|
|
465
|
|
466 (define_insn_reservation "z10_fsimpdf" 12
|
|
467 (and (eq_attr "cpu" "z10")
|
|
468 (eq_attr "type" "fsimpdf,fmuldf"))
|
|
469 "z10_e1_BOTH, z10_Gate_FP")
|
|
470 ; Wg "z10_e1_T, z10_Gate_FP")
|
|
471
|
|
472 (define_insn_reservation "z10_fsimpsf" 12
|
|
473 (and (eq_attr "cpu" "z10")
|
|
474 (eq_attr "type" "fsimpsf,fmulsf"))
|
|
475 "z10_e1_BOTH, z10_Gate_FP")
|
|
476 ; Wg "z10_e1_T, z10_Gate_FP")
|
|
477
|
|
478 (define_insn_reservation "z10_fmultf" 52
|
|
479 (and (eq_attr "cpu" "z10")
|
|
480 (eq_attr "type" "fmultf"))
|
|
481 "z10_e1_BOTH*4, z10_Gate_FP")
|
|
482 ; Wg "z10_e1_T*4, z10_Gate_FP")
|
|
483
|
|
484 (define_insn_reservation "z10_fsimptf" 14
|
|
485 (and (eq_attr "cpu" "z10")
|
|
486 (eq_attr "type" "fsimptf"))
|
|
487 "z10_e1_BOTH*2, z10_Gate_FP")
|
|
488 ; Wg "z10_e1_T*2, z10_Gate_FP")
|
|
489
|
|
490
|
|
491 ; BFP division
|
|
492
|
|
493 (define_insn_reservation "z10_fdivtf" 113
|
|
494 (and (eq_attr "cpu" "z10")
|
|
495 (eq_attr "type" "fdivtf"))
|
|
496 "z10_e1_T*4, z10_Gate_FP")
|
|
497
|
|
498 (define_insn_reservation "z10_fdivdf" 41
|
|
499 (and (eq_attr "cpu" "z10")
|
|
500 (eq_attr "type" "fdivdf"))
|
|
501 "z10_e1_T*4, z10_Gate_FP")
|
|
502
|
|
503 (define_insn_reservation "z10_fdivsf" 34
|
|
504 (and (eq_attr "cpu" "z10")
|
|
505 (eq_attr "type" "fdivsf"))
|
|
506 "z10_e1_T*4, z10_Gate_FP")
|
|
507
|
|
508
|
|
509 ; BFP sqrt
|
|
510
|
|
511 (define_insn_reservation "z10_fsqrtsf" 41
|
|
512 (and (eq_attr "cpu" "z10")
|
|
513 (eq_attr "type" "fsqrtsf"))
|
|
514 "z10_e1_T*4, z10_Gate_FP")
|
|
515
|
|
516 (define_insn_reservation "z10_fsqrtdf" 54
|
|
517 (and (eq_attr "cpu" "z10")
|
|
518 (eq_attr "type" "fsqrtdf"))
|
|
519 "z10_e1_T*4, z10_Gate_FP")
|
|
520
|
|
521 (define_insn_reservation "z10_fsqrtf" 122
|
|
522 (and (eq_attr "cpu" "z10")
|
|
523 (eq_attr "type" "fsqrttf"))
|
|
524 "z10_e1_T*4, z10_Gate_FP")
|
|
525
|
|
526
|
|
527 ; BFP load and store
|
|
528
|
|
529 (define_insn_reservation "z10_floadtf" 12
|
|
530 (and (eq_attr "cpu" "z10")
|
|
531 (eq_attr "type" "floadtf"))
|
|
532 "z10_e1_T, z10_Gate_FP")
|
|
533
|
|
534 (define_insn_reservation "z10_floaddf" 12
|
|
535 (and (eq_attr "cpu" "z10")
|
|
536 (eq_attr "type" "floaddf"))
|
|
537 "z10_e1_T, z10_Gate_FP")
|
|
538
|
|
539 (define_insn_reservation "z10_floadsf" 12
|
|
540 (and (eq_attr "cpu" "z10")
|
|
541 (eq_attr "type" "floadsf"))
|
|
542 "z10_e1_T, z10_Gate_FP")
|
|
543
|
|
544 (define_insn_reservation "z10_fstoredf" 12
|
|
545 (and (eq_attr "cpu" "z10")
|
|
546 (eq_attr "type" "fstoredf,fstoredd"))
|
|
547 "z10_e1_T, z10_Gate_FP")
|
|
548
|
|
549 (define_insn_reservation "z10_fstoresf" 12
|
|
550 (and (eq_attr "cpu" "z10")
|
|
551 (eq_attr "type" "fstoresf,fstoresd"))
|
|
552 "z10_e1_T, z10_Gate_FP")
|
|
553
|
|
554
|
|
555 ; BFP truncate
|
|
556 (define_insn_reservation "z10_ftrunctf" 12
|
|
557 (and (eq_attr "cpu" "z10")
|
|
558 (eq_attr "type" "ftrunctf"))
|
|
559 "z10_e1_T, z10_Gate_FP")
|
|
560
|
|
561 (define_insn_reservation "z10_ftruncdf" 16
|
|
562 (and (eq_attr "cpu" "z10")
|
|
563 (eq_attr "type" "ftruncdf"))
|
|
564 "z10_e1_T, z10_Gate_FP")
|
|
565
|
|
566
|
|
567 ; Conversion between BFP and int.
|
|
568 (define_insn_reservation "z10_ftoi" 13
|
|
569 (and (eq_attr "cpu" "z10")
|
|
570 (eq_attr "type" "ftoi"))
|
|
571 "z10_e1_T, z10_Gate_FP")
|
|
572
|
|
573 (define_insn_reservation "z10_itoftf" 14
|
|
574 (and (eq_attr "cpu" "z10")
|
|
575 (eq_attr "type" "itoftf"))
|
|
576 "z10_e1_T*2, z10_Gate_FP")
|
|
577
|
|
578 (define_insn_reservation "z10_itofsfdf" 12
|
|
579 (and (eq_attr "cpu" "z10")
|
|
580 (eq_attr "type" "itofdf,itofsf"))
|
|
581 "z10_e1_T, z10_Gate_FP")
|
|
582
|
|
583
|
|
584
|
|
585 ; BFP-related bypasses. There is no bypass for extended mode.
|
|
586 (define_bypass 1 "z10_fsimpdf" "z10_fstoredf")
|
|
587 (define_bypass 1 "z10_fsimpsf" "z10_fstoresf")
|
|
588 (define_bypass 1 "z10_floaddf" "z10_fsimpdf, z10_fstoredf, z10_floaddf")
|
|
589 (define_bypass 1 "z10_floadsf" "z10_fsimpsf, z10_fstoresf, z10_floadsf")
|
|
590
|
|
591
|
|
592 ;
|
|
593 ; insn_reservations for DFP instructions.
|
|
594 ;
|
|
595
|
|
596 ; Exact number of cycles is not known at compile-time.
|
|
597 (define_insn_reservation "z10_fdivddtd" 40
|
|
598 (and (eq_attr "cpu" "z10")
|
|
599 (eq_attr "type" "fdivdd,fdivtd"))
|
|
600 "z10_e1_BOTH,z10_Gate_DFU")
|
|
601
|
|
602 (define_insn_reservation "z10_ftruncsd" 38
|
|
603 (and (eq_attr "cpu" "z10")
|
|
604 (eq_attr "type" "ftruncsd"))
|
|
605 "z10_e1_BOTH*4,z10_Gate_DFU")
|
|
606
|
|
607 (define_insn_reservation "z10_ftruncdd" 340
|
|
608 (and (eq_attr "cpu" "z10")
|
|
609 (eq_attr "type" "ftruncsd"))
|
|
610 "z10_e1_BOTH*4,z10_Gate_DFU")
|
|
611
|
|
612 (define_insn_reservation "z10_floaddd" 12
|
|
613 (and (eq_attr "cpu" "z10")
|
|
614 (eq_attr "type" "floaddd"))
|
|
615 "z10_e1_BOTH,z10_Gate_DFU")
|
|
616
|
|
617 (define_insn_reservation "z10_floadsd" 12
|
|
618 (and (eq_attr "cpu" "z10")
|
|
619 (eq_attr "type" "floadsd"))
|
|
620 "z10_e1_BOTH,z10_Gate_DFU")
|
|
621
|
|
622 ; Exact number of cycles is not known at compile-time.
|
|
623 (define_insn_reservation "z10_fmulddtd" 35
|
|
624 (and (eq_attr "cpu" "z10")
|
|
625 (eq_attr "type" "fmuldd,fmultd"))
|
|
626 "z10_e1_BOTH,z10_Gate_DFU")
|
|
627
|
|
628 (define_insn_reservation "z10_fsimpdd" 17
|
|
629 (and (eq_attr "cpu" "z10")
|
|
630 (eq_attr "type" "fsimpdd"))
|
|
631 "z10_e1_BOTH,z10_Gate_DFU")
|
|
632
|
|
633 (define_insn_reservation "z10_fsimpsd" 17
|
|
634 (and (eq_attr "cpu" "z10")
|
|
635 (eq_attr "type" "fsimpsd"))
|
|
636 "z10_e1_BOTH,z10_Gate_DFU")
|
|
637
|
|
638 (define_insn_reservation "z10_fsimptd" 18
|
|
639 (and (eq_attr "cpu" "z10")
|
|
640 (eq_attr "type" "fsimptd"))
|
|
641 "z10_e1_BOTH,z10_Gate_DFU")
|
|
642
|
|
643 (define_insn_reservation "z10_itofdd" 36
|
|
644 (and (eq_attr "cpu" "z10")
|
|
645 (eq_attr "type" "itofdd"))
|
|
646 "z10_e1_BOTH*3,z10_Gate_DFU")
|
|
647
|
|
648 (define_insn_reservation "z10_itoftd" 49
|
|
649 (and (eq_attr "cpu" "z10")
|
|
650 (eq_attr "type" "itoftd"))
|
|
651 "z10_e1_BOTH*3,z10_Gate_DFU")
|
|
652
|
|
653 ; Exact number of cycles is not known at compile-time.
|
|
654 (define_insn_reservation "z10_ftoidfp" 30
|
|
655 (and (eq_attr "cpu" "z10")
|
|
656 (eq_attr "type" "ftoidfp"))
|
|
657 "z10_e1_BOTH*3,z10_Gate_DFU")
|
|
658
|
|
659
|
|
660 ;
|
|
661 ; Address-related bypasses
|
|
662 ;
|
|
663
|
|
664 ; Here is the cycle diagram for Address-related bypasses:
|
|
665 ; ... G1 G2 G3 A0 A1 A2 A3 E1 P1 P2 P3 R0 ...
|
|
666 ; ^ ^ ^ ^ ^
|
|
667 ; | | | | E1-type bypasses provide the new addr AFTER this cycle
|
|
668 ; | | | A3-type bypasses provide the new addr AFTER this cycle
|
|
669 ; | | A1-type bypasses provide the new addr AFTER this cycle
|
|
670 ; | AGI resolution, actual USE of address is DURING this cycle
|
|
671 ; AGI detection
|
|
672
|
|
673 (define_bypass 3 "z10_larl_A1, z10_la_fwd_A1, z10_other_fwd_A1, \
|
|
674 z10_int_fwd_A1"
|
|
675 "z10_agen, z10_la, z10_branch, z10_call, z10_load, \
|
|
676 z10_store, \
|
|
677 z10_cs, z10_stm, z10_other"
|
|
678 "s390_agen_dep_p")
|
|
679
|
|
680
|
|
681 (define_bypass 5 "z10_larl_fwd_A3, z10_load_fwd_A3, z10_other_fwd_A3, \
|
|
682 z10_other_fr_A3, z10_int_fwd_A3, z10_int_fr_A3"
|
|
683 "z10_agen, z10_la, z10_branch, z10_call, z10_load, \
|
|
684 z10_store, \
|
|
685 z10_cs, z10_stm, z10_other"
|
|
686 "s390_agen_dep_p")
|
|
687
|
|
688 (define_bypass 6 "z10_other_fr_E1, z10_other_super_c_E1, z10_other_super_E1, \
|
|
689 z10_other_fwd_E1, \
|
|
690 z10_lr_fr_E1, z10_larl_super_E1, \
|
|
691 z10_int_super_E1, z10_int_fwd_E1, z10_int_fr_E1"
|
|
692 "z10_agen, z10_la, z10_branch, z10_call, z10_load, \
|
|
693 z10_store, \
|
|
694 z10_cs, z10_stm, z10_other"
|
|
695 "s390_agen_dep_p")
|
|
696
|
|
697
|
|
698
|
|
699 ;
|
|
700 ; Try to avoid transitions between DFU-, BFU- and FXU-executed instructions as there is a
|
|
701 ; dispatch delay required.
|
|
702 ;
|
|
703
|
|
704
|
|
705 ; Declaration for some pseudo-pipeline stages that reflect the
|
|
706 ; dispatch gap when issueing an INT/FXU/BFU-executed instruction after
|
|
707 ; an instruction executed by a different unit has been executed. The
|
|
708 ; approach is that we pretend a pipelined execution of BFU operations
|
|
709 ; with as many stages as the gap is long and request that none of
|
|
710 ; these stages is busy when issueing a FXU- or DFU-executed
|
|
711 ; instruction. Similar for FXU- and DFU-executed instructions.
|
|
712
|
|
713 ; Declaration for FPU stages.
|
|
714 (define_cpu_unit "z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, z10_f5, z10_f6, \
|
|
715 z10_f7, z10_f8, z10_f9, z10_f10, z10_f11, z10_f12" "z10_cpu")
|
|
716 (define_reservation "z10_FP_PP" "z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, \
|
|
717 z10_f5, z10_f6, z10_f7, z10_f8, z10_f9, z10_f10, z10_f11, \
|
|
718 z10_f12")
|
|
719
|
|
720 ; Declaration for FXU stages.
|
|
721 (define_cpu_unit "z10_S1, z10_S2, z10_S3, z10_S4, z10_S5, z10_S6" "z10_cpu")
|
|
722 (define_cpu_unit "z10_T1, z10_T2, z10_T3, z10_T4, z10_T5, z10_T6" "z10_cpu")
|
|
723 (define_reservation "z10_INT_PP" "z10_S1 | z10_T1, z10_S2 | z10_T2, z10_S3 \
|
|
724 | z10_T3, z10_S4 | z10_T4, z10_S5 | \
|
|
725 z10_T5, z10_S6 | z10_T6")
|
|
726
|
|
727 ; Declaration for DFU stages.
|
|
728 (define_cpu_unit "z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, z10_d5, z10_d6"
|
|
729 "z10_cpu")
|
|
730 (define_reservation "z10_DFU_PP" "z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, \
|
|
731 z10_d5, z10_d6")
|
|
732
|
|
733
|
|
734 ; Pseudo-units representing whether the respective unit is available
|
|
735 ; in the sense that using it does not cause a dispatch delay.
|
|
736
|
|
737 (define_cpu_unit "z10_S_avail, z10_T_avail, z10_FP_avail, z10_DFU_avail"
|
|
738 "z10_cpu")
|
|
739
|
|
740 (absence_set "z10_FP_avail"
|
|
741 "z10_S1, z10_S2, z10_S3, z10_S4, z10_S5, z10_S6, z10_T1, z10_T2, z10_T3, z10_T4, \
|
|
742 z10_T5, z10_T6, \
|
|
743 z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, z10_d5, z10_d6")
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744
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745 (absence_set "z10_S_avail,z10_T_avail"
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746 "z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, z10_f5, z10_f6, z10_f7, \
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747 z10_f8, z10_f9, z10_f10, z10_f11, z10_f12, \
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748 z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, z10_d5, z10_d6")
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749
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750 (absence_set "z10_DFU_avail"
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751 "z10_S1, z10_S2, z10_S3, z10_S4, z10_S5, z10_S6, z10_T1, z10_T2, z10_T3, z10_T4, \
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752 z10_T5, z10_T6, \
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753 z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, z10_f5, z10_f6, z10_f7, \
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754 z10_f8, z10_f9, z10_f10, z10_f11, z10_f12")
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755
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756
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757 ; Pseudo-units to be used in insn_reservations.
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758
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759 (define_reservation "z10_Gate_ANY" "((z10_S_avail | z10_T_avail), z10_INT_PP)")
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760 (define_reservation "z10_Gate_BOTH" "((z10_S_avail + z10_T_avail), z10_INT_PP)")
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761
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762 (define_reservation "z10_Gate_FP" "z10_FP_avail, z10_FP_PP")
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763
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764 (define_reservation "z10_Gate_DFU" "z10_DFU_avail, z10_DFU_PP")
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