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1 ;; Scheduling description for Niagara-2.
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2 ;; Copyright (C) 2007 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; Niagara-2 is a single-issue processor.
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21
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22 (define_automaton "niagara2_0")
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23
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24 (define_cpu_unit "niag2_pipe" "niagara2_0")
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25
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26 (define_insn_reservation "niag2_25cycle" 25
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27 (and (eq_attr "cpu" "niagara2")
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28 (eq_attr "type" "flushw"))
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29 "niag2_pipe*25")
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30
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31 (define_insn_reservation "niag2_5cycle" 5
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32 (and (eq_attr "cpu" "niagara2")
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33 (eq_attr "type" "multi,flushw,iflush,trap"))
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34 "niag2_pipe*5")
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35
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36 (define_insn_reservation "niag2_6cycle" 4
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37 (and (eq_attr "cpu" "niagara2")
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38 (eq_attr "type" "savew"))
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39 "niag2_pipe*4")
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40
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41 /* Most basic operations are single-cycle. */
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42 (define_insn_reservation "niag2_ialu" 1
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43 (and (eq_attr "cpu" "niagara2")
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44 (eq_attr "type" "ialu,shift,compare,cmove"))
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45 "niag2_pipe")
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46
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47 (define_insn_reservation "niag2_imul" 5
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48 (and (eq_attr "cpu" "niagara2")
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49 (eq_attr "type" "imul"))
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50 "niag2_pipe*5")
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51
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52 (define_insn_reservation "niag2_idiv" 31
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53 (and (eq_attr "cpu" "niagara2")
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54 (eq_attr "type" "idiv"))
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55 "niag2_pipe*31")
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56
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57 (define_insn_reservation "niag2_branch" 5
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58 (and (eq_attr "cpu" "niagara2")
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59 (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch"))
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60 "niag2_pipe*5")
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61
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62 (define_insn_reservation "niag2_3cycle_load" 3
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63 (and (eq_attr "cpu" "niagara2")
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64 (eq_attr "type" "load,fpload"))
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65 "niag2_pipe*3")
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66
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67 (define_insn_reservation "niag2_1cycle_store" 1
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68 (and (eq_attr "cpu" "niagara2")
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69 (eq_attr "type" "store,fpstore"))
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70 "niag2_pipe")
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71
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72 (define_insn_reservation "niag2_fp" 3
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73 (and (eq_attr "cpu" "niagara2")
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74 (eq_attr "type" "fpmove,fpcmove,fpcrmove,fpcmp,fpmul"))
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75 "niag2_pipe*3")
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76
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77 (define_insn_reservation "niag2_fdivs" 19
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78 (and (eq_attr "cpu" "niagara2")
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79 (eq_attr "type" "fpdivs"))
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80 "niag2_pipe*19")
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81
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82 (define_insn_reservation "niag2_fdivd" 33
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83 (and (eq_attr "cpu" "niagara2")
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84 (eq_attr "type" "fpdivd"))
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85 "niag2_pipe*33")
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86
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87 (define_insn_reservation "niag2_vis" 6
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88 (and (eq_attr "cpu" "niagara2")
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89 (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist"))
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90 "niag2_pipe*6")
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