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1 ;; Scheduling description for SuperSPARC.
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2 ;; Copyright (C) 2002, 2007 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; The SuperSPARC is a tri-issue, which was considered quite parallel
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21 ;; at the time it was released. Much like UltraSPARC-I and UltraSPARC-II
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22 ;; there are two integer units but only one of them may take shifts.
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23 ;;
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24 ;; ??? If SuperSPARC has the same slotting rules as ultrasparc for these
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25 ;; ??? shifts, we should model that.
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26
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27 (define_automaton "supersparc_0,supersparc_1")
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28
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29 (define_cpu_unit "ss_memory, ss_shift, ss_iwport0, ss_iwport1" "supersparc_0")
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30 (define_cpu_unit "ss_fpalu" "supersparc_0")
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31 (define_cpu_unit "ss_fpmds" "supersparc_1")
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32
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33 (define_reservation "ss_iwport" "(ss_iwport0 | ss_iwport1)")
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34
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35 (define_insn_reservation "ss_iuload" 1
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36 (and (eq_attr "cpu" "supersparc")
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37 (eq_attr "type" "load,sload"))
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38 "ss_memory")
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39
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40 ;; Ok, fpu loads deliver the result in zero cycles. But we
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41 ;; have to show the ss_memory reservation somehow, thus...
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42 (define_insn_reservation "ss_fpload" 0
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43 (and (eq_attr "cpu" "supersparc")
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44 (eq_attr "type" "fpload"))
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45 "ss_memory")
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46
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47 (define_bypass 0 "ss_fpload" "ss_fp_alu,ss_fp_mult,ss_fp_divs,ss_fp_divd,ss_fp_sqrt")
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48
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49 (define_insn_reservation "ss_store" 1
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50 (and (eq_attr "cpu" "supersparc")
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51 (eq_attr "type" "store,fpstore"))
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52 "ss_memory")
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53
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54 (define_insn_reservation "ss_ialu_shift" 1
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55 (and (eq_attr "cpu" "supersparc")
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56 (eq_attr "type" "shift"))
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57 "ss_shift + ss_iwport")
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58
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59 (define_insn_reservation "ss_ialu_any" 1
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60 (and (eq_attr "cpu" "supersparc")
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61 (eq_attr "type" "load,sload,store,shift,ialu"))
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62 "ss_iwport")
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63
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64 (define_insn_reservation "ss_fp_alu" 3
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65 (and (eq_attr "cpu" "supersparc")
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66 (eq_attr "type" "fp,fpmove,fpcmp"))
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67 "ss_fpalu, nothing*2")
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68
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69 (define_insn_reservation "ss_fp_mult" 3
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70 (and (eq_attr "cpu" "supersparc")
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71 (eq_attr "type" "fpmul"))
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72 "ss_fpmds, nothing*2")
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73
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74 (define_insn_reservation "ss_fp_divs" 6
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75 (and (eq_attr "cpu" "supersparc")
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76 (eq_attr "type" "fpdivs"))
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77 "ss_fpmds*4, nothing*2")
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78
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79 (define_insn_reservation "ss_fp_divd" 9
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80 (and (eq_attr "cpu" "supersparc")
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81 (eq_attr "type" "fpdivd"))
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82 "ss_fpmds*7, nothing*2")
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83
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84 (define_insn_reservation "ss_fp_sqrt" 12
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85 (and (eq_attr "cpu" "supersparc")
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86 (eq_attr "type" "fpsqrts,fpsqrtd"))
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87 "ss_fpmds*10, nothing*2")
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88
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89 (define_insn_reservation "ss_imul" 4
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90 (and (eq_attr "cpu" "supersparc")
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91 (eq_attr "type" "imul"))
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92 "ss_fpmds*4")
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