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1 ;; GCC machine description for Tensilica's Xtensa architecture.
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2 ;; Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
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3 ;; Free Software Foundation, Inc.
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4 ;; Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
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5
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6 ;; This file is part of GCC.
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7
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8 ;; GCC is free software; you can redistribute it and/or modify it
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9 ;; under the terms of the GNU General Public License as published by
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10 ;; the Free Software Foundation; either version 3, or (at your option)
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11 ;; any later version.
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12
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13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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16 ;; License for more details.
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17
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22
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23 (define_constants [
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24 (A0_REG 0)
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25 (A1_REG 1)
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26 (A7_REG 7)
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27 (A8_REG 8)
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28
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29 (UNSPEC_NOP 2)
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30 (UNSPEC_PLT 3)
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31 (UNSPEC_RET_ADDR 4)
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32 (UNSPEC_TPOFF 5)
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33 (UNSPEC_DTPOFF 6)
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34 (UNSPEC_TLS_FUNC 7)
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35 (UNSPEC_TLS_ARG 8)
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36 (UNSPEC_TLS_CALL 9)
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37 (UNSPEC_TP 10)
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38 (UNSPEC_MEMW 11)
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39
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40 (UNSPECV_SET_FP 1)
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41 (UNSPECV_ENTRY 2)
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42 (UNSPECV_S32RI 4)
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43 (UNSPECV_S32C1I 5)
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44 (UNSPECV_EH_RETURN 6)
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45 (UNSPECV_SET_TP 7)
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46 ])
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47
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48 ;; This code iterator allows signed and unsigned widening multiplications
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49 ;; to use the same template.
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50 (define_code_iterator any_extend [sign_extend zero_extend])
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51
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52 ;; <u> expands to an empty string when doing a signed operation and
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53 ;; "u" when doing an unsigned operation.
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54 (define_code_attr u [(sign_extend "") (zero_extend "u")])
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55
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56 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
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57 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
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58
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59 ;; This code iterator allows four integer min/max operations to be
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60 ;; generated from one template.
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61 (define_code_iterator any_minmax [smin umin smax umax])
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62
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63 ;; <minmax> expands to the opcode name for any_minmax operations.
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64 (define_code_attr minmax [(smin "min") (umin "minu")
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65 (smax "max") (umax "maxu")])
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66
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67 ;; This code iterator allows all branch instructions to be generated from
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68 ;; a single define_expand template.
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69 (define_code_iterator any_cond [eq ne gt ge lt le gtu geu ltu leu
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70 uneq ltgt ungt unge unlt unle
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71 unordered ordered])
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72
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73 ;; This code iterator is for setting a register from a comparison.
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74 (define_code_iterator any_scc [eq ne gt ge lt le])
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75
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76 ;; This code iterator is for floating-point comparisons.
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77 (define_code_iterator any_scc_sf [eq lt le uneq unlt unle unordered])
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78 (define_code_attr scc_sf [(eq "oeq") (lt "olt") (le "ole")
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79 (uneq "ueq") (unlt "ult") (unle "ule")
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80 (unordered "un")])
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81
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82 ;; This iterator and attribute allow to combine most atomic operations.
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83 (define_code_iterator ATOMIC [and ior xor plus minus mult])
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84 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
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85 (plus "add") (minus "sub") (mult "nand")])
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86
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87 ;; This mode iterator allows the HI and QI patterns to be defined from
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88 ;; the same template.
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89 (define_mode_iterator HQI [HI QI])
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90
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91
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92 ;; Attributes.
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93
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94 (define_attr "type"
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95 "unknown,jump,call,load,store,move,arith,multi,nop,farith,fmadd,fdiv,fsqrt,fconv,fload,fstore,mul16,mul32,div32,mac16,rsr,wsr,entry"
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96 (const_string "unknown"))
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97
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98 (define_attr "mode"
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99 "unknown,none,QI,HI,SI,DI,SF,DF,BL"
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100 (const_string "unknown"))
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101
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102 (define_attr "length" "" (const_int 1))
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103
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104 ;; Describe a user's asm statement.
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105 (define_asm_attributes
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106 [(set_attr "type" "multi")])
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107
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108
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109 ;; Pipeline model.
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110
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111 ;; The Xtensa basically has simple 5-stage RISC pipeline.
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112 ;; Most instructions complete in 1 cycle, and it is OK to assume that
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113 ;; everything is fully pipelined. The exceptions have special insn
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114 ;; reservations in the pipeline description below. The Xtensa can
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115 ;; issue one instruction per cycle, so defining CPU units is unnecessary.
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116
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117 (define_insn_reservation "xtensa_any_insn" 1
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118 (eq_attr "type" "!load,fload,rsr,mul16,mul32,fmadd,fconv")
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119 "nothing")
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120
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121 (define_insn_reservation "xtensa_memory" 2
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122 (eq_attr "type" "load,fload")
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123 "nothing")
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124
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125 (define_insn_reservation "xtensa_sreg" 2
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126 (eq_attr "type" "rsr")
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127 "nothing")
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128
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129 (define_insn_reservation "xtensa_mul16" 2
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130 (eq_attr "type" "mul16")
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131 "nothing")
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132
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133 (define_insn_reservation "xtensa_mul32" 2
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134 (eq_attr "type" "mul32")
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135 "nothing")
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136
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137 (define_insn_reservation "xtensa_fmadd" 4
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138 (eq_attr "type" "fmadd")
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139 "nothing")
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140
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141 (define_insn_reservation "xtensa_fconv" 2
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142 (eq_attr "type" "fconv")
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143 "nothing")
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144
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145 ;; Include predicates and constraints.
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146
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147 (include "predicates.md")
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148 (include "constraints.md")
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149
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150
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151 ;; Addition.
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152
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153 (define_insn "addsi3"
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154 [(set (match_operand:SI 0 "register_operand" "=D,D,a,a,a")
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155 (plus:SI (match_operand:SI 1 "register_operand" "%d,d,r,r,r")
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156 (match_operand:SI 2 "add_operand" "d,O,r,J,N")))]
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157 ""
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158 "@
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159 add.n\t%0, %1, %2
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160 addi.n\t%0, %1, %d2
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161 add\t%0, %1, %2
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162 addi\t%0, %1, %d2
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163 addmi\t%0, %1, %x2"
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164 [(set_attr "type" "arith,arith,arith,arith,arith")
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165 (set_attr "mode" "SI")
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166 (set_attr "length" "2,2,3,3,3")])
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167
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168 (define_insn "*addx"
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169 [(set (match_operand:SI 0 "register_operand" "=a")
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170 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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171 (match_operand:SI 3 "addsubx_operand" "i"))
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172 (match_operand:SI 2 "register_operand" "r")))]
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173 "TARGET_ADDX"
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174 "addx%3\t%0, %1, %2"
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175 [(set_attr "type" "arith")
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176 (set_attr "mode" "SI")
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177 (set_attr "length" "3")])
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178
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179 (define_insn "addsf3"
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180 [(set (match_operand:SF 0 "register_operand" "=f")
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181 (plus:SF (match_operand:SF 1 "register_operand" "%f")
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182 (match_operand:SF 2 "register_operand" "f")))]
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183 "TARGET_HARD_FLOAT"
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184 "add.s\t%0, %1, %2"
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185 [(set_attr "type" "fmadd")
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186 (set_attr "mode" "SF")
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187 (set_attr "length" "3")])
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188
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189
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190 ;; Subtraction.
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191
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192 (define_insn "subsi3"
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193 [(set (match_operand:SI 0 "register_operand" "=a")
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194 (minus:SI (match_operand:SI 1 "register_operand" "r")
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195 (match_operand:SI 2 "register_operand" "r")))]
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196 ""
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197 "sub\t%0, %1, %2"
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198 [(set_attr "type" "arith")
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199 (set_attr "mode" "SI")
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200 (set_attr "length" "3")])
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201
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202 (define_insn "*subx"
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203 [(set (match_operand:SI 0 "register_operand" "=a")
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204 (minus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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205 (match_operand:SI 3 "addsubx_operand" "i"))
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206 (match_operand:SI 2 "register_operand" "r")))]
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207 "TARGET_ADDX"
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208 "subx%3\t%0, %1, %2"
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209 [(set_attr "type" "arith")
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210 (set_attr "mode" "SI")
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211 (set_attr "length" "3")])
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212
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213 (define_insn "subsf3"
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214 [(set (match_operand:SF 0 "register_operand" "=f")
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215 (minus:SF (match_operand:SF 1 "register_operand" "f")
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216 (match_operand:SF 2 "register_operand" "f")))]
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217 "TARGET_HARD_FLOAT"
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218 "sub.s\t%0, %1, %2"
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219 [(set_attr "type" "fmadd")
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220 (set_attr "mode" "SF")
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221 (set_attr "length" "3")])
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222
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223
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224 ;; Multiplication.
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225
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226 (define_expand "<u>mulsidi3"
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227 [(set (match_operand:DI 0 "register_operand")
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228 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
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229 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
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230 "TARGET_MUL32_HIGH"
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231 {
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232 rtx temp = gen_reg_rtx (SImode);
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233 emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
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234 emit_insn (gen_<u>mulsi3_highpart (gen_highpart (SImode, operands[0]),
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235 operands[1], operands[2]));
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236 emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), temp));
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237 DONE;
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238 })
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239
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240 (define_insn "<u>mulsi3_highpart"
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241 [(set (match_operand:SI 0 "register_operand" "=a")
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242 (truncate:SI
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243 (lshiftrt:DI
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244 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "%r"))
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245 (any_extend:DI (match_operand:SI 2 "register_operand" "r")))
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246 (const_int 32))))]
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247 "TARGET_MUL32_HIGH"
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248 "mul<su>h\t%0, %1, %2"
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249 [(set_attr "type" "mul32")
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250 (set_attr "mode" "SI")
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251 (set_attr "length" "3")])
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252
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253 (define_insn "mulsi3"
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254 [(set (match_operand:SI 0 "register_operand" "=a")
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255 (mult:SI (match_operand:SI 1 "register_operand" "%r")
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256 (match_operand:SI 2 "register_operand" "r")))]
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257 "TARGET_MUL32"
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258 "mull\t%0, %1, %2"
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259 [(set_attr "type" "mul32")
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260 (set_attr "mode" "SI")
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261 (set_attr "length" "3")])
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262
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263 (define_insn "mulhisi3"
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264 [(set (match_operand:SI 0 "register_operand" "=C,A")
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265 (mult:SI (sign_extend:SI
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266 (match_operand:HI 1 "register_operand" "%r,r"))
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267 (sign_extend:SI
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268 (match_operand:HI 2 "register_operand" "r,r"))))]
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269 "TARGET_MUL16 || TARGET_MAC16"
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270 "@
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271 mul16s\t%0, %1, %2
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272 mul.aa.ll\t%1, %2"
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273 [(set_attr "type" "mul16,mac16")
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274 (set_attr "mode" "SI")
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275 (set_attr "length" "3,3")])
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276
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277 (define_insn "umulhisi3"
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278 [(set (match_operand:SI 0 "register_operand" "=C,A")
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279 (mult:SI (zero_extend:SI
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280 (match_operand:HI 1 "register_operand" "%r,r"))
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281 (zero_extend:SI
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282 (match_operand:HI 2 "register_operand" "r,r"))))]
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283 "TARGET_MUL16 || TARGET_MAC16"
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284 "@
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285 mul16u\t%0, %1, %2
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286 umul.aa.ll\t%1, %2"
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287 [(set_attr "type" "mul16,mac16")
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288 (set_attr "mode" "SI")
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289 (set_attr "length" "3,3")])
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290
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291 (define_insn "muladdhisi"
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292 [(set (match_operand:SI 0 "register_operand" "=A")
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293 (plus:SI (mult:SI (sign_extend:SI
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294 (match_operand:HI 1 "register_operand" "%r"))
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295 (sign_extend:SI
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296 (match_operand:HI 2 "register_operand" "r")))
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297 (match_operand:SI 3 "register_operand" "0")))]
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298 "TARGET_MAC16"
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299 "mula.aa.ll\t%1, %2"
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300 [(set_attr "type" "mac16")
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301 (set_attr "mode" "SI")
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302 (set_attr "length" "3")])
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303
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304 (define_insn "mulsubhisi"
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305 [(set (match_operand:SI 0 "register_operand" "=A")
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306 (minus:SI (match_operand:SI 1 "register_operand" "0")
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307 (mult:SI (sign_extend:SI
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308 (match_operand:HI 2 "register_operand" "%r"))
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309 (sign_extend:SI
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310 (match_operand:HI 3 "register_operand" "r")))))]
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311 "TARGET_MAC16"
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312 "muls.aa.ll\t%2, %3"
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313 [(set_attr "type" "mac16")
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314 (set_attr "mode" "SI")
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315 (set_attr "length" "3")])
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316
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317 (define_insn "mulsf3"
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318 [(set (match_operand:SF 0 "register_operand" "=f")
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319 (mult:SF (match_operand:SF 1 "register_operand" "%f")
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320 (match_operand:SF 2 "register_operand" "f")))]
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321 "TARGET_HARD_FLOAT"
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322 "mul.s\t%0, %1, %2"
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323 [(set_attr "type" "fmadd")
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324 (set_attr "mode" "SF")
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325 (set_attr "length" "3")])
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326
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327 (define_insn "muladdsf3"
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328 [(set (match_operand:SF 0 "register_operand" "=f")
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329 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f")
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330 (match_operand:SF 2 "register_operand" "f"))
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331 (match_operand:SF 3 "register_operand" "0")))]
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332 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
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333 "madd.s\t%0, %1, %2"
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334 [(set_attr "type" "fmadd")
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335 (set_attr "mode" "SF")
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336 (set_attr "length" "3")])
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337
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338 (define_insn "mulsubsf3"
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339 [(set (match_operand:SF 0 "register_operand" "=f")
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340 (minus:SF (match_operand:SF 1 "register_operand" "0")
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341 (mult:SF (match_operand:SF 2 "register_operand" "%f")
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342 (match_operand:SF 3 "register_operand" "f"))))]
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343 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
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344 "msub.s\t%0, %2, %3"
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345 [(set_attr "type" "fmadd")
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346 (set_attr "mode" "SF")
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347 (set_attr "length" "3")])
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348
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349
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350 ;; Division.
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351
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352 (define_insn "divsi3"
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353 [(set (match_operand:SI 0 "register_operand" "=a")
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354 (div:SI (match_operand:SI 1 "register_operand" "r")
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355 (match_operand:SI 2 "register_operand" "r")))]
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356 "TARGET_DIV32"
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357 "quos\t%0, %1, %2"
|
|
|
358 [(set_attr "type" "div32")
|
|
|
359 (set_attr "mode" "SI")
|
|
|
360 (set_attr "length" "3")])
|
|
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361
|
|
|
362 (define_insn "udivsi3"
|
|
|
363 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
364 (udiv:SI (match_operand:SI 1 "register_operand" "r")
|
|
|
365 (match_operand:SI 2 "register_operand" "r")))]
|
|
|
366 "TARGET_DIV32"
|
|
|
367 "quou\t%0, %1, %2"
|
|
|
368 [(set_attr "type" "div32")
|
|
|
369 (set_attr "mode" "SI")
|
|
|
370 (set_attr "length" "3")])
|
|
|
371
|
|
|
372 (define_insn "divsf3"
|
|
|
373 [(set (match_operand:SF 0 "register_operand" "=f")
|
|
|
374 (div:SF (match_operand:SF 1 "register_operand" "f")
|
|
|
375 (match_operand:SF 2 "register_operand" "f")))]
|
|
|
376 "TARGET_HARD_FLOAT_DIV"
|
|
|
377 "div.s\t%0, %1, %2"
|
|
|
378 [(set_attr "type" "fdiv")
|
|
|
379 (set_attr "mode" "SF")
|
|
|
380 (set_attr "length" "3")])
|
|
|
381
|
|
|
382 (define_insn "*recipsf2"
|
|
|
383 [(set (match_operand:SF 0 "register_operand" "=f")
|
|
|
384 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
|
|
|
385 (match_operand:SF 2 "register_operand" "f")))]
|
|
|
386 "TARGET_HARD_FLOAT_RECIP && flag_unsafe_math_optimizations"
|
|
|
387 "recip.s\t%0, %2"
|
|
|
388 [(set_attr "type" "fdiv")
|
|
|
389 (set_attr "mode" "SF")
|
|
|
390 (set_attr "length" "3")])
|
|
|
391
|
|
|
392
|
|
|
393 ;; Remainders.
|
|
|
394
|
|
|
395 (define_insn "modsi3"
|
|
|
396 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
397 (mod:SI (match_operand:SI 1 "register_operand" "r")
|
|
|
398 (match_operand:SI 2 "register_operand" "r")))]
|
|
|
399 "TARGET_DIV32"
|
|
|
400 "rems\t%0, %1, %2"
|
|
|
401 [(set_attr "type" "div32")
|
|
|
402 (set_attr "mode" "SI")
|
|
|
403 (set_attr "length" "3")])
|
|
|
404
|
|
|
405 (define_insn "umodsi3"
|
|
|
406 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
407 (umod:SI (match_operand:SI 1 "register_operand" "r")
|
|
|
408 (match_operand:SI 2 "register_operand" "r")))]
|
|
|
409 "TARGET_DIV32"
|
|
|
410 "remu\t%0, %1, %2"
|
|
|
411 [(set_attr "type" "div32")
|
|
|
412 (set_attr "mode" "SI")
|
|
|
413 (set_attr "length" "3")])
|
|
|
414
|
|
|
415
|
|
|
416 ;; Square roots.
|
|
|
417
|
|
|
418 (define_insn "sqrtsf2"
|
|
|
419 [(set (match_operand:SF 0 "register_operand" "=f")
|
|
|
420 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
|
|
|
421 "TARGET_HARD_FLOAT_SQRT"
|
|
|
422 "sqrt.s\t%0, %1"
|
|
|
423 [(set_attr "type" "fsqrt")
|
|
|
424 (set_attr "mode" "SF")
|
|
|
425 (set_attr "length" "3")])
|
|
|
426
|
|
|
427 (define_insn "*rsqrtsf2"
|
|
|
428 [(set (match_operand:SF 0 "register_operand" "=f")
|
|
|
429 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
|
|
|
430 (sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
|
|
|
431 "TARGET_HARD_FLOAT_RSQRT && flag_unsafe_math_optimizations"
|
|
|
432 "rsqrt.s\t%0, %2"
|
|
|
433 [(set_attr "type" "fsqrt")
|
|
|
434 (set_attr "mode" "SF")
|
|
|
435 (set_attr "length" "3")])
|
|
|
436
|
|
|
437
|
|
|
438 ;; Absolute value.
|
|
|
439
|
|
|
440 (define_insn "abssi2"
|
|
|
441 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
442 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
|
|
|
443 "TARGET_ABS"
|
|
|
444 "abs\t%0, %1"
|
|
|
445 [(set_attr "type" "arith")
|
|
|
446 (set_attr "mode" "SI")
|
|
|
447 (set_attr "length" "3")])
|
|
|
448
|
|
|
449 (define_insn "abssf2"
|
|
|
450 [(set (match_operand:SF 0 "register_operand" "=f")
|
|
|
451 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
|
|
|
452 "TARGET_HARD_FLOAT"
|
|
|
453 "abs.s\t%0, %1"
|
|
|
454 [(set_attr "type" "farith")
|
|
|
455 (set_attr "mode" "SF")
|
|
|
456 (set_attr "length" "3")])
|
|
|
457
|
|
|
458
|
|
|
459 ;; Min and max.
|
|
|
460
|
|
|
461 (define_insn "<code>si3"
|
|
|
462 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
463 (any_minmax:SI (match_operand:SI 1 "register_operand" "%r")
|
|
|
464 (match_operand:SI 2 "register_operand" "r")))]
|
|
|
465 "TARGET_MINMAX"
|
|
|
466 "<minmax>\t%0, %1, %2"
|
|
|
467 [(set_attr "type" "arith")
|
|
|
468 (set_attr "mode" "SI")
|
|
|
469 (set_attr "length" "3")])
|
|
|
470
|
|
|
471
|
|
|
472 ;; Count leading/trailing zeros and find first bit.
|
|
|
473
|
|
|
474 (define_insn "clzsi2"
|
|
|
475 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
476 (clz:SI (match_operand:SI 1 "register_operand" "r")))]
|
|
|
477 "TARGET_NSA"
|
|
|
478 "nsau\t%0, %1"
|
|
|
479 [(set_attr "type" "arith")
|
|
|
480 (set_attr "mode" "SI")
|
|
|
481 (set_attr "length" "3")])
|
|
|
482
|
|
|
483 (define_expand "ctzsi2"
|
|
|
484 [(set (match_operand:SI 0 "register_operand" "")
|
|
|
485 (ctz:SI (match_operand:SI 1 "register_operand" "")))]
|
|
|
486 "TARGET_NSA"
|
|
|
487 {
|
|
|
488 rtx temp = gen_reg_rtx (SImode);
|
|
|
489 emit_insn (gen_negsi2 (temp, operands[1]));
|
|
|
490 emit_insn (gen_andsi3 (temp, temp, operands[1]));
|
|
|
491 emit_insn (gen_clzsi2 (temp, temp));
|
|
|
492 emit_insn (gen_negsi2 (temp, temp));
|
|
|
493 emit_insn (gen_addsi3 (operands[0], temp, GEN_INT (31)));
|
|
|
494 DONE;
|
|
|
495 })
|
|
|
496
|
|
|
497 (define_expand "ffssi2"
|
|
|
498 [(set (match_operand:SI 0 "register_operand" "")
|
|
|
499 (ffs:SI (match_operand:SI 1 "register_operand" "")))]
|
|
|
500 "TARGET_NSA"
|
|
|
501 {
|
|
|
502 rtx temp = gen_reg_rtx (SImode);
|
|
|
503 emit_insn (gen_negsi2 (temp, operands[1]));
|
|
|
504 emit_insn (gen_andsi3 (temp, temp, operands[1]));
|
|
|
505 emit_insn (gen_clzsi2 (temp, temp));
|
|
|
506 emit_insn (gen_negsi2 (temp, temp));
|
|
|
507 emit_insn (gen_addsi3 (operands[0], temp, GEN_INT (32)));
|
|
|
508 DONE;
|
|
|
509 })
|
|
|
510
|
|
|
511
|
|
|
512 ;; Negation and one's complement.
|
|
|
513
|
|
|
514 (define_insn "negsi2"
|
|
|
515 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
516 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
|
|
|
517 ""
|
|
|
518 "neg\t%0, %1"
|
|
|
519 [(set_attr "type" "arith")
|
|
|
520 (set_attr "mode" "SI")
|
|
|
521 (set_attr "length" "3")])
|
|
|
522
|
|
|
523 (define_expand "one_cmplsi2"
|
|
|
524 [(set (match_operand:SI 0 "register_operand" "")
|
|
|
525 (not:SI (match_operand:SI 1 "register_operand" "")))]
|
|
|
526 ""
|
|
|
527 {
|
|
|
528 rtx temp = gen_reg_rtx (SImode);
|
|
|
529 emit_insn (gen_movsi (temp, constm1_rtx));
|
|
|
530 emit_insn (gen_xorsi3 (operands[0], temp, operands[1]));
|
|
|
531 DONE;
|
|
|
532 })
|
|
|
533
|
|
|
534 (define_insn "negsf2"
|
|
|
535 [(set (match_operand:SF 0 "register_operand" "=f")
|
|
|
536 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
|
|
|
537 "TARGET_HARD_FLOAT"
|
|
|
538 "neg.s\t%0, %1"
|
|
|
539 [(set_attr "type" "farith")
|
|
|
540 (set_attr "mode" "SF")
|
|
|
541 (set_attr "length" "3")])
|
|
|
542
|
|
|
543
|
|
|
544 ;; Logical instructions.
|
|
|
545
|
|
|
546 (define_insn "andsi3"
|
|
|
547 [(set (match_operand:SI 0 "register_operand" "=a,a")
|
|
|
548 (and:SI (match_operand:SI 1 "register_operand" "%r,r")
|
|
|
549 (match_operand:SI 2 "mask_operand" "P,r")))]
|
|
|
550 ""
|
|
|
551 "@
|
|
|
552 extui\t%0, %1, 0, %K2
|
|
|
553 and\t%0, %1, %2"
|
|
|
554 [(set_attr "type" "arith,arith")
|
|
|
555 (set_attr "mode" "SI")
|
|
|
556 (set_attr "length" "3,3")])
|
|
|
557
|
|
|
558 (define_insn "iorsi3"
|
|
|
559 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
560 (ior:SI (match_operand:SI 1 "register_operand" "%r")
|
|
|
561 (match_operand:SI 2 "register_operand" "r")))]
|
|
|
562 ""
|
|
|
563 "or\t%0, %1, %2"
|
|
|
564 [(set_attr "type" "arith")
|
|
|
565 (set_attr "mode" "SI")
|
|
|
566 (set_attr "length" "3")])
|
|
|
567
|
|
|
568 (define_insn "xorsi3"
|
|
|
569 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
570 (xor:SI (match_operand:SI 1 "register_operand" "%r")
|
|
|
571 (match_operand:SI 2 "register_operand" "r")))]
|
|
|
572 ""
|
|
|
573 "xor\t%0, %1, %2"
|
|
|
574 [(set_attr "type" "arith")
|
|
|
575 (set_attr "mode" "SI")
|
|
|
576 (set_attr "length" "3")])
|
|
|
577
|
|
|
578
|
|
|
579 ;; Zero-extend instructions.
|
|
|
580
|
|
|
581 (define_insn "zero_extendhisi2"
|
|
|
582 [(set (match_operand:SI 0 "register_operand" "=a,a")
|
|
|
583 (zero_extend:SI (match_operand:HI 1 "nonimmed_operand" "r,U")))]
|
|
|
584 ""
|
|
|
585 "@
|
|
|
586 extui\t%0, %1, 0, 16
|
|
|
587 l16ui\t%0, %1"
|
|
|
588 [(set_attr "type" "arith,load")
|
|
|
589 (set_attr "mode" "SI")
|
|
|
590 (set_attr "length" "3,3")])
|
|
|
591
|
|
|
592 (define_insn "zero_extendqisi2"
|
|
|
593 [(set (match_operand:SI 0 "register_operand" "=a,a")
|
|
|
594 (zero_extend:SI (match_operand:QI 1 "nonimmed_operand" "r,U")))]
|
|
|
595 ""
|
|
|
596 "@
|
|
|
597 extui\t%0, %1, 0, 8
|
|
|
598 l8ui\t%0, %1"
|
|
|
599 [(set_attr "type" "arith,load")
|
|
|
600 (set_attr "mode" "SI")
|
|
|
601 (set_attr "length" "3,3")])
|
|
|
602
|
|
|
603
|
|
|
604 ;; Sign-extend instructions.
|
|
|
605
|
|
|
606 (define_expand "extendhisi2"
|
|
|
607 [(set (match_operand:SI 0 "register_operand" "")
|
|
|
608 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
|
|
|
609 ""
|
|
|
610 {
|
|
|
611 if (sext_operand (operands[1], HImode))
|
|
|
612 emit_insn (gen_extendhisi2_internal (operands[0], operands[1]));
|
|
|
613 else
|
|
|
614 xtensa_extend_reg (operands[0], operands[1]);
|
|
|
615 DONE;
|
|
|
616 })
|
|
|
617
|
|
|
618 (define_insn "extendhisi2_internal"
|
|
|
619 [(set (match_operand:SI 0 "register_operand" "=B,a")
|
|
|
620 (sign_extend:SI (match_operand:HI 1 "sext_operand" "r,U")))]
|
|
|
621 ""
|
|
|
622 "@
|
|
|
623 sext\t%0, %1, 15
|
|
|
624 l16si\t%0, %1"
|
|
|
625 [(set_attr "type" "arith,load")
|
|
|
626 (set_attr "mode" "SI")
|
|
|
627 (set_attr "length" "3,3")])
|
|
|
628
|
|
|
629 (define_expand "extendqisi2"
|
|
|
630 [(set (match_operand:SI 0 "register_operand" "")
|
|
|
631 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
|
|
|
632 ""
|
|
|
633 {
|
|
|
634 if (TARGET_SEXT)
|
|
|
635 emit_insn (gen_extendqisi2_internal (operands[0], operands[1]));
|
|
|
636 else
|
|
|
637 xtensa_extend_reg (operands[0], operands[1]);
|
|
|
638 DONE;
|
|
|
639 })
|
|
|
640
|
|
|
641 (define_insn "extendqisi2_internal"
|
|
|
642 [(set (match_operand:SI 0 "register_operand" "=B")
|
|
|
643 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
|
|
|
644 "TARGET_SEXT"
|
|
|
645 "sext\t%0, %1, 7"
|
|
|
646 [(set_attr "type" "arith")
|
|
|
647 (set_attr "mode" "SI")
|
|
|
648 (set_attr "length" "3")])
|
|
|
649
|
|
|
650
|
|
|
651 ;; Field extract instructions.
|
|
|
652
|
|
|
653 (define_expand "extv"
|
|
|
654 [(set (match_operand:SI 0 "register_operand" "")
|
|
|
655 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
|
|
|
656 (match_operand:SI 2 "const_int_operand" "")
|
|
|
657 (match_operand:SI 3 "const_int_operand" "")))]
|
|
|
658 "TARGET_SEXT"
|
|
|
659 {
|
|
|
660 if (!sext_fldsz_operand (operands[2], SImode))
|
|
|
661 FAIL;
|
|
|
662
|
|
|
663 /* We could expand to a right shift followed by SEXT but that's
|
|
|
664 no better than the standard left and right shift sequence. */
|
|
|
665 if (!lsbitnum_operand (operands[3], SImode))
|
|
|
666 FAIL;
|
|
|
667
|
|
|
668 emit_insn (gen_extv_internal (operands[0], operands[1],
|
|
|
669 operands[2], operands[3]));
|
|
|
670 DONE;
|
|
|
671 })
|
|
|
672
|
|
|
673 (define_insn "extv_internal"
|
|
|
674 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
675 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
|
|
|
676 (match_operand:SI 2 "sext_fldsz_operand" "i")
|
|
|
677 (match_operand:SI 3 "lsbitnum_operand" "i")))]
|
|
|
678 "TARGET_SEXT"
|
|
|
679 {
|
|
|
680 int fldsz = INTVAL (operands[2]);
|
|
|
681 operands[2] = GEN_INT (fldsz - 1);
|
|
|
682 return "sext\t%0, %1, %2";
|
|
|
683 }
|
|
|
684 [(set_attr "type" "arith")
|
|
|
685 (set_attr "mode" "SI")
|
|
|
686 (set_attr "length" "3")])
|
|
|
687
|
|
|
688 (define_expand "extzv"
|
|
|
689 [(set (match_operand:SI 0 "register_operand" "")
|
|
|
690 (zero_extract:SI (match_operand:SI 1 "register_operand" "")
|
|
|
691 (match_operand:SI 2 "const_int_operand" "")
|
|
|
692 (match_operand:SI 3 "const_int_operand" "")))]
|
|
|
693 ""
|
|
|
694 {
|
|
|
695 if (!extui_fldsz_operand (operands[2], SImode))
|
|
|
696 FAIL;
|
|
|
697 emit_insn (gen_extzv_internal (operands[0], operands[1],
|
|
|
698 operands[2], operands[3]));
|
|
|
699 DONE;
|
|
|
700 })
|
|
|
701
|
|
|
702 (define_insn "extzv_internal"
|
|
|
703 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
704 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
|
|
|
705 (match_operand:SI 2 "extui_fldsz_operand" "i")
|
|
|
706 (match_operand:SI 3 "const_int_operand" "i")))]
|
|
|
707 ""
|
|
|
708 {
|
|
|
709 int shift;
|
|
|
710 if (BITS_BIG_ENDIAN)
|
|
|
711 shift = (32 - (INTVAL (operands[2]) + INTVAL (operands[3]))) & 0x1f;
|
|
|
712 else
|
|
|
713 shift = INTVAL (operands[3]) & 0x1f;
|
|
|
714 operands[3] = GEN_INT (shift);
|
|
|
715 return "extui\t%0, %1, %3, %2";
|
|
|
716 }
|
|
|
717 [(set_attr "type" "arith")
|
|
|
718 (set_attr "mode" "SI")
|
|
|
719 (set_attr "length" "3")])
|
|
|
720
|
|
|
721
|
|
|
722 ;; Conversions.
|
|
|
723
|
|
|
724 (define_insn "fix_truncsfsi2"
|
|
|
725 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
726 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
|
|
|
727 "TARGET_HARD_FLOAT"
|
|
|
728 "trunc.s\t%0, %1, 0"
|
|
|
729 [(set_attr "type" "fconv")
|
|
|
730 (set_attr "mode" "SF")
|
|
|
731 (set_attr "length" "3")])
|
|
|
732
|
|
|
733 (define_insn "fixuns_truncsfsi2"
|
|
|
734 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
735 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "f")))]
|
|
|
736 "TARGET_HARD_FLOAT"
|
|
|
737 "utrunc.s\t%0, %1, 0"
|
|
|
738 [(set_attr "type" "fconv")
|
|
|
739 (set_attr "mode" "SF")
|
|
|
740 (set_attr "length" "3")])
|
|
|
741
|
|
|
742 (define_insn "floatsisf2"
|
|
|
743 [(set (match_operand:SF 0 "register_operand" "=f")
|
|
|
744 (float:SF (match_operand:SI 1 "register_operand" "a")))]
|
|
|
745 "TARGET_HARD_FLOAT"
|
|
|
746 "float.s\t%0, %1, 0"
|
|
|
747 [(set_attr "type" "fconv")
|
|
|
748 (set_attr "mode" "SF")
|
|
|
749 (set_attr "length" "3")])
|
|
|
750
|
|
|
751 (define_insn "floatunssisf2"
|
|
|
752 [(set (match_operand:SF 0 "register_operand" "=f")
|
|
|
753 (unsigned_float:SF (match_operand:SI 1 "register_operand" "a")))]
|
|
|
754 "TARGET_HARD_FLOAT"
|
|
|
755 "ufloat.s\t%0, %1, 0"
|
|
|
756 [(set_attr "type" "fconv")
|
|
|
757 (set_attr "mode" "SF")
|
|
|
758 (set_attr "length" "3")])
|
|
|
759
|
|
|
760
|
|
|
761 ;; Data movement instructions.
|
|
|
762
|
|
|
763 ;; 64-bit Integer moves
|
|
|
764
|
|
|
765 (define_expand "movdi"
|
|
|
766 [(set (match_operand:DI 0 "nonimmed_operand" "")
|
|
|
767 (match_operand:DI 1 "general_operand" ""))]
|
|
|
768 ""
|
|
|
769 {
|
|
|
770 if (CONSTANT_P (operands[1]) && !TARGET_CONST16)
|
|
|
771 operands[1] = force_const_mem (DImode, operands[1]);
|
|
|
772
|
|
|
773 if (!register_operand (operands[0], DImode)
|
|
|
774 && !register_operand (operands[1], DImode))
|
|
|
775 operands[1] = force_reg (DImode, operands[1]);
|
|
|
776
|
|
|
777 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
|
|
|
778 })
|
|
|
779
|
|
|
780 (define_insn_and_split "movdi_internal"
|
|
|
781 [(set (match_operand:DI 0 "nonimmed_operand" "=a,W,a,a,U")
|
|
|
782 (match_operand:DI 1 "move_operand" "r,i,T,U,r"))]
|
|
|
783 "register_operand (operands[0], DImode)
|
|
|
784 || register_operand (operands[1], DImode)"
|
|
|
785 "#"
|
|
|
786 "reload_completed"
|
|
|
787 [(set (match_dup 0) (match_dup 2))
|
|
|
788 (set (match_dup 1) (match_dup 3))]
|
|
|
789 {
|
|
|
790 xtensa_split_operand_pair (operands, SImode);
|
|
|
791 if (reg_overlap_mentioned_p (operands[0], operands[3]))
|
|
|
792 {
|
|
|
793 rtx tmp;
|
|
|
794 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
|
|
|
795 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
|
|
|
796 }
|
|
|
797 })
|
|
|
798
|
|
|
799 ;; 32-bit Integer moves
|
|
|
800
|
|
|
801 (define_expand "movsi"
|
|
|
802 [(set (match_operand:SI 0 "nonimmed_operand" "")
|
|
|
803 (match_operand:SI 1 "general_operand" ""))]
|
|
|
804 ""
|
|
|
805 {
|
|
|
806 if (xtensa_emit_move_sequence (operands, SImode))
|
|
|
807 DONE;
|
|
|
808 })
|
|
|
809
|
|
|
810 (define_insn "movsi_internal"
|
|
|
811 [(set (match_operand:SI 0 "nonimmed_operand" "=D,D,D,D,R,R,a,q,a,W,a,a,U,*a,*A")
|
|
|
812 (match_operand:SI 1 "move_operand" "M,D,d,R,D,d,r,r,I,i,T,U,r,*A,*r"))]
|
|
|
813 "xtensa_valid_move (SImode, operands)"
|
|
|
814 "@
|
|
|
815 movi.n\t%0, %x1
|
|
|
816 mov.n\t%0, %1
|
|
|
817 mov.n\t%0, %1
|
|
|
818 %v1l32i.n\t%0, %1
|
|
|
819 %v0s32i.n\t%1, %0
|
|
|
820 %v0s32i.n\t%1, %0
|
|
|
821 mov\t%0, %1
|
|
|
822 movsp\t%0, %1
|
|
|
823 movi\t%0, %x1
|
|
|
824 const16\t%0, %t1\;const16\t%0, %b1
|
|
|
825 %v1l32r\t%0, %1
|
|
|
826 %v1l32i\t%0, %1
|
|
|
827 %v0s32i\t%1, %0
|
|
|
828 rsr\t%0, ACCLO
|
|
|
829 wsr\t%1, ACCLO"
|
|
|
830 [(set_attr "type" "move,move,move,load,store,store,move,move,move,move,load,load,store,rsr,wsr")
|
|
|
831 (set_attr "mode" "SI")
|
|
|
832 (set_attr "length" "2,2,2,2,2,2,3,3,3,6,3,3,3,3,3")])
|
|
|
833
|
|
|
834 ;; 16-bit Integer moves
|
|
|
835
|
|
|
836 (define_expand "movhi"
|
|
|
837 [(set (match_operand:HI 0 "nonimmed_operand" "")
|
|
|
838 (match_operand:HI 1 "general_operand" ""))]
|
|
|
839 ""
|
|
|
840 {
|
|
|
841 if (xtensa_emit_move_sequence (operands, HImode))
|
|
|
842 DONE;
|
|
|
843 })
|
|
|
844
|
|
|
845 (define_insn "movhi_internal"
|
|
|
846 [(set (match_operand:HI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A")
|
|
|
847 (match_operand:HI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))]
|
|
|
848 "xtensa_valid_move (HImode, operands)"
|
|
|
849 "@
|
|
|
850 movi.n\t%0, %x1
|
|
|
851 mov.n\t%0, %1
|
|
|
852 mov\t%0, %1
|
|
|
853 movi\t%0, %x1
|
|
|
854 %v1l16ui\t%0, %1
|
|
|
855 %v0s16i\t%1, %0
|
|
|
856 rsr\t%0, ACCLO
|
|
|
857 wsr\t%1, ACCLO"
|
|
|
858 [(set_attr "type" "move,move,move,move,load,store,rsr,wsr")
|
|
|
859 (set_attr "mode" "HI")
|
|
|
860 (set_attr "length" "2,2,3,3,3,3,3,3")])
|
|
|
861
|
|
|
862 ;; 8-bit Integer moves
|
|
|
863
|
|
|
864 (define_expand "movqi"
|
|
|
865 [(set (match_operand:QI 0 "nonimmed_operand" "")
|
|
|
866 (match_operand:QI 1 "general_operand" ""))]
|
|
|
867 ""
|
|
|
868 {
|
|
|
869 if (xtensa_emit_move_sequence (operands, QImode))
|
|
|
870 DONE;
|
|
|
871 })
|
|
|
872
|
|
|
873 (define_insn "movqi_internal"
|
|
|
874 [(set (match_operand:QI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A")
|
|
|
875 (match_operand:QI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))]
|
|
|
876 "xtensa_valid_move (QImode, operands)"
|
|
|
877 "@
|
|
|
878 movi.n\t%0, %x1
|
|
|
879 mov.n\t%0, %1
|
|
|
880 mov\t%0, %1
|
|
|
881 movi\t%0, %x1
|
|
|
882 %v1l8ui\t%0, %1
|
|
|
883 %v0s8i\t%1, %0
|
|
|
884 rsr\t%0, ACCLO
|
|
|
885 wsr\t%1, ACCLO"
|
|
|
886 [(set_attr "type" "move,move,move,move,load,store,rsr,wsr")
|
|
|
887 (set_attr "mode" "QI")
|
|
|
888 (set_attr "length" "2,2,3,3,3,3,3,3")])
|
|
|
889
|
|
|
890 ;; Sub-word reloads from the constant pool.
|
|
|
891
|
|
|
892 (define_expand "reload<mode>_literal"
|
|
|
893 [(parallel [(match_operand:HQI 0 "register_operand" "=r")
|
|
|
894 (match_operand:HQI 1 "constantpool_operand" "")
|
|
|
895 (match_operand:SI 2 "register_operand" "=&r")])]
|
|
|
896 ""
|
|
|
897 {
|
|
|
898 rtx lit, scratch;
|
|
|
899 unsigned word_off, byte_off;
|
|
|
900
|
|
|
901 if (MEM_P (operands[1]))
|
|
|
902 {
|
|
|
903 lit = operands[1];
|
|
|
904 word_off = 0;
|
|
|
905 byte_off = 0;
|
|
|
906 }
|
|
|
907 else
|
|
|
908 {
|
|
|
909 gcc_assert (GET_CODE (operands[1]) == SUBREG);
|
|
|
910 lit = SUBREG_REG (operands[1]);
|
|
|
911 word_off = SUBREG_BYTE (operands[1]) & ~(UNITS_PER_WORD - 1);
|
|
|
912 byte_off = SUBREG_BYTE (operands[1]) - word_off;
|
|
|
913 }
|
|
|
914
|
|
|
915 lit = adjust_address (lit, SImode, word_off);
|
|
|
916 scratch = operands[2];
|
|
|
917 emit_insn (gen_movsi (scratch, lit));
|
|
|
918 emit_insn (gen_mov<mode> (operands[0],
|
|
|
919 gen_rtx_SUBREG (<MODE>mode, scratch, byte_off)));
|
|
|
920
|
|
|
921 DONE;
|
|
|
922 })
|
|
|
923
|
|
|
924 ;; 32-bit floating point moves
|
|
|
925
|
|
|
926 (define_expand "movsf"
|
|
|
927 [(set (match_operand:SF 0 "nonimmed_operand" "")
|
|
|
928 (match_operand:SF 1 "general_operand" ""))]
|
|
|
929 ""
|
|
|
930 {
|
|
|
931 if (!TARGET_CONST16 && CONSTANT_P (operands[1]))
|
|
|
932 operands[1] = force_const_mem (SFmode, operands[1]);
|
|
|
933
|
|
|
934 if ((!register_operand (operands[0], SFmode)
|
|
|
935 && !register_operand (operands[1], SFmode))
|
|
|
936 || (FP_REG_P (xt_true_regnum (operands[0]))
|
|
|
937 && !(reload_in_progress | reload_completed)
|
|
|
938 && (constantpool_mem_p (operands[1])
|
|
|
939 || CONSTANT_P (operands[1]))))
|
|
|
940 operands[1] = force_reg (SFmode, operands[1]);
|
|
|
941
|
|
|
942 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
|
|
|
943 })
|
|
|
944
|
|
|
945 (define_insn "movsf_internal"
|
|
|
946 [(set (match_operand:SF 0 "nonimmed_operand" "=f,f,U,D,D,R,a,f,a,W,a,a,U")
|
|
|
947 (match_operand:SF 1 "move_operand" "f,U,f,d,R,d,r,r,f,iF,T,U,r"))]
|
|
|
948 "((register_operand (operands[0], SFmode)
|
|
|
949 || register_operand (operands[1], SFmode))
|
|
|
950 && !(FP_REG_P (xt_true_regnum (operands[0]))
|
|
|
951 && (constantpool_mem_p (operands[1]) || CONSTANT_P (operands[1]))))"
|
|
|
952 "@
|
|
|
953 mov.s\t%0, %1
|
|
|
954 %v1lsi\t%0, %1
|
|
|
955 %v0ssi\t%1, %0
|
|
|
956 mov.n\t%0, %1
|
|
|
957 %v1l32i.n\t%0, %1
|
|
|
958 %v0s32i.n\t%1, %0
|
|
|
959 mov\t%0, %1
|
|
|
960 wfr\t%0, %1
|
|
|
961 rfr\t%0, %1
|
|
|
962 const16\t%0, %t1\;const16\t%0, %b1
|
|
|
963 %v1l32r\t%0, %1
|
|
|
964 %v1l32i\t%0, %1
|
|
|
965 %v0s32i\t%1, %0"
|
|
|
966 [(set_attr "type" "farith,fload,fstore,move,load,store,move,farith,farith,move,load,load,store")
|
|
|
967 (set_attr "mode" "SF")
|
|
|
968 (set_attr "length" "3,3,3,2,2,2,3,3,3,6,3,3,3")])
|
|
|
969
|
|
|
970 (define_insn "*lsiu"
|
|
|
971 [(set (match_operand:SF 0 "register_operand" "=f")
|
|
|
972 (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "+a")
|
|
|
973 (match_operand:SI 2 "fpmem_offset_operand" "i"))))
|
|
|
974 (set (match_dup 1)
|
|
|
975 (plus:SI (match_dup 1) (match_dup 2)))]
|
|
|
976 "TARGET_HARD_FLOAT"
|
|
|
977 {
|
|
|
978 if (TARGET_SERIALIZE_VOLATILE && volatile_refs_p (PATTERN (insn)))
|
|
|
979 output_asm_insn ("memw", operands);
|
|
|
980 return "lsiu\t%0, %1, %2";
|
|
|
981 }
|
|
|
982 [(set_attr "type" "fload")
|
|
|
983 (set_attr "mode" "SF")
|
|
|
984 (set_attr "length" "3")])
|
|
|
985
|
|
|
986 (define_insn "*ssiu"
|
|
|
987 [(set (mem:SF (plus:SI (match_operand:SI 0 "register_operand" "+a")
|
|
|
988 (match_operand:SI 1 "fpmem_offset_operand" "i")))
|
|
|
989 (match_operand:SF 2 "register_operand" "f"))
|
|
|
990 (set (match_dup 0)
|
|
|
991 (plus:SI (match_dup 0) (match_dup 1)))]
|
|
|
992 "TARGET_HARD_FLOAT"
|
|
|
993 {
|
|
|
994 if (TARGET_SERIALIZE_VOLATILE && volatile_refs_p (PATTERN (insn)))
|
|
|
995 output_asm_insn ("memw", operands);
|
|
|
996 return "ssiu\t%2, %0, %1";
|
|
|
997 }
|
|
|
998 [(set_attr "type" "fstore")
|
|
|
999 (set_attr "mode" "SF")
|
|
|
1000 (set_attr "length" "3")])
|
|
|
1001
|
|
|
1002 ;; 64-bit floating point moves
|
|
|
1003
|
|
|
1004 (define_expand "movdf"
|
|
|
1005 [(set (match_operand:DF 0 "nonimmed_operand" "")
|
|
|
1006 (match_operand:DF 1 "general_operand" ""))]
|
|
|
1007 ""
|
|
|
1008 {
|
|
|
1009 if (CONSTANT_P (operands[1]) && !TARGET_CONST16)
|
|
|
1010 operands[1] = force_const_mem (DFmode, operands[1]);
|
|
|
1011
|
|
|
1012 if (!register_operand (operands[0], DFmode)
|
|
|
1013 && !register_operand (operands[1], DFmode))
|
|
|
1014 operands[1] = force_reg (DFmode, operands[1]);
|
|
|
1015
|
|
|
1016 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
|
|
|
1017 })
|
|
|
1018
|
|
|
1019 (define_insn_and_split "movdf_internal"
|
|
|
1020 [(set (match_operand:DF 0 "nonimmed_operand" "=a,W,a,a,U")
|
|
|
1021 (match_operand:DF 1 "move_operand" "r,iF,T,U,r"))]
|
|
|
1022 "register_operand (operands[0], DFmode)
|
|
|
1023 || register_operand (operands[1], DFmode)"
|
|
|
1024 "#"
|
|
|
1025 "reload_completed"
|
|
|
1026 [(set (match_dup 0) (match_dup 2))
|
|
|
1027 (set (match_dup 1) (match_dup 3))]
|
|
|
1028 {
|
|
|
1029 xtensa_split_operand_pair (operands, SFmode);
|
|
|
1030 if (reg_overlap_mentioned_p (operands[0], operands[3]))
|
|
|
1031 {
|
|
|
1032 rtx tmp;
|
|
|
1033 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
|
|
|
1034 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
|
|
|
1035 }
|
|
|
1036 })
|
|
|
1037
|
|
|
1038 ;; Block moves
|
|
|
1039
|
|
|
1040 (define_expand "movmemsi"
|
|
|
1041 [(parallel [(set (match_operand:BLK 0 "" "")
|
|
|
1042 (match_operand:BLK 1 "" ""))
|
|
|
1043 (use (match_operand:SI 2 "arith_operand" ""))
|
|
|
1044 (use (match_operand:SI 3 "const_int_operand" ""))])]
|
|
|
1045 ""
|
|
|
1046 {
|
|
|
1047 if (!xtensa_expand_block_move (operands))
|
|
|
1048 FAIL;
|
|
|
1049 DONE;
|
|
|
1050 })
|
|
|
1051
|
|
|
1052
|
|
|
1053 ;; Shift instructions.
|
|
|
1054
|
|
|
1055 (define_expand "ashlsi3"
|
|
|
1056 [(set (match_operand:SI 0 "register_operand" "")
|
|
|
1057 (ashift:SI (match_operand:SI 1 "register_operand" "")
|
|
|
1058 (match_operand:SI 2 "arith_operand" "")))]
|
|
|
1059 ""
|
|
|
1060 {
|
|
|
1061 operands[1] = xtensa_copy_incoming_a7 (operands[1]);
|
|
|
1062 })
|
|
|
1063
|
|
|
1064 (define_insn "ashlsi3_internal"
|
|
|
1065 [(set (match_operand:SI 0 "register_operand" "=a,a")
|
|
|
1066 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
|
|
|
1067 (match_operand:SI 2 "arith_operand" "J,r")))]
|
|
|
1068 ""
|
|
|
1069 "@
|
|
|
1070 slli\t%0, %1, %R2
|
|
|
1071 ssl\t%2\;sll\t%0, %1"
|
|
|
1072 [(set_attr "type" "arith,arith")
|
|
|
1073 (set_attr "mode" "SI")
|
|
|
1074 (set_attr "length" "3,6")])
|
|
|
1075
|
|
|
1076 (define_insn "ashrsi3"
|
|
|
1077 [(set (match_operand:SI 0 "register_operand" "=a,a")
|
|
|
1078 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
|
|
|
1079 (match_operand:SI 2 "arith_operand" "J,r")))]
|
|
|
1080 ""
|
|
|
1081 "@
|
|
|
1082 srai\t%0, %1, %R2
|
|
|
1083 ssr\t%2\;sra\t%0, %1"
|
|
|
1084 [(set_attr "type" "arith,arith")
|
|
|
1085 (set_attr "mode" "SI")
|
|
|
1086 (set_attr "length" "3,6")])
|
|
|
1087
|
|
|
1088 (define_insn "lshrsi3"
|
|
|
1089 [(set (match_operand:SI 0 "register_operand" "=a,a")
|
|
|
1090 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
|
|
|
1091 (match_operand:SI 2 "arith_operand" "J,r")))]
|
|
|
1092 ""
|
|
|
1093 {
|
|
|
1094 if (which_alternative == 0)
|
|
|
1095 {
|
|
|
1096 if ((INTVAL (operands[2]) & 0x1f) < 16)
|
|
|
1097 return "srli\t%0, %1, %R2";
|
|
|
1098 else
|
|
|
1099 return "extui\t%0, %1, %R2, %L2";
|
|
|
1100 }
|
|
|
1101 return "ssr\t%2\;srl\t%0, %1";
|
|
|
1102 }
|
|
|
1103 [(set_attr "type" "arith,arith")
|
|
|
1104 (set_attr "mode" "SI")
|
|
|
1105 (set_attr "length" "3,6")])
|
|
|
1106
|
|
|
1107 (define_insn "rotlsi3"
|
|
|
1108 [(set (match_operand:SI 0 "register_operand" "=a,a")
|
|
|
1109 (rotate:SI (match_operand:SI 1 "register_operand" "r,r")
|
|
|
1110 (match_operand:SI 2 "arith_operand" "J,r")))]
|
|
|
1111 ""
|
|
|
1112 "@
|
|
|
1113 ssai\t%L2\;src\t%0, %1, %1
|
|
|
1114 ssl\t%2\;src\t%0, %1, %1"
|
|
|
1115 [(set_attr "type" "multi,multi")
|
|
|
1116 (set_attr "mode" "SI")
|
|
|
1117 (set_attr "length" "6,6")])
|
|
|
1118
|
|
|
1119 (define_insn "rotrsi3"
|
|
|
1120 [(set (match_operand:SI 0 "register_operand" "=a,a")
|
|
|
1121 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
|
|
|
1122 (match_operand:SI 2 "arith_operand" "J,r")))]
|
|
|
1123 ""
|
|
|
1124 "@
|
|
|
1125 ssai\t%R2\;src\t%0, %1, %1
|
|
|
1126 ssr\t%2\;src\t%0, %1, %1"
|
|
|
1127 [(set_attr "type" "multi,multi")
|
|
|
1128 (set_attr "mode" "SI")
|
|
|
1129 (set_attr "length" "6,6")])
|
|
|
1130
|
|
|
1131
|
|
|
1132 ;; Comparisons.
|
|
|
1133
|
|
|
1134 ;; Handle comparisons by stashing away the operands and then using that
|
|
|
1135 ;; information in the subsequent conditional branch.
|
|
|
1136
|
|
|
1137 (define_expand "cmpsi"
|
|
|
1138 [(set (cc0)
|
|
|
1139 (compare:CC (match_operand:SI 0 "register_operand" "")
|
|
|
1140 (match_operand:SI 1 "nonmemory_operand" "")))]
|
|
|
1141 ""
|
|
|
1142 {
|
|
|
1143 branch_cmp[0] = operands[0];
|
|
|
1144 branch_cmp[1] = operands[1];
|
|
|
1145 branch_type = CMP_SI;
|
|
|
1146 DONE;
|
|
|
1147 })
|
|
|
1148
|
|
|
1149 (define_expand "cmpsf"
|
|
|
1150 [(set (cc0)
|
|
|
1151 (compare:CC (match_operand:SF 0 "register_operand" "")
|
|
|
1152 (match_operand:SF 1 "register_operand" "")))]
|
|
|
1153 "TARGET_HARD_FLOAT"
|
|
|
1154 {
|
|
|
1155 branch_cmp[0] = operands[0];
|
|
|
1156 branch_cmp[1] = operands[1];
|
|
|
1157 branch_type = CMP_SF;
|
|
|
1158 DONE;
|
|
|
1159 })
|
|
|
1160
|
|
|
1161
|
|
|
1162 ;; Conditional branches.
|
|
|
1163
|
|
|
1164 (define_expand "b<code>"
|
|
|
1165 [(set (pc)
|
|
|
1166 (if_then_else (any_cond (cc0) (const_int 0))
|
|
|
1167 (label_ref (match_operand 0 "" ""))
|
|
|
1168 (pc)))]
|
|
|
1169 ""
|
|
|
1170 {
|
|
|
1171 xtensa_expand_conditional_branch (operands, <CODE>);
|
|
|
1172 DONE;
|
|
|
1173 })
|
|
|
1174
|
|
|
1175 ;; Branch patterns for standard integer comparisons
|
|
|
1176
|
|
|
1177 (define_insn "*btrue"
|
|
|
1178 [(set (pc)
|
|
|
1179 (if_then_else (match_operator 3 "branch_operator"
|
|
|
1180 [(match_operand:SI 0 "register_operand" "r,r")
|
|
|
1181 (match_operand:SI 1 "branch_operand" "K,r")])
|
|
|
1182 (label_ref (match_operand 2 "" ""))
|
|
|
1183 (pc)))]
|
|
|
1184 ""
|
|
|
1185 {
|
|
|
1186 return xtensa_emit_branch (false, which_alternative == 0, operands);
|
|
|
1187 }
|
|
|
1188 [(set_attr "type" "jump,jump")
|
|
|
1189 (set_attr "mode" "none")
|
|
|
1190 (set_attr "length" "3,3")])
|
|
|
1191
|
|
|
1192 (define_insn "*bfalse"
|
|
|
1193 [(set (pc)
|
|
|
1194 (if_then_else (match_operator 3 "branch_operator"
|
|
|
1195 [(match_operand:SI 0 "register_operand" "r,r")
|
|
|
1196 (match_operand:SI 1 "branch_operand" "K,r")])
|
|
|
1197 (pc)
|
|
|
1198 (label_ref (match_operand 2 "" ""))))]
|
|
|
1199 ""
|
|
|
1200 {
|
|
|
1201 return xtensa_emit_branch (true, which_alternative == 0, operands);
|
|
|
1202 }
|
|
|
1203 [(set_attr "type" "jump,jump")
|
|
|
1204 (set_attr "mode" "none")
|
|
|
1205 (set_attr "length" "3,3")])
|
|
|
1206
|
|
|
1207 (define_insn "*ubtrue"
|
|
|
1208 [(set (pc)
|
|
|
1209 (if_then_else (match_operator 3 "ubranch_operator"
|
|
|
1210 [(match_operand:SI 0 "register_operand" "r,r")
|
|
|
1211 (match_operand:SI 1 "ubranch_operand" "L,r")])
|
|
|
1212 (label_ref (match_operand 2 "" ""))
|
|
|
1213 (pc)))]
|
|
|
1214 ""
|
|
|
1215 {
|
|
|
1216 return xtensa_emit_branch (false, which_alternative == 0, operands);
|
|
|
1217 }
|
|
|
1218 [(set_attr "type" "jump,jump")
|
|
|
1219 (set_attr "mode" "none")
|
|
|
1220 (set_attr "length" "3,3")])
|
|
|
1221
|
|
|
1222 (define_insn "*ubfalse"
|
|
|
1223 [(set (pc)
|
|
|
1224 (if_then_else (match_operator 3 "ubranch_operator"
|
|
|
1225 [(match_operand:SI 0 "register_operand" "r,r")
|
|
|
1226 (match_operand:SI 1 "ubranch_operand" "L,r")])
|
|
|
1227 (pc)
|
|
|
1228 (label_ref (match_operand 2 "" ""))))]
|
|
|
1229 ""
|
|
|
1230 {
|
|
|
1231 return xtensa_emit_branch (true, which_alternative == 0, operands);
|
|
|
1232 }
|
|
|
1233 [(set_attr "type" "jump,jump")
|
|
|
1234 (set_attr "mode" "none")
|
|
|
1235 (set_attr "length" "3,3")])
|
|
|
1236
|
|
|
1237 ;; Branch patterns for bit testing
|
|
|
1238
|
|
|
1239 (define_insn "*bittrue"
|
|
|
1240 [(set (pc)
|
|
|
1241 (if_then_else (match_operator 3 "boolean_operator"
|
|
|
1242 [(zero_extract:SI
|
|
|
1243 (match_operand:SI 0 "register_operand" "r,r")
|
|
|
1244 (const_int 1)
|
|
|
1245 (match_operand:SI 1 "arith_operand" "J,r"))
|
|
|
1246 (const_int 0)])
|
|
|
1247 (label_ref (match_operand 2 "" ""))
|
|
|
1248 (pc)))]
|
|
|
1249 ""
|
|
|
1250 {
|
|
|
1251 return xtensa_emit_bit_branch (false, which_alternative == 0, operands);
|
|
|
1252 }
|
|
|
1253 [(set_attr "type" "jump")
|
|
|
1254 (set_attr "mode" "none")
|
|
|
1255 (set_attr "length" "3")])
|
|
|
1256
|
|
|
1257 (define_insn "*bitfalse"
|
|
|
1258 [(set (pc)
|
|
|
1259 (if_then_else (match_operator 3 "boolean_operator"
|
|
|
1260 [(zero_extract:SI
|
|
|
1261 (match_operand:SI 0 "register_operand" "r,r")
|
|
|
1262 (const_int 1)
|
|
|
1263 (match_operand:SI 1 "arith_operand" "J,r"))
|
|
|
1264 (const_int 0)])
|
|
|
1265 (pc)
|
|
|
1266 (label_ref (match_operand 2 "" ""))))]
|
|
|
1267 ""
|
|
|
1268 {
|
|
|
1269 return xtensa_emit_bit_branch (true, which_alternative == 0, operands);
|
|
|
1270 }
|
|
|
1271 [(set_attr "type" "jump")
|
|
|
1272 (set_attr "mode" "none")
|
|
|
1273 (set_attr "length" "3")])
|
|
|
1274
|
|
|
1275 (define_insn "*masktrue"
|
|
|
1276 [(set (pc)
|
|
|
1277 (if_then_else (match_operator 3 "boolean_operator"
|
|
|
1278 [(and:SI (match_operand:SI 0 "register_operand" "r")
|
|
|
1279 (match_operand:SI 1 "register_operand" "r"))
|
|
|
1280 (const_int 0)])
|
|
|
1281 (label_ref (match_operand 2 "" ""))
|
|
|
1282 (pc)))]
|
|
|
1283 ""
|
|
|
1284 {
|
|
|
1285 switch (GET_CODE (operands[3]))
|
|
|
1286 {
|
|
|
1287 case EQ: return "bnone\t%0, %1, %2";
|
|
|
1288 case NE: return "bany\t%0, %1, %2";
|
|
|
1289 default: gcc_unreachable ();
|
|
|
1290 }
|
|
|
1291 }
|
|
|
1292 [(set_attr "type" "jump")
|
|
|
1293 (set_attr "mode" "none")
|
|
|
1294 (set_attr "length" "3")])
|
|
|
1295
|
|
|
1296 (define_insn "*maskfalse"
|
|
|
1297 [(set (pc)
|
|
|
1298 (if_then_else (match_operator 3 "boolean_operator"
|
|
|
1299 [(and:SI (match_operand:SI 0 "register_operand" "r")
|
|
|
1300 (match_operand:SI 1 "register_operand" "r"))
|
|
|
1301 (const_int 0)])
|
|
|
1302 (pc)
|
|
|
1303 (label_ref (match_operand 2 "" ""))))]
|
|
|
1304 ""
|
|
|
1305 {
|
|
|
1306 switch (GET_CODE (operands[3]))
|
|
|
1307 {
|
|
|
1308 case EQ: return "bany\t%0, %1, %2";
|
|
|
1309 case NE: return "bnone\t%0, %1, %2";
|
|
|
1310 default: gcc_unreachable ();
|
|
|
1311 }
|
|
|
1312 }
|
|
|
1313 [(set_attr "type" "jump")
|
|
|
1314 (set_attr "mode" "none")
|
|
|
1315 (set_attr "length" "3")])
|
|
|
1316
|
|
|
1317
|
|
|
1318 ;; Define the loop insns used by bct optimization to represent the
|
|
|
1319 ;; start and end of a zero-overhead loop (in loop.c). This start
|
|
|
1320 ;; template generates the loop insn; the end template doesn't generate
|
|
|
1321 ;; any instructions since loop end is handled in hardware.
|
|
|
1322
|
|
|
1323 (define_insn "zero_cost_loop_start"
|
|
|
1324 [(set (pc)
|
|
|
1325 (if_then_else (eq (match_operand:SI 0 "register_operand" "a")
|
|
|
1326 (const_int 0))
|
|
|
1327 (label_ref (match_operand 1 "" ""))
|
|
|
1328 (pc)))
|
|
|
1329 (set (reg:SI 19)
|
|
|
1330 (plus:SI (match_dup 0) (const_int -1)))]
|
|
|
1331 ""
|
|
|
1332 "loopnez\t%0, %l1"
|
|
|
1333 [(set_attr "type" "jump")
|
|
|
1334 (set_attr "mode" "none")
|
|
|
1335 (set_attr "length" "3")])
|
|
|
1336
|
|
|
1337 (define_insn "zero_cost_loop_end"
|
|
|
1338 [(set (pc)
|
|
|
1339 (if_then_else (ne (reg:SI 19) (const_int 0))
|
|
|
1340 (label_ref (match_operand 0 "" ""))
|
|
|
1341 (pc)))
|
|
|
1342 (set (reg:SI 19)
|
|
|
1343 (plus:SI (reg:SI 19) (const_int -1)))]
|
|
|
1344 ""
|
|
|
1345 {
|
|
|
1346 xtensa_emit_loop_end (insn, operands);
|
|
|
1347 return "";
|
|
|
1348 }
|
|
|
1349 [(set_attr "type" "jump")
|
|
|
1350 (set_attr "mode" "none")
|
|
|
1351 (set_attr "length" "0")])
|
|
|
1352
|
|
|
1353
|
|
|
1354 ;; Setting a register from a comparison.
|
|
|
1355
|
|
|
1356 (define_expand "s<code>"
|
|
|
1357 [(set (match_operand:SI 0 "register_operand" "")
|
|
|
1358 (any_scc:SI (match_dup 1)
|
|
|
1359 (match_dup 2)))]
|
|
|
1360 ""
|
|
|
1361 {
|
|
|
1362 operands[1] = gen_rtx_<CODE> (SImode, branch_cmp[0], branch_cmp[1]);
|
|
|
1363 if (!xtensa_expand_scc (operands))
|
|
|
1364 FAIL;
|
|
|
1365 DONE;
|
|
|
1366 })
|
|
|
1367
|
|
|
1368
|
|
|
1369 ;; Conditional moves.
|
|
|
1370
|
|
|
1371 (define_expand "movsicc"
|
|
|
1372 [(set (match_operand:SI 0 "register_operand" "")
|
|
|
1373 (if_then_else:SI (match_operand 1 "comparison_operator" "")
|
|
|
1374 (match_operand:SI 2 "register_operand" "")
|
|
|
1375 (match_operand:SI 3 "register_operand" "")))]
|
|
|
1376 ""
|
|
|
1377 {
|
|
|
1378 if (!xtensa_expand_conditional_move (operands, 0))
|
|
|
1379 FAIL;
|
|
|
1380 DONE;
|
|
|
1381 })
|
|
|
1382
|
|
|
1383 (define_expand "movsfcc"
|
|
|
1384 [(set (match_operand:SF 0 "register_operand" "")
|
|
|
1385 (if_then_else:SF (match_operand 1 "comparison_operator" "")
|
|
|
1386 (match_operand:SF 2 "register_operand" "")
|
|
|
1387 (match_operand:SF 3 "register_operand" "")))]
|
|
|
1388 ""
|
|
|
1389 {
|
|
|
1390 if (!xtensa_expand_conditional_move (operands, 1))
|
|
|
1391 FAIL;
|
|
|
1392 DONE;
|
|
|
1393 })
|
|
|
1394
|
|
|
1395 (define_insn "movsicc_internal0"
|
|
|
1396 [(set (match_operand:SI 0 "register_operand" "=a,a")
|
|
|
1397 (if_then_else:SI (match_operator 4 "branch_operator"
|
|
|
1398 [(match_operand:SI 1 "register_operand" "r,r")
|
|
|
1399 (const_int 0)])
|
|
|
1400 (match_operand:SI 2 "register_operand" "r,0")
|
|
|
1401 (match_operand:SI 3 "register_operand" "0,r")))]
|
|
|
1402 ""
|
|
|
1403 {
|
|
|
1404 return xtensa_emit_movcc (which_alternative == 1, false, false, operands);
|
|
|
1405 }
|
|
|
1406 [(set_attr "type" "move,move")
|
|
|
1407 (set_attr "mode" "SI")
|
|
|
1408 (set_attr "length" "3,3")])
|
|
|
1409
|
|
|
1410 (define_insn "movsicc_internal1"
|
|
|
1411 [(set (match_operand:SI 0 "register_operand" "=a,a")
|
|
|
1412 (if_then_else:SI (match_operator 4 "boolean_operator"
|
|
|
1413 [(match_operand:CC 1 "register_operand" "b,b")
|
|
|
1414 (const_int 0)])
|
|
|
1415 (match_operand:SI 2 "register_operand" "r,0")
|
|
|
1416 (match_operand:SI 3 "register_operand" "0,r")))]
|
|
|
1417 "TARGET_BOOLEANS"
|
|
|
1418 {
|
|
|
1419 return xtensa_emit_movcc (which_alternative == 1, false, true, operands);
|
|
|
1420 }
|
|
|
1421 [(set_attr "type" "move,move")
|
|
|
1422 (set_attr "mode" "SI")
|
|
|
1423 (set_attr "length" "3,3")])
|
|
|
1424
|
|
|
1425 (define_insn "movsfcc_internal0"
|
|
|
1426 [(set (match_operand:SF 0 "register_operand" "=a,a,f,f")
|
|
|
1427 (if_then_else:SF (match_operator 4 "branch_operator"
|
|
|
1428 [(match_operand:SI 1 "register_operand" "r,r,r,r")
|
|
|
1429 (const_int 0)])
|
|
|
1430 (match_operand:SF 2 "register_operand" "r,0,f,0")
|
|
|
1431 (match_operand:SF 3 "register_operand" "0,r,0,f")))]
|
|
|
1432 ""
|
|
|
1433 {
|
|
|
1434 return xtensa_emit_movcc ((which_alternative & 1) == 1,
|
|
|
1435 which_alternative >= 2, false, operands);
|
|
|
1436 }
|
|
|
1437 [(set_attr "type" "move,move,move,move")
|
|
|
1438 (set_attr "mode" "SF")
|
|
|
1439 (set_attr "length" "3,3,3,3")])
|
|
|
1440
|
|
|
1441 (define_insn "movsfcc_internal1"
|
|
|
1442 [(set (match_operand:SF 0 "register_operand" "=a,a,f,f")
|
|
|
1443 (if_then_else:SF (match_operator 4 "boolean_operator"
|
|
|
1444 [(match_operand:CC 1 "register_operand" "b,b,b,b")
|
|
|
1445 (const_int 0)])
|
|
|
1446 (match_operand:SF 2 "register_operand" "r,0,f,0")
|
|
|
1447 (match_operand:SF 3 "register_operand" "0,r,0,f")))]
|
|
|
1448 "TARGET_BOOLEANS"
|
|
|
1449 {
|
|
|
1450 return xtensa_emit_movcc ((which_alternative & 1) == 1,
|
|
|
1451 which_alternative >= 2, true, operands);
|
|
|
1452 }
|
|
|
1453 [(set_attr "type" "move,move,move,move")
|
|
|
1454 (set_attr "mode" "SF")
|
|
|
1455 (set_attr "length" "3,3,3,3")])
|
|
|
1456
|
|
|
1457
|
|
|
1458 ;; Floating-point comparisons.
|
|
|
1459
|
|
|
1460 (define_insn "s<code>_sf"
|
|
|
1461 [(set (match_operand:CC 0 "register_operand" "=b")
|
|
|
1462 (any_scc_sf:CC (match_operand:SF 1 "register_operand" "f")
|
|
|
1463 (match_operand:SF 2 "register_operand" "f")))]
|
|
|
1464 "TARGET_HARD_FLOAT"
|
|
|
1465 "<scc_sf>.s\t%0, %1, %2"
|
|
|
1466 [(set_attr "type" "farith")
|
|
|
1467 (set_attr "mode" "BL")
|
|
|
1468 (set_attr "length" "3")])
|
|
|
1469
|
|
|
1470
|
|
|
1471 ;; Unconditional branches.
|
|
|
1472
|
|
|
1473 (define_insn "jump"
|
|
|
1474 [(set (pc)
|
|
|
1475 (label_ref (match_operand 0 "" "")))]
|
|
|
1476 ""
|
|
|
1477 "j\t%l0"
|
|
|
1478 [(set_attr "type" "jump")
|
|
|
1479 (set_attr "mode" "none")
|
|
|
1480 (set_attr "length" "3")])
|
|
|
1481
|
|
|
1482 (define_expand "indirect_jump"
|
|
|
1483 [(set (pc)
|
|
|
1484 (match_operand 0 "register_operand" ""))]
|
|
|
1485 ""
|
|
|
1486 {
|
|
|
1487 rtx dest = operands[0];
|
|
|
1488 if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
|
|
|
1489 operands[0] = copy_to_mode_reg (Pmode, dest);
|
|
|
1490
|
|
|
1491 emit_jump_insn (gen_indirect_jump_internal (dest));
|
|
|
1492 DONE;
|
|
|
1493 })
|
|
|
1494
|
|
|
1495 (define_insn "indirect_jump_internal"
|
|
|
1496 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
|
|
|
1497 ""
|
|
|
1498 "jx\t%0"
|
|
|
1499 [(set_attr "type" "jump")
|
|
|
1500 (set_attr "mode" "none")
|
|
|
1501 (set_attr "length" "3")])
|
|
|
1502
|
|
|
1503
|
|
|
1504 (define_expand "tablejump"
|
|
|
1505 [(use (match_operand:SI 0 "register_operand" ""))
|
|
|
1506 (use (label_ref (match_operand 1 "" "")))]
|
|
|
1507 ""
|
|
|
1508 {
|
|
|
1509 rtx target = operands[0];
|
|
|
1510 if (flag_pic)
|
|
|
1511 {
|
|
|
1512 /* For PIC, the table entry is relative to the start of the table. */
|
|
|
1513 rtx label = gen_reg_rtx (SImode);
|
|
|
1514 target = gen_reg_rtx (SImode);
|
|
|
1515 emit_move_insn (label, gen_rtx_LABEL_REF (SImode, operands[1]));
|
|
|
1516 emit_insn (gen_addsi3 (target, operands[0], label));
|
|
|
1517 }
|
|
|
1518 emit_jump_insn (gen_tablejump_internal (target, operands[1]));
|
|
|
1519 DONE;
|
|
|
1520 })
|
|
|
1521
|
|
|
1522 (define_insn "tablejump_internal"
|
|
|
1523 [(set (pc)
|
|
|
1524 (match_operand:SI 0 "register_operand" "r"))
|
|
|
1525 (use (label_ref (match_operand 1 "" "")))]
|
|
|
1526 ""
|
|
|
1527 "jx\t%0"
|
|
|
1528 [(set_attr "type" "jump")
|
|
|
1529 (set_attr "mode" "none")
|
|
|
1530 (set_attr "length" "3")])
|
|
|
1531
|
|
|
1532
|
|
|
1533 ;; Function calls.
|
|
|
1534
|
|
|
1535 (define_expand "sym_PLT"
|
|
|
1536 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PLT))]
|
|
|
1537 ""
|
|
|
1538 "")
|
|
|
1539
|
|
|
1540 (define_expand "call"
|
|
|
1541 [(call (match_operand 0 "memory_operand" "")
|
|
|
1542 (match_operand 1 "" ""))]
|
|
|
1543 ""
|
|
|
1544 {
|
|
|
1545 rtx addr = XEXP (operands[0], 0);
|
|
|
1546 if (flag_pic && GET_CODE (addr) == SYMBOL_REF
|
|
|
1547 && (!SYMBOL_REF_LOCAL_P (addr) || SYMBOL_REF_EXTERNAL_P (addr)))
|
|
|
1548 addr = gen_sym_PLT (addr);
|
|
|
1549 if (!call_insn_operand (addr, VOIDmode))
|
|
|
1550 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
|
|
|
1551 })
|
|
|
1552
|
|
|
1553 (define_insn "call_internal"
|
|
|
1554 [(call (mem (match_operand:SI 0 "call_insn_operand" "nir"))
|
|
|
1555 (match_operand 1 "" "i"))]
|
|
|
1556 ""
|
|
|
1557 {
|
|
|
1558 return xtensa_emit_call (0, operands);
|
|
|
1559 }
|
|
|
1560 [(set_attr "type" "call")
|
|
|
1561 (set_attr "mode" "none")
|
|
|
1562 (set_attr "length" "3")])
|
|
|
1563
|
|
|
1564 (define_expand "call_value"
|
|
|
1565 [(set (match_operand 0 "register_operand" "")
|
|
|
1566 (call (match_operand 1 "memory_operand" "")
|
|
|
1567 (match_operand 2 "" "")))]
|
|
|
1568 ""
|
|
|
1569 {
|
|
|
1570 rtx addr = XEXP (operands[1], 0);
|
|
|
1571 if (flag_pic && GET_CODE (addr) == SYMBOL_REF
|
|
|
1572 && (!SYMBOL_REF_LOCAL_P (addr) || SYMBOL_REF_EXTERNAL_P (addr)))
|
|
|
1573 addr = gen_sym_PLT (addr);
|
|
|
1574 if (!call_insn_operand (addr, VOIDmode))
|
|
|
1575 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
|
|
|
1576 })
|
|
|
1577
|
|
|
1578 (define_insn "call_value_internal"
|
|
|
1579 [(set (match_operand 0 "register_operand" "=a")
|
|
|
1580 (call (mem (match_operand:SI 1 "call_insn_operand" "nir"))
|
|
|
1581 (match_operand 2 "" "i")))]
|
|
|
1582 ""
|
|
|
1583 {
|
|
|
1584 return xtensa_emit_call (1, operands);
|
|
|
1585 }
|
|
|
1586 [(set_attr "type" "call")
|
|
|
1587 (set_attr "mode" "none")
|
|
|
1588 (set_attr "length" "3")])
|
|
|
1589
|
|
|
1590 (define_insn "entry"
|
|
|
1591 [(set (reg:SI A1_REG)
|
|
|
1592 (unspec_volatile:SI [(match_operand:SI 0 "const_int_operand" "i")]
|
|
|
1593 UNSPECV_ENTRY))]
|
|
|
1594 ""
|
|
|
1595 "entry\tsp, %0"
|
|
|
1596 [(set_attr "type" "entry")
|
|
|
1597 (set_attr "mode" "SI")
|
|
|
1598 (set_attr "length" "3")])
|
|
|
1599
|
|
|
1600 (define_insn "return"
|
|
|
1601 [(return)
|
|
|
1602 (use (reg:SI A0_REG))]
|
|
|
1603 "reload_completed"
|
|
|
1604 {
|
|
|
1605 return (TARGET_DENSITY ? "retw.n" : "retw");
|
|
|
1606 }
|
|
|
1607 [(set_attr "type" "jump")
|
|
|
1608 (set_attr "mode" "none")
|
|
|
1609 (set_attr "length" "2")])
|
|
|
1610
|
|
|
1611
|
|
|
1612 ;; Miscellaneous instructions.
|
|
|
1613
|
|
|
1614 (define_expand "prologue"
|
|
|
1615 [(const_int 0)]
|
|
|
1616 ""
|
|
|
1617 {
|
|
|
1618 xtensa_expand_prologue ();
|
|
|
1619 DONE;
|
|
|
1620 })
|
|
|
1621
|
|
|
1622 (define_expand "epilogue"
|
|
|
1623 [(return)]
|
|
|
1624 ""
|
|
|
1625 {
|
|
|
1626 emit_jump_insn (gen_return ());
|
|
|
1627 DONE;
|
|
|
1628 })
|
|
|
1629
|
|
|
1630 (define_insn "nop"
|
|
|
1631 [(const_int 0)]
|
|
|
1632 ""
|
|
|
1633 {
|
|
|
1634 return (TARGET_DENSITY ? "nop.n" : "nop");
|
|
|
1635 }
|
|
|
1636 [(set_attr "type" "nop")
|
|
|
1637 (set_attr "mode" "none")
|
|
|
1638 (set_attr "length" "3")])
|
|
|
1639
|
|
|
1640 (define_expand "nonlocal_goto"
|
|
|
1641 [(match_operand:SI 0 "general_operand" "")
|
|
|
1642 (match_operand:SI 1 "general_operand" "")
|
|
|
1643 (match_operand:SI 2 "general_operand" "")
|
|
|
1644 (match_operand:SI 3 "" "")]
|
|
|
1645 ""
|
|
|
1646 {
|
|
|
1647 xtensa_expand_nonlocal_goto (operands);
|
|
|
1648 DONE;
|
|
|
1649 })
|
|
|
1650
|
|
|
1651 ;; Stuff an address into the return address register along with the window
|
|
|
1652 ;; size in the high bits. Because we don't have the window size of the
|
|
|
1653 ;; previous frame, assume the function called out with a CALL8 since that
|
|
|
1654 ;; is what compilers always use. Note: __builtin_frob_return_addr has
|
|
|
1655 ;; already been applied to the handler, but the generic version doesn't
|
|
|
1656 ;; allow us to frob it quite enough, so we just frob here.
|
|
|
1657
|
|
|
1658 (define_insn_and_split "eh_return"
|
|
|
1659 [(set (reg:SI A0_REG)
|
|
|
1660 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
|
|
|
1661 UNSPECV_EH_RETURN))
|
|
|
1662 (clobber (match_scratch:SI 1 "=r"))]
|
|
|
1663 ""
|
|
|
1664 "#"
|
|
|
1665 "reload_completed"
|
|
|
1666 [(set (match_dup 1) (ashift:SI (match_dup 0) (const_int 2)))
|
|
|
1667 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
|
|
|
1668 (set (reg:SI A0_REG) (rotatert:SI (match_dup 1) (const_int 2)))]
|
|
|
1669 "")
|
|
|
1670
|
|
|
1671 ;; Setting up a frame pointer is tricky for Xtensa because GCC doesn't
|
|
|
1672 ;; know if a frame pointer is required until the reload pass, and
|
|
|
1673 ;; because there may be an incoming argument value in the hard frame
|
|
|
1674 ;; pointer register (a7). If there is an incoming argument in that
|
|
|
1675 ;; register, the "set_frame_ptr" insn gets inserted immediately after
|
|
|
1676 ;; the insn that copies the incoming argument to a pseudo or to the
|
|
|
1677 ;; stack. This serves several purposes here: (1) it keeps the
|
|
|
1678 ;; optimizer from copy-propagating or scheduling the use of a7 as an
|
|
|
1679 ;; incoming argument away from the beginning of the function; (2) we
|
|
|
1680 ;; can use a post-reload splitter to expand away the insn if a frame
|
|
|
1681 ;; pointer is not required, so that the post-reload scheduler can do
|
|
|
1682 ;; the right thing; and (3) it makes it easy for the prologue expander
|
|
|
1683 ;; to search for this insn to determine whether it should add a new insn
|
|
|
1684 ;; to set up the frame pointer.
|
|
|
1685
|
|
|
1686 (define_insn "set_frame_ptr"
|
|
|
1687 [(set (reg:SI A7_REG) (unspec_volatile:SI [(const_int 0)] UNSPECV_SET_FP))]
|
|
|
1688 ""
|
|
|
1689 {
|
|
|
1690 if (frame_pointer_needed)
|
|
|
1691 return "mov\ta7, sp";
|
|
|
1692 return "";
|
|
|
1693 }
|
|
|
1694 [(set_attr "type" "move")
|
|
|
1695 (set_attr "mode" "SI")
|
|
|
1696 (set_attr "length" "3")])
|
|
|
1697
|
|
|
1698 ;; Post-reload splitter to remove fp assignment when it's not needed.
|
|
|
1699 (define_split
|
|
|
1700 [(set (reg:SI A7_REG) (unspec_volatile:SI [(const_int 0)] UNSPECV_SET_FP))]
|
|
|
1701 "reload_completed && !frame_pointer_needed"
|
|
|
1702 [(unspec [(const_int 0)] UNSPEC_NOP)]
|
|
|
1703 "")
|
|
|
1704
|
|
|
1705 ;; The preceding splitter needs something to split the insn into;
|
|
|
1706 ;; things start breaking if the result is just a "use" so instead we
|
|
|
1707 ;; generate the following insn.
|
|
|
1708 (define_insn "*unspec_nop"
|
|
|
1709 [(unspec [(const_int 0)] UNSPEC_NOP)]
|
|
|
1710 ""
|
|
|
1711 ""
|
|
|
1712 [(set_attr "type" "nop")
|
|
|
1713 (set_attr "mode" "none")
|
|
|
1714 (set_attr "length" "0")])
|
|
|
1715
|
|
|
1716
|
|
|
1717 ;; TLS support
|
|
|
1718
|
|
|
1719 (define_expand "sym_TPOFF"
|
|
|
1720 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_TPOFF))]
|
|
|
1721 ""
|
|
|
1722 "")
|
|
|
1723
|
|
|
1724 (define_expand "sym_DTPOFF"
|
|
|
1725 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_DTPOFF))]
|
|
|
1726 ""
|
|
|
1727 "")
|
|
|
1728
|
|
|
1729 (define_insn "load_tp"
|
|
|
1730 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
1731 (unspec:SI [(const_int 0)] UNSPEC_TP))]
|
|
|
1732 "TARGET_THREADPTR"
|
|
|
1733 "rur\t%0, THREADPTR"
|
|
|
1734 [(set_attr "type" "rsr")
|
|
|
1735 (set_attr "mode" "SI")
|
|
|
1736 (set_attr "length" "3")])
|
|
|
1737
|
|
|
1738 (define_insn "set_tp"
|
|
|
1739 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
|
|
|
1740 UNSPECV_SET_TP)]
|
|
|
1741 "TARGET_THREADPTR"
|
|
|
1742 "wur\t%0, THREADPTR"
|
|
|
1743 [(set_attr "type" "wsr")
|
|
|
1744 (set_attr "mode" "SI")
|
|
|
1745 (set_attr "length" "3")])
|
|
|
1746
|
|
|
1747 (define_insn "tls_func"
|
|
|
1748 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
1749 (unspec:SI [(match_operand:SI 1 "tls_symbol_operand" "")]
|
|
|
1750 UNSPEC_TLS_FUNC))]
|
|
|
1751 "TARGET_THREADPTR && HAVE_AS_TLS"
|
|
|
1752 "movi\t%0, %1@TLSFUNC"
|
|
|
1753 [(set_attr "type" "load")
|
|
|
1754 (set_attr "mode" "SI")
|
|
|
1755 (set_attr "length" "3")])
|
|
|
1756
|
|
|
1757 (define_insn "tls_arg"
|
|
|
1758 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
1759 (unspec:SI [(match_operand:SI 1 "tls_symbol_operand" "")]
|
|
|
1760 UNSPEC_TLS_ARG))]
|
|
|
1761 "TARGET_THREADPTR && HAVE_AS_TLS"
|
|
|
1762 "movi\t%0, %1@TLSARG"
|
|
|
1763 [(set_attr "type" "load")
|
|
|
1764 (set_attr "mode" "SI")
|
|
|
1765 (set_attr "length" "3")])
|
|
|
1766
|
|
|
1767 (define_insn "tls_call"
|
|
|
1768 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
1769 (call (mem:SI (unspec:SI [(match_operand:SI 1 "register_operand" "r")
|
|
|
1770 (match_operand:SI 2 "tls_symbol_operand" "")]
|
|
|
1771 UNSPEC_TLS_CALL))
|
|
|
1772 (match_operand 3 "" "i")))]
|
|
|
1773 "TARGET_THREADPTR && HAVE_AS_TLS"
|
|
|
1774 "callx8.tls %1, %2@TLSCALL"
|
|
|
1775 [(set_attr "type" "call")
|
|
|
1776 (set_attr "mode" "none")
|
|
|
1777 (set_attr "length" "3")])
|
|
|
1778
|
|
|
1779
|
|
|
1780 ;; Instructions for the Xtensa "boolean" option.
|
|
|
1781
|
|
|
1782 (define_insn "*booltrue"
|
|
|
1783 [(set (pc)
|
|
|
1784 (if_then_else (match_operator 2 "boolean_operator"
|
|
|
1785 [(match_operand:CC 0 "register_operand" "b")
|
|
|
1786 (const_int 0)])
|
|
|
1787 (label_ref (match_operand 1 "" ""))
|
|
|
1788 (pc)))]
|
|
|
1789 "TARGET_BOOLEANS"
|
|
|
1790 {
|
|
|
1791 if (GET_CODE (operands[2]) == EQ)
|
|
|
1792 return "bf\t%0, %1";
|
|
|
1793 else
|
|
|
1794 return "bt\t%0, %1";
|
|
|
1795 }
|
|
|
1796 [(set_attr "type" "jump")
|
|
|
1797 (set_attr "mode" "none")
|
|
|
1798 (set_attr "length" "3")])
|
|
|
1799
|
|
|
1800 (define_insn "*boolfalse"
|
|
|
1801 [(set (pc)
|
|
|
1802 (if_then_else (match_operator 2 "boolean_operator"
|
|
|
1803 [(match_operand:CC 0 "register_operand" "b")
|
|
|
1804 (const_int 0)])
|
|
|
1805 (pc)
|
|
|
1806 (label_ref (match_operand 1 "" ""))))]
|
|
|
1807 "TARGET_BOOLEANS"
|
|
|
1808 {
|
|
|
1809 if (GET_CODE (operands[2]) == EQ)
|
|
|
1810 return "bt\t%0, %1";
|
|
|
1811 else
|
|
|
1812 return "bf\t%0, %1";
|
|
|
1813 }
|
|
|
1814 [(set_attr "type" "jump")
|
|
|
1815 (set_attr "mode" "none")
|
|
|
1816 (set_attr "length" "3")])
|
|
|
1817
|
|
|
1818
|
|
|
1819 ;; Atomic operations
|
|
|
1820
|
|
|
1821 (define_expand "memory_barrier"
|
|
|
1822 [(set (match_dup 0)
|
|
|
1823 (unspec:BLK [(match_dup 0)] UNSPEC_MEMW))]
|
|
|
1824 ""
|
|
|
1825 {
|
|
|
1826 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
|
|
|
1827 MEM_VOLATILE_P (operands[0]) = 1;
|
|
|
1828 })
|
|
|
1829
|
|
|
1830 (define_insn "*memory_barrier"
|
|
|
1831 [(set (match_operand:BLK 0 "" "")
|
|
|
1832 (unspec:BLK [(match_dup 0)] UNSPEC_MEMW))]
|
|
|
1833 ""
|
|
|
1834 "memw"
|
|
|
1835 [(set_attr "type" "unknown")
|
|
|
1836 (set_attr "mode" "none")
|
|
|
1837 (set_attr "length" "3")])
|
|
|
1838
|
|
|
1839 ;; sync_lock_release is only implemented for SImode.
|
|
|
1840 ;; For other modes, just use the default of a store with a memory_barrier.
|
|
|
1841 (define_insn "sync_lock_releasesi"
|
|
|
1842 [(set (match_operand:SI 0 "mem_operand" "=U")
|
|
|
1843 (unspec_volatile:SI
|
|
|
1844 [(match_operand:SI 1 "register_operand" "r")]
|
|
|
1845 UNSPECV_S32RI))]
|
|
|
1846 "TARGET_RELEASE_SYNC"
|
|
|
1847 "s32ri\t%1, %0"
|
|
|
1848 [(set_attr "type" "store")
|
|
|
1849 (set_attr "mode" "SI")
|
|
|
1850 (set_attr "length" "3")])
|
|
|
1851
|
|
|
1852 (define_insn "sync_compare_and_swapsi"
|
|
|
1853 [(parallel
|
|
|
1854 [(set (match_operand:SI 0 "register_operand" "=a")
|
|
|
1855 (match_operand:SI 1 "mem_operand" "+U"))
|
|
|
1856 (set (match_dup 1)
|
|
|
1857 (unspec_volatile:SI
|
|
|
1858 [(match_dup 1)
|
|
|
1859 (match_operand:SI 2 "register_operand" "r")
|
|
|
1860 (match_operand:SI 3 "register_operand" "0")]
|
|
|
1861 UNSPECV_S32C1I))])]
|
|
|
1862 "TARGET_S32C1I"
|
|
|
1863 "wsr\t%2, SCOMPARE1\;s32c1i\t%3, %1"
|
|
|
1864 [(set_attr "type" "multi")
|
|
|
1865 (set_attr "mode" "SI")
|
|
|
1866 (set_attr "length" "6")])
|
|
|
1867
|
|
|
1868 (define_expand "sync_compare_and_swap<mode>"
|
|
|
1869 [(parallel
|
|
|
1870 [(set (match_operand:HQI 0 "register_operand" "")
|
|
|
1871 (match_operand:HQI 1 "mem_operand" ""))
|
|
|
1872 (set (match_dup 1)
|
|
|
1873 (unspec_volatile:HQI
|
|
|
1874 [(match_dup 1)
|
|
|
1875 (match_operand:HQI 2 "register_operand" "")
|
|
|
1876 (match_operand:HQI 3 "register_operand" "")]
|
|
|
1877 UNSPECV_S32C1I))])]
|
|
|
1878 "TARGET_S32C1I"
|
|
|
1879 {
|
|
|
1880 xtensa_expand_compare_and_swap (operands[0], operands[1],
|
|
|
1881 operands[2], operands[3]);
|
|
|
1882 DONE;
|
|
|
1883 })
|
|
|
1884
|
|
|
1885 (define_expand "sync_lock_test_and_set<mode>"
|
|
|
1886 [(match_operand:HQI 0 "register_operand")
|
|
|
1887 (match_operand:HQI 1 "memory_operand")
|
|
|
1888 (match_operand:HQI 2 "register_operand")]
|
|
|
1889 "TARGET_S32C1I"
|
|
|
1890 {
|
|
|
1891 xtensa_expand_atomic (SET, operands[0], operands[1], operands[2], false);
|
|
|
1892 DONE;
|
|
|
1893 })
|
|
|
1894
|
|
|
1895 (define_expand "sync_<atomic><mode>"
|
|
|
1896 [(set (match_operand:HQI 0 "memory_operand")
|
|
|
1897 (ATOMIC:HQI (match_dup 0)
|
|
|
1898 (match_operand:HQI 1 "register_operand")))]
|
|
|
1899 "TARGET_S32C1I"
|
|
|
1900 {
|
|
|
1901 xtensa_expand_atomic (<CODE>, NULL_RTX, operands[0], operands[1], false);
|
|
|
1902 DONE;
|
|
|
1903 })
|
|
|
1904
|
|
|
1905 (define_expand "sync_old_<atomic><mode>"
|
|
|
1906 [(set (match_operand:HQI 0 "register_operand")
|
|
|
1907 (match_operand:HQI 1 "memory_operand"))
|
|
|
1908 (set (match_dup 1)
|
|
|
1909 (ATOMIC:HQI (match_dup 1)
|
|
|
1910 (match_operand:HQI 2 "register_operand")))]
|
|
|
1911 "TARGET_S32C1I"
|
|
|
1912 {
|
|
|
1913 xtensa_expand_atomic (<CODE>, operands[0], operands[1], operands[2], false);
|
|
|
1914 DONE;
|
|
|
1915 })
|
|
|
1916
|
|
|
1917 (define_expand "sync_new_<atomic><mode>"
|
|
|
1918 [(set (match_operand:HQI 0 "register_operand")
|
|
|
1919 (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
|
|
|
1920 (match_operand:HQI 2 "register_operand")))
|
|
|
1921 (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
|
|
|
1922 "TARGET_S32C1I"
|
|
|
1923 {
|
|
|
1924 xtensa_expand_atomic (<CODE>, operands[0], operands[1], operands[2], true);
|
|
|
1925 DONE;
|
|
|
1926 })
|
