|
111
|
1 ;; GCC machine description for AVX512F instructions
|
|
|
2 ;; Copyright (C) 2013-2017 Free Software Foundation, Inc.
|
|
|
3 ;;
|
|
|
4 ;; This file is part of GCC.
|
|
|
5 ;;
|
|
|
6 ;; GCC is free software; you can redistribute it and/or modify
|
|
|
7 ;; it under the terms of the GNU General Public License as published by
|
|
|
8 ;; the Free Software Foundation; either version 3, or (at your option)
|
|
|
9 ;; any later version.
|
|
|
10 ;;
|
|
|
11 ;; GCC is distributed in the hope that it will be useful,
|
|
|
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
14 ;; GNU General Public License for more details.
|
|
|
15 ;;
|
|
|
16 ;; You should have received a copy of the GNU General Public License
|
|
|
17 ;; along with GCC; see the file COPYING3. If not see
|
|
|
18 ;; <http://www.gnu.org/licenses/>.
|
|
|
19
|
|
|
20 ;; Some iterators for extending subst as much as possible
|
|
|
21 ;; All vectors (Use it for destination)
|
|
|
22 (define_mode_iterator SUBST_V
|
|
|
23 [V64QI V32QI V16QI
|
|
|
24 V32HI V16HI V8HI
|
|
|
25 V16SI V8SI V4SI
|
|
|
26 V8DI V4DI V2DI
|
|
|
27 V16SF V8SF V4SF
|
|
|
28 V8DF V4DF V2DF])
|
|
|
29
|
|
|
30 (define_mode_iterator SUBST_S
|
|
|
31 [QI HI SI DI])
|
|
|
32
|
|
|
33 (define_mode_iterator SUBST_A
|
|
|
34 [V64QI V32QI V16QI
|
|
|
35 V32HI V16HI V8HI
|
|
|
36 V16SI V8SI V4SI
|
|
|
37 V8DI V4DI V2DI
|
|
|
38 V16SF V8SF V4SF
|
|
|
39 V8DF V4DF V2DF
|
|
|
40 QI HI SI DI SF DF
|
|
|
41 CCFP CCFPU])
|
|
|
42
|
|
|
43 (define_subst_attr "mask_name" "mask" "" "_mask")
|
|
|
44 (define_subst_attr "mask_applied" "mask" "false" "true")
|
|
|
45 (define_subst_attr "mask_operand2" "mask" "" "%{%3%}%N2")
|
|
|
46 (define_subst_attr "mask_operand3" "mask" "" "%{%4%}%N3")
|
|
|
47 (define_subst_attr "mask_operand3_1" "mask" "" "%%{%%4%%}%%N3") ;; for sprintf
|
|
|
48 (define_subst_attr "mask_operand4" "mask" "" "%{%5%}%N4")
|
|
|
49 (define_subst_attr "mask_operand6" "mask" "" "%{%7%}%N6")
|
|
|
50 (define_subst_attr "mask_operand7" "mask" "" "%{%8%}%N7")
|
|
|
51 (define_subst_attr "mask_operand10" "mask" "" "%{%11%}%N10")
|
|
|
52 (define_subst_attr "mask_operand11" "mask" "" "%{%12%}%N11")
|
|
|
53 (define_subst_attr "mask_operand18" "mask" "" "%{%19%}%N18")
|
|
|
54 (define_subst_attr "mask_operand19" "mask" "" "%{%20%}%N19")
|
|
|
55 (define_subst_attr "mask_codefor" "mask" "*" "")
|
|
|
56 (define_subst_attr "mask_operand_arg34" "mask" "" ", operands[3], operands[4]")
|
|
|
57 (define_subst_attr "mask_mode512bit_condition" "mask" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
|
|
|
58 (define_subst_attr "mask_avx512vl_condition" "mask" "1" "TARGET_AVX512VL")
|
|
|
59 (define_subst_attr "mask_avx512bw_condition" "mask" "1" "TARGET_AVX512BW")
|
|
|
60 (define_subst_attr "mask_avx512dq_condition" "mask" "1" "TARGET_AVX512DQ")
|
|
|
61 (define_subst_attr "store_mask_constraint" "mask" "vm" "v")
|
|
|
62 (define_subst_attr "store_mask_predicate" "mask" "nonimmediate_operand" "register_operand")
|
|
|
63 (define_subst_attr "mask_prefix" "mask" "vex" "evex")
|
|
|
64 (define_subst_attr "mask_prefix2" "mask" "maybe_vex" "evex")
|
|
|
65 (define_subst_attr "mask_prefix3" "mask" "orig,vex" "evex,evex")
|
|
|
66 (define_subst_attr "mask_prefix4" "mask" "orig,orig,vex" "evex,evex,evex")
|
|
|
67 (define_subst_attr "mask_expand_op3" "mask" "3" "5")
|
|
|
68
|
|
|
69 (define_subst "mask"
|
|
|
70 [(set (match_operand:SUBST_V 0)
|
|
|
71 (match_operand:SUBST_V 1))]
|
|
|
72 "TARGET_AVX512F"
|
|
|
73 [(set (match_dup 0)
|
|
|
74 (vec_merge:SUBST_V
|
|
|
75 (match_dup 1)
|
|
|
76 (match_operand:SUBST_V 2 "vector_move_operand" "0C")
|
|
|
77 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))])
|
|
|
78
|
|
|
79 (define_subst_attr "mask_scalar_merge_name" "mask_scalar_merge" "" "_mask")
|
|
|
80 (define_subst_attr "mask_scalar_merge_operand3" "mask_scalar_merge" "" "%{%3%}")
|
|
|
81 (define_subst_attr "mask_scalar_merge_operand4" "mask_scalar_merge" "" "%{%4%}")
|
|
|
82
|
|
|
83 (define_subst "mask_scalar_merge"
|
|
|
84 [(set (match_operand:SUBST_S 0)
|
|
|
85 (match_operand:SUBST_S 1))]
|
|
|
86 "TARGET_AVX512F"
|
|
|
87 [(set (match_dup 0)
|
|
|
88 (and:SUBST_S
|
|
|
89 (match_dup 1)
|
|
|
90 (match_operand:SUBST_S 3 "register_operand" "Yk")))])
|
|
|
91
|
|
|
92 (define_subst_attr "sd_maskz_name" "sd" "" "_maskz_1")
|
|
|
93 (define_subst_attr "sd_mask_op4" "sd" "" "%{%5%}%N4")
|
|
|
94 (define_subst_attr "sd_mask_op5" "sd" "" "%{%6%}%N5")
|
|
|
95 (define_subst_attr "sd_mask_codefor" "sd" "*" "")
|
|
|
96 (define_subst_attr "sd_mask_mode512bit_condition" "sd" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
|
|
|
97
|
|
|
98 (define_subst "sd"
|
|
|
99 [(set (match_operand:SUBST_V 0)
|
|
|
100 (match_operand:SUBST_V 1))]
|
|
|
101 ""
|
|
|
102 [(set (match_dup 0)
|
|
|
103 (vec_merge:SUBST_V
|
|
|
104 (match_dup 1)
|
|
|
105 (match_operand:SUBST_V 2 "const0_operand" "C")
|
|
|
106 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))
|
|
|
107 ])
|
|
|
108
|
|
|
109 (define_subst_attr "round_name" "round" "" "_round")
|
|
|
110 (define_subst_attr "round_mask_operand2" "mask" "%R2" "%R4")
|
|
|
111 (define_subst_attr "round_mask_operand3" "mask" "%R3" "%R5")
|
|
|
112 (define_subst_attr "round_mask_operand4" "mask" "%R4" "%R6")
|
|
|
113 (define_subst_attr "round_sd_mask_operand4" "sd" "%R4" "%R6")
|
|
|
114 (define_subst_attr "round_op2" "round" "" "%R2")
|
|
|
115 (define_subst_attr "round_op3" "round" "" "%R3")
|
|
|
116 (define_subst_attr "round_op4" "round" "" "%R4")
|
|
|
117 (define_subst_attr "round_op5" "round" "" "%R5")
|
|
|
118 (define_subst_attr "round_op6" "round" "" "%R6")
|
|
|
119 (define_subst_attr "round_mask_op2" "round" "" "<round_mask_operand2>")
|
|
|
120 (define_subst_attr "round_mask_op3" "round" "" "<round_mask_operand3>")
|
|
|
121 (define_subst_attr "round_mask_op4" "round" "" "<round_mask_operand4>")
|
|
|
122 (define_subst_attr "round_sd_mask_op4" "round" "" "<round_sd_mask_operand4>")
|
|
|
123 (define_subst_attr "round_constraint" "round" "vm" "v")
|
|
|
124 (define_subst_attr "round_constraint2" "round" "m" "v")
|
|
|
125 (define_subst_attr "round_constraint3" "round" "rm" "r")
|
|
|
126 (define_subst_attr "round_nimm_predicate" "round" "vector_operand" "register_operand")
|
|
|
127 (define_subst_attr "round_nimm_scalar_predicate" "round" "nonimmediate_operand" "register_operand")
|
|
|
128 (define_subst_attr "round_prefix" "round" "vex" "evex")
|
|
|
129 (define_subst_attr "round_mode512bit_condition" "round" "1" "(<MODE>mode == V16SFmode
|
|
|
130 || <MODE>mode == V8DFmode
|
|
|
131 || <MODE>mode == V8DImode
|
|
|
132 || <MODE>mode == V16SImode)")
|
|
|
133 (define_subst_attr "round_modev8sf_condition" "round" "1" "(<MODE>mode == V8SFmode)")
|
|
|
134 (define_subst_attr "round_modev4sf_condition" "round" "1" "(<MODE>mode == V4SFmode)")
|
|
|
135 (define_subst_attr "round_codefor" "round" "*" "")
|
|
|
136 (define_subst_attr "round_opnum" "round" "5" "6")
|
|
|
137
|
|
|
138 (define_subst "round"
|
|
|
139 [(set (match_operand:SUBST_A 0)
|
|
|
140 (match_operand:SUBST_A 1))]
|
|
|
141 "TARGET_AVX512F"
|
|
|
142 [(set (match_dup 0)
|
|
|
143 (unspec:SUBST_A [(match_dup 1)
|
|
|
144 (match_operand:SI 2 "const_4_or_8_to_11_operand")]
|
|
|
145 UNSPEC_EMBEDDED_ROUNDING))
|
|
|
146 ])
|
|
|
147
|
|
|
148 (define_subst_attr "round_saeonly_name" "round_saeonly" "" "_round")
|
|
|
149 (define_subst_attr "round_saeonly_mask_operand2" "mask" "%r2" "%r4")
|
|
|
150 (define_subst_attr "round_saeonly_mask_operand3" "mask" "%r3" "%r5")
|
|
|
151 (define_subst_attr "round_saeonly_mask_operand4" "mask" "%r4" "%r6")
|
|
|
152 (define_subst_attr "round_saeonly_mask_scalar_merge_operand4" "mask_scalar_merge" "%r4" "%r5")
|
|
|
153 (define_subst_attr "round_saeonly_sd_mask_operand5" "sd" "%r5" "%r7")
|
|
|
154 (define_subst_attr "round_saeonly_op2" "round_saeonly" "" "%r2")
|
|
|
155 (define_subst_attr "round_saeonly_op3" "round_saeonly" "" "%r3")
|
|
|
156 (define_subst_attr "round_saeonly_op4" "round_saeonly" "" "%r4")
|
|
|
157 (define_subst_attr "round_saeonly_op5" "round_saeonly" "" "%r5")
|
|
|
158 (define_subst_attr "round_saeonly_op6" "round_saeonly" "" "%r6")
|
|
|
159 (define_subst_attr "round_saeonly_prefix" "round_saeonly" "vex" "evex")
|
|
|
160 (define_subst_attr "round_saeonly_mask_op2" "round_saeonly" "" "<round_saeonly_mask_operand2>")
|
|
|
161 (define_subst_attr "round_saeonly_mask_op3" "round_saeonly" "" "<round_saeonly_mask_operand3>")
|
|
|
162 (define_subst_attr "round_saeonly_mask_op4" "round_saeonly" "" "<round_saeonly_mask_operand4>")
|
|
|
163 (define_subst_attr "round_saeonly_mask_scalar_merge_op4" "round_saeonly" "" "<round_saeonly_mask_scalar_merge_operand4>")
|
|
|
164 (define_subst_attr "round_saeonly_sd_mask_op5" "round_saeonly" "" "<round_saeonly_sd_mask_operand5>")
|
|
|
165 (define_subst_attr "round_saeonly_mask_arg3" "round_saeonly" "" ", operands[<mask_expand_op3>]")
|
|
|
166 (define_subst_attr "round_saeonly_constraint" "round_saeonly" "vm" "v")
|
|
|
167 (define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v")
|
|
|
168 (define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "vector_operand" "register_operand")
|
|
|
169 (define_subst_attr "round_saeonly_nimm_scalar_predicate" "round_saeonly" "nonimmediate_operand" "register_operand")
|
|
|
170 (define_subst_attr "round_saeonly_mode512bit_condition" "round_saeonly" "1" "(<MODE>mode == V16SFmode
|
|
|
171 || <MODE>mode == V8DFmode
|
|
|
172 || <MODE>mode == V8DImode
|
|
|
173 || <MODE>mode == V16SImode)")
|
|
|
174 (define_subst_attr "round_saeonly_modev8sf_condition" "round_saeonly" "1" "(<MODE>mode == V8SFmode)")
|
|
|
175
|
|
|
176 (define_subst "round_saeonly"
|
|
|
177 [(set (match_operand:SUBST_A 0)
|
|
|
178 (match_operand:SUBST_A 1))]
|
|
|
179 "TARGET_AVX512F"
|
|
|
180 [(set (match_dup 0)
|
|
|
181 (unspec:SUBST_A [(match_dup 1)
|
|
|
182 (match_operand:SI 2 "const48_operand")]
|
|
|
183 UNSPEC_EMBEDDED_ROUNDING))
|
|
|
184 ])
|
|
|
185
|
|
|
186 (define_subst_attr "round_expand_name" "round_expand" "" "_round")
|
|
|
187 (define_subst_attr "round_expand_nimm_predicate" "round_expand" "nonimmediate_operand" "register_operand")
|
|
|
188 (define_subst_attr "round_expand_operand" "round_expand" "" ", operands[5]")
|
|
|
189
|
|
|
190 (define_subst "round_expand"
|
|
|
191 [(match_operand:SUBST_V 0)
|
|
|
192 (match_operand:SUBST_V 1)
|
|
|
193 (match_operand:SUBST_V 2)
|
|
|
194 (match_operand:SUBST_V 3)
|
|
|
195 (match_operand:SUBST_S 4)]
|
|
|
196 "TARGET_AVX512F"
|
|
|
197 [(match_dup 0)
|
|
|
198 (match_dup 1)
|
|
|
199 (match_dup 2)
|
|
|
200 (match_dup 3)
|
|
|
201 (match_dup 4)
|
|
|
202 (unspec [(match_operand:SI 5 "const_4_or_8_to_11_operand")] UNSPEC_EMBEDDED_ROUNDING)])
|
|
|
203
|
|
|
204 (define_subst_attr "round_saeonly_expand_name" "round_saeonly_expand" "" "_round")
|
|
|
205 (define_subst_attr "round_saeonly_expand_nimm_predicate" "round_saeonly_expand" "nonimmediate_operand" "register_operand")
|
|
|
206 (define_subst_attr "round_saeonly_expand_operand6" "round_saeonly_expand" "" ", operands[6]")
|
|
|
207
|
|
|
208 (define_subst "round_saeonly_expand"
|
|
|
209 [(match_operand:SUBST_V 0)
|
|
|
210 (match_operand:SUBST_V 1)
|
|
|
211 (match_operand:SUBST_V 2)
|
|
|
212 (match_operand:SUBST_A 3)
|
|
|
213 (match_operand:SI 4)
|
|
|
214 (match_operand:SUBST_S 5)]
|
|
|
215 "TARGET_AVX512F"
|
|
|
216 [(match_dup 0)
|
|
|
217 (match_dup 1)
|
|
|
218 (match_dup 2)
|
|
|
219 (match_dup 3)
|
|
|
220 (match_dup 4)
|
|
|
221 (match_dup 5)
|
|
|
222 (unspec [(match_operand:SI 6 "const48_operand")] UNSPEC_EMBEDDED_ROUNDING)])
|
|
|
223
|
|
|
224 (define_subst_attr "mask_expand4_name" "mask_expand4" "" "_mask")
|
|
|
225 (define_subst_attr "mask_expand4_args" "mask_expand4" "" ", operands[4], operands[5]")
|
|
|
226
|
|
|
227 (define_subst "mask_expand4"
|
|
|
228 [(match_operand:SUBST_V 0)
|
|
|
229 (match_operand:SUBST_V 1)
|
|
|
230 (match_operand:SUBST_V 2)
|
|
|
231 (match_operand:SI 3)]
|
|
|
232 "TARGET_AVX512VL"
|
|
|
233 [(match_dup 0)
|
|
|
234 (match_dup 1)
|
|
|
235 (match_dup 2)
|
|
|
236 (match_dup 3)
|
|
|
237 (match_operand:SUBST_V 4 "vector_move_operand")
|
|
|
238 (match_operand:<avx512fmaskmode> 5 "register_operand")])
|
|
|
239
|
|
|
240 (define_subst_attr "mask_scalar_name" "mask_scalar" "" "_mask")
|
|
|
241 (define_subst_attr "mask_scalar_operand3" "mask_scalar" "" "%{%4%}%N3")
|
|
|
242 (define_subst_attr "mask_scalar_operand4" "mask_scalar" "" "%{%5%}%N4")
|
|
|
243
|
|
|
244 (define_subst "mask_scalar"
|
|
|
245 [(set (match_operand:SUBST_V 0)
|
|
|
246 (vec_merge:SUBST_V
|
|
|
247 (match_operand:SUBST_V 1)
|
|
|
248 (match_operand:SUBST_V 2)
|
|
|
249 (const_int 1)))]
|
|
|
250 "TARGET_AVX512F"
|
|
|
251 [(set (match_dup 0)
|
|
|
252 (vec_merge:SUBST_V
|
|
|
253 (vec_merge:SUBST_V
|
|
|
254 (match_dup 1)
|
|
|
255 (match_operand:SUBST_V 3 "vector_move_operand" "0C")
|
|
|
256 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
|
|
|
257 (match_dup 2)
|
|
|
258 (const_int 1)))])
|
|
|
259
|
|
|
260 (define_subst_attr "round_scalar_name" "round_scalar" "" "_round")
|
|
|
261 (define_subst_attr "round_scalar_mask_operand3" "mask_scalar" "%R3" "%R5")
|
|
|
262 (define_subst_attr "round_scalar_mask_op3" "round_scalar" "" "<round_scalar_mask_operand3>")
|
|
|
263 (define_subst_attr "round_scalar_constraint" "round_scalar" "vm" "v")
|
|
|
264 (define_subst_attr "round_scalar_prefix" "round_scalar" "vex" "evex")
|
|
|
265
|
|
|
266 (define_subst "round_scalar"
|
|
|
267 [(set (match_operand:SUBST_V 0)
|
|
|
268 (vec_merge:SUBST_V
|
|
|
269 (match_operand:SUBST_V 1)
|
|
|
270 (match_operand:SUBST_V 2)
|
|
|
271 (const_int 1)))]
|
|
|
272 "TARGET_AVX512F"
|
|
|
273 [(set (match_dup 0)
|
|
|
274 (unspec:SUBST_V [
|
|
|
275 (vec_merge:SUBST_V
|
|
|
276 (match_dup 1)
|
|
|
277 (match_dup 2)
|
|
|
278 (const_int 1))
|
|
|
279 (match_operand:SI 3 "const_4_or_8_to_11_operand")]
|
|
|
280 UNSPEC_EMBEDDED_ROUNDING))])
|
|
|
281
|
|
|
282 (define_subst_attr "round_saeonly_scalar_name" "round_saeonly_scalar" "" "_round")
|
|
|
283 (define_subst_attr "round_saeonly_scalar_mask_operand3" "mask_scalar" "%r3" "%r5")
|
|
|
284 (define_subst_attr "round_saeonly_scalar_mask_operand4" "mask_scalar" "%r4" "%r6")
|
|
|
285 (define_subst_attr "round_saeonly_scalar_mask_op3" "round_saeonly_scalar" "" "<round_saeonly_scalar_mask_operand3>")
|
|
|
286 (define_subst_attr "round_saeonly_scalar_mask_op4" "round_saeonly_scalar" "" "<round_saeonly_scalar_mask_operand4>")
|
|
|
287 (define_subst_attr "round_saeonly_scalar_constraint" "round_saeonly_scalar" "vm" "v")
|
|
|
288 (define_subst_attr "round_saeonly_scalar_prefix" "round_saeonly_scalar" "vex" "evex")
|
|
|
289 (define_subst_attr "round_saeonly_scalar_nimm_predicate" "round_saeonly_scalar" "vector_operand" "register_operand")
|
|
|
290
|
|
|
291 (define_subst "round_saeonly_scalar"
|
|
|
292 [(set (match_operand:SUBST_V 0)
|
|
|
293 (vec_merge:SUBST_V
|
|
|
294 (match_operand:SUBST_V 1)
|
|
|
295 (match_operand:SUBST_V 2)
|
|
|
296 (const_int 1)))]
|
|
|
297 "TARGET_AVX512F"
|
|
|
298 [(set (match_dup 0)
|
|
|
299 (unspec:SUBST_V [
|
|
|
300 (vec_merge:SUBST_V
|
|
|
301 (match_dup 1)
|
|
|
302 (match_dup 2)
|
|
|
303 (const_int 1))
|
|
|
304 (match_operand:SI 3 "const48_operand")]
|
|
|
305 UNSPEC_EMBEDDED_ROUNDING))])
|
