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1 ;; Constraint definitions for IA-64
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2 ;; Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; Register constraints
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21
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22 (define_register_constraint "a" "ADDL_REGS"
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23 "addl register")
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24
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25 (define_register_constraint "b" "BR_REGS"
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26 "branch register")
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27
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28 (define_register_constraint "c" "PR_REGS"
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29 "predicate register")
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30
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31 (define_register_constraint "d" "AR_M_REGS"
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32 "memory pipeline application register")
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33
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34 (define_register_constraint "e" "AR_I_REGS"
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35 "integer pipeline application register")
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36
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37 (define_register_constraint "f" "FR_REGS"
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38 "floating-point register")
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39
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40 (define_register_constraint "x" "FP_REGS"
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41 "floating-point register, excluding f31 and f127, used for fldp")
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42
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43 ;; Integer constraints
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44
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45 (define_constraint "I"
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46 "14 bit signed immediate for arithmetic instructions"
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47 (and (match_code "const_int")
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48 (match_test "(unsigned HOST_WIDE_INT)ival + 0x2000 < 0x4000")))
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49
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50 (define_constraint "J"
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51 "22 bit signed immediate for arith instructions with r0/r1/r2/r3 source"
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52 (and (match_code "const_int")
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53 (match_test "(unsigned HOST_WIDE_INT)ival + 0x200000 < 0x400000")))
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54
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55 (define_constraint "j"
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56 "(2**32-2**13)..(2**32-1) for addp4 instructions"
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57 (and (match_code "const_int")
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58 (match_test "(unsigned HOST_WIDE_INT)ival >= 0xffffe000
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59 && (unsigned HOST_WIDE_INT)ival <= 0xffffffff")))
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60
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61 (define_constraint "K"
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62 "8 bit signed immediate for logical instructions"
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63 (and (match_code "const_int")
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64 (match_test "(unsigned HOST_WIDE_INT)ival + 0x80 < 0x100")))
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65
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66 (define_constraint "L"
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67 "8 bit adjusted signed immediate for compare pseudo-ops"
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68 (and (match_code "const_int")
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69 (match_test "(unsigned HOST_WIDE_INT)ival + 0x7F < 0x100")))
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70
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71 (define_constraint "M"
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72 "6 bit unsigned immediate for shift counts"
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73 (and (match_code "const_int")
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74 (match_test "(unsigned HOST_WIDE_INT)ival < 0x40")))
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75
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76 (define_constraint "N"
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77 "9 bit signed immediate for load/store post-increments"
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78 (and (match_code "const_int")
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79 (match_test "(unsigned HOST_WIDE_INT)ival + 0x100 < 0x200")))
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80
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81 (define_constraint "O"
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82 "constant zero"
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83 (and (match_code "const_int")
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84 (match_test "ival == 0")))
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85
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86 (define_constraint "P"
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87 "0 or -1 for dep instruction"
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88 (and (match_code "const_int")
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89 (match_test "ival == 0 || ival == -1")))
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90
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91 ;; Floating-point constraints
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92
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93 (define_constraint "G"
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94 "0.0 and 1.0 for fr0 and fr1"
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95 (and (match_code "const_double")
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96 (match_test "op == CONST0_RTX (mode) || op == CONST1_RTX (mode)")))
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97
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98 (define_constraint "H"
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99 "0.0"
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100 (and (match_code "const_double")
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101 (match_test "op == CONST0_RTX (mode)")))
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102
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103 ;; Extra constraints
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104
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105 ;; Note that while this accepts mem, it only accepts non-volatile mem,
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106 ;; and so cannot be "fixed" by adjusting the address. Thus it cannot
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107 ;; and does not use define_memory_constraint.
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108 (define_constraint "Q"
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109 "Non-volatile memory for FP_REG loads/stores"
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110 (and (match_operand 0 "memory_operand")
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111 (match_test "!MEM_VOLATILE_P (op)")))
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112
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113 (define_constraint "R"
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114 "1..4 for shladd arguments"
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115 (and (match_code "const_int")
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116 (match_test "ival >= 1 && ival <= 4")))
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117
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118 (define_constraint "T"
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119 "Symbol ref to small-address-area"
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120 (match_operand 0 "small_addr_symbolic_operand"))
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121
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122 (define_constraint "U"
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123 "vector zero constant"
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124 (and (match_code "const_vector")
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125 (match_test "op == CONST0_RTX (mode)")))
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126
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127 (define_constraint "W"
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128 "An integer vector, such that conversion to an integer yields a
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129 value appropriate for an integer 'J' constraint."
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130 (and (match_code "const_vector")
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131 (match_test "GET_MODE_CLASS (mode) == MODE_VECTOR_INT")
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132 (match_test
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133 "satisfies_constraint_J (simplify_subreg (DImode, op, mode, 0))")))
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134
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135 (define_constraint "Y"
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136 "A V2SF vector containing elements that satisfy 'G'"
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137 (and (match_code "const_vector")
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138 (match_test "mode == V2SFmode")
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139 (match_test "satisfies_constraint_G (XVECEXP (op, 0, 0))")
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140 (match_test "satisfies_constraint_G (XVECEXP (op, 0, 1))")))
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141
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142 ;; Memory constraints
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143
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144 (define_memory_constraint "S"
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145 "Non-post-inc memory for asms and other unsavory creatures"
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146 (and (match_code "mem")
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147 (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
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