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1 ;; ARM 1026EJ-S Pipeline Description
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2 ;; Copyright (C) 2003, 2007 Free Software Foundation, Inc.
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3 ;; Written by CodeSourcery, LLC.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but
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13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 ;; General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>. */
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20
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21 ;; These descriptions are based on the information contained in the
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22 ;; ARM1026EJ-S Technical Reference Manual, Copyright (c) 2003 ARM
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23 ;; Limited.
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24 ;;
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25
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26 ;; This automaton provides a pipeline description for the ARM
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27 ;; 1026EJ-S core.
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28 ;;
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29 ;; The model given here assumes that the condition for all conditional
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30 ;; instructions is "true", i.e., that all of the instructions are
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31 ;; actually executed.
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32
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33 (define_automaton "arm1026ejs")
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34
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35 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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36 ;; Pipelines
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37 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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38
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39 ;; There are two pipelines:
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40 ;;
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41 ;; - An Arithmetic Logic Unit (ALU) pipeline.
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42 ;;
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43 ;; The ALU pipeline has fetch, issue, decode, execute, memory, and
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44 ;; write stages. We only need to model the execute, memory and write
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45 ;; stages.
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46 ;;
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47 ;; - A Load-Store Unit (LSU) pipeline.
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48 ;;
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49 ;; The LSU pipeline has decode, execute, memory, and write stages.
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50 ;; We only model the execute, memory and write stages.
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51
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52 (define_cpu_unit "a_e,a_m,a_w" "arm1026ejs")
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53 (define_cpu_unit "l_e,l_m,l_w" "arm1026ejs")
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54
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55 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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56 ;; ALU Instructions
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57 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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58
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59 ;; ALU instructions require three cycles to execute, and use the ALU
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60 ;; pipeline in each of the three stages. The results are available
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61 ;; after the execute stage stage has finished.
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62 ;;
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63 ;; If the destination register is the PC, the pipelines are stalled
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64 ;; for several cycles. That case is not modeled here.
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65
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66 ;; ALU operations with no shifted operand
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67 (define_insn_reservation "alu_op" 1
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68 (and (eq_attr "tune" "arm1026ejs")
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69 (eq_attr "type" "alu"))
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70 "a_e,a_m,a_w")
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71
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72 ;; ALU operations with a shift-by-constant operand
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73 (define_insn_reservation "alu_shift_op" 1
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74 (and (eq_attr "tune" "arm1026ejs")
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75 (eq_attr "type" "alu_shift"))
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76 "a_e,a_m,a_w")
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77
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78 ;; ALU operations with a shift-by-register operand
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79 ;; These really stall in the decoder, in order to read
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80 ;; the shift value in a second cycle. Pretend we take two cycles in
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81 ;; the execute stage.
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82 (define_insn_reservation "alu_shift_reg_op" 2
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83 (and (eq_attr "tune" "arm1026ejs")
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84 (eq_attr "type" "alu_shift_reg"))
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85 "a_e*2,a_m,a_w")
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86
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87 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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88 ;; Multiplication Instructions
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89 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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90
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91 ;; Multiplication instructions loop in the execute stage until the
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92 ;; instruction has been passed through the multiplier array enough
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93 ;; times.
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94
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95 ;; The result of the "smul" and "smulw" instructions is not available
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96 ;; until after the memory stage.
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97 (define_insn_reservation "mult1" 2
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98 (and (eq_attr "tune" "arm1026ejs")
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99 (eq_attr "insn" "smulxy,smulwy"))
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100 "a_e,a_m,a_w")
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101
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102 ;; The "smlaxy" and "smlawx" instructions require two iterations through
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103 ;; the execute stage; the result is available immediately following
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104 ;; the execute stage.
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105 (define_insn_reservation "mult2" 2
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106 (and (eq_attr "tune" "arm1026ejs")
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107 (eq_attr "insn" "smlaxy,smlalxy,smlawx"))
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108 "a_e*2,a_m,a_w")
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109
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110 ;; The "smlalxy", "mul", and "mla" instructions require two iterations
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111 ;; through the execute stage; the result is not available until after
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112 ;; the memory stage.
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113 (define_insn_reservation "mult3" 3
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114 (and (eq_attr "tune" "arm1026ejs")
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115 (eq_attr "insn" "smlalxy,mul,mla"))
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116 "a_e*2,a_m,a_w")
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117
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118 ;; The "muls" and "mlas" instructions loop in the execute stage for
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119 ;; four iterations in order to set the flags. The value result is
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120 ;; available after three iterations.
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121 (define_insn_reservation "mult4" 3
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122 (and (eq_attr "tune" "arm1026ejs")
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123 (eq_attr "insn" "muls,mlas"))
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124 "a_e*4,a_m,a_w")
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125
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126 ;; Long multiply instructions that produce two registers of
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127 ;; output (such as umull) make their results available in two cycles;
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128 ;; the least significant word is available before the most significant
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129 ;; word. That fact is not modeled; instead, the instructions are
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130 ;; described.as if the entire result was available at the end of the
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131 ;; cycle in which both words are available.
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132
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133 ;; The "umull", "umlal", "smull", and "smlal" instructions all take
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134 ;; three iterations through the execute cycle, and make their results
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135 ;; available after the memory cycle.
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136 (define_insn_reservation "mult5" 4
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137 (and (eq_attr "tune" "arm1026ejs")
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138 (eq_attr "insn" "umull,umlal,smull,smlal"))
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139 "a_e*3,a_m,a_w")
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140
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141 ;; The "umulls", "umlals", "smulls", and "smlals" instructions loop in
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142 ;; the execute stage for five iterations in order to set the flags.
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143 ;; The value result is available after four iterations.
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144 (define_insn_reservation "mult6" 4
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145 (and (eq_attr "tune" "arm1026ejs")
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146 (eq_attr "insn" "umulls,umlals,smulls,smlals"))
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147 "a_e*5,a_m,a_w")
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148
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149 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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150 ;; Load/Store Instructions
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151 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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152
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153 ;; The models for load/store instructions do not accurately describe
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154 ;; the difference between operations with a base register writeback
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155 ;; (such as "ldm!"). These models assume that all memory references
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156 ;; hit in dcache.
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157
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158 ;; LSU instructions require six cycles to execute. They use the ALU
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159 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
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160 ;; three through six.
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161 ;; Loads and stores which use a scaled register offset or scaled
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162 ;; register pre-indexed addressing mode take three cycles EXCEPT for
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163 ;; those that are base + offset with LSL of 0 or 2, or base - offset
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164 ;; with LSL of zero. The remainder take 1 cycle to execute.
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165 ;; For 4byte loads there is a bypass from the load stage
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166
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167 (define_insn_reservation "load1_op" 2
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168 (and (eq_attr "tune" "arm1026ejs")
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169 (eq_attr "type" "load_byte,load1"))
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170 "a_e+l_e,l_m,a_w+l_w")
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171
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172 (define_insn_reservation "store1_op" 0
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173 (and (eq_attr "tune" "arm1026ejs")
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174 (eq_attr "type" "store1"))
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175 "a_e+l_e,l_m,a_w+l_w")
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176
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177 ;; A load's result can be stored by an immediately following store
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178 (define_bypass 1 "load1_op" "store1_op" "arm_no_early_store_addr_dep")
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179
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180 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
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181 ;; registers have been processed.
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182 ;;
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183 ;; The time it takes to load the data depends on whether or not the
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184 ;; base address is 64-bit aligned; if it is not, an additional cycle
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185 ;; is required. This model assumes that the address is always 64-bit
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186 ;; aligned. Because the processor can load two registers per cycle,
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187 ;; that assumption means that we use the same instruction reservations
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188 ;; for loading 2k and 2k - 1 registers.
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189 ;;
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190 ;; The ALU pipeline is stalled until the completion of the last memory
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191 ;; stage in the LSU pipeline. That is modeled by keeping the ALU
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192 ;; execute stage busy until that point.
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193 ;;
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194 ;; As with ALU operations, if one of the destination registers is the
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195 ;; PC, there are additional stalls; that is not modeled.
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196
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197 (define_insn_reservation "load2_op" 2
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198 (and (eq_attr "tune" "arm1026ejs")
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199 (eq_attr "type" "load2"))
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200 "a_e+l_e,l_m,a_w+l_w")
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201
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202 (define_insn_reservation "store2_op" 0
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203 (and (eq_attr "tune" "arm1026ejs")
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204 (eq_attr "type" "store2"))
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205 "a_e+l_e,l_m,a_w+l_w")
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206
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207 (define_insn_reservation "load34_op" 3
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208 (and (eq_attr "tune" "arm1026ejs")
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209 (eq_attr "type" "load3,load4"))
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210 "a_e+l_e,a_e+l_e+l_m,a_e+l_m,a_w+l_w")
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211
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212 (define_insn_reservation "store34_op" 0
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213 (and (eq_attr "tune" "arm1026ejs")
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214 (eq_attr "type" "store3,store4"))
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215 "a_e+l_e,a_e+l_e+l_m,a_e+l_m,a_w+l_w")
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216
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217 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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218 ;; Branch and Call Instructions
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219 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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220
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221 ;; Branch instructions are difficult to model accurately. The ARM
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222 ;; core can predict most branches. If the branch is predicted
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223 ;; correctly, and predicted early enough, the branch can be completely
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224 ;; eliminated from the instruction stream. Some branches can
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225 ;; therefore appear to require zero cycles to execute. We assume that
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226 ;; all branches are predicted correctly, and that the latency is
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227 ;; therefore the minimum value.
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228
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229 (define_insn_reservation "branch_op" 0
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230 (and (eq_attr "tune" "arm1026ejs")
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231 (eq_attr "type" "branch"))
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232 "nothing")
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233
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234 ;; The latency for a call is not predictable. Therefore, we use 32 as
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235 ;; roughly equivalent to positive infinity.
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236
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237 (define_insn_reservation "call_op" 32
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238 (and (eq_attr "tune" "arm1026ejs")
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239 (eq_attr "type" "call"))
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240 "nothing")
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