Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/i386/driver-i386.c @ 63:b7f97abdc517 gcc-4.6-20100522
update gcc from gcc-4.5.0 to gcc-4.6
author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
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date | Mon, 24 May 2010 12:47:05 +0900 |
parents | 77e2b8dfacca |
children | f6334be47118 |
rev | line source |
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0 | 1 /* Subroutines for the gcc driver. |
2 Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc. | |
3 | |
4 This file is part of GCC. | |
5 | |
6 GCC is free software; you can redistribute it and/or modify | |
7 it under the terms of the GNU General Public License as published by | |
8 the Free Software Foundation; either version 3, or (at your option) | |
9 any later version. | |
10 | |
11 GCC is distributed in the hope that it will be useful, | |
12 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 GNU General Public License for more details. | |
15 | |
16 You should have received a copy of the GNU General Public License | |
17 along with GCC; see the file COPYING3. If not see | |
18 <http://www.gnu.org/licenses/>. */ | |
19 | |
20 #include "config.h" | |
21 #include "system.h" | |
22 #include "coretypes.h" | |
23 #include "tm.h" | |
24 #include <stdlib.h> | |
25 | |
26 const char *host_detect_local_cpu (int argc, const char **argv); | |
27 | |
28 #ifdef __GNUC__ | |
29 #include "cpuid.h" | |
30 | |
31 struct cache_desc | |
32 { | |
33 unsigned sizekb; | |
34 unsigned assoc; | |
35 unsigned line; | |
36 }; | |
37 | |
38 /* Returns command line parameters that describe size and | |
39 cache line size of the processor caches. */ | |
40 | |
41 static char * | |
42 describe_cache (struct cache_desc level1, struct cache_desc level2) | |
43 { | |
44 char size[100], line[100], size2[100]; | |
45 | |
46 /* At the moment, gcc does not use the information | |
47 about the associativity of the cache. */ | |
48 | |
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49 snprintf (size, sizeof (size), |
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50 "--param l1-cache-size=%u ", level1.sizekb); |
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51 snprintf (line, sizeof (line), |
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52 "--param l1-cache-line-size=%u ", level1.line); |
0 | 53 |
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54 snprintf (size2, sizeof (size2), |
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55 "--param l2-cache-size=%u ", level2.sizekb); |
0 | 56 |
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57 return concat (size, line, size2, NULL); |
0 | 58 } |
59 | |
60 /* Detect L2 cache parameters using CPUID extended function 0x80000006. */ | |
61 | |
62 static void | |
63 detect_l2_cache (struct cache_desc *level2) | |
64 { | |
65 unsigned eax, ebx, ecx, edx; | |
66 unsigned assoc; | |
67 | |
68 __cpuid (0x80000006, eax, ebx, ecx, edx); | |
69 | |
70 level2->sizekb = (ecx >> 16) & 0xffff; | |
71 level2->line = ecx & 0xff; | |
72 | |
73 assoc = (ecx >> 12) & 0xf; | |
74 if (assoc == 6) | |
75 assoc = 8; | |
76 else if (assoc == 8) | |
77 assoc = 16; | |
78 else if (assoc >= 0xa && assoc <= 0xc) | |
79 assoc = 32 + (assoc - 0xa) * 16; | |
80 else if (assoc >= 0xd && assoc <= 0xe) | |
81 assoc = 96 + (assoc - 0xd) * 32; | |
82 | |
83 level2->assoc = assoc; | |
84 } | |
85 | |
86 /* Returns the description of caches for an AMD processor. */ | |
87 | |
88 static const char * | |
89 detect_caches_amd (unsigned max_ext_level) | |
90 { | |
91 unsigned eax, ebx, ecx, edx; | |
92 | |
93 struct cache_desc level1, level2 = {0, 0, 0}; | |
94 | |
95 if (max_ext_level < 0x80000005) | |
96 return ""; | |
97 | |
98 __cpuid (0x80000005, eax, ebx, ecx, edx); | |
99 | |
100 level1.sizekb = (ecx >> 24) & 0xff; | |
101 level1.assoc = (ecx >> 16) & 0xff; | |
102 level1.line = ecx & 0xff; | |
103 | |
104 if (max_ext_level >= 0x80000006) | |
105 detect_l2_cache (&level2); | |
106 | |
107 return describe_cache (level1, level2); | |
108 } | |
109 | |
110 /* Decodes the size, the associativity and the cache line size of | |
111 L1/L2 caches of an Intel processor. Values are based on | |
112 "Intel Processor Identification and the CPUID Instruction" | |
113 [Application Note 485], revision -032, December 2007. */ | |
114 | |
115 static void | |
116 decode_caches_intel (unsigned reg, bool xeon_mp, | |
117 struct cache_desc *level1, struct cache_desc *level2) | |
118 { | |
119 int i; | |
120 | |
121 for (i = 24; i >= 0; i -= 8) | |
122 switch ((reg >> i) & 0xff) | |
123 { | |
124 case 0x0a: | |
125 level1->sizekb = 8; level1->assoc = 2; level1->line = 32; | |
126 break; | |
127 case 0x0c: | |
128 level1->sizekb = 16; level1->assoc = 4; level1->line = 32; | |
129 break; | |
130 case 0x2c: | |
131 level1->sizekb = 32; level1->assoc = 8; level1->line = 64; | |
132 break; | |
133 case 0x39: | |
134 level2->sizekb = 128; level2->assoc = 4; level2->line = 64; | |
135 break; | |
136 case 0x3a: | |
137 level2->sizekb = 192; level2->assoc = 6; level2->line = 64; | |
138 break; | |
139 case 0x3b: | |
140 level2->sizekb = 128; level2->assoc = 2; level2->line = 64; | |
141 break; | |
142 case 0x3c: | |
143 level2->sizekb = 256; level2->assoc = 4; level2->line = 64; | |
144 break; | |
145 case 0x3d: | |
146 level2->sizekb = 384; level2->assoc = 6; level2->line = 64; | |
147 break; | |
148 case 0x3e: | |
149 level2->sizekb = 512; level2->assoc = 4; level2->line = 64; | |
150 break; | |
151 case 0x41: | |
152 level2->sizekb = 128; level2->assoc = 4; level2->line = 32; | |
153 break; | |
154 case 0x42: | |
155 level2->sizekb = 256; level2->assoc = 4; level2->line = 32; | |
156 break; | |
157 case 0x43: | |
158 level2->sizekb = 512; level2->assoc = 4; level2->line = 32; | |
159 break; | |
160 case 0x44: | |
161 level2->sizekb = 1024; level2->assoc = 4; level2->line = 32; | |
162 break; | |
163 case 0x45: | |
164 level2->sizekb = 2048; level2->assoc = 4; level2->line = 32; | |
165 break; | |
166 case 0x49: | |
167 if (xeon_mp) | |
168 break; | |
169 level2->sizekb = 4096; level2->assoc = 16; level2->line = 64; | |
170 break; | |
171 case 0x4e: | |
172 level2->sizekb = 6144; level2->assoc = 24; level2->line = 64; | |
173 break; | |
174 case 0x60: | |
175 level1->sizekb = 16; level1->assoc = 8; level1->line = 64; | |
176 break; | |
177 case 0x66: | |
178 level1->sizekb = 8; level1->assoc = 4; level1->line = 64; | |
179 break; | |
180 case 0x67: | |
181 level1->sizekb = 16; level1->assoc = 4; level1->line = 64; | |
182 break; | |
183 case 0x68: | |
184 level1->sizekb = 32; level1->assoc = 4; level1->line = 64; | |
185 break; | |
186 case 0x78: | |
187 level2->sizekb = 1024; level2->assoc = 4; level2->line = 64; | |
188 break; | |
189 case 0x79: | |
190 level2->sizekb = 128; level2->assoc = 8; level2->line = 64; | |
191 break; | |
192 case 0x7a: | |
193 level2->sizekb = 256; level2->assoc = 8; level2->line = 64; | |
194 break; | |
195 case 0x7b: | |
196 level2->sizekb = 512; level2->assoc = 8; level2->line = 64; | |
197 break; | |
198 case 0x7c: | |
199 level2->sizekb = 1024; level2->assoc = 8; level2->line = 64; | |
200 break; | |
201 case 0x7d: | |
202 level2->sizekb = 2048; level2->assoc = 8; level2->line = 64; | |
203 break; | |
204 case 0x7f: | |
205 level2->sizekb = 512; level2->assoc = 2; level2->line = 64; | |
206 break; | |
207 case 0x82: | |
208 level2->sizekb = 256; level2->assoc = 8; level2->line = 32; | |
209 break; | |
210 case 0x83: | |
211 level2->sizekb = 512; level2->assoc = 8; level2->line = 32; | |
212 break; | |
213 case 0x84: | |
214 level2->sizekb = 1024; level2->assoc = 8; level2->line = 32; | |
215 break; | |
216 case 0x85: | |
217 level2->sizekb = 2048; level2->assoc = 8; level2->line = 32; | |
218 break; | |
219 case 0x86: | |
220 level2->sizekb = 512; level2->assoc = 4; level2->line = 64; | |
221 break; | |
222 case 0x87: | |
223 level2->sizekb = 1024; level2->assoc = 8; level2->line = 64; | |
224 | |
225 default: | |
226 break; | |
227 } | |
228 } | |
229 | |
230 /* Detect cache parameters using CPUID function 2. */ | |
231 | |
232 static void | |
233 detect_caches_cpuid2 (bool xeon_mp, | |
234 struct cache_desc *level1, struct cache_desc *level2) | |
235 { | |
236 unsigned regs[4]; | |
237 int nreps, i; | |
238 | |
239 __cpuid (2, regs[0], regs[1], regs[2], regs[3]); | |
240 | |
241 nreps = regs[0] & 0x0f; | |
242 regs[0] &= ~0x0f; | |
243 | |
244 while (--nreps >= 0) | |
245 { | |
246 for (i = 0; i < 4; i++) | |
247 if (regs[i] && !((regs[i] >> 31) & 1)) | |
248 decode_caches_intel (regs[i], xeon_mp, level1, level2); | |
249 | |
250 if (nreps) | |
251 __cpuid (2, regs[0], regs[1], regs[2], regs[3]); | |
252 } | |
253 } | |
254 | |
255 /* Detect cache parameters using CPUID function 4. This | |
256 method doesn't require hardcoded tables. */ | |
257 | |
258 enum cache_type | |
259 { | |
260 CACHE_END = 0, | |
261 CACHE_DATA = 1, | |
262 CACHE_INST = 2, | |
263 CACHE_UNIFIED = 3 | |
264 }; | |
265 | |
266 static void | |
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267 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2, |
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268 struct cache_desc *level3) |
0 | 269 { |
270 struct cache_desc *cache; | |
271 | |
272 unsigned eax, ebx, ecx, edx; | |
273 int count; | |
274 | |
275 for (count = 0;; count++) | |
276 { | |
277 __cpuid_count(4, count, eax, ebx, ecx, edx); | |
278 switch (eax & 0x1f) | |
279 { | |
280 case CACHE_END: | |
281 return; | |
282 case CACHE_DATA: | |
283 case CACHE_UNIFIED: | |
284 { | |
285 switch ((eax >> 5) & 0x07) | |
286 { | |
287 case 1: | |
288 cache = level1; | |
289 break; | |
290 case 2: | |
291 cache = level2; | |
292 break; | |
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293 case 3: |
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294 cache = level3; |
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295 break; |
0 | 296 default: |
297 cache = NULL; | |
298 } | |
299 | |
300 if (cache) | |
301 { | |
302 unsigned sets = ecx + 1; | |
303 unsigned part = ((ebx >> 12) & 0x03ff) + 1; | |
304 | |
305 cache->assoc = ((ebx >> 22) & 0x03ff) + 1; | |
306 cache->line = (ebx & 0x0fff) + 1; | |
307 | |
308 cache->sizekb = (cache->assoc * part | |
309 * cache->line * sets) / 1024; | |
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310 } |
0 | 311 } |
312 default: | |
313 break; | |
314 } | |
315 } | |
316 } | |
317 | |
318 /* Returns the description of caches for an Intel processor. */ | |
319 | |
320 static const char * | |
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321 detect_caches_intel (bool xeon_mp, unsigned max_level, |
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322 unsigned max_ext_level, unsigned *l2sizekb) |
0 | 323 { |
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324 struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0}; |
0 | 325 |
326 if (max_level >= 4) | |
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327 detect_caches_cpuid4 (&level1, &level2, &level3); |
0 | 328 else if (max_level >= 2) |
329 detect_caches_cpuid2 (xeon_mp, &level1, &level2); | |
330 else | |
331 return ""; | |
332 | |
333 if (level1.sizekb == 0) | |
334 return ""; | |
335 | |
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336 /* Let the L3 replace the L2. This assumes inclusive caches |
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337 and single threaded program for now. */ |
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338 if (level3.sizekb) |
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339 level2 = level3; |
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340 |
0 | 341 /* Intel CPUs are equipped with AMD style L2 cache info. Try this |
342 method if other methods fail to provide L2 cache parameters. */ | |
343 if (level2.sizekb == 0 && max_ext_level >= 0x80000006) | |
344 detect_l2_cache (&level2); | |
345 | |
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346 *l2sizekb = level2.sizekb; |
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347 |
0 | 348 return describe_cache (level1, level2); |
349 } | |
350 | |
351 enum vendor_signatures | |
352 { | |
353 SIG_INTEL = 0x756e6547 /* Genu */, | |
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354 SIG_AMD = 0x68747541 /* Auth */ |
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355 }; |
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356 |
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357 enum processor_signatures |
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358 { |
0 | 359 SIG_GEODE = 0x646f6547 /* Geod */ |
360 }; | |
361 | |
362 /* This will be called by the spec parser in gcc.c when it sees | |
363 a %:local_cpu_detect(args) construct. Currently it will be called | |
364 with either "arch" or "tune" as argument depending on if -march=native | |
365 or -mtune=native is to be substituted. | |
366 | |
367 It returns a string containing new command line parameters to be | |
368 put at the place of the above two options, depending on what CPU | |
369 this is executed. E.g. "-march=k8" on an AMD64 machine | |
370 for -march=native. | |
371 | |
372 ARGC and ARGV are set depending on the actual arguments given | |
373 in the spec. */ | |
374 | |
375 const char *host_detect_local_cpu (int argc, const char **argv) | |
376 { | |
377 enum processor_type processor = PROCESSOR_I386; | |
378 const char *cpu = "i386"; | |
379 | |
380 const char *cache = ""; | |
381 const char *options = ""; | |
382 | |
383 unsigned int eax, ebx, ecx, edx; | |
384 | |
385 unsigned int max_level, ext_level; | |
386 | |
387 unsigned int vendor; | |
388 unsigned int model, family; | |
389 | |
390 unsigned int has_sse3, has_ssse3, has_cmpxchg16b; | |
391 unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2; | |
392 | |
393 /* Extended features */ | |
394 unsigned int has_lahf_lm = 0, has_sse4a = 0; | |
395 unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0; | |
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396 unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0; |
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397 unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0; |
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398 unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0; |
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399 unsigned int has_fma4 = 0, has_xop = 0; |
0 | 400 |
401 bool arch; | |
402 | |
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403 unsigned int l2sizekb = 0; |
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404 |
0 | 405 if (argc < 1) |
406 return NULL; | |
407 | |
408 arch = !strcmp (argv[0], "arch"); | |
409 | |
410 if (!arch && strcmp (argv[0], "tune")) | |
411 return NULL; | |
412 | |
413 max_level = __get_cpuid_max (0, &vendor); | |
414 if (max_level < 1) | |
415 goto done; | |
416 | |
417 __cpuid (1, eax, ebx, ecx, edx); | |
418 | |
419 model = (eax >> 4) & 0x0f; | |
420 family = (eax >> 8) & 0x0f; | |
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421 if (vendor == SIG_INTEL) |
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422 { |
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423 unsigned int extended_model, extended_family; |
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|
424 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
425 extended_model = (eax >> 12) & 0xf0; |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
426 extended_family = (eax >> 20) & 0xff; |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
427 if (family == 0x0f) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
428 { |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
429 family += extended_family; |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
430 model += extended_model; |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
431 } |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
432 else if (family == 0x06) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
433 model += extended_model; |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
434 } |
0 | 435 |
436 has_sse3 = ecx & bit_SSE3; | |
437 has_ssse3 = ecx & bit_SSSE3; | |
19
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
438 has_sse4_1 = ecx & bit_SSE4_1; |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
439 has_sse4_2 = ecx & bit_SSE4_2; |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
440 has_avx = ecx & bit_AVX; |
0 | 441 has_cmpxchg16b = ecx & bit_CMPXCHG16B; |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
442 has_movbe = ecx & bit_MOVBE; |
19
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
443 has_popcnt = ecx & bit_POPCNT; |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
444 has_aes = ecx & bit_AES; |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
445 has_pclmul = ecx & bit_PCLMUL; |
0 | 446 |
447 has_cmpxchg8b = edx & bit_CMPXCHG8B; | |
448 has_cmov = edx & bit_CMOV; | |
449 has_mmx = edx & bit_MMX; | |
450 has_sse = edx & bit_SSE; | |
451 has_sse2 = edx & bit_SSE2; | |
452 | |
453 /* Check cpuid level of extended features. */ | |
454 __cpuid (0x80000000, ext_level, ebx, ecx, edx); | |
455 | |
456 if (ext_level > 0x80000000) | |
457 { | |
458 __cpuid (0x80000001, eax, ebx, ecx, edx); | |
459 | |
460 has_lahf_lm = ecx & bit_LAHF_LM; | |
461 has_sse4a = ecx & bit_SSE4a; | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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diff
changeset
|
462 has_abm = ecx & bit_ABM; |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
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diff
changeset
|
463 has_lwp = ecx & bit_LWP; |
63
b7f97abdc517
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55
diff
changeset
|
464 has_fma4 = ecx & bit_FMA4; |
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update gcc from gcc-4.5.0 to gcc-4.6
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55
diff
changeset
|
465 has_xop = ecx & bit_XOP; |
0 | 466 |
467 has_longmode = edx & bit_LM; | |
468 has_3dnowp = edx & bit_3DNOWP; | |
469 has_3dnow = edx & bit_3DNOW; | |
470 } | |
471 | |
472 if (!arch) | |
473 { | |
474 if (vendor == SIG_AMD) | |
475 cache = detect_caches_amd (ext_level); | |
476 else if (vendor == SIG_INTEL) | |
477 { | |
478 bool xeon_mp = (family == 15 && model == 6); | |
63
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update gcc from gcc-4.5.0 to gcc-4.6
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parents:
55
diff
changeset
|
479 cache = detect_caches_intel (xeon_mp, max_level, |
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parents:
55
diff
changeset
|
480 ext_level, &l2sizekb); |
0 | 481 } |
482 } | |
483 | |
484 if (vendor == SIG_AMD) | |
485 { | |
19
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
486 unsigned int name; |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
487 |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
488 /* Detect geode processor by its processor signature. */ |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
489 if (ext_level > 0x80000001) |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
490 __cpuid (0x80000002, name, ebx, ecx, edx); |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
491 else |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
492 name = 0; |
0 | 493 |
19
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
494 if (name == SIG_GEODE) |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
495 processor = PROCESSOR_GEODE; |
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
496 else if (has_xop) |
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update gcc from gcc-4.5.0 to gcc-4.6
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parents:
55
diff
changeset
|
497 processor = PROCESSOR_BDVER1; |
19
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
498 else if (has_sse4a) |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
499 processor = PROCESSOR_AMDFAM10; |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
500 else if (has_sse2 || has_longmode) |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
501 processor = PROCESSOR_K8; |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
502 else if (has_3dnowp) |
0 | 503 processor = PROCESSOR_ATHLON; |
19
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
504 else if (has_mmx) |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
505 processor = PROCESSOR_K6; |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
506 else |
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
507 processor = PROCESSOR_PENTIUM; |
0 | 508 } |
509 else | |
510 { | |
511 switch (family) | |
512 { | |
513 case 4: | |
514 processor = PROCESSOR_I486; | |
515 break; | |
516 case 5: | |
517 processor = PROCESSOR_PENTIUM; | |
518 break; | |
519 case 6: | |
520 processor = PROCESSOR_PENTIUMPRO; | |
521 break; | |
522 case 15: | |
523 processor = PROCESSOR_PENTIUM4; | |
524 break; | |
525 default: | |
526 /* We have no idea. */ | |
527 processor = PROCESSOR_GENERIC32; | |
528 } | |
529 } | |
530 | |
531 switch (processor) | |
532 { | |
533 case PROCESSOR_I386: | |
534 /* Default. */ | |
535 break; | |
536 case PROCESSOR_I486: | |
537 cpu = "i486"; | |
538 break; | |
539 case PROCESSOR_PENTIUM: | |
540 if (arch && has_mmx) | |
541 cpu = "pentium-mmx"; | |
542 else | |
543 cpu = "pentium"; | |
544 break; | |
545 case PROCESSOR_PENTIUMPRO: | |
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
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parents:
55
diff
changeset
|
546 switch (model) |
0 | 547 { |
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
548 case 0x1c: |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
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parents:
55
diff
changeset
|
549 case 0x26: |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
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parents:
55
diff
changeset
|
550 /* Atom. */ |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
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parents:
55
diff
changeset
|
551 cpu = "atom"; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
552 break; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
553 case 0x1a: |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
554 case 0x1e: |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
555 case 0x1f: |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
556 case 0x2e: |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
557 /* FIXME: Optimize for Nehalem. */ |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
558 cpu = "core2"; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
559 break; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
560 case 0x25: |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
561 case 0x2f: |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
562 /* FIXME: Optimize for Westmere. */ |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
563 cpu = "core2"; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
564 break; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
565 case 0x17: |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
566 case 0x1d: |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
567 /* Penryn. FIXME: -mtune=core2 is slower than -mtune=generic */ |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
568 cpu = "core2"; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
569 break; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
570 case 0x0f: |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
571 /* Merom. FIXME: -mtune=core2 is slower than -mtune=generic */ |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
572 cpu = "core2"; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
573 break; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
574 default: |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
575 if (arch) |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
576 { |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
577 if (has_ssse3) |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
578 /* If it is an unknown CPU with SSSE3, assume Core 2. */ |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
579 cpu = "core2"; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
580 else if (has_sse3) |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
581 /* It is Core Duo. */ |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
582 cpu = "pentium-m"; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
583 else if (has_sse2) |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
584 /* It is Pentium M. */ |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
585 cpu = "pentium-m"; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
586 else if (has_sse) |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
587 /* It is Pentium III. */ |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
588 cpu = "pentium3"; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
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parents:
55
diff
changeset
|
589 else if (has_mmx) |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
590 /* It is Pentium II. */ |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
591 cpu = "pentium2"; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
592 else |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
593 /* Default to Pentium Pro. */ |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
594 cpu = "pentiumpro"; |
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
595 } |
0 | 596 else |
63
b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
597 /* For -mtune, we default to -mtune=generic. */ |
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598 cpu = "generic"; |
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599 break; |
0 | 600 } |
601 break; | |
602 case PROCESSOR_PENTIUM4: | |
603 if (has_sse3) | |
604 { | |
605 if (has_longmode) | |
606 cpu = "nocona"; | |
607 else | |
608 cpu = "prescott"; | |
609 } | |
610 else | |
611 cpu = "pentium4"; | |
612 break; | |
613 case PROCESSOR_GEODE: | |
614 cpu = "geode"; | |
615 break; | |
616 case PROCESSOR_K6: | |
617 if (arch && has_3dnow) | |
618 cpu = "k6-3"; | |
619 else | |
620 cpu = "k6"; | |
621 break; | |
622 case PROCESSOR_ATHLON: | |
623 if (arch && has_sse) | |
624 cpu = "athlon-4"; | |
625 else | |
626 cpu = "athlon"; | |
627 break; | |
628 case PROCESSOR_K8: | |
629 if (arch && has_sse3) | |
630 cpu = "k8-sse3"; | |
631 else | |
632 cpu = "k8"; | |
633 break; | |
634 case PROCESSOR_AMDFAM10: | |
635 cpu = "amdfam10"; | |
636 break; | |
63
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637 case PROCESSOR_BDVER1: |
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638 cpu = "bdver1"; |
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639 break; |
0 | 640 |
641 default: | |
642 /* Use something reasonable. */ | |
643 if (arch) | |
644 { | |
645 if (has_ssse3) | |
646 cpu = "core2"; | |
647 else if (has_sse3) | |
648 { | |
649 if (has_longmode) | |
650 cpu = "nocona"; | |
651 else | |
652 cpu = "prescott"; | |
653 } | |
654 else if (has_sse2) | |
655 cpu = "pentium4"; | |
656 else if (has_cmov) | |
657 cpu = "pentiumpro"; | |
658 else if (has_mmx) | |
659 cpu = "pentium-mmx"; | |
660 else if (has_cmpxchg8b) | |
661 cpu = "pentium"; | |
662 } | |
663 else | |
664 cpu = "generic"; | |
665 } | |
666 | |
667 if (arch) | |
668 { | |
669 if (has_cmpxchg16b) | |
55
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670 options = concat (options, " -mcx16", NULL); |
0 | 671 if (has_lahf_lm) |
55
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672 options = concat (options, " -msahf", NULL); |
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673 if (has_movbe) |
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674 options = concat (options, " -mmovbe", NULL); |
19
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675 if (has_aes) |
55
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676 options = concat (options, " -maes", NULL); |
19
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677 if (has_pclmul) |
55
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678 options = concat (options, " -mpclmul", NULL); |
19
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679 if (has_popcnt) |
55
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680 options = concat (options, " -mpopcnt", NULL); |
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681 if (has_abm) |
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682 options = concat (options, " -mabm", NULL); |
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683 if (has_lwp) |
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684 options = concat (options, " -mlwp", NULL); |
63
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685 if (has_fma4) |
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686 options = concat (options, " -mfma4", NULL); |
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687 if (has_xop) |
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688 options = concat (options, " -mxop", NULL); |
55
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689 |
19
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690 if (has_avx) |
55
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691 options = concat (options, " -mavx", NULL); |
19
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692 else if (has_sse4_2) |
55
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693 options = concat (options, " -msse4.2", NULL); |
19
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694 else if (has_sse4_1) |
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695 options = concat (options, " -msse4.1", NULL); |
0 | 696 } |
697 | |
698 done: | |
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699 return concat (cache, "-m", argv[0], "=", cpu, options, NULL); |
0 | 700 } |
701 #else | |
702 | |
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703 /* If we aren't compiling with GCC then the driver will just ignore |
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704 -march and -mtune "native" target and will leave to the newly |
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705 built compiler to generate code for its default target. */ |
0 | 706 |
55
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707 const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED, |
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708 const char **argv ATTRIBUTE_UNUSED) |
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709 { |
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710 return NULL; |
0 | 711 } |
712 #endif /* __GNUC__ */ |