Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/mcore/mcore.c @ 63:b7f97abdc517 gcc-4.6-20100522
update gcc from gcc-4.5.0 to gcc-4.6
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Mon, 24 May 2010 12:47:05 +0900 |
| parents | 77e2b8dfacca |
| children | f6334be47118 |
| rev | line source |
|---|---|
| 0 | 1 /* Output routines for Motorola MCore processor |
|
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2 Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, |
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3 2009 Free Software Foundation, Inc. |
| 0 | 4 |
| 5 This file is part of GCC. | |
| 6 | |
| 7 GCC is free software; you can redistribute it and/or modify it | |
| 8 under the terms of the GNU General Public License as published | |
| 9 by the Free Software Foundation; either version 3, or (at your | |
| 10 option) any later version. | |
| 11 | |
| 12 GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 15 License for more details. | |
| 16 | |
| 17 You should have received a copy of the GNU General Public License | |
| 18 along with GCC; see the file COPYING3. If not see | |
| 19 <http://www.gnu.org/licenses/>. */ | |
| 20 | |
| 21 #include "config.h" | |
| 22 #include "system.h" | |
| 23 #include "coretypes.h" | |
| 24 #include "tm.h" | |
| 25 #include "rtl.h" | |
| 26 #include "tree.h" | |
| 27 #include "tm_p.h" | |
| 28 #include "assert.h" | |
| 29 #include "mcore.h" | |
| 30 #include "regs.h" | |
| 31 #include "hard-reg-set.h" | |
| 32 #include "insn-config.h" | |
| 33 #include "conditions.h" | |
| 34 #include "output.h" | |
| 35 #include "insn-attr.h" | |
| 36 #include "flags.h" | |
| 37 #include "obstack.h" | |
| 38 #include "expr.h" | |
| 39 #include "reload.h" | |
| 40 #include "recog.h" | |
| 41 #include "function.h" | |
| 42 #include "ggc.h" | |
| 43 #include "toplev.h" | |
| 44 #include "target.h" | |
| 45 #include "target-def.h" | |
| 46 #include "df.h" | |
| 47 | |
| 48 /* Maximum size we are allowed to grow the stack in a single operation. | |
| 49 If we want more, we must do it in increments of at most this size. | |
| 50 If this value is 0, we don't check at all. */ | |
| 51 int mcore_stack_increment = STACK_UNITS_MAXSTEP; | |
| 52 | |
| 53 /* For dumping information about frame sizes. */ | |
| 54 char * mcore_current_function_name = 0; | |
| 55 long mcore_current_compilation_timestamp = 0; | |
| 56 | |
| 57 /* Global variables for machine-dependent things. */ | |
| 58 | |
| 59 /* Provides the class number of the smallest class containing | |
| 60 reg number. */ | |
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61 const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] = |
| 0 | 62 { |
| 63 GENERAL_REGS, ONLYR1_REGS, LRW_REGS, LRW_REGS, | |
| 64 LRW_REGS, LRW_REGS, LRW_REGS, LRW_REGS, | |
| 65 LRW_REGS, LRW_REGS, LRW_REGS, LRW_REGS, | |
| 66 LRW_REGS, LRW_REGS, LRW_REGS, GENERAL_REGS, | |
| 67 GENERAL_REGS, C_REGS, NO_REGS, NO_REGS, | |
| 68 }; | |
| 69 | |
| 70 /* Provide reg_class from a letter such as appears in the machine | |
| 71 description. */ | |
| 72 const enum reg_class reg_class_from_letter[] = | |
| 73 { | |
| 74 /* a */ LRW_REGS, /* b */ ONLYR1_REGS, /* c */ C_REGS, /* d */ NO_REGS, | |
| 75 /* e */ NO_REGS, /* f */ NO_REGS, /* g */ NO_REGS, /* h */ NO_REGS, | |
| 76 /* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ NO_REGS, | |
| 77 /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS, | |
| 78 /* q */ NO_REGS, /* r */ GENERAL_REGS, /* s */ NO_REGS, /* t */ NO_REGS, | |
| 79 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ NO_REGS, /* x */ ALL_REGS, | |
| 80 /* y */ NO_REGS, /* z */ NO_REGS | |
| 81 }; | |
| 82 | |
| 83 struct mcore_frame | |
| 84 { | |
| 85 int arg_size; /* Stdarg spills (bytes). */ | |
| 86 int reg_size; /* Non-volatile reg saves (bytes). */ | |
| 87 int reg_mask; /* Non-volatile reg saves. */ | |
| 88 int local_size; /* Locals. */ | |
| 89 int outbound_size; /* Arg overflow on calls out. */ | |
| 90 int pad_outbound; | |
| 91 int pad_local; | |
| 92 int pad_reg; | |
| 93 /* Describe the steps we'll use to grow it. */ | |
| 94 #define MAX_STACK_GROWS 4 /* Gives us some spare space. */ | |
| 95 int growth[MAX_STACK_GROWS]; | |
| 96 int arg_offset; | |
| 97 int reg_offset; | |
| 98 int reg_growth; | |
| 99 int local_growth; | |
| 100 }; | |
| 101 | |
| 102 typedef enum | |
| 103 { | |
| 104 COND_NO, | |
| 105 COND_MOV_INSN, | |
| 106 COND_CLR_INSN, | |
| 107 COND_INC_INSN, | |
| 108 COND_DEC_INSN, | |
| 109 COND_BRANCH_INSN | |
| 110 } | |
| 111 cond_type; | |
| 112 | |
| 113 static void output_stack_adjust (int, int); | |
| 114 static int calc_live_regs (int *); | |
| 115 static int try_constant_tricks (long, HOST_WIDE_INT *, HOST_WIDE_INT *); | |
| 116 static const char * output_inline_const (enum machine_mode, rtx *); | |
| 117 static void layout_mcore_frame (struct mcore_frame *); | |
| 118 static void mcore_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int); | |
| 119 static cond_type is_cond_candidate (rtx); | |
| 120 static rtx emit_new_cond_insn (rtx, int); | |
| 121 static rtx conditionalize_block (rtx); | |
| 122 static void conditionalize_optimization (void); | |
| 123 static void mcore_reorg (void); | |
| 124 static rtx handle_structs_in_regs (enum machine_mode, const_tree, int); | |
| 125 static void mcore_mark_dllexport (tree); | |
| 126 static void mcore_mark_dllimport (tree); | |
| 127 static int mcore_dllexport_p (tree); | |
| 128 static int mcore_dllimport_p (tree); | |
| 129 static tree mcore_handle_naked_attribute (tree *, tree, tree, int, bool *); | |
| 130 #ifdef OBJECT_FORMAT_ELF | |
| 131 static void mcore_asm_named_section (const char *, | |
| 132 unsigned int, tree); | |
| 133 #endif | |
| 134 static void mcore_unique_section (tree, int); | |
| 135 static void mcore_encode_section_info (tree, rtx, int); | |
| 136 static const char *mcore_strip_name_encoding (const char *); | |
| 137 static int mcore_const_costs (rtx, RTX_CODE); | |
| 138 static int mcore_and_cost (rtx); | |
| 139 static int mcore_ior_cost (rtx); | |
| 140 static bool mcore_rtx_costs (rtx, int, int, int *, bool); | |
| 141 static void mcore_external_libcall (rtx); | |
| 142 static bool mcore_return_in_memory (const_tree, const_tree); | |
| 143 static int mcore_arg_partial_bytes (CUMULATIVE_ARGS *, | |
| 144 enum machine_mode, | |
| 145 tree, bool); | |
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146 static void mcore_asm_trampoline_template (FILE *); |
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147 static void mcore_trampoline_init (rtx, tree, rtx); |
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148 |
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149 /* MCore specific attributes. */ |
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150 |
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151 static const struct attribute_spec mcore_attribute_table[] = |
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152 { |
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153 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
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154 { "dllexport", 0, 0, true, false, false, NULL }, |
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155 { "dllimport", 0, 0, true, false, false, NULL }, |
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156 { "naked", 0, 0, true, false, false, mcore_handle_naked_attribute }, |
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157 { NULL, 0, 0, false, false, false, NULL } |
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158 }; |
| 0 | 159 |
| 160 /* Initialize the GCC target structure. */ | |
| 161 #undef TARGET_ASM_EXTERNAL_LIBCALL | |
| 162 #define TARGET_ASM_EXTERNAL_LIBCALL mcore_external_libcall | |
| 163 | |
| 164 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES | |
| 165 #undef TARGET_MERGE_DECL_ATTRIBUTES | |
| 166 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes | |
| 167 #endif | |
| 168 | |
| 169 #ifdef OBJECT_FORMAT_ELF | |
| 170 #undef TARGET_ASM_UNALIGNED_HI_OP | |
| 171 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" | |
| 172 #undef TARGET_ASM_UNALIGNED_SI_OP | |
| 173 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t" | |
| 174 #endif | |
| 175 | |
| 176 #undef TARGET_ATTRIBUTE_TABLE | |
| 177 #define TARGET_ATTRIBUTE_TABLE mcore_attribute_table | |
| 178 #undef TARGET_ASM_UNIQUE_SECTION | |
| 179 #define TARGET_ASM_UNIQUE_SECTION mcore_unique_section | |
| 180 #undef TARGET_ASM_FUNCTION_RODATA_SECTION | |
| 181 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section | |
| 182 #undef TARGET_DEFAULT_TARGET_FLAGS | |
| 183 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT | |
| 184 #undef TARGET_ENCODE_SECTION_INFO | |
| 185 #define TARGET_ENCODE_SECTION_INFO mcore_encode_section_info | |
| 186 #undef TARGET_STRIP_NAME_ENCODING | |
| 187 #define TARGET_STRIP_NAME_ENCODING mcore_strip_name_encoding | |
| 188 #undef TARGET_RTX_COSTS | |
| 189 #define TARGET_RTX_COSTS mcore_rtx_costs | |
| 190 #undef TARGET_ADDRESS_COST | |
| 191 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0 | |
| 192 #undef TARGET_MACHINE_DEPENDENT_REORG | |
| 193 #define TARGET_MACHINE_DEPENDENT_REORG mcore_reorg | |
| 194 | |
|
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195 #undef TARGET_PROMOTE_FUNCTION_MODE |
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196 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote |
| 0 | 197 #undef TARGET_PROMOTE_PROTOTYPES |
| 198 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true | |
| 199 | |
| 200 #undef TARGET_RETURN_IN_MEMORY | |
| 201 #define TARGET_RETURN_IN_MEMORY mcore_return_in_memory | |
| 202 #undef TARGET_MUST_PASS_IN_STACK | |
| 203 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
| 204 #undef TARGET_PASS_BY_REFERENCE | |
| 205 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack | |
| 206 #undef TARGET_ARG_PARTIAL_BYTES | |
| 207 #define TARGET_ARG_PARTIAL_BYTES mcore_arg_partial_bytes | |
| 208 | |
| 209 #undef TARGET_SETUP_INCOMING_VARARGS | |
| 210 #define TARGET_SETUP_INCOMING_VARARGS mcore_setup_incoming_varargs | |
| 211 | |
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212 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
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213 #define TARGET_ASM_TRAMPOLINE_TEMPLATE mcore_asm_trampoline_template |
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214 #undef TARGET_TRAMPOLINE_INIT |
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215 #define TARGET_TRAMPOLINE_INIT mcore_trampoline_init |
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216 |
| 0 | 217 struct gcc_target targetm = TARGET_INITIALIZER; |
| 218 | |
| 219 /* Adjust the stack and return the number of bytes taken to do it. */ | |
| 220 static void | |
| 221 output_stack_adjust (int direction, int size) | |
| 222 { | |
| 223 /* If extending stack a lot, we do it incrementally. */ | |
| 224 if (direction < 0 && size > mcore_stack_increment && mcore_stack_increment > 0) | |
| 225 { | |
| 226 rtx tmp = gen_rtx_REG (SImode, 1); | |
| 227 rtx memref; | |
| 228 | |
| 229 emit_insn (gen_movsi (tmp, GEN_INT (mcore_stack_increment))); | |
| 230 do | |
| 231 { | |
| 232 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp)); | |
| 233 memref = gen_rtx_MEM (SImode, stack_pointer_rtx); | |
| 234 MEM_VOLATILE_P (memref) = 1; | |
| 235 emit_insn (gen_movsi (memref, stack_pointer_rtx)); | |
| 236 size -= mcore_stack_increment; | |
| 237 } | |
| 238 while (size > mcore_stack_increment); | |
| 239 | |
| 240 /* SIZE is now the residual for the last adjustment, | |
| 241 which doesn't require a probe. */ | |
| 242 } | |
| 243 | |
| 244 if (size) | |
| 245 { | |
| 246 rtx insn; | |
| 247 rtx val = GEN_INT (size); | |
| 248 | |
| 249 if (size > 32) | |
| 250 { | |
| 251 rtx nval = gen_rtx_REG (SImode, 1); | |
| 252 emit_insn (gen_movsi (nval, val)); | |
| 253 val = nval; | |
| 254 } | |
| 255 | |
| 256 if (direction > 0) | |
| 257 insn = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, val); | |
| 258 else | |
| 259 insn = gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, val); | |
| 260 | |
| 261 emit_insn (insn); | |
| 262 } | |
| 263 } | |
| 264 | |
| 265 /* Work out the registers which need to be saved, | |
| 266 both as a mask and a count. */ | |
| 267 | |
| 268 static int | |
| 269 calc_live_regs (int * count) | |
| 270 { | |
| 271 int reg; | |
| 272 int live_regs_mask = 0; | |
| 273 | |
| 274 * count = 0; | |
| 275 | |
| 276 for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++) | |
| 277 { | |
| 278 if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) | |
| 279 { | |
| 280 (*count)++; | |
| 281 live_regs_mask |= (1 << reg); | |
| 282 } | |
| 283 } | |
| 284 | |
| 285 return live_regs_mask; | |
| 286 } | |
| 287 | |
| 288 /* Print the operand address in x to the stream. */ | |
| 289 | |
| 290 void | |
| 291 mcore_print_operand_address (FILE * stream, rtx x) | |
| 292 { | |
| 293 switch (GET_CODE (x)) | |
| 294 { | |
| 295 case REG: | |
| 296 fprintf (stream, "(%s)", reg_names[REGNO (x)]); | |
| 297 break; | |
| 298 | |
| 299 case PLUS: | |
| 300 { | |
| 301 rtx base = XEXP (x, 0); | |
| 302 rtx index = XEXP (x, 1); | |
| 303 | |
| 304 if (GET_CODE (base) != REG) | |
| 305 { | |
| 306 /* Ensure that BASE is a register (one of them must be). */ | |
| 307 rtx temp = base; | |
| 308 base = index; | |
| 309 index = temp; | |
| 310 } | |
| 311 | |
| 312 switch (GET_CODE (index)) | |
| 313 { | |
| 314 case CONST_INT: | |
| 315 fprintf (stream, "(%s," HOST_WIDE_INT_PRINT_DEC ")", | |
| 316 reg_names[REGNO(base)], INTVAL (index)); | |
| 317 break; | |
| 318 | |
| 319 default: | |
| 320 gcc_unreachable (); | |
| 321 } | |
| 322 } | |
| 323 | |
| 324 break; | |
| 325 | |
| 326 default: | |
| 327 output_addr_const (stream, x); | |
| 328 break; | |
| 329 } | |
| 330 } | |
| 331 | |
| 332 /* Print operand x (an rtx) in assembler syntax to file stream | |
| 333 according to modifier code. | |
| 334 | |
| 335 'R' print the next register or memory location along, i.e. the lsw in | |
| 336 a double word value | |
| 337 'O' print a constant without the # | |
| 338 'M' print a constant as its negative | |
| 339 'P' print log2 of a power of two | |
| 340 'Q' print log2 of an inverse of a power of two | |
| 341 'U' print register for ldm/stm instruction | |
| 342 'X' print byte number for xtrbN instruction. */ | |
| 343 | |
| 344 void | |
| 345 mcore_print_operand (FILE * stream, rtx x, int code) | |
| 346 { | |
| 347 switch (code) | |
| 348 { | |
| 349 case 'N': | |
| 350 if (INTVAL(x) == -1) | |
| 351 fprintf (asm_out_file, "32"); | |
| 352 else | |
| 353 fprintf (asm_out_file, "%d", exact_log2 (INTVAL (x) + 1)); | |
| 354 break; | |
| 355 case 'P': | |
| 356 fprintf (asm_out_file, "%d", exact_log2 (INTVAL (x) & 0xffffffff)); | |
| 357 break; | |
| 358 case 'Q': | |
| 359 fprintf (asm_out_file, "%d", exact_log2 (~INTVAL (x))); | |
| 360 break; | |
| 361 case 'O': | |
| 362 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); | |
| 363 break; | |
| 364 case 'M': | |
| 365 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, - INTVAL (x)); | |
| 366 break; | |
| 367 case 'R': | |
| 368 /* Next location along in memory or register. */ | |
| 369 switch (GET_CODE (x)) | |
| 370 { | |
| 371 case REG: | |
| 372 fputs (reg_names[REGNO (x) + 1], (stream)); | |
| 373 break; | |
| 374 case MEM: | |
| 375 mcore_print_operand_address | |
| 376 (stream, XEXP (adjust_address (x, SImode, 4), 0)); | |
| 377 break; | |
| 378 default: | |
| 379 gcc_unreachable (); | |
| 380 } | |
| 381 break; | |
| 382 case 'U': | |
| 383 fprintf (asm_out_file, "%s-%s", reg_names[REGNO (x)], | |
| 384 reg_names[REGNO (x) + 3]); | |
| 385 break; | |
| 386 case 'x': | |
| 387 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); | |
| 388 break; | |
| 389 case 'X': | |
| 390 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, 3 - INTVAL (x) / 8); | |
| 391 break; | |
| 392 | |
| 393 default: | |
| 394 switch (GET_CODE (x)) | |
| 395 { | |
| 396 case REG: | |
| 397 fputs (reg_names[REGNO (x)], (stream)); | |
| 398 break; | |
| 399 case MEM: | |
| 400 output_address (XEXP (x, 0)); | |
| 401 break; | |
| 402 default: | |
| 403 output_addr_const (stream, x); | |
| 404 break; | |
| 405 } | |
| 406 break; | |
| 407 } | |
| 408 } | |
| 409 | |
| 410 /* What does a constant cost ? */ | |
| 411 | |
| 412 static int | |
| 413 mcore_const_costs (rtx exp, enum rtx_code code) | |
| 414 { | |
| 415 HOST_WIDE_INT val = INTVAL (exp); | |
| 416 | |
| 417 /* Easy constants. */ | |
| 418 if ( CONST_OK_FOR_I (val) | |
| 419 || CONST_OK_FOR_M (val) | |
| 420 || CONST_OK_FOR_N (val) | |
| 421 || (code == PLUS && CONST_OK_FOR_L (val))) | |
| 422 return 1; | |
| 423 else if (code == AND | |
| 424 && ( CONST_OK_FOR_M (~val) | |
| 425 || CONST_OK_FOR_N (~val))) | |
| 426 return 2; | |
| 427 else if (code == PLUS | |
| 428 && ( CONST_OK_FOR_I (-val) | |
| 429 || CONST_OK_FOR_M (-val) | |
| 430 || CONST_OK_FOR_N (-val))) | |
| 431 return 2; | |
| 432 | |
| 433 return 5; | |
| 434 } | |
| 435 | |
| 436 /* What does an and instruction cost - we do this b/c immediates may | |
| 437 have been relaxed. We want to ensure that cse will cse relaxed immeds | |
| 438 out. Otherwise we'll get bad code (multiple reloads of the same const). */ | |
| 439 | |
| 440 static int | |
| 441 mcore_and_cost (rtx x) | |
| 442 { | |
| 443 HOST_WIDE_INT val; | |
| 444 | |
| 445 if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
| 446 return 2; | |
| 447 | |
| 448 val = INTVAL (XEXP (x, 1)); | |
| 449 | |
| 450 /* Do it directly. */ | |
| 451 if (CONST_OK_FOR_K (val) || CONST_OK_FOR_M (~val)) | |
| 452 return 2; | |
| 453 /* Takes one instruction to load. */ | |
| 454 else if (const_ok_for_mcore (val)) | |
| 455 return 3; | |
| 456 /* Takes two instructions to load. */ | |
| 457 else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val)) | |
| 458 return 4; | |
| 459 | |
| 460 /* Takes a lrw to load. */ | |
| 461 return 5; | |
| 462 } | |
| 463 | |
| 464 /* What does an or cost - see and_cost(). */ | |
| 465 | |
| 466 static int | |
| 467 mcore_ior_cost (rtx x) | |
| 468 { | |
| 469 HOST_WIDE_INT val; | |
| 470 | |
| 471 if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
| 472 return 2; | |
| 473 | |
| 474 val = INTVAL (XEXP (x, 1)); | |
| 475 | |
| 476 /* Do it directly with bclri. */ | |
| 477 if (CONST_OK_FOR_M (val)) | |
| 478 return 2; | |
| 479 /* Takes one instruction to load. */ | |
| 480 else if (const_ok_for_mcore (val)) | |
| 481 return 3; | |
| 482 /* Takes two instructions to load. */ | |
| 483 else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val)) | |
| 484 return 4; | |
| 485 | |
| 486 /* Takes a lrw to load. */ | |
| 487 return 5; | |
| 488 } | |
| 489 | |
| 490 static bool | |
| 491 mcore_rtx_costs (rtx x, int code, int outer_code, int * total, | |
| 492 bool speed ATTRIBUTE_UNUSED) | |
| 493 { | |
| 494 switch (code) | |
| 495 { | |
| 496 case CONST_INT: | |
|
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497 *total = mcore_const_costs (x, (enum rtx_code) outer_code); |
| 0 | 498 return true; |
| 499 case CONST: | |
| 500 case LABEL_REF: | |
| 501 case SYMBOL_REF: | |
| 502 *total = 5; | |
| 503 return true; | |
| 504 case CONST_DOUBLE: | |
| 505 *total = 10; | |
| 506 return true; | |
| 507 | |
| 508 case AND: | |
| 509 *total = COSTS_N_INSNS (mcore_and_cost (x)); | |
| 510 return true; | |
| 511 | |
| 512 case IOR: | |
| 513 *total = COSTS_N_INSNS (mcore_ior_cost (x)); | |
| 514 return true; | |
| 515 | |
| 516 case DIV: | |
| 517 case UDIV: | |
| 518 case MOD: | |
| 519 case UMOD: | |
| 520 case FLOAT: | |
| 521 case FIX: | |
| 522 *total = COSTS_N_INSNS (100); | |
| 523 return true; | |
| 524 | |
| 525 default: | |
| 526 return false; | |
| 527 } | |
| 528 } | |
| 529 | |
|
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530 /* Prepare the operands for a comparison. Return whether the branch/setcc |
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531 should reverse the operands. */ |
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532 |
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533 bool |
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534 mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1) |
| 0 | 535 { |
|
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536 rtx cc_reg = gen_rtx_REG (CCmode, CC_REG); |
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537 bool invert; |
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538 |
| 0 | 539 if (GET_CODE (op1) == CONST_INT) |
| 540 { | |
| 541 HOST_WIDE_INT val = INTVAL (op1); | |
| 542 | |
| 543 switch (code) | |
| 544 { | |
|
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545 case GTU: |
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546 /* Unsigned > 0 is the same as != 0; everything else is converted |
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547 below to LEU (reversed cmphs). */ |
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548 if (val == 0) |
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549 code = NE; |
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550 break; |
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551 |
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552 /* Check whether (LE A imm) can become (LT A imm + 1), |
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553 or (GT A imm) can become (GE A imm + 1). */ |
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554 case GT: |
| 0 | 555 case LE: |
| 556 if (CONST_OK_FOR_J (val + 1)) | |
| 557 { | |
|
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558 op1 = GEN_INT (val + 1); |
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559 code = code == LE ? LT : GE; |
| 0 | 560 } |
| 561 break; | |
| 562 | |
| 563 default: | |
| 564 break; | |
| 565 } | |
| 566 } | |
|
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567 |
| 0 | 568 if (CONSTANT_P (op1) && GET_CODE (op1) != CONST_INT) |
| 569 op1 = force_reg (SImode, op1); | |
| 570 | |
| 571 /* cmpnei: 0-31 (K immediate) | |
| 572 cmplti: 1-32 (J immediate, 0 using btsti x,31). */ | |
|
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573 invert = false; |
| 0 | 574 switch (code) |
| 575 { | |
| 576 case EQ: /* Use inverted condition, cmpne. */ | |
| 577 code = NE; | |
|
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578 invert = true; |
| 0 | 579 /* Drop through. */ |
| 580 | |
| 581 case NE: /* Use normal condition, cmpne. */ | |
| 582 if (GET_CODE (op1) == CONST_INT && ! CONST_OK_FOR_K (INTVAL (op1))) | |
| 583 op1 = force_reg (SImode, op1); | |
| 584 break; | |
| 585 | |
| 586 case LE: /* Use inverted condition, reversed cmplt. */ | |
| 587 code = GT; | |
|
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588 invert = true; |
| 0 | 589 /* Drop through. */ |
| 590 | |
| 591 case GT: /* Use normal condition, reversed cmplt. */ | |
| 592 if (GET_CODE (op1) == CONST_INT) | |
| 593 op1 = force_reg (SImode, op1); | |
| 594 break; | |
| 595 | |
| 596 case GE: /* Use inverted condition, cmplt. */ | |
| 597 code = LT; | |
|
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598 invert = true; |
| 0 | 599 /* Drop through. */ |
| 600 | |
| 601 case LT: /* Use normal condition, cmplt. */ | |
| 602 if (GET_CODE (op1) == CONST_INT && | |
| 603 /* covered by btsti x,31. */ | |
| 604 INTVAL (op1) != 0 && | |
| 605 ! CONST_OK_FOR_J (INTVAL (op1))) | |
| 606 op1 = force_reg (SImode, op1); | |
| 607 break; | |
| 608 | |
| 609 case GTU: /* Use inverted condition, cmple. */ | |
|
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610 /* We coped with unsigned > 0 above. */ |
| 0 | 611 gcc_assert (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0); |
| 612 code = LEU; | |
|
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613 invert = true; |
| 0 | 614 /* Drop through. */ |
| 615 | |
| 616 case LEU: /* Use normal condition, reversed cmphs. */ | |
| 617 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0) | |
| 618 op1 = force_reg (SImode, op1); | |
| 619 break; | |
| 620 | |
| 621 case LTU: /* Use inverted condition, cmphs. */ | |
| 622 code = GEU; | |
|
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623 invert = true; |
| 0 | 624 /* Drop through. */ |
| 625 | |
| 626 case GEU: /* Use normal condition, cmphs. */ | |
| 627 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0) | |
| 628 op1 = force_reg (SImode, op1); | |
| 629 break; | |
| 630 | |
| 631 default: | |
| 632 break; | |
| 633 } | |
| 634 | |
|
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635 emit_insn (gen_rtx_SET (VOIDmode, |
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636 cc_reg, |
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637 gen_rtx_fmt_ee (code, CCmode, op0, op1))); |
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638 return invert; |
| 0 | 639 } |
| 640 | |
| 641 int | |
| 642 mcore_symbolic_address_p (rtx x) | |
| 643 { | |
| 644 switch (GET_CODE (x)) | |
| 645 { | |
| 646 case SYMBOL_REF: | |
| 647 case LABEL_REF: | |
| 648 return 1; | |
| 649 case CONST: | |
| 650 x = XEXP (x, 0); | |
| 651 return ( (GET_CODE (XEXP (x, 0)) == SYMBOL_REF | |
| 652 || GET_CODE (XEXP (x, 0)) == LABEL_REF) | |
| 653 && GET_CODE (XEXP (x, 1)) == CONST_INT); | |
| 654 default: | |
| 655 return 0; | |
| 656 } | |
| 657 } | |
| 658 | |
| 659 /* Functions to output assembly code for a function call. */ | |
| 660 | |
| 661 char * | |
| 662 mcore_output_call (rtx operands[], int index) | |
| 663 { | |
| 664 static char buffer[20]; | |
| 665 rtx addr = operands [index]; | |
| 666 | |
| 667 if (REG_P (addr)) | |
| 668 { | |
| 669 if (TARGET_CG_DATA) | |
| 670 { | |
| 671 gcc_assert (mcore_current_function_name); | |
| 672 | |
| 673 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name, | |
| 674 "unknown", 1); | |
| 675 } | |
| 676 | |
| 677 sprintf (buffer, "jsr\t%%%d", index); | |
| 678 } | |
| 679 else | |
| 680 { | |
| 681 if (TARGET_CG_DATA) | |
| 682 { | |
| 683 gcc_assert (mcore_current_function_name); | |
| 684 gcc_assert (GET_CODE (addr) == SYMBOL_REF); | |
| 685 | |
| 686 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name, | |
| 687 XSTR (addr, 0), 0); | |
| 688 } | |
| 689 | |
| 690 sprintf (buffer, "jbsr\t%%%d", index); | |
| 691 } | |
| 692 | |
| 693 return buffer; | |
| 694 } | |
| 695 | |
| 696 /* Can we load a constant with a single instruction ? */ | |
| 697 | |
| 698 int | |
| 699 const_ok_for_mcore (HOST_WIDE_INT value) | |
| 700 { | |
| 701 if (value >= 0 && value <= 127) | |
| 702 return 1; | |
| 703 | |
| 704 /* Try exact power of two. */ | |
| 705 if (CONST_OK_FOR_M (value)) | |
| 706 return 1; | |
| 707 | |
| 708 /* Try exact power of two - 1. */ | |
| 709 if (CONST_OK_FOR_N (value) && value != -1) | |
| 710 return 1; | |
| 711 | |
| 712 return 0; | |
| 713 } | |
| 714 | |
| 715 /* Can we load a constant inline with up to 2 instructions ? */ | |
| 716 | |
| 717 int | |
| 718 mcore_const_ok_for_inline (HOST_WIDE_INT value) | |
| 719 { | |
| 720 HOST_WIDE_INT x, y; | |
| 721 | |
| 722 return try_constant_tricks (value, & x, & y) > 0; | |
| 723 } | |
| 724 | |
| 725 /* Are we loading the constant using a not ? */ | |
| 726 | |
| 727 int | |
| 728 mcore_const_trick_uses_not (HOST_WIDE_INT value) | |
| 729 { | |
| 730 HOST_WIDE_INT x, y; | |
| 731 | |
| 732 return try_constant_tricks (value, & x, & y) == 2; | |
| 733 } | |
| 734 | |
| 735 /* Try tricks to load a constant inline and return the trick number if | |
| 736 success (0 is non-inlinable). | |
| 737 | |
| 738 0: not inlinable | |
| 739 1: single instruction (do the usual thing) | |
| 740 2: single insn followed by a 'not' | |
| 741 3: single insn followed by a subi | |
| 742 4: single insn followed by an addi | |
| 743 5: single insn followed by rsubi | |
| 744 6: single insn followed by bseti | |
| 745 7: single insn followed by bclri | |
| 746 8: single insn followed by rotli | |
| 747 9: single insn followed by lsli | |
| 748 10: single insn followed by ixh | |
| 749 11: single insn followed by ixw. */ | |
| 750 | |
| 751 static int | |
| 752 try_constant_tricks (HOST_WIDE_INT value, HOST_WIDE_INT * x, HOST_WIDE_INT * y) | |
| 753 { | |
| 754 HOST_WIDE_INT i; | |
| 755 unsigned HOST_WIDE_INT bit, shf, rot; | |
| 756 | |
| 757 if (const_ok_for_mcore (value)) | |
| 758 return 1; /* Do the usual thing. */ | |
| 759 | |
| 760 if (! TARGET_HARDLIT) | |
| 761 return 0; | |
| 762 | |
| 763 if (const_ok_for_mcore (~value)) | |
| 764 { | |
| 765 *x = ~value; | |
| 766 return 2; | |
| 767 } | |
| 768 | |
| 769 for (i = 1; i <= 32; i++) | |
| 770 { | |
| 771 if (const_ok_for_mcore (value - i)) | |
| 772 { | |
| 773 *x = value - i; | |
| 774 *y = i; | |
| 775 | |
| 776 return 3; | |
| 777 } | |
| 778 | |
| 779 if (const_ok_for_mcore (value + i)) | |
| 780 { | |
| 781 *x = value + i; | |
| 782 *y = i; | |
| 783 | |
| 784 return 4; | |
| 785 } | |
| 786 } | |
| 787 | |
| 788 bit = 0x80000000ULL; | |
| 789 | |
| 790 for (i = 0; i <= 31; i++) | |
| 791 { | |
| 792 if (const_ok_for_mcore (i - value)) | |
| 793 { | |
| 794 *x = i - value; | |
| 795 *y = i; | |
| 796 | |
| 797 return 5; | |
| 798 } | |
| 799 | |
| 800 if (const_ok_for_mcore (value & ~bit)) | |
| 801 { | |
| 802 *y = bit; | |
| 803 *x = value & ~bit; | |
| 804 return 6; | |
| 805 } | |
| 806 | |
| 807 if (const_ok_for_mcore (value | bit)) | |
| 808 { | |
| 809 *y = ~bit; | |
| 810 *x = value | bit; | |
| 811 | |
| 812 return 7; | |
| 813 } | |
| 814 | |
| 815 bit >>= 1; | |
| 816 } | |
| 817 | |
| 818 shf = value; | |
| 819 rot = value; | |
| 820 | |
| 821 for (i = 1; i < 31; i++) | |
| 822 { | |
| 823 int c; | |
| 824 | |
| 825 /* MCore has rotate left. */ | |
| 826 c = rot << 31; | |
| 827 rot >>= 1; | |
| 828 rot &= 0x7FFFFFFF; | |
| 829 rot |= c; /* Simulate rotate. */ | |
| 830 | |
| 831 if (const_ok_for_mcore (rot)) | |
| 832 { | |
| 833 *y = i; | |
| 834 *x = rot; | |
| 835 | |
| 836 return 8; | |
| 837 } | |
| 838 | |
| 839 if (shf & 1) | |
| 840 shf = 0; /* Can't use logical shift, low order bit is one. */ | |
| 841 | |
| 842 shf >>= 1; | |
| 843 | |
| 844 if (shf != 0 && const_ok_for_mcore (shf)) | |
| 845 { | |
| 846 *y = i; | |
| 847 *x = shf; | |
| 848 | |
| 849 return 9; | |
| 850 } | |
| 851 } | |
| 852 | |
| 853 if ((value % 3) == 0 && const_ok_for_mcore (value / 3)) | |
| 854 { | |
| 855 *x = value / 3; | |
| 856 | |
| 857 return 10; | |
| 858 } | |
| 859 | |
| 860 if ((value % 5) == 0 && const_ok_for_mcore (value / 5)) | |
| 861 { | |
| 862 *x = value / 5; | |
| 863 | |
| 864 return 11; | |
| 865 } | |
| 866 | |
| 867 return 0; | |
| 868 } | |
| 869 | |
| 870 /* Check whether reg is dead at first. This is done by searching ahead | |
| 871 for either the next use (i.e., reg is live), a death note, or a set of | |
| 872 reg. Don't just use dead_or_set_p() since reload does not always mark | |
| 873 deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We | |
| 874 can ignore subregs by extracting the actual register. BRC */ | |
| 875 | |
| 876 int | |
| 877 mcore_is_dead (rtx first, rtx reg) | |
| 878 { | |
| 879 rtx insn; | |
| 880 | |
| 881 /* For mcore, subregs can't live independently of their parent regs. */ | |
| 882 if (GET_CODE (reg) == SUBREG) | |
| 883 reg = SUBREG_REG (reg); | |
| 884 | |
| 885 /* Dies immediately. */ | |
| 886 if (dead_or_set_p (first, reg)) | |
| 887 return 1; | |
| 888 | |
| 889 /* Look for conclusive evidence of live/death, otherwise we have | |
| 890 to assume that it is live. */ | |
| 891 for (insn = NEXT_INSN (first); insn; insn = NEXT_INSN (insn)) | |
| 892 { | |
| 893 if (GET_CODE (insn) == JUMP_INSN) | |
| 894 return 0; /* We lose track, assume it is alive. */ | |
| 895 | |
| 896 else if (GET_CODE(insn) == CALL_INSN) | |
| 897 { | |
| 898 /* Call's might use it for target or register parms. */ | |
| 899 if (reg_referenced_p (reg, PATTERN (insn)) | |
| 900 || find_reg_fusage (insn, USE, reg)) | |
| 901 return 0; | |
| 902 else if (dead_or_set_p (insn, reg)) | |
| 903 return 1; | |
| 904 } | |
| 905 else if (GET_CODE (insn) == INSN) | |
| 906 { | |
| 907 if (reg_referenced_p (reg, PATTERN (insn))) | |
| 908 return 0; | |
| 909 else if (dead_or_set_p (insn, reg)) | |
| 910 return 1; | |
| 911 } | |
| 912 } | |
| 913 | |
| 914 /* No conclusive evidence either way, we cannot take the chance | |
| 915 that control flow hid the use from us -- "I'm not dead yet". */ | |
| 916 return 0; | |
| 917 } | |
| 918 | |
| 919 /* Count the number of ones in mask. */ | |
| 920 | |
| 921 int | |
| 922 mcore_num_ones (HOST_WIDE_INT mask) | |
| 923 { | |
| 924 /* A trick to count set bits recently posted on comp.compilers. */ | |
| 925 mask = (mask >> 1 & 0x55555555) + (mask & 0x55555555); | |
| 926 mask = ((mask >> 2) & 0x33333333) + (mask & 0x33333333); | |
| 927 mask = ((mask >> 4) + mask) & 0x0f0f0f0f; | |
| 928 mask = ((mask >> 8) + mask); | |
| 929 | |
| 930 return (mask + (mask >> 16)) & 0xff; | |
| 931 } | |
| 932 | |
| 933 /* Count the number of zeros in mask. */ | |
| 934 | |
| 935 int | |
| 936 mcore_num_zeros (HOST_WIDE_INT mask) | |
| 937 { | |
| 938 return 32 - mcore_num_ones (mask); | |
| 939 } | |
| 940 | |
| 941 /* Determine byte being masked. */ | |
| 942 | |
| 943 int | |
| 944 mcore_byte_offset (unsigned int mask) | |
| 945 { | |
| 946 if (mask == 0x00ffffffL) | |
| 947 return 0; | |
| 948 else if (mask == 0xff00ffffL) | |
| 949 return 1; | |
| 950 else if (mask == 0xffff00ffL) | |
| 951 return 2; | |
| 952 else if (mask == 0xffffff00L) | |
| 953 return 3; | |
| 954 | |
| 955 return -1; | |
| 956 } | |
| 957 | |
| 958 /* Determine halfword being masked. */ | |
| 959 | |
| 960 int | |
| 961 mcore_halfword_offset (unsigned int mask) | |
| 962 { | |
| 963 if (mask == 0x0000ffffL) | |
| 964 return 0; | |
| 965 else if (mask == 0xffff0000L) | |
| 966 return 1; | |
| 967 | |
| 968 return -1; | |
| 969 } | |
| 970 | |
| 971 /* Output a series of bseti's corresponding to mask. */ | |
| 972 | |
| 973 const char * | |
| 974 mcore_output_bseti (rtx dst, int mask) | |
| 975 { | |
| 976 rtx out_operands[2]; | |
| 977 int bit; | |
| 978 | |
| 979 out_operands[0] = dst; | |
| 980 | |
| 981 for (bit = 0; bit < 32; bit++) | |
| 982 { | |
| 983 if ((mask & 0x1) == 0x1) | |
| 984 { | |
| 985 out_operands[1] = GEN_INT (bit); | |
| 986 | |
| 987 output_asm_insn ("bseti\t%0,%1", out_operands); | |
| 988 } | |
| 989 mask >>= 1; | |
| 990 } | |
| 991 | |
| 992 return ""; | |
| 993 } | |
| 994 | |
| 995 /* Output a series of bclri's corresponding to mask. */ | |
| 996 | |
| 997 const char * | |
| 998 mcore_output_bclri (rtx dst, int mask) | |
| 999 { | |
| 1000 rtx out_operands[2]; | |
| 1001 int bit; | |
| 1002 | |
| 1003 out_operands[0] = dst; | |
| 1004 | |
| 1005 for (bit = 0; bit < 32; bit++) | |
| 1006 { | |
| 1007 if ((mask & 0x1) == 0x0) | |
| 1008 { | |
| 1009 out_operands[1] = GEN_INT (bit); | |
| 1010 | |
| 1011 output_asm_insn ("bclri\t%0,%1", out_operands); | |
| 1012 } | |
| 1013 | |
| 1014 mask >>= 1; | |
| 1015 } | |
| 1016 | |
| 1017 return ""; | |
| 1018 } | |
| 1019 | |
| 1020 /* Output a conditional move of two constants that are +/- 1 within each | |
| 1021 other. See the "movtK" patterns in mcore.md. I'm not sure this is | |
| 1022 really worth the effort. */ | |
| 1023 | |
| 1024 const char * | |
| 1025 mcore_output_cmov (rtx operands[], int cmp_t, const char * test) | |
| 1026 { | |
| 1027 HOST_WIDE_INT load_value; | |
| 1028 HOST_WIDE_INT adjust_value; | |
| 1029 rtx out_operands[4]; | |
| 1030 | |
| 1031 out_operands[0] = operands[0]; | |
| 1032 | |
| 1033 /* Check to see which constant is loadable. */ | |
| 1034 if (const_ok_for_mcore (INTVAL (operands[1]))) | |
| 1035 { | |
| 1036 out_operands[1] = operands[1]; | |
| 1037 out_operands[2] = operands[2]; | |
| 1038 } | |
| 1039 else if (const_ok_for_mcore (INTVAL (operands[2]))) | |
| 1040 { | |
| 1041 out_operands[1] = operands[2]; | |
| 1042 out_operands[2] = operands[1]; | |
| 1043 | |
| 1044 /* Complement test since constants are swapped. */ | |
| 1045 cmp_t = (cmp_t == 0); | |
| 1046 } | |
| 1047 load_value = INTVAL (out_operands[1]); | |
| 1048 adjust_value = INTVAL (out_operands[2]); | |
| 1049 | |
| 1050 /* First output the test if folded into the pattern. */ | |
| 1051 | |
| 1052 if (test) | |
| 1053 output_asm_insn (test, operands); | |
| 1054 | |
| 1055 /* Load the constant - for now, only support constants that can be | |
| 1056 generated with a single instruction. maybe add general inlinable | |
| 1057 constants later (this will increase the # of patterns since the | |
| 1058 instruction sequence has a different length attribute). */ | |
| 1059 if (load_value >= 0 && load_value <= 127) | |
| 1060 output_asm_insn ("movi\t%0,%1", out_operands); | |
| 1061 else if (CONST_OK_FOR_M (load_value)) | |
| 1062 output_asm_insn ("bgeni\t%0,%P1", out_operands); | |
| 1063 else if (CONST_OK_FOR_N (load_value)) | |
| 1064 output_asm_insn ("bmaski\t%0,%N1", out_operands); | |
| 1065 | |
| 1066 /* Output the constant adjustment. */ | |
| 1067 if (load_value > adjust_value) | |
| 1068 { | |
| 1069 if (cmp_t) | |
| 1070 output_asm_insn ("decf\t%0", out_operands); | |
| 1071 else | |
| 1072 output_asm_insn ("dect\t%0", out_operands); | |
| 1073 } | |
| 1074 else | |
| 1075 { | |
| 1076 if (cmp_t) | |
| 1077 output_asm_insn ("incf\t%0", out_operands); | |
| 1078 else | |
| 1079 output_asm_insn ("inct\t%0", out_operands); | |
| 1080 } | |
| 1081 | |
| 1082 return ""; | |
| 1083 } | |
| 1084 | |
| 1085 /* Outputs the peephole for moving a constant that gets not'ed followed | |
| 1086 by an and (i.e. combine the not and the and into andn). BRC */ | |
| 1087 | |
| 1088 const char * | |
| 1089 mcore_output_andn (rtx insn ATTRIBUTE_UNUSED, rtx operands[]) | |
| 1090 { | |
| 1091 HOST_WIDE_INT x, y; | |
| 1092 rtx out_operands[3]; | |
| 1093 const char * load_op; | |
| 1094 char buf[256]; | |
| 1095 int trick_no; | |
| 1096 | |
| 1097 trick_no = try_constant_tricks (INTVAL (operands[1]), &x, &y); | |
| 1098 gcc_assert (trick_no == 2); | |
| 1099 | |
| 1100 out_operands[0] = operands[0]; | |
| 1101 out_operands[1] = GEN_INT (x); | |
| 1102 out_operands[2] = operands[2]; | |
| 1103 | |
| 1104 if (x >= 0 && x <= 127) | |
| 1105 load_op = "movi\t%0,%1"; | |
| 1106 | |
| 1107 /* Try exact power of two. */ | |
| 1108 else if (CONST_OK_FOR_M (x)) | |
| 1109 load_op = "bgeni\t%0,%P1"; | |
| 1110 | |
| 1111 /* Try exact power of two - 1. */ | |
| 1112 else if (CONST_OK_FOR_N (x)) | |
| 1113 load_op = "bmaski\t%0,%N1"; | |
| 1114 | |
| 1115 else | |
| 1116 { | |
| 1117 load_op = "BADMOVI-andn\t%0, %1"; | |
| 1118 gcc_unreachable (); | |
| 1119 } | |
| 1120 | |
| 1121 sprintf (buf, "%s\n\tandn\t%%2,%%0", load_op); | |
| 1122 output_asm_insn (buf, out_operands); | |
| 1123 | |
| 1124 return ""; | |
| 1125 } | |
| 1126 | |
| 1127 /* Output an inline constant. */ | |
| 1128 | |
| 1129 static const char * | |
| 1130 output_inline_const (enum machine_mode mode, rtx operands[]) | |
| 1131 { | |
| 1132 HOST_WIDE_INT x = 0, y = 0; | |
| 1133 int trick_no; | |
| 1134 rtx out_operands[3]; | |
| 1135 char buf[256]; | |
| 1136 char load_op[256]; | |
| 1137 const char *dst_fmt; | |
| 1138 HOST_WIDE_INT value; | |
| 1139 | |
| 1140 value = INTVAL (operands[1]); | |
| 1141 | |
| 1142 trick_no = try_constant_tricks (value, &x, &y); | |
| 1143 /* lrw's are handled separately: Large inlinable constants never get | |
| 1144 turned into lrw's. Our caller uses try_constant_tricks to back | |
| 1145 off to an lrw rather than calling this routine. */ | |
| 1146 gcc_assert (trick_no != 0); | |
| 1147 | |
| 1148 if (trick_no == 1) | |
| 1149 x = value; | |
| 1150 | |
| 1151 /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */ | |
| 1152 out_operands[0] = operands[0]; | |
| 1153 out_operands[1] = GEN_INT (x); | |
| 1154 | |
| 1155 if (trick_no > 2) | |
| 1156 out_operands[2] = GEN_INT (y); | |
| 1157 | |
| 1158 /* Select dst format based on mode. */ | |
| 1159 if (mode == DImode && (! TARGET_LITTLE_END)) | |
| 1160 dst_fmt = "%R0"; | |
| 1161 else | |
| 1162 dst_fmt = "%0"; | |
| 1163 | |
| 1164 if (x >= 0 && x <= 127) | |
| 1165 sprintf (load_op, "movi\t%s,%%1", dst_fmt); | |
| 1166 | |
| 1167 /* Try exact power of two. */ | |
| 1168 else if (CONST_OK_FOR_M (x)) | |
| 1169 sprintf (load_op, "bgeni\t%s,%%P1", dst_fmt); | |
| 1170 | |
| 1171 /* Try exact power of two - 1. */ | |
| 1172 else if (CONST_OK_FOR_N (x)) | |
| 1173 sprintf (load_op, "bmaski\t%s,%%N1", dst_fmt); | |
| 1174 | |
| 1175 else | |
| 1176 { | |
| 1177 sprintf (load_op, "BADMOVI-inline_const %s, %%1", dst_fmt); | |
| 1178 gcc_unreachable (); | |
| 1179 } | |
| 1180 | |
| 1181 switch (trick_no) | |
| 1182 { | |
| 1183 case 1: | |
| 1184 strcpy (buf, load_op); | |
| 1185 break; | |
| 1186 case 2: /* not */ | |
| 1187 sprintf (buf, "%s\n\tnot\t%s\t// %ld 0x%lx", load_op, dst_fmt, value, value); | |
| 1188 break; | |
| 1189 case 3: /* add */ | |
| 1190 sprintf (buf, "%s\n\taddi\t%s,%%2\t// %ld 0x%lx", load_op, dst_fmt, value, value); | |
| 1191 break; | |
| 1192 case 4: /* sub */ | |
| 1193 sprintf (buf, "%s\n\tsubi\t%s,%%2\t// %ld 0x%lx", load_op, dst_fmt, value, value); | |
| 1194 break; | |
| 1195 case 5: /* rsub */ | |
| 1196 /* Never happens unless -mrsubi, see try_constant_tricks(). */ | |
| 1197 sprintf (buf, "%s\n\trsubi\t%s,%%2\t// %ld 0x%lx", load_op, dst_fmt, value, value); | |
| 1198 break; | |
| 1199 case 6: /* bseti */ | |
| 1200 sprintf (buf, "%s\n\tbseti\t%s,%%P2\t// %ld 0x%lx", load_op, dst_fmt, value, value); | |
| 1201 break; | |
| 1202 case 7: /* bclr */ | |
| 1203 sprintf (buf, "%s\n\tbclri\t%s,%%Q2\t// %ld 0x%lx", load_op, dst_fmt, value, value); | |
| 1204 break; | |
| 1205 case 8: /* rotl */ | |
| 1206 sprintf (buf, "%s\n\trotli\t%s,%%2\t// %ld 0x%lx", load_op, dst_fmt, value, value); | |
| 1207 break; | |
| 1208 case 9: /* lsl */ | |
| 1209 sprintf (buf, "%s\n\tlsli\t%s,%%2\t// %ld 0x%lx", load_op, dst_fmt, value, value); | |
| 1210 break; | |
| 1211 case 10: /* ixh */ | |
| 1212 sprintf (buf, "%s\n\tixh\t%s,%s\t// %ld 0x%lx", load_op, dst_fmt, dst_fmt, value, value); | |
| 1213 break; | |
| 1214 case 11: /* ixw */ | |
| 1215 sprintf (buf, "%s\n\tixw\t%s,%s\t// %ld 0x%lx", load_op, dst_fmt, dst_fmt, value, value); | |
| 1216 break; | |
| 1217 default: | |
| 1218 return ""; | |
| 1219 } | |
| 1220 | |
| 1221 output_asm_insn (buf, out_operands); | |
| 1222 | |
| 1223 return ""; | |
| 1224 } | |
| 1225 | |
| 1226 /* Output a move of a word or less value. */ | |
| 1227 | |
| 1228 const char * | |
| 1229 mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[], | |
| 1230 enum machine_mode mode ATTRIBUTE_UNUSED) | |
| 1231 { | |
| 1232 rtx dst = operands[0]; | |
| 1233 rtx src = operands[1]; | |
| 1234 | |
| 1235 if (GET_CODE (dst) == REG) | |
| 1236 { | |
| 1237 if (GET_CODE (src) == REG) | |
| 1238 { | |
| 1239 if (REGNO (src) == CC_REG) /* r-c */ | |
| 1240 return "mvc\t%0"; | |
| 1241 else | |
| 1242 return "mov\t%0,%1"; /* r-r*/ | |
| 1243 } | |
| 1244 else if (GET_CODE (src) == MEM) | |
| 1245 { | |
| 1246 if (GET_CODE (XEXP (src, 0)) == LABEL_REF) | |
| 1247 return "lrw\t%0,[%1]"; /* a-R */ | |
| 1248 else | |
| 1249 switch (GET_MODE (src)) /* r-m */ | |
| 1250 { | |
| 1251 case SImode: | |
| 1252 return "ldw\t%0,%1"; | |
| 1253 case HImode: | |
| 1254 return "ld.h\t%0,%1"; | |
| 1255 case QImode: | |
| 1256 return "ld.b\t%0,%1"; | |
| 1257 default: | |
| 1258 gcc_unreachable (); | |
| 1259 } | |
| 1260 } | |
| 1261 else if (GET_CODE (src) == CONST_INT) | |
| 1262 { | |
| 1263 HOST_WIDE_INT x, y; | |
| 1264 | |
| 1265 if (CONST_OK_FOR_I (INTVAL (src))) /* r-I */ | |
| 1266 return "movi\t%0,%1"; | |
| 1267 else if (CONST_OK_FOR_M (INTVAL (src))) /* r-M */ | |
| 1268 return "bgeni\t%0,%P1\t// %1 %x1"; | |
| 1269 else if (CONST_OK_FOR_N (INTVAL (src))) /* r-N */ | |
| 1270 return "bmaski\t%0,%N1\t// %1 %x1"; | |
| 1271 else if (try_constant_tricks (INTVAL (src), &x, &y)) /* R-P */ | |
| 1272 return output_inline_const (SImode, operands); /* 1-2 insns */ | |
| 1273 else | |
| 1274 return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */ | |
| 1275 } | |
| 1276 else | |
| 1277 return "lrw\t%0, %1"; /* Into the literal pool. */ | |
| 1278 } | |
| 1279 else if (GET_CODE (dst) == MEM) /* m-r */ | |
| 1280 switch (GET_MODE (dst)) | |
| 1281 { | |
| 1282 case SImode: | |
| 1283 return "stw\t%1,%0"; | |
| 1284 case HImode: | |
| 1285 return "st.h\t%1,%0"; | |
| 1286 case QImode: | |
| 1287 return "st.b\t%1,%0"; | |
| 1288 default: | |
| 1289 gcc_unreachable (); | |
| 1290 } | |
| 1291 | |
| 1292 gcc_unreachable (); | |
| 1293 } | |
| 1294 | |
| 1295 /* Return a sequence of instructions to perform DI or DF move. | |
| 1296 Since the MCORE cannot move a DI or DF in one instruction, we have | |
| 1297 to take care when we see overlapping source and dest registers. */ | |
| 1298 | |
| 1299 const char * | |
| 1300 mcore_output_movedouble (rtx operands[], enum machine_mode mode ATTRIBUTE_UNUSED) | |
| 1301 { | |
| 1302 rtx dst = operands[0]; | |
| 1303 rtx src = operands[1]; | |
| 1304 | |
| 1305 if (GET_CODE (dst) == REG) | |
| 1306 { | |
| 1307 if (GET_CODE (src) == REG) | |
| 1308 { | |
| 1309 int dstreg = REGNO (dst); | |
| 1310 int srcreg = REGNO (src); | |
| 1311 | |
| 1312 /* Ensure the second source not overwritten. */ | |
| 1313 if (srcreg + 1 == dstreg) | |
| 1314 return "mov %R0,%R1\n\tmov %0,%1"; | |
| 1315 else | |
| 1316 return "mov %0,%1\n\tmov %R0,%R1"; | |
| 1317 } | |
| 1318 else if (GET_CODE (src) == MEM) | |
| 1319 { | |
| 1320 rtx memexp = memexp = XEXP (src, 0); | |
| 1321 int dstreg = REGNO (dst); | |
| 1322 int basereg = -1; | |
| 1323 | |
| 1324 if (GET_CODE (memexp) == LABEL_REF) | |
| 1325 return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]"; | |
| 1326 else if (GET_CODE (memexp) == REG) | |
| 1327 basereg = REGNO (memexp); | |
| 1328 else if (GET_CODE (memexp) == PLUS) | |
| 1329 { | |
| 1330 if (GET_CODE (XEXP (memexp, 0)) == REG) | |
| 1331 basereg = REGNO (XEXP (memexp, 0)); | |
| 1332 else if (GET_CODE (XEXP (memexp, 1)) == REG) | |
| 1333 basereg = REGNO (XEXP (memexp, 1)); | |
| 1334 else | |
| 1335 gcc_unreachable (); | |
| 1336 } | |
| 1337 else | |
| 1338 gcc_unreachable (); | |
| 1339 | |
| 1340 /* ??? length attribute is wrong here. */ | |
| 1341 if (dstreg == basereg) | |
| 1342 { | |
| 1343 /* Just load them in reverse order. */ | |
| 1344 return "ldw\t%R0,%R1\n\tldw\t%0,%1"; | |
| 1345 | |
| 1346 /* XXX: alternative: move basereg to basereg+1 | |
| 1347 and then fall through. */ | |
| 1348 } | |
| 1349 else | |
| 1350 return "ldw\t%0,%1\n\tldw\t%R0,%R1"; | |
| 1351 } | |
| 1352 else if (GET_CODE (src) == CONST_INT) | |
| 1353 { | |
| 1354 if (TARGET_LITTLE_END) | |
| 1355 { | |
| 1356 if (CONST_OK_FOR_I (INTVAL (src))) | |
| 1357 output_asm_insn ("movi %0,%1", operands); | |
| 1358 else if (CONST_OK_FOR_M (INTVAL (src))) | |
| 1359 output_asm_insn ("bgeni %0,%P1", operands); | |
| 1360 else if (CONST_OK_FOR_N (INTVAL (src))) | |
| 1361 output_asm_insn ("bmaski %0,%N1", operands); | |
| 1362 else | |
| 1363 gcc_unreachable (); | |
| 1364 | |
| 1365 if (INTVAL (src) < 0) | |
| 1366 return "bmaski %R0,32"; | |
| 1367 else | |
| 1368 return "movi %R0,0"; | |
| 1369 } | |
| 1370 else | |
| 1371 { | |
| 1372 if (CONST_OK_FOR_I (INTVAL (src))) | |
| 1373 output_asm_insn ("movi %R0,%1", operands); | |
| 1374 else if (CONST_OK_FOR_M (INTVAL (src))) | |
| 1375 output_asm_insn ("bgeni %R0,%P1", operands); | |
| 1376 else if (CONST_OK_FOR_N (INTVAL (src))) | |
| 1377 output_asm_insn ("bmaski %R0,%N1", operands); | |
| 1378 else | |
| 1379 gcc_unreachable (); | |
| 1380 | |
| 1381 if (INTVAL (src) < 0) | |
| 1382 return "bmaski %0,32"; | |
| 1383 else | |
| 1384 return "movi %0,0"; | |
| 1385 } | |
| 1386 } | |
| 1387 else | |
| 1388 gcc_unreachable (); | |
| 1389 } | |
| 1390 else if (GET_CODE (dst) == MEM && GET_CODE (src) == REG) | |
| 1391 return "stw\t%1,%0\n\tstw\t%R1,%R0"; | |
| 1392 else | |
| 1393 gcc_unreachable (); | |
| 1394 } | |
| 1395 | |
| 1396 /* Predicates used by the templates. */ | |
| 1397 | |
| 1398 int | |
| 1399 mcore_arith_S_operand (rtx op) | |
| 1400 { | |
| 1401 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (~INTVAL (op))) | |
| 1402 return 1; | |
| 1403 | |
| 1404 return 0; | |
| 1405 } | |
| 1406 | |
| 1407 /* Expand insert bit field. BRC */ | |
| 1408 | |
| 1409 int | |
| 1410 mcore_expand_insv (rtx operands[]) | |
| 1411 { | |
| 1412 int width = INTVAL (operands[1]); | |
| 1413 int posn = INTVAL (operands[2]); | |
| 1414 int mask; | |
| 1415 rtx mreg, sreg, ereg; | |
| 1416 | |
| 1417 /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191) | |
| 1418 for width==1 must be removed. Look around line 368. This is something | |
| 1419 we really want the md part to do. */ | |
| 1420 if (width == 1 && GET_CODE (operands[3]) == CONST_INT) | |
| 1421 { | |
| 1422 /* Do directly with bseti or bclri. */ | |
| 1423 /* RBE: 2/97 consider only low bit of constant. */ | |
| 1424 if ((INTVAL (operands[3]) & 1) == 0) | |
| 1425 { | |
| 1426 mask = ~(1 << posn); | |
| 1427 emit_insn (gen_rtx_SET (SImode, operands[0], | |
| 1428 gen_rtx_AND (SImode, operands[0], GEN_INT (mask)))); | |
| 1429 } | |
| 1430 else | |
| 1431 { | |
| 1432 mask = 1 << posn; | |
| 1433 emit_insn (gen_rtx_SET (SImode, operands[0], | |
| 1434 gen_rtx_IOR (SImode, operands[0], GEN_INT (mask)))); | |
| 1435 } | |
| 1436 | |
| 1437 return 1; | |
| 1438 } | |
| 1439 | |
| 1440 /* Look at some bit-field placements that we aren't interested | |
| 1441 in handling ourselves, unless specifically directed to do so. */ | |
| 1442 if (! TARGET_W_FIELD) | |
| 1443 return 0; /* Generally, give up about now. */ | |
| 1444 | |
| 1445 if (width == 8 && posn % 8 == 0) | |
| 1446 /* Byte sized and aligned; let caller break it up. */ | |
| 1447 return 0; | |
| 1448 | |
| 1449 if (width == 16 && posn % 16 == 0) | |
| 1450 /* Short sized and aligned; let caller break it up. */ | |
| 1451 return 0; | |
| 1452 | |
| 1453 /* The general case - we can do this a little bit better than what the | |
| 1454 machine independent part tries. This will get rid of all the subregs | |
| 1455 that mess up constant folding in combine when working with relaxed | |
| 1456 immediates. */ | |
| 1457 | |
| 1458 /* If setting the entire field, do it directly. */ | |
| 1459 if (GET_CODE (operands[3]) == CONST_INT | |
| 1460 && INTVAL (operands[3]) == ((1 << width) - 1)) | |
| 1461 { | |
| 1462 mreg = force_reg (SImode, GEN_INT (INTVAL (operands[3]) << posn)); | |
| 1463 emit_insn (gen_rtx_SET (SImode, operands[0], | |
| 1464 gen_rtx_IOR (SImode, operands[0], mreg))); | |
| 1465 return 1; | |
| 1466 } | |
| 1467 | |
| 1468 /* Generate the clear mask. */ | |
| 1469 mreg = force_reg (SImode, GEN_INT (~(((1 << width) - 1) << posn))); | |
| 1470 | |
| 1471 /* Clear the field, to overlay it later with the source. */ | |
| 1472 emit_insn (gen_rtx_SET (SImode, operands[0], | |
| 1473 gen_rtx_AND (SImode, operands[0], mreg))); | |
| 1474 | |
| 1475 /* If the source is constant 0, we've nothing to add back. */ | |
| 1476 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) == 0) | |
| 1477 return 1; | |
| 1478 | |
| 1479 /* XXX: Should we worry about more games with constant values? | |
| 1480 We've covered the high profile: set/clear single-bit and many-bit | |
| 1481 fields. How often do we see "arbitrary bit pattern" constants? */ | |
| 1482 sreg = copy_to_mode_reg (SImode, operands[3]); | |
| 1483 | |
| 1484 /* Extract src as same width as dst (needed for signed values). We | |
| 1485 always have to do this since we widen everything to SImode. | |
| 1486 We don't have to mask if we're shifting this up against the | |
| 1487 MSB of the register (e.g., the shift will push out any hi-order | |
| 1488 bits. */ | |
| 1489 if (width + posn != (int) GET_MODE_SIZE (SImode)) | |
| 1490 { | |
| 1491 ereg = force_reg (SImode, GEN_INT ((1 << width) - 1)); | |
| 1492 emit_insn (gen_rtx_SET (SImode, sreg, | |
| 1493 gen_rtx_AND (SImode, sreg, ereg))); | |
| 1494 } | |
| 1495 | |
| 1496 /* Insert source value in dest. */ | |
| 1497 if (posn != 0) | |
| 1498 emit_insn (gen_rtx_SET (SImode, sreg, | |
| 1499 gen_rtx_ASHIFT (SImode, sreg, GEN_INT (posn)))); | |
| 1500 | |
| 1501 emit_insn (gen_rtx_SET (SImode, operands[0], | |
| 1502 gen_rtx_IOR (SImode, operands[0], sreg))); | |
| 1503 | |
| 1504 return 1; | |
| 1505 } | |
| 1506 | |
| 1507 /* ??? Block move stuff stolen from m88k. This code has not been | |
| 1508 verified for correctness. */ | |
| 1509 | |
| 1510 /* Emit code to perform a block move. Choose the best method. | |
| 1511 | |
| 1512 OPERANDS[0] is the destination. | |
| 1513 OPERANDS[1] is the source. | |
| 1514 OPERANDS[2] is the size. | |
| 1515 OPERANDS[3] is the alignment safe to use. */ | |
| 1516 | |
| 1517 /* Emit code to perform a block move with an offset sequence of ldw/st | |
| 1518 instructions (..., ldw 0, stw 1, ldw 1, stw 0, ...). SIZE and ALIGN are | |
| 1519 known constants. DEST and SRC are registers. OFFSET is the known | |
| 1520 starting point for the output pattern. */ | |
| 1521 | |
| 1522 static const enum machine_mode mode_from_align[] = | |
| 1523 { | |
| 1524 VOIDmode, QImode, HImode, VOIDmode, SImode, | |
| 1525 }; | |
| 1526 | |
| 1527 static void | |
| 1528 block_move_sequence (rtx dst_mem, rtx src_mem, int size, int align) | |
| 1529 { | |
| 1530 rtx temp[2]; | |
| 1531 enum machine_mode mode[2]; | |
| 1532 int amount[2]; | |
| 1533 bool active[2]; | |
| 1534 int phase = 0; | |
| 1535 int next; | |
| 1536 int offset_ld = 0; | |
| 1537 int offset_st = 0; | |
| 1538 rtx x; | |
| 1539 | |
| 1540 x = XEXP (dst_mem, 0); | |
| 1541 if (!REG_P (x)) | |
| 1542 { | |
| 1543 x = force_reg (Pmode, x); | |
| 1544 dst_mem = replace_equiv_address (dst_mem, x); | |
| 1545 } | |
| 1546 | |
| 1547 x = XEXP (src_mem, 0); | |
| 1548 if (!REG_P (x)) | |
| 1549 { | |
| 1550 x = force_reg (Pmode, x); | |
| 1551 src_mem = replace_equiv_address (src_mem, x); | |
| 1552 } | |
| 1553 | |
| 1554 active[0] = active[1] = false; | |
| 1555 | |
| 1556 do | |
| 1557 { | |
| 1558 next = phase; | |
| 1559 phase ^= 1; | |
| 1560 | |
| 1561 if (size > 0) | |
| 1562 { | |
| 1563 int next_amount; | |
| 1564 | |
| 1565 next_amount = (size >= 4 ? 4 : (size >= 2 ? 2 : 1)); | |
| 1566 next_amount = MIN (next_amount, align); | |
| 1567 | |
| 1568 amount[next] = next_amount; | |
| 1569 mode[next] = mode_from_align[next_amount]; | |
| 1570 temp[next] = gen_reg_rtx (mode[next]); | |
| 1571 | |
| 1572 x = adjust_address (src_mem, mode[next], offset_ld); | |
| 1573 emit_insn (gen_rtx_SET (VOIDmode, temp[next], x)); | |
| 1574 | |
| 1575 offset_ld += next_amount; | |
| 1576 size -= next_amount; | |
| 1577 active[next] = true; | |
| 1578 } | |
| 1579 | |
| 1580 if (active[phase]) | |
| 1581 { | |
| 1582 active[phase] = false; | |
| 1583 | |
| 1584 x = adjust_address (dst_mem, mode[phase], offset_st); | |
| 1585 emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase])); | |
| 1586 | |
| 1587 offset_st += amount[phase]; | |
| 1588 } | |
| 1589 } | |
| 1590 while (active[next]); | |
| 1591 } | |
| 1592 | |
| 1593 bool | |
| 1594 mcore_expand_block_move (rtx *operands) | |
| 1595 { | |
| 1596 HOST_WIDE_INT align, bytes, max; | |
| 1597 | |
| 1598 if (GET_CODE (operands[2]) != CONST_INT) | |
| 1599 return false; | |
| 1600 | |
| 1601 bytes = INTVAL (operands[2]); | |
| 1602 align = INTVAL (operands[3]); | |
| 1603 | |
| 1604 if (bytes <= 0) | |
| 1605 return false; | |
| 1606 if (align > 4) | |
| 1607 align = 4; | |
| 1608 | |
| 1609 switch (align) | |
| 1610 { | |
| 1611 case 4: | |
| 1612 if (bytes & 1) | |
| 1613 max = 4*4; | |
| 1614 else if (bytes & 3) | |
| 1615 max = 8*4; | |
| 1616 else | |
| 1617 max = 16*4; | |
| 1618 break; | |
| 1619 case 2: | |
| 1620 max = 4*2; | |
| 1621 break; | |
| 1622 case 1: | |
| 1623 max = 4*1; | |
| 1624 break; | |
| 1625 default: | |
| 1626 gcc_unreachable (); | |
| 1627 } | |
| 1628 | |
| 1629 if (bytes <= max) | |
| 1630 { | |
| 1631 block_move_sequence (operands[0], operands[1], bytes, align); | |
| 1632 return true; | |
| 1633 } | |
| 1634 | |
| 1635 return false; | |
| 1636 } | |
| 1637 | |
| 1638 | |
| 1639 /* Code to generate prologue and epilogue sequences. */ | |
| 1640 static int number_of_regs_before_varargs; | |
| 1641 | |
| 1642 /* Set by TARGET_SETUP_INCOMING_VARARGS to indicate to prolog that this is | |
| 1643 for a varargs function. */ | |
| 1644 static int current_function_anonymous_args; | |
| 1645 | |
| 1646 #define STACK_BYTES (STACK_BOUNDARY/BITS_PER_UNIT) | |
| 1647 #define STORE_REACH (64) /* Maximum displace of word store + 4. */ | |
| 1648 #define ADDI_REACH (32) /* Maximum addi operand. */ | |
| 1649 | |
| 1650 static void | |
| 1651 layout_mcore_frame (struct mcore_frame * infp) | |
| 1652 { | |
| 1653 int n; | |
| 1654 unsigned int i; | |
| 1655 int nbytes; | |
| 1656 int regarg; | |
| 1657 int localregarg; | |
| 1658 int localreg; | |
| 1659 int outbounds; | |
| 1660 unsigned int growths; | |
| 1661 int step; | |
| 1662 | |
| 1663 /* Might have to spill bytes to re-assemble a big argument that | |
| 1664 was passed partially in registers and partially on the stack. */ | |
| 1665 nbytes = crtl->args.pretend_args_size; | |
| 1666 | |
| 1667 /* Determine how much space for spilled anonymous args (e.g., stdarg). */ | |
| 1668 if (current_function_anonymous_args) | |
| 1669 nbytes += (NPARM_REGS - number_of_regs_before_varargs) * UNITS_PER_WORD; | |
| 1670 | |
| 1671 infp->arg_size = nbytes; | |
| 1672 | |
| 1673 /* How much space to save non-volatile registers we stomp. */ | |
| 1674 infp->reg_mask = calc_live_regs (& n); | |
| 1675 infp->reg_size = n * 4; | |
| 1676 | |
| 1677 /* And the rest of it... locals and space for overflowed outbounds. */ | |
| 1678 infp->local_size = get_frame_size (); | |
| 1679 infp->outbound_size = crtl->outgoing_args_size; | |
| 1680 | |
| 1681 /* Make sure we have a whole number of words for the locals. */ | |
| 1682 if (infp->local_size % STACK_BYTES) | |
| 1683 infp->local_size = (infp->local_size + STACK_BYTES - 1) & ~ (STACK_BYTES -1); | |
| 1684 | |
| 1685 /* Only thing we know we have to pad is the outbound space, since | |
| 1686 we've aligned our locals assuming that base of locals is aligned. */ | |
| 1687 infp->pad_local = 0; | |
| 1688 infp->pad_reg = 0; | |
| 1689 infp->pad_outbound = 0; | |
| 1690 if (infp->outbound_size % STACK_BYTES) | |
| 1691 infp->pad_outbound = STACK_BYTES - (infp->outbound_size % STACK_BYTES); | |
| 1692 | |
| 1693 /* Now we see how we want to stage the prologue so that it does | |
| 1694 the most appropriate stack growth and register saves to either: | |
| 1695 (1) run fast, | |
| 1696 (2) reduce instruction space, or | |
| 1697 (3) reduce stack space. */ | |
| 1698 for (i = 0; i < ARRAY_SIZE (infp->growth); i++) | |
| 1699 infp->growth[i] = 0; | |
| 1700 | |
| 1701 regarg = infp->reg_size + infp->arg_size; | |
| 1702 localregarg = infp->local_size + regarg; | |
| 1703 localreg = infp->local_size + infp->reg_size; | |
| 1704 outbounds = infp->outbound_size + infp->pad_outbound; | |
| 1705 growths = 0; | |
| 1706 | |
| 1707 /* XXX: Consider one where we consider localregarg + outbound too! */ | |
| 1708 | |
| 1709 /* Frame of <= 32 bytes and using stm would get <= 2 registers. | |
| 1710 use stw's with offsets and buy the frame in one shot. */ | |
| 1711 if (localregarg <= ADDI_REACH | |
| 1712 && (infp->reg_size <= 8 || (infp->reg_mask & 0xc000) != 0xc000)) | |
| 1713 { | |
| 1714 /* Make sure we'll be aligned. */ | |
| 1715 if (localregarg % STACK_BYTES) | |
| 1716 infp->pad_reg = STACK_BYTES - (localregarg % STACK_BYTES); | |
| 1717 | |
| 1718 step = localregarg + infp->pad_reg; | |
| 1719 infp->reg_offset = infp->local_size; | |
| 1720 | |
| 1721 if (outbounds + step <= ADDI_REACH && !frame_pointer_needed) | |
| 1722 { | |
| 1723 step += outbounds; | |
| 1724 infp->reg_offset += outbounds; | |
| 1725 outbounds = 0; | |
| 1726 } | |
| 1727 | |
| 1728 infp->arg_offset = step - 4; | |
| 1729 infp->growth[growths++] = step; | |
| 1730 infp->reg_growth = growths; | |
| 1731 infp->local_growth = growths; | |
| 1732 | |
| 1733 /* If we haven't already folded it in. */ | |
| 1734 if (outbounds) | |
| 1735 infp->growth[growths++] = outbounds; | |
| 1736 | |
| 1737 goto finish; | |
| 1738 } | |
| 1739 | |
| 1740 /* Frame can't be done with a single subi, but can be done with 2 | |
| 1741 insns. If the 'stm' is getting <= 2 registers, we use stw's and | |
| 1742 shift some of the stack purchase into the first subi, so both are | |
| 1743 single instructions. */ | |
| 1744 if (localregarg <= STORE_REACH | |
| 1745 && (infp->local_size > ADDI_REACH) | |
| 1746 && (infp->reg_size <= 8 || (infp->reg_mask & 0xc000) != 0xc000)) | |
| 1747 { | |
| 1748 int all; | |
| 1749 | |
| 1750 /* Make sure we'll be aligned; use either pad_reg or pad_local. */ | |
| 1751 if (localregarg % STACK_BYTES) | |
| 1752 infp->pad_reg = STACK_BYTES - (localregarg % STACK_BYTES); | |
| 1753 | |
| 1754 all = localregarg + infp->pad_reg + infp->pad_local; | |
| 1755 step = ADDI_REACH; /* As much up front as we can. */ | |
| 1756 if (step > all) | |
| 1757 step = all; | |
| 1758 | |
| 1759 /* XXX: Consider whether step will still be aligned; we believe so. */ | |
| 1760 infp->arg_offset = step - 4; | |
| 1761 infp->growth[growths++] = step; | |
| 1762 infp->reg_growth = growths; | |
| 1763 infp->reg_offset = step - infp->pad_reg - infp->reg_size; | |
| 1764 all -= step; | |
| 1765 | |
| 1766 /* Can we fold in any space required for outbounds? */ | |
| 1767 if (outbounds + all <= ADDI_REACH && !frame_pointer_needed) | |
| 1768 { | |
| 1769 all += outbounds; | |
| 1770 outbounds = 0; | |
| 1771 } | |
| 1772 | |
| 1773 /* Get the rest of the locals in place. */ | |
| 1774 step = all; | |
| 1775 infp->growth[growths++] = step; | |
| 1776 infp->local_growth = growths; | |
| 1777 all -= step; | |
| 1778 | |
| 1779 assert (all == 0); | |
| 1780 | |
| 1781 /* Finish off if we need to do so. */ | |
| 1782 if (outbounds) | |
| 1783 infp->growth[growths++] = outbounds; | |
| 1784 | |
| 1785 goto finish; | |
| 1786 } | |
| 1787 | |
| 1788 /* Registers + args is nicely aligned, so we'll buy that in one shot. | |
| 1789 Then we buy the rest of the frame in 1 or 2 steps depending on | |
| 1790 whether we need a frame pointer. */ | |
| 1791 if ((regarg % STACK_BYTES) == 0) | |
| 1792 { | |
| 1793 infp->growth[growths++] = regarg; | |
| 1794 infp->reg_growth = growths; | |
| 1795 infp->arg_offset = regarg - 4; | |
| 1796 infp->reg_offset = 0; | |
| 1797 | |
| 1798 if (infp->local_size % STACK_BYTES) | |
| 1799 infp->pad_local = STACK_BYTES - (infp->local_size % STACK_BYTES); | |
| 1800 | |
| 1801 step = infp->local_size + infp->pad_local; | |
| 1802 | |
| 1803 if (!frame_pointer_needed) | |
| 1804 { | |
| 1805 step += outbounds; | |
| 1806 outbounds = 0; | |
| 1807 } | |
| 1808 | |
| 1809 infp->growth[growths++] = step; | |
| 1810 infp->local_growth = growths; | |
| 1811 | |
| 1812 /* If there's any left to be done. */ | |
| 1813 if (outbounds) | |
| 1814 infp->growth[growths++] = outbounds; | |
| 1815 | |
| 1816 goto finish; | |
| 1817 } | |
| 1818 | |
| 1819 /* XXX: optimizations that we'll want to play with.... | |
| 1820 -- regarg is not aligned, but it's a small number of registers; | |
| 1821 use some of localsize so that regarg is aligned and then | |
| 1822 save the registers. */ | |
| 1823 | |
| 1824 /* Simple encoding; plods down the stack buying the pieces as it goes. | |
| 1825 -- does not optimize space consumption. | |
| 1826 -- does not attempt to optimize instruction counts. | |
| 1827 -- but it is safe for all alignments. */ | |
| 1828 if (regarg % STACK_BYTES != 0) | |
| 1829 infp->pad_reg = STACK_BYTES - (regarg % STACK_BYTES); | |
| 1830 | |
| 1831 infp->growth[growths++] = infp->arg_size + infp->reg_size + infp->pad_reg; | |
| 1832 infp->reg_growth = growths; | |
| 1833 infp->arg_offset = infp->growth[0] - 4; | |
| 1834 infp->reg_offset = 0; | |
| 1835 | |
| 1836 if (frame_pointer_needed) | |
| 1837 { | |
| 1838 if (infp->local_size % STACK_BYTES != 0) | |
| 1839 infp->pad_local = STACK_BYTES - (infp->local_size % STACK_BYTES); | |
| 1840 | |
| 1841 infp->growth[growths++] = infp->local_size + infp->pad_local; | |
| 1842 infp->local_growth = growths; | |
| 1843 | |
| 1844 infp->growth[growths++] = outbounds; | |
| 1845 } | |
| 1846 else | |
| 1847 { | |
| 1848 if ((infp->local_size + outbounds) % STACK_BYTES != 0) | |
| 1849 infp->pad_local = STACK_BYTES - ((infp->local_size + outbounds) % STACK_BYTES); | |
| 1850 | |
| 1851 infp->growth[growths++] = infp->local_size + infp->pad_local + outbounds; | |
| 1852 infp->local_growth = growths; | |
| 1853 } | |
| 1854 | |
| 1855 /* Anything else that we've forgotten?, plus a few consistency checks. */ | |
| 1856 finish: | |
| 1857 assert (infp->reg_offset >= 0); | |
| 1858 assert (growths <= MAX_STACK_GROWS); | |
| 1859 | |
| 1860 for (i = 0; i < growths; i++) | |
| 1861 gcc_assert (!(infp->growth[i] % STACK_BYTES)); | |
| 1862 } | |
| 1863 | |
| 1864 /* Define the offset between two registers, one to be eliminated, and | |
| 1865 the other its replacement, at the start of a routine. */ | |
| 1866 | |
| 1867 int | |
| 1868 mcore_initial_elimination_offset (int from, int to) | |
| 1869 { | |
| 1870 int above_frame; | |
| 1871 int below_frame; | |
| 1872 struct mcore_frame fi; | |
| 1873 | |
| 1874 layout_mcore_frame (& fi); | |
| 1875 | |
| 1876 /* fp to ap */ | |
| 1877 above_frame = fi.local_size + fi.pad_local + fi.reg_size + fi.pad_reg; | |
| 1878 /* sp to fp */ | |
| 1879 below_frame = fi.outbound_size + fi.pad_outbound; | |
| 1880 | |
| 1881 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) | |
| 1882 return above_frame; | |
| 1883 | |
| 1884 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
| 1885 return above_frame + below_frame; | |
| 1886 | |
| 1887 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
| 1888 return below_frame; | |
| 1889 | |
| 1890 gcc_unreachable (); | |
| 1891 } | |
| 1892 | |
| 1893 /* Keep track of some information about varargs for the prolog. */ | |
| 1894 | |
| 1895 static void | |
| 1896 mcore_setup_incoming_varargs (CUMULATIVE_ARGS *args_so_far, | |
| 1897 enum machine_mode mode, tree type, | |
| 1898 int * ptr_pretend_size ATTRIBUTE_UNUSED, | |
| 1899 int second_time ATTRIBUTE_UNUSED) | |
| 1900 { | |
| 1901 current_function_anonymous_args = 1; | |
| 1902 | |
| 1903 /* We need to know how many argument registers are used before | |
| 1904 the varargs start, so that we can push the remaining argument | |
| 1905 registers during the prologue. */ | |
| 1906 number_of_regs_before_varargs = *args_so_far + mcore_num_arg_regs (mode, type); | |
| 1907 | |
| 1908 /* There is a bug somewhere in the arg handling code. | |
| 1909 Until I can find it this workaround always pushes the | |
| 1910 last named argument onto the stack. */ | |
| 1911 number_of_regs_before_varargs = *args_so_far; | |
| 1912 | |
| 1913 /* The last named argument may be split between argument registers | |
| 1914 and the stack. Allow for this here. */ | |
| 1915 if (number_of_regs_before_varargs > NPARM_REGS) | |
| 1916 number_of_regs_before_varargs = NPARM_REGS; | |
| 1917 } | |
| 1918 | |
| 1919 void | |
| 1920 mcore_expand_prolog (void) | |
| 1921 { | |
| 1922 struct mcore_frame fi; | |
| 1923 int space_allocated = 0; | |
| 1924 int growth = 0; | |
| 1925 | |
| 1926 /* Find out what we're doing. */ | |
| 1927 layout_mcore_frame (&fi); | |
| 1928 | |
| 1929 space_allocated = fi.arg_size + fi.reg_size + fi.local_size + | |
| 1930 fi.outbound_size + fi.pad_outbound + fi.pad_local + fi.pad_reg; | |
| 1931 | |
| 1932 if (TARGET_CG_DATA) | |
| 1933 { | |
| 1934 /* Emit a symbol for this routine's frame size. */ | |
| 1935 rtx x; | |
| 1936 | |
| 1937 x = DECL_RTL (current_function_decl); | |
| 1938 | |
| 1939 gcc_assert (GET_CODE (x) == MEM); | |
| 1940 | |
| 1941 x = XEXP (x, 0); | |
| 1942 | |
| 1943 gcc_assert (GET_CODE (x) == SYMBOL_REF); | |
| 1944 | |
| 1945 if (mcore_current_function_name) | |
| 1946 free (mcore_current_function_name); | |
| 1947 | |
| 1948 mcore_current_function_name = xstrdup (XSTR (x, 0)); | |
| 1949 | |
| 1950 ASM_OUTPUT_CG_NODE (asm_out_file, mcore_current_function_name, space_allocated); | |
| 1951 | |
| 1952 if (cfun->calls_alloca) | |
| 1953 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name, "alloca", 1); | |
| 1954 | |
| 1955 /* 970425: RBE: | |
| 1956 We're looking at how the 8byte alignment affects stack layout | |
| 1957 and where we had to pad things. This emits information we can | |
| 1958 extract which tells us about frame sizes and the like. */ | |
| 1959 fprintf (asm_out_file, | |
| 1960 "\t.equ\t__$frame$info$_%s_$_%d_%d_x%x_%d_%d_%d,0\n", | |
| 1961 mcore_current_function_name, | |
| 1962 fi.arg_size, fi.reg_size, fi.reg_mask, | |
| 1963 fi.local_size, fi.outbound_size, | |
| 1964 frame_pointer_needed); | |
| 1965 } | |
| 1966 | |
| 1967 if (mcore_naked_function_p ()) | |
| 1968 return; | |
| 1969 | |
| 1970 /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */ | |
| 1971 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */ | |
| 1972 | |
| 1973 /* If we have a parameter passed partially in regs and partially in memory, | |
| 1974 the registers will have been stored to memory already in function.c. So | |
| 1975 we only need to do something here for varargs functions. */ | |
| 1976 if (fi.arg_size != 0 && crtl->args.pretend_args_size == 0) | |
| 1977 { | |
| 1978 int offset; | |
| 1979 int rn = FIRST_PARM_REG + NPARM_REGS - 1; | |
| 1980 int remaining = fi.arg_size; | |
| 1981 | |
| 1982 for (offset = fi.arg_offset; remaining >= 4; offset -= 4, rn--, remaining -= 4) | |
| 1983 { | |
| 1984 emit_insn (gen_movsi | |
| 1985 (gen_rtx_MEM (SImode, | |
| 1986 plus_constant (stack_pointer_rtx, offset)), | |
| 1987 gen_rtx_REG (SImode, rn))); | |
| 1988 } | |
| 1989 } | |
| 1990 | |
| 1991 /* Do we need another stack adjustment before we do the register saves? */ | |
| 1992 if (growth < fi.reg_growth) | |
| 1993 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */ | |
| 1994 | |
| 1995 if (fi.reg_size != 0) | |
| 1996 { | |
| 1997 int i; | |
| 1998 int offs = fi.reg_offset; | |
| 1999 | |
| 2000 for (i = 15; i >= 0; i--) | |
| 2001 { | |
| 2002 if (offs == 0 && i == 15 && ((fi.reg_mask & 0xc000) == 0xc000)) | |
| 2003 { | |
| 2004 int first_reg = 15; | |
| 2005 | |
| 2006 while (fi.reg_mask & (1 << first_reg)) | |
| 2007 first_reg--; | |
| 2008 first_reg++; | |
| 2009 | |
| 2010 emit_insn (gen_store_multiple (gen_rtx_MEM (SImode, stack_pointer_rtx), | |
| 2011 gen_rtx_REG (SImode, first_reg), | |
| 2012 GEN_INT (16 - first_reg))); | |
| 2013 | |
| 2014 i -= (15 - first_reg); | |
| 2015 offs += (16 - first_reg) * 4; | |
| 2016 } | |
| 2017 else if (fi.reg_mask & (1 << i)) | |
| 2018 { | |
| 2019 emit_insn (gen_movsi | |
| 2020 (gen_rtx_MEM (SImode, | |
| 2021 plus_constant (stack_pointer_rtx, offs)), | |
| 2022 gen_rtx_REG (SImode, i))); | |
| 2023 offs += 4; | |
| 2024 } | |
| 2025 } | |
| 2026 } | |
| 2027 | |
| 2028 /* Figure the locals + outbounds. */ | |
| 2029 if (frame_pointer_needed) | |
| 2030 { | |
| 2031 /* If we haven't already purchased to 'fp'. */ | |
| 2032 if (growth < fi.local_growth) | |
| 2033 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */ | |
| 2034 | |
| 2035 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx)); | |
| 2036 | |
| 2037 /* ... and then go any remaining distance for outbounds, etc. */ | |
| 2038 if (fi.growth[growth]) | |
| 2039 output_stack_adjust (-1, fi.growth[growth++]); | |
| 2040 } | |
| 2041 else | |
| 2042 { | |
| 2043 if (growth < fi.local_growth) | |
| 2044 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */ | |
| 2045 if (fi.growth[growth]) | |
| 2046 output_stack_adjust (-1, fi.growth[growth++]); | |
| 2047 } | |
| 2048 } | |
| 2049 | |
| 2050 void | |
| 2051 mcore_expand_epilog (void) | |
| 2052 { | |
| 2053 struct mcore_frame fi; | |
| 2054 int i; | |
| 2055 int offs; | |
| 2056 int growth = MAX_STACK_GROWS - 1 ; | |
| 2057 | |
| 2058 | |
| 2059 /* Find out what we're doing. */ | |
| 2060 layout_mcore_frame(&fi); | |
| 2061 | |
| 2062 if (mcore_naked_function_p ()) | |
| 2063 return; | |
| 2064 | |
| 2065 /* If we had a frame pointer, restore the sp from that. */ | |
| 2066 if (frame_pointer_needed) | |
| 2067 { | |
| 2068 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx)); | |
| 2069 growth = fi.local_growth - 1; | |
| 2070 } | |
| 2071 else | |
| 2072 { | |
| 2073 /* XXX: while loop should accumulate and do a single sell. */ | |
| 2074 while (growth >= fi.local_growth) | |
| 2075 { | |
| 2076 if (fi.growth[growth] != 0) | |
| 2077 output_stack_adjust (1, fi.growth[growth]); | |
| 2078 growth--; | |
| 2079 } | |
| 2080 } | |
| 2081 | |
| 2082 /* Make sure we've shrunk stack back to the point where the registers | |
| 2083 were laid down. This is typically 0/1 iterations. Then pull the | |
| 2084 register save information back off the stack. */ | |
| 2085 while (growth >= fi.reg_growth) | |
| 2086 output_stack_adjust ( 1, fi.growth[growth--]); | |
| 2087 | |
| 2088 offs = fi.reg_offset; | |
| 2089 | |
| 2090 for (i = 15; i >= 0; i--) | |
| 2091 { | |
| 2092 if (offs == 0 && i == 15 && ((fi.reg_mask & 0xc000) == 0xc000)) | |
| 2093 { | |
| 2094 int first_reg; | |
| 2095 | |
| 2096 /* Find the starting register. */ | |
| 2097 first_reg = 15; | |
| 2098 | |
| 2099 while (fi.reg_mask & (1 << first_reg)) | |
| 2100 first_reg--; | |
| 2101 | |
| 2102 first_reg++; | |
| 2103 | |
| 2104 emit_insn (gen_load_multiple (gen_rtx_REG (SImode, first_reg), | |
| 2105 gen_rtx_MEM (SImode, stack_pointer_rtx), | |
| 2106 GEN_INT (16 - first_reg))); | |
| 2107 | |
| 2108 i -= (15 - first_reg); | |
| 2109 offs += (16 - first_reg) * 4; | |
| 2110 } | |
| 2111 else if (fi.reg_mask & (1 << i)) | |
| 2112 { | |
| 2113 emit_insn (gen_movsi | |
| 2114 (gen_rtx_REG (SImode, i), | |
| 2115 gen_rtx_MEM (SImode, | |
| 2116 plus_constant (stack_pointer_rtx, offs)))); | |
| 2117 offs += 4; | |
| 2118 } | |
| 2119 } | |
| 2120 | |
| 2121 /* Give back anything else. */ | |
| 2122 /* XXX: Should accumulate total and then give it back. */ | |
| 2123 while (growth >= 0) | |
| 2124 output_stack_adjust ( 1, fi.growth[growth--]); | |
| 2125 } | |
| 2126 | |
| 2127 /* This code is borrowed from the SH port. */ | |
| 2128 | |
| 2129 /* The MCORE cannot load a large constant into a register, constants have to | |
| 2130 come from a pc relative load. The reference of a pc relative load | |
| 2131 instruction must be less than 1k in front of the instruction. This | |
| 2132 means that we often have to dump a constant inside a function, and | |
| 2133 generate code to branch around it. | |
| 2134 | |
| 2135 It is important to minimize this, since the branches will slow things | |
| 2136 down and make things bigger. | |
| 2137 | |
| 2138 Worst case code looks like: | |
| 2139 | |
| 2140 lrw L1,r0 | |
| 2141 br L2 | |
| 2142 align | |
| 2143 L1: .long value | |
| 2144 L2: | |
| 2145 .. | |
| 2146 | |
| 2147 lrw L3,r0 | |
| 2148 br L4 | |
| 2149 align | |
| 2150 L3: .long value | |
| 2151 L4: | |
| 2152 .. | |
| 2153 | |
| 2154 We fix this by performing a scan before scheduling, which notices which | |
| 2155 instructions need to have their operands fetched from the constant table | |
| 2156 and builds the table. | |
| 2157 | |
| 2158 The algorithm is: | |
| 2159 | |
| 2160 scan, find an instruction which needs a pcrel move. Look forward, find the | |
| 2161 last barrier which is within MAX_COUNT bytes of the requirement. | |
| 2162 If there isn't one, make one. Process all the instructions between | |
| 2163 the find and the barrier. | |
| 2164 | |
| 2165 In the above example, we can tell that L3 is within 1k of L1, so | |
| 2166 the first move can be shrunk from the 2 insn+constant sequence into | |
| 2167 just 1 insn, and the constant moved to L3 to make: | |
| 2168 | |
| 2169 lrw L1,r0 | |
| 2170 .. | |
| 2171 lrw L3,r0 | |
| 2172 bra L4 | |
| 2173 align | |
| 2174 L3:.long value | |
| 2175 L4:.long value | |
| 2176 | |
| 2177 Then the second move becomes the target for the shortening process. */ | |
| 2178 | |
| 2179 typedef struct | |
| 2180 { | |
| 2181 rtx value; /* Value in table. */ | |
| 2182 rtx label; /* Label of value. */ | |
| 2183 } pool_node; | |
| 2184 | |
| 2185 /* The maximum number of constants that can fit into one pool, since | |
| 2186 the pc relative range is 0...1020 bytes and constants are at least 4 | |
| 2187 bytes long. We subtract 4 from the range to allow for the case where | |
| 2188 we need to add a branch/align before the constant pool. */ | |
| 2189 | |
| 2190 #define MAX_COUNT 1016 | |
| 2191 #define MAX_POOL_SIZE (MAX_COUNT/4) | |
| 2192 static pool_node pool_vector[MAX_POOL_SIZE]; | |
| 2193 static int pool_size; | |
| 2194 | |
| 2195 /* Dump out any constants accumulated in the final pass. These | |
| 2196 will only be labels. */ | |
| 2197 | |
| 2198 const char * | |
| 2199 mcore_output_jump_label_table (void) | |
| 2200 { | |
| 2201 int i; | |
| 2202 | |
| 2203 if (pool_size) | |
| 2204 { | |
| 2205 fprintf (asm_out_file, "\t.align 2\n"); | |
| 2206 | |
| 2207 for (i = 0; i < pool_size; i++) | |
| 2208 { | |
| 2209 pool_node * p = pool_vector + i; | |
| 2210 | |
| 2211 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (p->label)); | |
| 2212 | |
| 2213 output_asm_insn (".long %0", &p->value); | |
| 2214 } | |
| 2215 | |
| 2216 pool_size = 0; | |
| 2217 } | |
| 2218 | |
| 2219 return ""; | |
| 2220 } | |
| 2221 | |
| 2222 /* Check whether insn is a candidate for a conditional. */ | |
| 2223 | |
| 2224 static cond_type | |
| 2225 is_cond_candidate (rtx insn) | |
| 2226 { | |
| 2227 /* The only things we conditionalize are those that can be directly | |
| 2228 changed into a conditional. Only bother with SImode items. If | |
| 2229 we wanted to be a little more aggressive, we could also do other | |
| 2230 modes such as DImode with reg-reg move or load 0. */ | |
| 2231 if (GET_CODE (insn) == INSN) | |
| 2232 { | |
| 2233 rtx pat = PATTERN (insn); | |
| 2234 rtx src, dst; | |
| 2235 | |
| 2236 if (GET_CODE (pat) != SET) | |
| 2237 return COND_NO; | |
| 2238 | |
| 2239 dst = XEXP (pat, 0); | |
| 2240 | |
| 2241 if ((GET_CODE (dst) != REG && | |
| 2242 GET_CODE (dst) != SUBREG) || | |
| 2243 GET_MODE (dst) != SImode) | |
| 2244 return COND_NO; | |
| 2245 | |
| 2246 src = XEXP (pat, 1); | |
| 2247 | |
| 2248 if ((GET_CODE (src) == REG || | |
| 2249 (GET_CODE (src) == SUBREG && | |
| 2250 GET_CODE (SUBREG_REG (src)) == REG)) && | |
| 2251 GET_MODE (src) == SImode) | |
| 2252 return COND_MOV_INSN; | |
| 2253 else if (GET_CODE (src) == CONST_INT && | |
| 2254 INTVAL (src) == 0) | |
| 2255 return COND_CLR_INSN; | |
| 2256 else if (GET_CODE (src) == PLUS && | |
| 2257 (GET_CODE (XEXP (src, 0)) == REG || | |
| 2258 (GET_CODE (XEXP (src, 0)) == SUBREG && | |
| 2259 GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) && | |
| 2260 GET_MODE (XEXP (src, 0)) == SImode && | |
| 2261 GET_CODE (XEXP (src, 1)) == CONST_INT && | |
| 2262 INTVAL (XEXP (src, 1)) == 1) | |
| 2263 return COND_INC_INSN; | |
| 2264 else if (((GET_CODE (src) == MINUS && | |
| 2265 GET_CODE (XEXP (src, 1)) == CONST_INT && | |
| 2266 INTVAL( XEXP (src, 1)) == 1) || | |
| 2267 (GET_CODE (src) == PLUS && | |
| 2268 GET_CODE (XEXP (src, 1)) == CONST_INT && | |
| 2269 INTVAL (XEXP (src, 1)) == -1)) && | |
| 2270 (GET_CODE (XEXP (src, 0)) == REG || | |
| 2271 (GET_CODE (XEXP (src, 0)) == SUBREG && | |
| 2272 GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) && | |
| 2273 GET_MODE (XEXP (src, 0)) == SImode) | |
| 2274 return COND_DEC_INSN; | |
| 2275 | |
| 2276 /* Some insns that we don't bother with: | |
| 2277 (set (rx:DI) (ry:DI)) | |
| 2278 (set (rx:DI) (const_int 0)) | |
| 2279 */ | |
| 2280 | |
| 2281 } | |
| 2282 else if (GET_CODE (insn) == JUMP_INSN && | |
| 2283 GET_CODE (PATTERN (insn)) == SET && | |
| 2284 GET_CODE (XEXP (PATTERN (insn), 1)) == LABEL_REF) | |
| 2285 return COND_BRANCH_INSN; | |
| 2286 | |
| 2287 return COND_NO; | |
| 2288 } | |
| 2289 | |
| 2290 /* Emit a conditional version of insn and replace the old insn with the | |
| 2291 new one. Return the new insn if emitted. */ | |
| 2292 | |
| 2293 static rtx | |
| 2294 emit_new_cond_insn (rtx insn, int cond) | |
| 2295 { | |
| 2296 rtx c_insn = 0; | |
| 2297 rtx pat, dst, src; | |
| 2298 cond_type num; | |
| 2299 | |
| 2300 if ((num = is_cond_candidate (insn)) == COND_NO) | |
| 2301 return NULL; | |
| 2302 | |
| 2303 pat = PATTERN (insn); | |
| 2304 | |
| 2305 if (GET_CODE (insn) == INSN) | |
| 2306 { | |
| 2307 dst = SET_DEST (pat); | |
| 2308 src = SET_SRC (pat); | |
| 2309 } | |
| 2310 else | |
| 2311 { | |
| 2312 dst = JUMP_LABEL (insn); | |
| 2313 src = NULL_RTX; | |
| 2314 } | |
| 2315 | |
| 2316 switch (num) | |
| 2317 { | |
| 2318 case COND_MOV_INSN: | |
| 2319 case COND_CLR_INSN: | |
| 2320 if (cond) | |
| 2321 c_insn = gen_movt0 (dst, src, dst); | |
| 2322 else | |
| 2323 c_insn = gen_movt0 (dst, dst, src); | |
| 2324 break; | |
| 2325 | |
| 2326 case COND_INC_INSN: | |
| 2327 if (cond) | |
| 2328 c_insn = gen_incscc (dst, dst); | |
| 2329 else | |
| 2330 c_insn = gen_incscc_false (dst, dst); | |
| 2331 break; | |
| 2332 | |
| 2333 case COND_DEC_INSN: | |
| 2334 if (cond) | |
| 2335 c_insn = gen_decscc (dst, dst); | |
| 2336 else | |
| 2337 c_insn = gen_decscc_false (dst, dst); | |
| 2338 break; | |
| 2339 | |
| 2340 case COND_BRANCH_INSN: | |
| 2341 if (cond) | |
| 2342 c_insn = gen_branch_true (dst); | |
| 2343 else | |
| 2344 c_insn = gen_branch_false (dst); | |
| 2345 break; | |
| 2346 | |
| 2347 default: | |
| 2348 return NULL; | |
| 2349 } | |
| 2350 | |
| 2351 /* Only copy the notes if they exist. */ | |
| 2352 if (rtx_length [GET_CODE (c_insn)] >= 7 && rtx_length [GET_CODE (insn)] >= 7) | |
| 2353 { | |
| 2354 /* We really don't need to bother with the notes and links at this | |
| 2355 point, but go ahead and save the notes. This will help is_dead() | |
| 2356 when applying peepholes (links don't matter since they are not | |
| 2357 used any more beyond this point for the mcore). */ | |
| 2358 REG_NOTES (c_insn) = REG_NOTES (insn); | |
| 2359 } | |
| 2360 | |
| 2361 if (num == COND_BRANCH_INSN) | |
| 2362 { | |
| 2363 /* For jumps, we need to be a little bit careful and emit the new jump | |
| 2364 before the old one and to update the use count for the target label. | |
| 2365 This way, the barrier following the old (uncond) jump will get | |
| 2366 deleted, but the label won't. */ | |
| 2367 c_insn = emit_jump_insn_before (c_insn, insn); | |
| 2368 | |
| 2369 ++ LABEL_NUSES (dst); | |
| 2370 | |
| 2371 JUMP_LABEL (c_insn) = dst; | |
| 2372 } | |
| 2373 else | |
| 2374 c_insn = emit_insn_after (c_insn, insn); | |
| 2375 | |
| 2376 delete_insn (insn); | |
| 2377 | |
| 2378 return c_insn; | |
| 2379 } | |
| 2380 | |
| 2381 /* Attempt to change a basic block into a series of conditional insns. This | |
| 2382 works by taking the branch at the end of the 1st block and scanning for the | |
| 2383 end of the 2nd block. If all instructions in the 2nd block have cond. | |
| 2384 versions and the label at the start of block 3 is the same as the target | |
| 2385 from the branch at block 1, then conditionalize all insn in block 2 using | |
| 2386 the inverse condition of the branch at block 1. (Note I'm bending the | |
| 2387 definition of basic block here.) | |
| 2388 | |
| 2389 e.g., change: | |
| 2390 | |
| 2391 bt L2 <-- end of block 1 (delete) | |
| 2392 mov r7,r8 | |
| 2393 addu r7,1 | |
| 2394 br L3 <-- end of block 2 | |
| 2395 | |
| 2396 L2: ... <-- start of block 3 (NUSES==1) | |
| 2397 L3: ... | |
| 2398 | |
| 2399 to: | |
| 2400 | |
| 2401 movf r7,r8 | |
| 2402 incf r7 | |
| 2403 bf L3 | |
| 2404 | |
| 2405 L3: ... | |
| 2406 | |
| 2407 we can delete the L2 label if NUSES==1 and re-apply the optimization | |
| 2408 starting at the last instruction of block 2. This may allow an entire | |
| 2409 if-then-else statement to be conditionalized. BRC */ | |
| 2410 static rtx | |
| 2411 conditionalize_block (rtx first) | |
| 2412 { | |
| 2413 rtx insn; | |
| 2414 rtx br_pat; | |
| 2415 rtx end_blk_1_br = 0; | |
| 2416 rtx end_blk_2_insn = 0; | |
| 2417 rtx start_blk_3_lab = 0; | |
| 2418 int cond; | |
| 2419 int br_lab_num; | |
| 2420 int blk_size = 0; | |
| 2421 | |
| 2422 | |
| 2423 /* Check that the first insn is a candidate conditional jump. This is | |
| 2424 the one that we'll eliminate. If not, advance to the next insn to | |
| 2425 try. */ | |
| 2426 if (GET_CODE (first) != JUMP_INSN || | |
| 2427 GET_CODE (PATTERN (first)) != SET || | |
| 2428 GET_CODE (XEXP (PATTERN (first), 1)) != IF_THEN_ELSE) | |
| 2429 return NEXT_INSN (first); | |
| 2430 | |
| 2431 /* Extract some information we need. */ | |
| 2432 end_blk_1_br = first; | |
| 2433 br_pat = PATTERN (end_blk_1_br); | |
| 2434 | |
| 2435 /* Complement the condition since we use the reverse cond. for the insns. */ | |
| 2436 cond = (GET_CODE (XEXP (XEXP (br_pat, 1), 0)) == EQ); | |
| 2437 | |
| 2438 /* Determine what kind of branch we have. */ | |
| 2439 if (GET_CODE (XEXP (XEXP (br_pat, 1), 1)) == LABEL_REF) | |
| 2440 { | |
| 2441 /* A normal branch, so extract label out of first arm. */ | |
| 2442 br_lab_num = CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat, 1), 1), 0)); | |
| 2443 } | |
| 2444 else | |
| 2445 { | |
| 2446 /* An inverse branch, so extract the label out of the 2nd arm | |
| 2447 and complement the condition. */ | |
| 2448 cond = (cond == 0); | |
| 2449 br_lab_num = CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat, 1), 2), 0)); | |
| 2450 } | |
| 2451 | |
| 2452 /* Scan forward for the start of block 2: it must start with a | |
| 2453 label and that label must be the same as the branch target | |
| 2454 label from block 1. We don't care about whether block 2 actually | |
| 2455 ends with a branch or a label (an uncond. branch is | |
| 2456 conditionalizable). */ | |
| 2457 for (insn = NEXT_INSN (first); insn; insn = NEXT_INSN (insn)) | |
| 2458 { | |
| 2459 enum rtx_code code; | |
| 2460 | |
| 2461 code = GET_CODE (insn); | |
| 2462 | |
| 2463 /* Look for the label at the start of block 3. */ | |
| 2464 if (code == CODE_LABEL && CODE_LABEL_NUMBER (insn) == br_lab_num) | |
| 2465 break; | |
| 2466 | |
| 2467 /* Skip barriers, notes, and conditionalizable insns. If the | |
| 2468 insn is not conditionalizable or makes this optimization fail, | |
| 2469 just return the next insn so we can start over from that point. */ | |
| 2470 if (code != BARRIER && code != NOTE && !is_cond_candidate (insn)) | |
| 2471 return NEXT_INSN (insn); | |
| 2472 | |
| 2473 /* Remember the last real insn before the label (i.e. end of block 2). */ | |
| 2474 if (code == JUMP_INSN || code == INSN) | |
| 2475 { | |
| 2476 blk_size ++; | |
| 2477 end_blk_2_insn = insn; | |
| 2478 } | |
| 2479 } | |
| 2480 | |
| 2481 if (!insn) | |
| 2482 return insn; | |
| 2483 | |
| 2484 /* It is possible for this optimization to slow performance if the blocks | |
| 2485 are long. This really depends upon whether the branch is likely taken | |
| 2486 or not. If the branch is taken, we slow performance in many cases. But, | |
| 2487 if the branch is not taken, we always help performance (for a single | |
| 2488 block, but for a double block (i.e. when the optimization is re-applied) | |
| 2489 this is not true since the 'right thing' depends on the overall length of | |
| 2490 the collapsed block). As a compromise, don't apply this optimization on | |
| 2491 blocks larger than size 2 (unlikely for the mcore) when speed is important. | |
| 2492 the best threshold depends on the latencies of the instructions (i.e., | |
| 2493 the branch penalty). */ | |
| 2494 if (optimize > 1 && blk_size > 2) | |
| 2495 return insn; | |
| 2496 | |
| 2497 /* At this point, we've found the start of block 3 and we know that | |
| 2498 it is the destination of the branch from block 1. Also, all | |
| 2499 instructions in the block 2 are conditionalizable. So, apply the | |
| 2500 conditionalization and delete the branch. */ | |
| 2501 start_blk_3_lab = insn; | |
| 2502 | |
| 2503 for (insn = NEXT_INSN (end_blk_1_br); insn != start_blk_3_lab; | |
| 2504 insn = NEXT_INSN (insn)) | |
| 2505 { | |
| 2506 rtx newinsn; | |
| 2507 | |
| 2508 if (INSN_DELETED_P (insn)) | |
| 2509 continue; | |
| 2510 | |
| 2511 /* Try to form a conditional variant of the instruction and emit it. */ | |
| 2512 if ((newinsn = emit_new_cond_insn (insn, cond))) | |
| 2513 { | |
| 2514 if (end_blk_2_insn == insn) | |
| 2515 end_blk_2_insn = newinsn; | |
| 2516 | |
| 2517 insn = newinsn; | |
| 2518 } | |
| 2519 } | |
| 2520 | |
| 2521 /* Note whether we will delete the label starting blk 3 when the jump | |
| 2522 gets deleted. If so, we want to re-apply this optimization at the | |
| 2523 last real instruction right before the label. */ | |
| 2524 if (LABEL_NUSES (start_blk_3_lab) == 1) | |
| 2525 { | |
| 2526 start_blk_3_lab = 0; | |
| 2527 } | |
| 2528 | |
| 2529 /* ??? we probably should redistribute the death notes for this insn, esp. | |
| 2530 the death of cc, but it doesn't really matter this late in the game. | |
| 2531 The peepholes all use is_dead() which will find the correct death | |
| 2532 regardless of whether there is a note. */ | |
| 2533 delete_insn (end_blk_1_br); | |
| 2534 | |
| 2535 if (! start_blk_3_lab) | |
| 2536 return end_blk_2_insn; | |
| 2537 | |
| 2538 /* Return the insn right after the label at the start of block 3. */ | |
| 2539 return NEXT_INSN (start_blk_3_lab); | |
| 2540 } | |
| 2541 | |
| 2542 /* Apply the conditionalization of blocks optimization. This is the | |
| 2543 outer loop that traverses through the insns scanning for a branch | |
| 2544 that signifies an opportunity to apply the optimization. Note that | |
| 2545 this optimization is applied late. If we could apply it earlier, | |
| 2546 say before cse 2, it may expose more optimization opportunities. | |
| 2547 but, the pay back probably isn't really worth the effort (we'd have | |
| 2548 to update all reg/flow/notes/links/etc to make it work - and stick it | |
| 2549 in before cse 2). */ | |
| 2550 | |
| 2551 static void | |
| 2552 conditionalize_optimization (void) | |
| 2553 { | |
| 2554 rtx insn; | |
| 2555 | |
| 2556 for (insn = get_insns (); insn; insn = conditionalize_block (insn)) | |
| 2557 continue; | |
| 2558 } | |
| 2559 | |
| 2560 static int saved_warn_return_type = -1; | |
| 2561 static int saved_warn_return_type_count = 0; | |
| 2562 | |
| 2563 /* This is to handle loads from the constant pool. */ | |
| 2564 | |
| 2565 static void | |
| 2566 mcore_reorg (void) | |
| 2567 { | |
| 2568 /* Reset this variable. */ | |
| 2569 current_function_anonymous_args = 0; | |
| 2570 | |
| 2571 /* Restore the warn_return_type if it has been altered. */ | |
| 2572 if (saved_warn_return_type != -1) | |
| 2573 { | |
| 2574 /* Only restore the value if we have reached another function. | |
| 2575 The test of warn_return_type occurs in final_function () in | |
| 2576 c-decl.c a long time after the code for the function is generated, | |
| 2577 so we need a counter to tell us when we have finished parsing that | |
| 2578 function and can restore the flag. */ | |
| 2579 if (--saved_warn_return_type_count == 0) | |
| 2580 { | |
| 2581 warn_return_type = saved_warn_return_type; | |
| 2582 saved_warn_return_type = -1; | |
| 2583 } | |
| 2584 } | |
| 2585 | |
| 2586 if (optimize == 0) | |
| 2587 return; | |
| 2588 | |
| 2589 /* Conditionalize blocks where we can. */ | |
| 2590 conditionalize_optimization (); | |
| 2591 | |
| 2592 /* Literal pool generation is now pushed off until the assembler. */ | |
| 2593 } | |
| 2594 | |
| 2595 | |
| 2596 /* Return true if X is something that can be moved directly into r15. */ | |
| 2597 | |
| 2598 bool | |
| 2599 mcore_r15_operand_p (rtx x) | |
| 2600 { | |
| 2601 switch (GET_CODE (x)) | |
| 2602 { | |
| 2603 case CONST_INT: | |
| 2604 return mcore_const_ok_for_inline (INTVAL (x)); | |
| 2605 | |
| 2606 case REG: | |
| 2607 case SUBREG: | |
| 2608 case MEM: | |
| 2609 return 1; | |
| 2610 | |
| 2611 default: | |
| 2612 return 0; | |
| 2613 } | |
| 2614 } | |
| 2615 | |
| 2616 /* Implement SECONDARY_RELOAD_CLASS. If RCLASS contains r15, and we can't | |
| 2617 directly move X into it, use r1-r14 as a temporary. */ | |
| 2618 | |
| 2619 enum reg_class | |
| 2620 mcore_secondary_reload_class (enum reg_class rclass, | |
| 2621 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
| 2622 { | |
| 2623 if (TEST_HARD_REG_BIT (reg_class_contents[rclass], 15) | |
| 2624 && !mcore_r15_operand_p (x)) | |
| 2625 return LRW_REGS; | |
| 2626 return NO_REGS; | |
| 2627 } | |
| 2628 | |
| 2629 /* Return the reg_class to use when reloading the rtx X into the class | |
| 2630 RCLASS. If X is too complex to move directly into r15, prefer to | |
| 2631 use LRW_REGS instead. */ | |
| 2632 | |
| 2633 enum reg_class | |
| 2634 mcore_reload_class (rtx x, enum reg_class rclass) | |
| 2635 { | |
| 2636 if (reg_class_subset_p (LRW_REGS, rclass) && !mcore_r15_operand_p (x)) | |
| 2637 return LRW_REGS; | |
| 2638 | |
| 2639 return rclass; | |
| 2640 } | |
| 2641 | |
| 2642 /* Tell me if a pair of reg/subreg rtx's actually refer to the same | |
| 2643 register. Note that the current version doesn't worry about whether | |
| 2644 they are the same mode or note (e.g., a QImode in r2 matches an HImode | |
| 2645 in r2 matches an SImode in r2. Might think in the future about whether | |
| 2646 we want to be able to say something about modes. */ | |
| 2647 | |
| 2648 int | |
| 2649 mcore_is_same_reg (rtx x, rtx y) | |
| 2650 { | |
| 2651 /* Strip any and all of the subreg wrappers. */ | |
| 2652 while (GET_CODE (x) == SUBREG) | |
| 2653 x = SUBREG_REG (x); | |
| 2654 | |
| 2655 while (GET_CODE (y) == SUBREG) | |
| 2656 y = SUBREG_REG (y); | |
| 2657 | |
| 2658 if (GET_CODE(x) == REG && GET_CODE(y) == REG && REGNO(x) == REGNO(y)) | |
| 2659 return 1; | |
| 2660 | |
| 2661 return 0; | |
| 2662 } | |
| 2663 | |
| 2664 void | |
| 2665 mcore_override_options (void) | |
| 2666 { | |
| 2667 /* Only the m340 supports little endian code. */ | |
| 2668 if (TARGET_LITTLE_END && ! TARGET_M340) | |
| 2669 target_flags |= MASK_M340; | |
| 2670 } | |
| 2671 | |
| 2672 /* Compute the number of word sized registers needed to | |
| 2673 hold a function argument of mode MODE and type TYPE. */ | |
| 2674 | |
| 2675 int | |
| 2676 mcore_num_arg_regs (enum machine_mode mode, const_tree type) | |
| 2677 { | |
| 2678 int size; | |
| 2679 | |
| 2680 if (targetm.calls.must_pass_in_stack (mode, type)) | |
| 2681 return 0; | |
| 2682 | |
| 2683 if (type && mode == BLKmode) | |
| 2684 size = int_size_in_bytes (type); | |
| 2685 else | |
| 2686 size = GET_MODE_SIZE (mode); | |
| 2687 | |
| 2688 return ROUND_ADVANCE (size); | |
| 2689 } | |
| 2690 | |
| 2691 static rtx | |
| 2692 handle_structs_in_regs (enum machine_mode mode, const_tree type, int reg) | |
| 2693 { | |
| 2694 int size; | |
| 2695 | |
| 2696 /* The MCore ABI defines that a structure whose size is not a whole multiple | |
| 2697 of bytes is passed packed into registers (or spilled onto the stack if | |
| 2698 not enough registers are available) with the last few bytes of the | |
| 2699 structure being packed, left-justified, into the last register/stack slot. | |
| 2700 GCC handles this correctly if the last word is in a stack slot, but we | |
| 2701 have to generate a special, PARALLEL RTX if the last word is in an | |
| 2702 argument register. */ | |
| 2703 if (type | |
| 2704 && TYPE_MODE (type) == BLKmode | |
| 2705 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
| 2706 && (size = int_size_in_bytes (type)) > UNITS_PER_WORD | |
| 2707 && (size % UNITS_PER_WORD != 0) | |
| 2708 && (reg + mcore_num_arg_regs (mode, type) <= (FIRST_PARM_REG + NPARM_REGS))) | |
| 2709 { | |
| 2710 rtx arg_regs [NPARM_REGS]; | |
| 2711 int nregs; | |
| 2712 rtx result; | |
| 2713 rtvec rtvec; | |
| 2714 | |
| 2715 for (nregs = 0; size > 0; size -= UNITS_PER_WORD) | |
| 2716 { | |
| 2717 arg_regs [nregs] = | |
| 2718 gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, reg ++), | |
| 2719 GEN_INT (nregs * UNITS_PER_WORD)); | |
| 2720 nregs ++; | |
| 2721 } | |
| 2722 | |
| 2723 /* We assume here that NPARM_REGS == 6. The assert checks this. */ | |
| 2724 assert (ARRAY_SIZE (arg_regs) == 6); | |
| 2725 rtvec = gen_rtvec (nregs, arg_regs[0], arg_regs[1], arg_regs[2], | |
| 2726 arg_regs[3], arg_regs[4], arg_regs[5]); | |
| 2727 | |
| 2728 result = gen_rtx_PARALLEL (mode, rtvec); | |
| 2729 return result; | |
| 2730 } | |
| 2731 | |
| 2732 return gen_rtx_REG (mode, reg); | |
| 2733 } | |
| 2734 | |
| 2735 rtx | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2736 mcore_function_value (const_tree valtype, const_tree func) |
| 0 | 2737 { |
| 2738 enum machine_mode mode; | |
| 2739 int unsigned_p; | |
| 2740 | |
| 2741 mode = TYPE_MODE (valtype); | |
| 2742 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2743 /* Since we promote return types, we must promote the mode here too. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2744 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1); |
| 0 | 2745 |
| 2746 return handle_structs_in_regs (mode, valtype, FIRST_RET_REG); | |
| 2747 } | |
| 2748 | |
| 2749 /* Define where to put the arguments to a function. | |
| 2750 Value is zero to push the argument on the stack, | |
| 2751 or a hard register in which to store the argument. | |
| 2752 | |
| 2753 MODE is the argument's machine mode. | |
| 2754 TYPE is the data type of the argument (as a tree). | |
| 2755 This is null for libcalls where that information may | |
| 2756 not be available. | |
| 2757 CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
| 2758 the preceding args and about the function being called. | |
| 2759 NAMED is nonzero if this argument is a named parameter | |
| 2760 (otherwise it is an extra parameter matching an ellipsis). | |
| 2761 | |
| 2762 On MCore the first args are normally in registers | |
| 2763 and the rest are pushed. Any arg that starts within the first | |
| 2764 NPARM_REGS words is at least partially passed in a register unless | |
| 2765 its data type forbids. */ | |
| 2766 | |
| 2767 rtx | |
| 2768 mcore_function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode, | |
| 2769 tree type, int named) | |
| 2770 { | |
| 2771 int arg_reg; | |
| 2772 | |
| 2773 if (! named || mode == VOIDmode) | |
| 2774 return 0; | |
| 2775 | |
| 2776 if (targetm.calls.must_pass_in_stack (mode, type)) | |
| 2777 return 0; | |
| 2778 | |
| 2779 arg_reg = ROUND_REG (cum, mode); | |
| 2780 | |
| 2781 if (arg_reg < NPARM_REGS) | |
| 2782 return handle_structs_in_regs (mode, type, FIRST_PARM_REG + arg_reg); | |
| 2783 | |
| 2784 return 0; | |
| 2785 } | |
| 2786 | |
| 2787 /* Returns the number of bytes of argument registers required to hold *part* | |
| 2788 of a parameter of machine mode MODE and type TYPE (which may be NULL if | |
| 2789 the type is not known). If the argument fits entirely in the argument | |
| 2790 registers, or entirely on the stack, then 0 is returned. CUM is the | |
| 2791 number of argument registers already used by earlier parameters to | |
| 2792 the function. */ | |
| 2793 | |
| 2794 static int | |
| 2795 mcore_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
| 2796 tree type, bool named) | |
| 2797 { | |
| 2798 int reg = ROUND_REG (*cum, mode); | |
| 2799 | |
| 2800 if (named == 0) | |
| 2801 return 0; | |
| 2802 | |
| 2803 if (targetm.calls.must_pass_in_stack (mode, type)) | |
| 2804 return 0; | |
| 2805 | |
| 2806 /* REG is not the *hardware* register number of the register that holds | |
| 2807 the argument, it is the *argument* register number. So for example, | |
| 2808 the first argument to a function goes in argument register 0, which | |
| 2809 translates (for the MCore) into hardware register 2. The second | |
| 2810 argument goes into argument register 1, which translates into hardware | |
| 2811 register 3, and so on. NPARM_REGS is the number of argument registers | |
| 2812 supported by the target, not the maximum hardware register number of | |
| 2813 the target. */ | |
| 2814 if (reg >= NPARM_REGS) | |
| 2815 return 0; | |
| 2816 | |
| 2817 /* If the argument fits entirely in registers, return 0. */ | |
| 2818 if (reg + mcore_num_arg_regs (mode, type) <= NPARM_REGS) | |
| 2819 return 0; | |
| 2820 | |
| 2821 /* The argument overflows the number of available argument registers. | |
| 2822 Compute how many argument registers have not yet been assigned to | |
| 2823 hold an argument. */ | |
| 2824 reg = NPARM_REGS - reg; | |
| 2825 | |
| 2826 /* Return partially in registers and partially on the stack. */ | |
| 2827 return reg * UNITS_PER_WORD; | |
| 2828 } | |
| 2829 | |
| 2830 /* Return nonzero if SYMBOL is marked as being dllexport'd. */ | |
| 2831 | |
| 2832 int | |
| 2833 mcore_dllexport_name_p (const char * symbol) | |
| 2834 { | |
| 2835 return symbol[0] == '@' && symbol[1] == 'e' && symbol[2] == '.'; | |
| 2836 } | |
| 2837 | |
| 2838 /* Return nonzero if SYMBOL is marked as being dllimport'd. */ | |
| 2839 | |
| 2840 int | |
| 2841 mcore_dllimport_name_p (const char * symbol) | |
| 2842 { | |
| 2843 return symbol[0] == '@' && symbol[1] == 'i' && symbol[2] == '.'; | |
| 2844 } | |
| 2845 | |
| 2846 /* Mark a DECL as being dllexport'd. */ | |
| 2847 | |
| 2848 static void | |
| 2849 mcore_mark_dllexport (tree decl) | |
| 2850 { | |
| 2851 const char * oldname; | |
| 2852 char * newname; | |
| 2853 rtx rtlname; | |
| 2854 tree idp; | |
| 2855 | |
| 2856 rtlname = XEXP (DECL_RTL (decl), 0); | |
| 2857 | |
| 2858 if (GET_CODE (rtlname) == MEM) | |
| 2859 rtlname = XEXP (rtlname, 0); | |
| 2860 gcc_assert (GET_CODE (rtlname) == SYMBOL_REF); | |
| 2861 oldname = XSTR (rtlname, 0); | |
| 2862 | |
| 2863 if (mcore_dllexport_name_p (oldname)) | |
| 2864 return; /* Already done. */ | |
| 2865 | |
| 2866 newname = XALLOCAVEC (char, strlen (oldname) + 4); | |
| 2867 sprintf (newname, "@e.%s", oldname); | |
| 2868 | |
| 2869 /* We pass newname through get_identifier to ensure it has a unique | |
| 2870 address. RTL processing can sometimes peek inside the symbol ref | |
| 2871 and compare the string's addresses to see if two symbols are | |
| 2872 identical. */ | |
| 2873 /* ??? At least I think that's why we do this. */ | |
| 2874 idp = get_identifier (newname); | |
| 2875 | |
| 2876 XEXP (DECL_RTL (decl), 0) = | |
| 2877 gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (idp)); | |
| 2878 } | |
| 2879 | |
| 2880 /* Mark a DECL as being dllimport'd. */ | |
| 2881 | |
| 2882 static void | |
| 2883 mcore_mark_dllimport (tree decl) | |
| 2884 { | |
| 2885 const char * oldname; | |
| 2886 char * newname; | |
| 2887 tree idp; | |
| 2888 rtx rtlname; | |
| 2889 rtx newrtl; | |
| 2890 | |
| 2891 rtlname = XEXP (DECL_RTL (decl), 0); | |
| 2892 | |
| 2893 if (GET_CODE (rtlname) == MEM) | |
| 2894 rtlname = XEXP (rtlname, 0); | |
| 2895 gcc_assert (GET_CODE (rtlname) == SYMBOL_REF); | |
| 2896 oldname = XSTR (rtlname, 0); | |
| 2897 | |
| 2898 gcc_assert (!mcore_dllexport_name_p (oldname)); | |
| 2899 if (mcore_dllimport_name_p (oldname)) | |
| 2900 return; /* Already done. */ | |
| 2901 | |
| 2902 /* ??? One can well ask why we're making these checks here, | |
| 2903 and that would be a good question. */ | |
| 2904 | |
| 2905 /* Imported variables can't be initialized. */ | |
| 2906 if (TREE_CODE (decl) == VAR_DECL | |
| 2907 && !DECL_VIRTUAL_P (decl) | |
| 2908 && DECL_INITIAL (decl)) | |
| 2909 { | |
| 2910 error ("initialized variable %q+D is marked dllimport", decl); | |
| 2911 return; | |
| 2912 } | |
| 2913 | |
| 2914 /* `extern' needn't be specified with dllimport. | |
| 2915 Specify `extern' now and hope for the best. Sigh. */ | |
| 2916 if (TREE_CODE (decl) == VAR_DECL | |
| 2917 /* ??? Is this test for vtables needed? */ | |
| 2918 && !DECL_VIRTUAL_P (decl)) | |
| 2919 { | |
| 2920 DECL_EXTERNAL (decl) = 1; | |
| 2921 TREE_PUBLIC (decl) = 1; | |
| 2922 } | |
| 2923 | |
| 2924 newname = XALLOCAVEC (char, strlen (oldname) + 11); | |
| 2925 sprintf (newname, "@i.__imp_%s", oldname); | |
| 2926 | |
| 2927 /* We pass newname through get_identifier to ensure it has a unique | |
| 2928 address. RTL processing can sometimes peek inside the symbol ref | |
| 2929 and compare the string's addresses to see if two symbols are | |
| 2930 identical. */ | |
| 2931 /* ??? At least I think that's why we do this. */ | |
| 2932 idp = get_identifier (newname); | |
| 2933 | |
| 2934 newrtl = gen_rtx_MEM (Pmode, | |
| 2935 gen_rtx_SYMBOL_REF (Pmode, | |
| 2936 IDENTIFIER_POINTER (idp))); | |
| 2937 XEXP (DECL_RTL (decl), 0) = newrtl; | |
| 2938 } | |
| 2939 | |
| 2940 static int | |
| 2941 mcore_dllexport_p (tree decl) | |
| 2942 { | |
| 2943 if ( TREE_CODE (decl) != VAR_DECL | |
| 2944 && TREE_CODE (decl) != FUNCTION_DECL) | |
| 2945 return 0; | |
| 2946 | |
| 2947 return lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl)) != 0; | |
| 2948 } | |
| 2949 | |
| 2950 static int | |
| 2951 mcore_dllimport_p (tree decl) | |
| 2952 { | |
| 2953 if ( TREE_CODE (decl) != VAR_DECL | |
| 2954 && TREE_CODE (decl) != FUNCTION_DECL) | |
| 2955 return 0; | |
| 2956 | |
| 2957 return lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl)) != 0; | |
| 2958 } | |
| 2959 | |
| 2960 /* We must mark dll symbols specially. Definitions of dllexport'd objects | |
| 2961 install some info in the .drective (PE) or .exports (ELF) sections. */ | |
| 2962 | |
| 2963 static void | |
| 2964 mcore_encode_section_info (tree decl, rtx rtl ATTRIBUTE_UNUSED, int first ATTRIBUTE_UNUSED) | |
| 2965 { | |
| 2966 /* Mark the decl so we can tell from the rtl whether the object is | |
| 2967 dllexport'd or dllimport'd. */ | |
| 2968 if (mcore_dllexport_p (decl)) | |
| 2969 mcore_mark_dllexport (decl); | |
| 2970 else if (mcore_dllimport_p (decl)) | |
| 2971 mcore_mark_dllimport (decl); | |
| 2972 | |
| 2973 /* It might be that DECL has already been marked as dllimport, but | |
| 2974 a subsequent definition nullified that. The attribute is gone | |
| 2975 but DECL_RTL still has @i.__imp_foo. We need to remove that. */ | |
| 2976 else if ((TREE_CODE (decl) == FUNCTION_DECL | |
| 2977 || TREE_CODE (decl) == VAR_DECL) | |
| 2978 && DECL_RTL (decl) != NULL_RTX | |
| 2979 && GET_CODE (DECL_RTL (decl)) == MEM | |
| 2980 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == MEM | |
| 2981 && GET_CODE (XEXP (XEXP (DECL_RTL (decl), 0), 0)) == SYMBOL_REF | |
| 2982 && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0))) | |
| 2983 { | |
| 2984 const char * oldname = XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0); | |
| 2985 tree idp = get_identifier (oldname + 9); | |
| 2986 rtx newrtl = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (idp)); | |
| 2987 | |
| 2988 XEXP (DECL_RTL (decl), 0) = newrtl; | |
| 2989 | |
| 2990 /* We previously set TREE_PUBLIC and DECL_EXTERNAL. | |
| 2991 ??? We leave these alone for now. */ | |
| 2992 } | |
| 2993 } | |
| 2994 | |
| 2995 /* Undo the effects of the above. */ | |
| 2996 | |
| 2997 static const char * | |
| 2998 mcore_strip_name_encoding (const char * str) | |
| 2999 { | |
| 3000 return str + (str[0] == '@' ? 3 : 0); | |
| 3001 } | |
| 3002 | |
| 3003 /* MCore specific attribute support. | |
| 3004 dllexport - for exporting a function/variable that will live in a dll | |
| 3005 dllimport - for importing a function/variable from a dll | |
| 3006 naked - do not create a function prologue/epilogue. */ | |
| 3007 | |
| 3008 /* Handle a "naked" attribute; arguments as in | |
| 3009 struct attribute_spec.handler. */ | |
| 3010 | |
| 3011 static tree | |
| 3012 mcore_handle_naked_attribute (tree * node, tree name, tree args ATTRIBUTE_UNUSED, | |
| 3013 int flags ATTRIBUTE_UNUSED, bool * no_add_attrs) | |
| 3014 { | |
| 3015 if (TREE_CODE (*node) == FUNCTION_DECL) | |
| 3016 { | |
| 3017 /* PR14310 - don't complain about lack of return statement | |
| 3018 in naked functions. The solution here is a gross hack | |
| 3019 but this is the only way to solve the problem without | |
| 3020 adding a new feature to GCC. I did try submitting a patch | |
| 3021 that would add such a new feature, but it was (rightfully) | |
| 3022 rejected on the grounds that it was creeping featurism, | |
| 3023 so hence this code. */ | |
| 3024 if (warn_return_type) | |
| 3025 { | |
| 3026 saved_warn_return_type = warn_return_type; | |
| 3027 warn_return_type = 0; | |
| 3028 saved_warn_return_type_count = 2; | |
| 3029 } | |
| 3030 else if (saved_warn_return_type_count) | |
| 3031 saved_warn_return_type_count = 2; | |
| 3032 } | |
| 3033 else | |
| 3034 { | |
|
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3035 warning (OPT_Wattributes, "%qE attribute only applies to functions", |
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3036 name); |
| 0 | 3037 *no_add_attrs = true; |
| 3038 } | |
| 3039 | |
| 3040 return NULL_TREE; | |
| 3041 } | |
| 3042 | |
| 3043 /* ??? It looks like this is PE specific? Oh well, this is what the | |
| 3044 old code did as well. */ | |
| 3045 | |
| 3046 static void | |
| 3047 mcore_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) | |
| 3048 { | |
| 3049 int len; | |
| 3050 const char * name; | |
| 3051 char * string; | |
| 3052 const char * prefix; | |
| 3053 | |
| 3054 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
| 3055 | |
| 3056 /* Strip off any encoding in name. */ | |
| 3057 name = (* targetm.strip_name_encoding) (name); | |
| 3058 | |
| 3059 /* The object is put in, for example, section .text$foo. | |
| 3060 The linker will then ultimately place them in .text | |
| 3061 (everything from the $ on is stripped). */ | |
| 3062 if (TREE_CODE (decl) == FUNCTION_DECL) | |
| 3063 prefix = ".text$"; | |
| 3064 /* For compatibility with EPOC, we ignore the fact that the | |
| 3065 section might have relocs against it. */ | |
| 3066 else if (decl_readonly_section (decl, 0)) | |
| 3067 prefix = ".rdata$"; | |
| 3068 else | |
| 3069 prefix = ".data$"; | |
| 3070 | |
| 3071 len = strlen (name) + strlen (prefix); | |
| 3072 string = XALLOCAVEC (char, len + 1); | |
| 3073 | |
| 3074 sprintf (string, "%s%s", prefix, name); | |
| 3075 | |
| 3076 DECL_SECTION_NAME (decl) = build_string (len, string); | |
| 3077 } | |
| 3078 | |
| 3079 int | |
| 3080 mcore_naked_function_p (void) | |
| 3081 { | |
| 3082 return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE; | |
| 3083 } | |
| 3084 | |
| 3085 #ifdef OBJECT_FORMAT_ELF | |
| 3086 static void | |
| 3087 mcore_asm_named_section (const char *name, | |
| 3088 unsigned int flags ATTRIBUTE_UNUSED, | |
| 3089 tree decl ATTRIBUTE_UNUSED) | |
| 3090 { | |
| 3091 fprintf (asm_out_file, "\t.section %s\n", name); | |
| 3092 } | |
| 3093 #endif /* OBJECT_FORMAT_ELF */ | |
| 3094 | |
| 3095 /* Worker function for TARGET_ASM_EXTERNAL_LIBCALL. */ | |
| 3096 | |
| 3097 static void | |
| 3098 mcore_external_libcall (rtx fun) | |
| 3099 { | |
| 3100 fprintf (asm_out_file, "\t.import\t"); | |
| 3101 assemble_name (asm_out_file, XSTR (fun, 0)); | |
| 3102 fprintf (asm_out_file, "\n"); | |
| 3103 } | |
| 3104 | |
| 3105 /* Worker function for TARGET_RETURN_IN_MEMORY. */ | |
| 3106 | |
| 3107 static bool | |
| 3108 mcore_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) | |
| 3109 { | |
| 3110 const HOST_WIDE_INT size = int_size_in_bytes (type); | |
| 3111 return (size == -1 || size > 2 * UNITS_PER_WORD); | |
| 3112 } | |
|
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3113 |
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3114 /* Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE. |
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3115 Output assembler code for a block containing the constant parts |
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3116 of a trampoline, leaving space for the variable parts. |
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3117 |
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3118 On the MCore, the trampoline looks like: |
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3119 lrw r1, function |
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3120 lrw r13, area |
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3121 jmp r13 |
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3122 or r0, r0 |
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3123 .literals */ |
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3124 |
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3125 static void |
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3126 mcore_asm_trampoline_template (FILE *f) |
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3127 { |
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3128 fprintf (f, "\t.short 0x7102\n"); |
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3129 fprintf (f, "\t.short 0x7d02\n"); |
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3130 fprintf (f, "\t.short 0x00cd\n"); |
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3131 fprintf (f, "\t.short 0x1e00\n"); |
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3132 fprintf (f, "\t.long 0\n"); |
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3133 fprintf (f, "\t.long 0\n"); |
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3134 } |
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3135 |
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3136 /* Worker function for TARGET_TRAMPOLINE_INIT. */ |
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3137 |
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3138 static void |
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3139 mcore_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) |
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3140 { |
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3141 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); |
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3142 rtx mem; |
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3143 |
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3144 emit_block_move (m_tramp, assemble_trampoline_template (), |
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3145 GEN_INT (2*UNITS_PER_WORD), BLOCK_OP_NORMAL); |
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3146 |
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3147 mem = adjust_address (m_tramp, SImode, 8); |
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3148 emit_move_insn (mem, chain_value); |
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3149 mem = adjust_address (m_tramp, SImode, 12); |
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3150 emit_move_insn (mem, fnaddr); |
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3151 } |