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1 ;; DFA-based pipeline description for MIPS32 model 74k.
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2 ;; Contributed by MIPS Technologies and CodeSourcery.
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3 ;;
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4 ;; Reference:
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5 ;; "MIPS32 74K Microarchitecure Specification Rev. 01.02 Jun 15, 2006"
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6 ;; "MIPS32 74Kf Processor Core Datasheet Jun 2, 2006"
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7 ;;
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8 ;; Copyright (C) 2007 Free Software Foundation, Inc.
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9 ;;
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10 ;; This file is part of GCC.
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11 ;;
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12 ;; GCC is free software; you can redistribute it and/or modify it
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13 ;; under the terms of the GNU General Public License as published
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14 ;; by the Free Software Foundation; either version 3, or (at your
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15 ;; option) any later version.
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16
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17 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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18 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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19 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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20 ;; License for more details.
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21
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22 ;; You should have received a copy of the GNU General Public License
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23 ;; along with GCC; see the file COPYING3. If not see
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24 ;; <http://www.gnu.org/licenses/>.
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25
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26 (define_automaton "r74k_mdu_pipe, r74k_alu_pipe, r74k_agen_pipe, r74k_fpu")
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27 (define_cpu_unit "r74k_mul" "r74k_mdu_pipe")
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28 (define_cpu_unit "r74k_alu" "r74k_alu_pipe")
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29 (define_cpu_unit "r74k_agen" "r74k_agen_pipe")
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30 (define_cpu_unit "r74k_fpu_arith" "r74k_fpu")
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31 (define_cpu_unit "r74k_fpu_ldst" "r74k_fpu")
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32
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33 ;; --------------------------------------------------------------
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34 ;; Producers
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35 ;; --------------------------------------------------------------
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36
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37 ;; ALU: Logicals/Arithmetics
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38 ;; - Logicals, move (addu/addiu with rt = 0), Set less than,
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39 ;; sign extend - 1 cycle
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40 (define_insn_reservation "r74k_int_logical" 1
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41 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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42 (eq_attr "type" "logical,move,signext,slt"))
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43 "r74k_alu")
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44
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45 ;; - Arithmetics - 2 cycles
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46 (define_insn_reservation "r74k_int_arith" 2
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47 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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48 (eq_attr "type" "arith,const,shift,clz"))
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49 "r74k_alu")
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50
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51 (define_insn_reservation "r74k_int_nop" 0
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52 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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53 (eq_attr "type" "nop"))
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54 "nothing")
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55
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56 (define_insn_reservation "r74k_int_cmove" 4
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57 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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58 (eq_attr "type" "condmove"))
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59 "r74k_agen*2")
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60
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61 ;; MDU: fully pipelined multiplier
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62 ;; mult - delivers result to hi/lo in 4 cycle (pipelined)
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63 (define_insn_reservation "r74k_int_mult" 4
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64 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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65 (eq_attr "type" "imul"))
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66 "r74k_alu+r74k_mul")
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67
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68 ;; madd, msub - delivers result to hi/lo in 4 cycle (pipelined)
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69 (define_insn_reservation "r74k_int_madd" 4
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70 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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71 (eq_attr "type" "imadd"))
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72 "r74k_alu+r74k_mul")
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73
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74 ;; mul - delivers result to general register in 7 cycles
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75 (define_insn_reservation "r74k_int_mul3" 7
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76 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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77 (eq_attr "type" "imul3"))
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78 "r74k_alu+r74k_mul")
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79
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80 ;; mfhi, mflo, mflhxu - deliver result to gpr in 7 cycles
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81 (define_insn_reservation "r74k_int_mfhilo" 7
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82 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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83 (eq_attr "type" "mfhilo"))
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84 "r74k_alu+r74k_mul")
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85
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86 ;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
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87 (define_insn_reservation "r74k_int_mthilo" 7
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88 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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89 (eq_attr "type" "mthilo"))
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90 "r74k_alu+r74k_mul")
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91
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92 ;; div - default to 50 cycles for 32bit operands. Faster for 8 bit,
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93 ;; but is tricky to identify.
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94 (define_insn_reservation "r74k_int_div" 50
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95 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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96 (eq_attr "type" "idiv"))
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97 "r74k_alu+r74k_mul*50")
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98
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99 ;; call
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100 (define_insn_reservation "r74k_int_call" 1
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101 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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102 (eq_attr "type" "call"))
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103 "r74k_agen")
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104
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105 ;; branch/jump
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106 (define_insn_reservation "r74k_int_jump" 1
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107 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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108 (eq_attr "type" "branch,jump"))
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109 "r74k_agen")
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110
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111 ;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
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112 ;; prefetch: prefetch, prefetchx
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113 (define_insn_reservation "r74k_int_load" 3
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114 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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115 (eq_attr "type" "load,prefetch,prefetchx"))
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116 "r74k_agen")
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117
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118 ;; stores
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119 (define_insn_reservation "r74k_int_store" 1
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120 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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121 (and (eq_attr "type" "store")
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122 (eq_attr "mode" "!unknown")))
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123 "r74k_agen")
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124
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125
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126 ;; Unknowns - Currently these include blockage, consttable and alignment
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127 ;; rtls. They do not really affect scheduling latency, (blockage
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128 ;; affects scheduling via log links, but not used here).
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129 ;;
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130 (define_insn_reservation "r74k_unknown" 1
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131 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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132 (eq_attr "type" "unknown"))
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133 "r74k_alu")
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134
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135 (define_insn_reservation "r74k_multi" 10
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136 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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137 (eq_attr "type" "multi"))
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138 "(r74k_alu+r74k_agen)*10")
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139
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140 ;; --------------------------------------------------------------
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141 ;; Bypass to Consumer
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142 ;; --------------------------------------------------------------
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143
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144 ;; load->next use : 3 cycles (Default)
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145 ;; load->load base: 4 cycles
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146 ;; load->store base: 4 cycles
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147 (define_bypass 4 "r74k_int_load" "r74k_int_load")
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148 (define_bypass 4 "r74k_int_load" "r74k_int_store" "!store_data_bypass_p")
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149
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150 ;; logical/move/slt/signext->next use : 1 cycles (Default)
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151 ;; logical/move/slt/signext->load base: 2 cycles
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152 ;; logical/move/slt/signext->store base: 2 cycles
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153 (define_bypass 2 "r74k_int_logical" "r74k_int_load")
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154 (define_bypass 2 "r74k_int_logical" "r74k_int_store" "!store_data_bypass_p")
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155
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156 ;; arith->next use : 2 cycles (Default)
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157 ;; arith->load base: 3 cycles
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158 ;; arith->store base: 3 cycles
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159 (define_bypass 3 "r74k_int_arith" "r74k_int_load")
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160 (define_bypass 3 "r74k_int_arith" "r74k_int_store" "!store_data_bypass_p")
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161
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162 ;; cmove->next use : 4 cycles (Default)
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163 ;; cmove->load base: 5 cycles
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164 ;; cmove->store base: 5 cycles
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165 (define_bypass 5 "r74k_int_cmove" "r74k_int_load")
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166 (define_bypass 5 "r74k_int_cmove" "r74k_int_store" "!store_data_bypass_p")
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167
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168 ;; mult/madd/msub->int_mfhilo : 4 cycles (default)
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169 ;; mult->madd/msub : 1 cycles
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170 ;; madd/msub->madd/msub : 1 cycles
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171 (define_bypass 1 "r74k_int_mult,r74k_int_mul3" "r74k_int_madd"
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172 "mips_linked_madd_p")
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173 (define_bypass 1 "r74k_int_madd" "r74k_int_madd"
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174 "mips_linked_madd_p")
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175
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176 ;; --------------------------------------------------------------
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177 ;; Floating Point Instructions
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178 ;; --------------------------------------------------------------
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179
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180 ;; 74Kf FPU runs at 1:1 or 2:1 core/FPU clock ratio.
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181
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182 ;; fadd, fabs, fneg,
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183 (define_insn_reservation "r74kf1_1_fadd" 4
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184 (and (eq_attr "cpu" "74kf1_1")
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185 (eq_attr "type" "fadd,fabs,fneg"))
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186 "r74k_fpu_arith")
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187
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188 (define_insn_reservation "r74kf2_1_fadd" 8
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189 (and (eq_attr "cpu" "74kf2_1")
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190 (eq_attr "type" "fadd,fabs,fneg"))
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191 "r74k_fpu_arith*2")
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192
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193 (define_insn_reservation "r74kf3_2_fadd" 6
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194 (and (eq_attr "cpu" "74kf3_2")
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195 (eq_attr "type" "fadd,fabs,fneg"))
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196 "r74k_fpu_arith")
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197
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198 ;; fmove, fcmove
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199 (define_insn_reservation "r74kf1_1_fmove" 4
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200 (and (eq_attr "cpu" "74kf1_1")
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201 (eq_attr "type" "fmove"))
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202 "r74k_fpu_arith")
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203
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204 (define_insn_reservation "r74kf2_1_fmove" 8
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205 (and (eq_attr "cpu" "74kf2_1")
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206 (eq_attr "type" "fmove"))
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207 "r74k_fpu_arith*2")
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208
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209 (define_insn_reservation "r74kf3_2_fmove" 6
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210 (and (eq_attr "cpu" "74kf3_2")
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211 (eq_attr "type" "fmove"))
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212 "r74k_fpu_arith")
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213
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214 ;; fload
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215 (define_insn_reservation "r74kf1_1_fload" 4
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216 (and (eq_attr "cpu" "74kf1_1")
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217 (eq_attr "type" "fpload,fpidxload"))
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218 "r74k_agen+r74k_fpu_ldst")
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219
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220 (define_insn_reservation "r74kf2_1_fload" 8
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221 (and (eq_attr "cpu" "74kf2_1")
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222 (eq_attr "type" "fpload,fpidxload"))
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223 "r74k_agen+(r74k_fpu_ldst*2)")
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224
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225 (define_insn_reservation "r74kf3_2_fload" 6
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226 (and (eq_attr "cpu" "74kf3_2")
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227 (eq_attr "type" "fpload,fpidxload"))
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228 "r74k_agen+r74k_fpu_ldst")
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229
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230 ;; fstore
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231 (define_insn_reservation "r74kf1_1_fstore" 1
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232 (and (eq_attr "cpu" "74kf1_1")
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233 (eq_attr "type" "fpstore,fpidxstore"))
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234 "r74k_agen+r74k_fpu_ldst")
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235
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236 (define_insn_reservation "r74kf2_1_fstore" 2
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237 (and (eq_attr "cpu" "74kf2_1")
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238 (eq_attr "type" "fpstore,fpidxstore"))
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239 "r74k_agen+(r74k_fpu_ldst*2)")
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240
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241 (define_insn_reservation "r74kf3_2_fstore" 1
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242 (and (eq_attr "cpu" "74kf3_2")
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243 (eq_attr "type" "fpstore,fpidxstore"))
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244 "r74k_agen+r74k_fpu_ldst")
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245
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246 ;; fmul, fmadd
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247 (define_insn_reservation "r74kf1_1_fmul_sf" 4
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248 (and (eq_attr "cpu" "74kf1_1")
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249 (and (eq_attr "type" "fmul,fmadd")
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250 (eq_attr "mode" "SF")))
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251 "r74k_fpu_arith")
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252
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253 (define_insn_reservation "r74kf2_1_fmul_sf" 8
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254 (and (eq_attr "cpu" "74kf2_1")
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255 (and (eq_attr "type" "fmul,fmadd")
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256 (eq_attr "mode" "SF")))
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257 "r74k_fpu_arith*2")
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258
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259 (define_insn_reservation "r74kf3_2_fmul_sf" 6
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260 (and (eq_attr "cpu" "74kf3_2")
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261 (and (eq_attr "type" "fmul,fmadd")
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262 (eq_attr "mode" "SF")))
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263 "r74k_fpu_arith")
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264
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265 (define_insn_reservation "r74kf1_1_fmul_df" 5
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266 (and (eq_attr "cpu" "74kf1_1")
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267 (and (eq_attr "type" "fmul,fmadd")
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268 (eq_attr "mode" "DF")))
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269 "r74k_fpu_arith*2")
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270
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271 (define_insn_reservation "r74kf2_1_fmul_df" 10
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272 (and (eq_attr "cpu" "74kf2_1")
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273 (and (eq_attr "type" "fmul,fmadd")
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274 (eq_attr "mode" "DF")))
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275 "r74k_fpu_arith*4")
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276
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277 (define_insn_reservation "r74kf3_2_fmul_df" 7
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278 (and (eq_attr "cpu" "74kf3_2")
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279 (and (eq_attr "type" "fmul,fmadd")
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280 (eq_attr "mode" "DF")))
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281 "r74k_fpu_arith*2")
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282
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283 ;; fdiv, fsqrt
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284 (define_insn_reservation "r74kf1_1_fdiv_sf" 17
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285 (and (eq_attr "cpu" "74kf1_1")
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286 (and (eq_attr "type" "fdiv,fsqrt")
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287 (eq_attr "mode" "SF")))
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288 "r74k_fpu_arith*14")
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289
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290 (define_insn_reservation "r74kf2_1_fdiv_sf" 34
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291 (and (eq_attr "cpu" "74kf2_1")
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292 (and (eq_attr "type" "fdiv,fsqrt")
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293 (eq_attr "mode" "SF")))
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294 "r74k_fpu_arith*28")
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295
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296 (define_insn_reservation "r74kf3_2_fdiv_sf" 25
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297 (and (eq_attr "cpu" "74kf3_2")
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298 (and (eq_attr "type" "fdiv,fsqrt")
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299 (eq_attr "mode" "SF")))
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300 "r74k_fpu_arith*14")
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301
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302 (define_insn_reservation "r74kf1_1_fdiv_df" 32
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303 (and (eq_attr "cpu" "74kf1_1")
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304 (and (eq_attr "type" "fdiv,fsqrt")
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305 (eq_attr "mode" "DF")))
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306 "r74k_fpu_arith*29")
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307
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308 (define_insn_reservation "r74kf2_1_fdiv_df" 64
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309 (and (eq_attr "cpu" "74kf2_1")
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310 (and (eq_attr "type" "fdiv,fsqrt")
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311 (eq_attr "mode" "DF")))
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312 "r74k_fpu_arith*58")
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313
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314 (define_insn_reservation "r74kf3_2_fdiv_df" 48
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315 (and (eq_attr "cpu" "74kf3_2")
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316 (and (eq_attr "type" "fdiv,fsqrt")
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317 (eq_attr "mode" "DF")))
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318 "r74k_fpu_arith*29")
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319
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320 ;; frsqrt
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321 (define_insn_reservation "r74kf1_1_frsqrt_sf" 17
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322 (and (eq_attr "cpu" "74kf1_1")
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323 (and (eq_attr "type" "frsqrt")
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324 (eq_attr "mode" "SF")))
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325 "r74k_fpu_arith*14")
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326
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327 (define_insn_reservation "r74kf2_1_frsqrt_sf" 34
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328 (and (eq_attr "cpu" "74kf2_1")
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329 (and (eq_attr "type" "frsqrt")
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330 (eq_attr "mode" "SF")))
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331 "r74k_fpu_arith*28")
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332
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333 (define_insn_reservation "r74kf3_2_frsqrt_sf" 25
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334 (and (eq_attr "cpu" "74kf3_2")
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335 (and (eq_attr "type" "frsqrt")
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336 (eq_attr "mode" "SF")))
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337 "r74k_fpu_arith*14")
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338
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339 (define_insn_reservation "r74kf1_1_frsqrt_df" 36
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340 (and (eq_attr "cpu" "74kf1_1")
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341 (and (eq_attr "type" "frsqrt")
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342 (eq_attr "mode" "DF")))
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343 "r74k_fpu_arith*31")
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344
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345 (define_insn_reservation "r74kf2_1_frsqrt_df" 72
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346 (and (eq_attr "cpu" "74kf2_1")
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347 (and (eq_attr "type" "frsqrt")
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348 (eq_attr "mode" "DF")))
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349 "r74k_fpu_arith*62")
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350
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351 (define_insn_reservation "r74kf3_2_frsqrt_df" 54
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352 (and (eq_attr "cpu" "74kf3_2")
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353 (and (eq_attr "type" "frsqrt")
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354 (eq_attr "mode" "DF")))
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355 "r74k_fpu_arith*31")
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356
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357 ;; fcmp
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358 (define_insn_reservation "r74kf1_1_fcmp" 4
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359 (and (eq_attr "cpu" "74kf1_1")
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360 (eq_attr "type" "fcmp"))
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361 "r74k_fpu_arith")
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362
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363 (define_insn_reservation "r74kf2_1_fcmp" 8
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364 (and (eq_attr "cpu" "74kf2_1")
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365 (eq_attr "type" "fcmp"))
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366 "r74k_fpu_arith*2")
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367
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368 (define_insn_reservation "r74kf3_2_fcmp" 6
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369 (and (eq_attr "cpu" "74kf3_2")
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370 (eq_attr "type" "fcmp"))
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371 "r74k_fpu_arith")
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372
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373 ;; fcvt
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374 (define_insn_reservation "r74kf1_1_fcvt" 4
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375 (and (eq_attr "cpu" "74kf1_1")
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376 (eq_attr "type" "fcvt"))
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377 "r74k_fpu_arith")
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378
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379 (define_insn_reservation "r74kf2_1_fcvt" 8
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380 (and (eq_attr "cpu" "74kf2_1")
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381 (eq_attr "type" "fcvt"))
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382 "r74k_fpu_arith*2")
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383
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384 (define_insn_reservation "r74kf3_2_fcvt" 6
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385 (and (eq_attr "cpu" "74kf3_2")
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386 (eq_attr "type" "fcvt"))
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387 "r74k_fpu_arith")
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388
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389 ;; fxfer (MTC1, DMTC1: latency is 4) (MFC1, DMFC1: latency is 1)
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390 (define_insn_reservation "r74kf1_1_fxfer_to_c1" 4
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391 (and (eq_attr "cpu" "74kf1_1")
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392 (eq_attr "type" "mtc"))
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393 "r74k_fpu_arith")
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394
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395 (define_insn_reservation "r74kf2_1_fxfer_to_c1" 8
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396 (and (eq_attr "cpu" "74kf2_1")
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397 (eq_attr "type" "mtc"))
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398 "r74k_fpu_arith*2")
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399
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400 (define_insn_reservation "r74kf3_2_fxfer_to_c1" 6
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401 (and (eq_attr "cpu" "74kf3_2")
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402 (eq_attr "type" "mtc"))
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403 "r74k_fpu_arith")
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404
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405 (define_insn_reservation "r74kf1_1_fxfer_from_c1" 1
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406 (and (eq_attr "cpu" "74kf1_1")
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407 (eq_attr "type" "mfc"))
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408 "r74k_fpu_arith")
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409
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410 (define_insn_reservation "r74kf2_1_fxfer_from_c1" 2
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411 (and (eq_attr "cpu" "74kf2_1")
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412 (eq_attr "type" "mfc"))
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413 "r74k_fpu_arith*2")
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414
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415 (define_insn_reservation "r74kf3_2_fxfer_from_c1" 1
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416 (and (eq_attr "cpu" "74kf3_2")
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417 (eq_attr "type" "mfc"))
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418 "r74k_fpu_arith")
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