Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/mips/mips.h @ 63:b7f97abdc517 gcc-4.6-20100522
update gcc from gcc-4.5.0 to gcc-4.6
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Mon, 24 May 2010 12:47:05 +0900 |
| parents | 77e2b8dfacca |
| children | f6334be47118 |
| rev | line source |
|---|---|
| 0 | 1 /* Definitions of target machine for GNU compiler. MIPS version. |
| 2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998 | |
|
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3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010 |
| 0 | 4 Free Software Foundation, Inc. |
| 5 Contributed by A. Lichnewsky (lich@inria.inria.fr). | |
| 6 Changed by Michael Meissner (meissner@osf.org). | |
| 7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and | |
| 8 Brendan Eich (brendan@microunity.com). | |
| 9 | |
| 10 This file is part of GCC. | |
| 11 | |
| 12 GCC is free software; you can redistribute it and/or modify | |
| 13 it under the terms of the GNU General Public License as published by | |
| 14 the Free Software Foundation; either version 3, or (at your option) | |
| 15 any later version. | |
| 16 | |
| 17 GCC is distributed in the hope that it will be useful, | |
| 18 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 20 GNU General Public License for more details. | |
| 21 | |
| 22 You should have received a copy of the GNU General Public License | |
| 23 along with GCC; see the file COPYING3. If not see | |
| 24 <http://www.gnu.org/licenses/>. */ | |
| 25 | |
| 26 | |
| 27 #include "config/vxworks-dummy.h" | |
| 28 | |
| 29 /* MIPS external variables defined in mips.c. */ | |
| 30 | |
| 31 /* Which processor to schedule for. Since there is no difference between | |
| 32 a R2000 and R3000 in terms of the scheduler, we collapse them into | |
| 33 just an R3000. The elements of the enumeration must match exactly | |
| 34 the cpu attribute in the mips.md machine description. */ | |
| 35 | |
| 36 enum processor_type { | |
| 37 PROCESSOR_R3000, | |
| 38 PROCESSOR_4KC, | |
| 39 PROCESSOR_4KP, | |
| 40 PROCESSOR_5KC, | |
| 41 PROCESSOR_5KF, | |
| 42 PROCESSOR_20KC, | |
| 43 PROCESSOR_24KC, | |
| 44 PROCESSOR_24KF2_1, | |
| 45 PROCESSOR_24KF1_1, | |
| 46 PROCESSOR_74KC, | |
| 47 PROCESSOR_74KF2_1, | |
| 48 PROCESSOR_74KF1_1, | |
| 49 PROCESSOR_74KF3_2, | |
| 50 PROCESSOR_LOONGSON_2E, | |
| 51 PROCESSOR_LOONGSON_2F, | |
| 52 PROCESSOR_M4K, | |
| 53 PROCESSOR_OCTEON, | |
| 54 PROCESSOR_R3900, | |
| 55 PROCESSOR_R6000, | |
| 56 PROCESSOR_R4000, | |
| 57 PROCESSOR_R4100, | |
| 58 PROCESSOR_R4111, | |
| 59 PROCESSOR_R4120, | |
| 60 PROCESSOR_R4130, | |
| 61 PROCESSOR_R4300, | |
| 62 PROCESSOR_R4600, | |
| 63 PROCESSOR_R4650, | |
| 64 PROCESSOR_R5000, | |
| 65 PROCESSOR_R5400, | |
| 66 PROCESSOR_R5500, | |
| 67 PROCESSOR_R7000, | |
| 68 PROCESSOR_R8000, | |
| 69 PROCESSOR_R9000, | |
| 70 PROCESSOR_R10000, | |
| 71 PROCESSOR_SB1, | |
| 72 PROCESSOR_SB1A, | |
| 73 PROCESSOR_SR71000, | |
| 74 PROCESSOR_XLR, | |
| 75 PROCESSOR_MAX | |
| 76 }; | |
| 77 | |
| 78 /* Costs of various operations on the different architectures. */ | |
| 79 | |
| 80 struct mips_rtx_cost_data | |
| 81 { | |
| 82 unsigned short fp_add; | |
| 83 unsigned short fp_mult_sf; | |
| 84 unsigned short fp_mult_df; | |
| 85 unsigned short fp_div_sf; | |
| 86 unsigned short fp_div_df; | |
| 87 unsigned short int_mult_si; | |
| 88 unsigned short int_mult_di; | |
| 89 unsigned short int_div_si; | |
| 90 unsigned short int_div_di; | |
| 91 unsigned short branch_cost; | |
| 92 unsigned short memory_latency; | |
| 93 }; | |
| 94 | |
| 95 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32), | |
| 96 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended | |
| 97 to work on a 64-bit machine. */ | |
| 98 | |
| 99 #define ABI_32 0 | |
| 100 #define ABI_N32 1 | |
| 101 #define ABI_64 2 | |
| 102 #define ABI_EABI 3 | |
| 103 #define ABI_O64 4 | |
| 104 | |
| 105 /* Masks that affect tuning. | |
| 106 | |
| 107 PTF_AVOID_BRANCHLIKELY | |
| 108 Set if it is usually not profitable to use branch-likely instructions | |
| 109 for this target, typically because the branches are always predicted | |
| 110 taken and so incur a large overhead when not taken. */ | |
| 111 #define PTF_AVOID_BRANCHLIKELY 0x1 | |
| 112 | |
| 113 /* Information about one recognized processor. Defined here for the | |
| 114 benefit of TARGET_CPU_CPP_BUILTINS. */ | |
| 115 struct mips_cpu_info { | |
| 116 /* The 'canonical' name of the processor as far as GCC is concerned. | |
| 117 It's typically a manufacturer's prefix followed by a numerical | |
| 118 designation. It should be lowercase. */ | |
| 119 const char *name; | |
| 120 | |
| 121 /* The internal processor number that most closely matches this | |
| 122 entry. Several processors can have the same value, if there's no | |
| 123 difference between them from GCC's point of view. */ | |
| 124 enum processor_type cpu; | |
| 125 | |
| 126 /* The ISA level that the processor implements. */ | |
| 127 int isa; | |
| 128 | |
| 129 /* A mask of PTF_* values. */ | |
| 130 unsigned int tune_flags; | |
| 131 }; | |
| 132 | |
| 133 /* Enumerates the setting of the -mcode-readable option. */ | |
| 134 enum mips_code_readable_setting { | |
| 135 CODE_READABLE_NO, | |
| 136 CODE_READABLE_PCREL, | |
| 137 CODE_READABLE_YES | |
| 138 }; | |
| 139 | |
| 140 /* Macros to silence warnings about numbers being signed in traditional | |
| 141 C and unsigned in ISO C when compiled on 32-bit hosts. */ | |
| 142 | |
| 143 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */ | |
| 144 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */ | |
| 145 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */ | |
| 146 | |
| 147 | |
| 148 /* Run-time compilation parameters selecting different hardware subsets. */ | |
| 149 | |
| 150 /* True if we are generating position-independent VxWorks RTP code. */ | |
| 151 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic) | |
| 152 | |
| 153 /* True if the output file is marked as ".abicalls; .option pic0" | |
| 154 (-call_nonpic). */ | |
| 155 #define TARGET_ABICALLS_PIC0 \ | |
| 156 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT) | |
| 157 | |
| 158 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */ | |
| 159 #define TARGET_ABICALLS_PIC2 \ | |
| 160 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0) | |
| 161 | |
| 162 /* True if the call patterns should be split into a jalr followed by | |
| 163 an instruction to restore $gp. It is only safe to split the load | |
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164 from the call when every use of $gp is explicit. |
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165 |
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166 See mips_must_initialize_gp_p for details about how we manage the |
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167 global pointer. */ |
| 0 | 168 |
| 169 #define TARGET_SPLIT_CALLS \ | |
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170 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed) |
| 0 | 171 |
| 172 /* True if we're generating a form of -mabicalls in which we can use | |
| 173 operators like %hi and %lo to refer to locally-binding symbols. | |
| 174 We can only do this for -mno-shared, and only then if we can use | |
| 175 relocation operations instead of assembly macros. It isn't really | |
| 176 worth using absolute sequences for 64-bit symbols because GOT | |
| 177 accesses are so much shorter. */ | |
| 178 | |
| 179 #define TARGET_ABSOLUTE_ABICALLS \ | |
| 180 (TARGET_ABICALLS \ | |
| 181 && !TARGET_SHARED \ | |
| 182 && TARGET_EXPLICIT_RELOCS \ | |
| 183 && !ABI_HAS_64BIT_SYMBOLS) | |
| 184 | |
| 185 /* True if we can optimize sibling calls. For simplicity, we only | |
| 186 handle cases in which call_insn_operand will reject invalid | |
| 187 sibcall addresses. There are two cases in which this isn't true: | |
| 188 | |
| 189 - TARGET_MIPS16. call_insn_operand accepts constant addresses | |
| 190 but there is no direct jump instruction. It isn't worth | |
| 191 using sibling calls in this case anyway; they would usually | |
| 192 be longer than normal calls. | |
| 193 | |
| 194 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand | |
| 195 accepts global constants, but all sibcalls must be indirect. */ | |
| 196 #define TARGET_SIBCALLS \ | |
| 197 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS)) | |
| 198 | |
| 199 /* True if we need to use a global offset table to access some symbols. */ | |
| 200 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC) | |
| 201 | |
| 202 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */ | |
| 203 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI) | |
| 204 | |
| 205 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */ | |
| 206 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP) | |
| 207 | |
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208 /* True if we should use .cprestore to store to the cprestore slot. |
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209 |
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210 We continue to use .cprestore for explicit-reloc code so that JALs |
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211 inside inline asms will work correctly. */ |
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212 #define TARGET_CPRESTORE_DIRECTIVE \ |
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213 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16) |
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214 |
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215 /* True if we can use the J and JAL instructions. */ |
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216 #define TARGET_ABSOLUTE_JUMPS \ |
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217 (!flag_pic || TARGET_ABSOLUTE_ABICALLS) |
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218 |
| 0 | 219 /* True if indirect calls must use register class PIC_FN_ADDR_REG. |
| 220 This is true for both the PIC and non-PIC VxWorks RTP modes. */ | |
| 221 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP) | |
| 222 | |
| 223 /* True if .gpword or .gpdword should be used for switch tables. | |
| 224 | |
| 225 Although GAS does understand .gpdword, the SGI linker mishandles | |
| 226 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64). | |
| 227 We therefore disable GP-relative switch tables for n64 on IRIX targets. */ | |
| 228 #define TARGET_GPWORD \ | |
| 229 (TARGET_ABICALLS \ | |
| 230 && !TARGET_ABSOLUTE_ABICALLS \ | |
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231 && !(mips_abi == ABI_64 && TARGET_IRIX6)) |
| 0 | 232 |
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233 /* True if the output must have a writable .eh_frame. |
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234 See ASM_PREFERRED_EH_DATA_FORMAT for details. */ |
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235 #ifdef HAVE_LD_PERSONALITY_RELAXATION |
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236 #define TARGET_WRITABLE_EH_FRAME 0 |
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237 #else |
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238 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED) |
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239 #endif |
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240 |
| 0 | 241 /* Generate mips16 code */ |
| 242 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0) | |
| 243 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */ | |
| 244 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32) | |
| 245 /* Generate mips16e register save/restore sequences. */ | |
| 246 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32) | |
| 247 | |
| 248 /* True if we're generating a form of MIPS16 code in which general | |
| 249 text loads are allowed. */ | |
| 250 #define TARGET_MIPS16_TEXT_LOADS \ | |
| 251 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES) | |
| 252 | |
| 253 /* True if we're generating a form of MIPS16 code in which PC-relative | |
| 254 loads are allowed. */ | |
| 255 #define TARGET_MIPS16_PCREL_LOADS \ | |
| 256 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL) | |
| 257 | |
| 258 /* Generic ISA defines. */ | |
| 259 #define ISA_MIPS1 (mips_isa == 1) | |
| 260 #define ISA_MIPS2 (mips_isa == 2) | |
| 261 #define ISA_MIPS3 (mips_isa == 3) | |
| 262 #define ISA_MIPS4 (mips_isa == 4) | |
| 263 #define ISA_MIPS32 (mips_isa == 32) | |
| 264 #define ISA_MIPS32R2 (mips_isa == 33) | |
| 265 #define ISA_MIPS64 (mips_isa == 64) | |
| 266 #define ISA_MIPS64R2 (mips_isa == 65) | |
| 267 | |
| 268 /* Architecture target defines. */ | |
| 269 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E) | |
| 270 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) | |
| 271 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) | |
| 272 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) | |
| 273 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) | |
| 274 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) | |
| 275 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130) | |
| 276 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400) | |
| 277 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500) | |
| 278 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000) | |
| 279 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000) | |
| 280 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON) | |
| 281 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \ | |
| 282 || mips_arch == PROCESSOR_SB1A) | |
| 283 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) | |
| 284 | |
| 285 /* Scheduling target defines. */ | |
| 286 #define TUNE_20KC (mips_tune == PROCESSOR_20KC) | |
| 287 #define TUNE_24K (mips_tune == PROCESSOR_24KC \ | |
| 288 || mips_tune == PROCESSOR_24KF2_1 \ | |
| 289 || mips_tune == PROCESSOR_24KF1_1) | |
| 290 #define TUNE_74K (mips_tune == PROCESSOR_74KC \ | |
| 291 || mips_tune == PROCESSOR_74KF2_1 \ | |
| 292 || mips_tune == PROCESSOR_74KF1_1 \ | |
| 293 || mips_tune == PROCESSOR_74KF3_2) | |
| 294 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ | |
| 295 || mips_tune == PROCESSOR_LOONGSON_2F) | |
| 296 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) | |
| 297 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) | |
| 298 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) | |
| 299 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120) | |
| 300 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130) | |
| 301 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000) | |
| 302 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400) | |
| 303 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500) | |
| 304 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000) | |
| 305 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000) | |
| 306 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000) | |
| 307 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON) | |
| 308 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ | |
| 309 || mips_tune == PROCESSOR_SB1A) | |
| 310 | |
| 311 /* Whether vector modes and intrinsics for ST Microelectronics | |
| 312 Loongson-2E/2F processors should be enabled. In o32 pairs of | |
| 313 floating-point registers provide 64-bit values. */ | |
| 314 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \ | |
| 315 && TARGET_LOONGSON_2EF) | |
| 316 | |
| 317 /* True if the pre-reload scheduler should try to create chains of | |
| 318 multiply-add or multiply-subtract instructions. For example, | |
| 319 suppose we have: | |
| 320 | |
| 321 t1 = a * b | |
| 322 t2 = t1 + c * d | |
| 323 t3 = e * f | |
| 324 t4 = t3 - g * h | |
| 325 | |
| 326 t1 will have a higher priority than t2 and t3 will have a higher | |
| 327 priority than t4. However, before reload, there is no dependence | |
| 328 between t1 and t3, and they can often have similar priorities. | |
| 329 The scheduler will then tend to prefer: | |
| 330 | |
| 331 t1 = a * b | |
| 332 t3 = e * f | |
| 333 t2 = t1 + c * d | |
| 334 t4 = t3 - g * h | |
| 335 | |
| 336 which stops us from making full use of macc/madd-style instructions. | |
| 337 This sort of situation occurs frequently in Fourier transforms and | |
| 338 in unrolled loops. | |
| 339 | |
| 340 To counter this, the TUNE_MACC_CHAINS code will reorder the ready | |
| 341 queue so that chained multiply-add and multiply-subtract instructions | |
| 342 appear ahead of any other instruction that is likely to clobber lo. | |
| 343 In the example above, if t2 and t3 become ready at the same time, | |
| 344 the code ensures that t2 is scheduled first. | |
| 345 | |
| 346 Multiply-accumulate instructions are a bigger win for some targets | |
| 347 than others, so this macro is defined on an opt-in basis. */ | |
| 348 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \ | |
| 349 || TUNE_MIPS4120 \ | |
| 350 || TUNE_MIPS4130 \ | |
| 351 || TUNE_24K) | |
| 352 | |
| 353 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64) | |
| 354 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64) | |
| 355 | |
| 356 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is | |
| 357 directly accessible, while the command-line options select | |
| 358 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI | |
| 359 in use. */ | |
| 360 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16) | |
| 361 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16) | |
|
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362 |
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363 /* False if SC acts as a memory barrier with respect to itself, |
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364 otherwise a SYNC will be emitted after SC for atomic operations |
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365 that require ordering between the SC and following loads and |
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366 stores. It does not tell anything about ordering of loads and |
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367 stores prior to and following the SC, only about the SC itself and |
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368 those loads and stores follow it. */ |
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369 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON) |
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370 |
| 0 | 371 /* IRIX specific stuff. */ |
| 372 #define TARGET_IRIX6 0 | |
| 373 | |
| 374 /* Define preprocessor macros for the -march and -mtune options. | |
| 375 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected | |
| 376 processor. If INFO's canonical name is "foo", define PREFIX to | |
| 377 be "foo", and define an additional macro PREFIX_FOO. */ | |
| 378 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \ | |
| 379 do \ | |
| 380 { \ | |
| 381 char *macro, *p; \ | |
| 382 \ | |
| 383 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \ | |
| 384 for (p = macro; *p != 0; p++) \ | |
| 385 *p = TOUPPER (*p); \ | |
| 386 \ | |
| 387 builtin_define (macro); \ | |
| 388 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \ | |
| 389 free (macro); \ | |
| 390 } \ | |
| 391 while (0) | |
| 392 | |
| 393 /* Target CPU builtins. */ | |
| 394 #define TARGET_CPU_CPP_BUILTINS() \ | |
| 395 do \ | |
| 396 { \ | |
| 397 /* Everyone but IRIX defines this to mips. */ \ | |
|
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398 if (!TARGET_IRIX6) \ |
| 0 | 399 builtin_assert ("machine=mips"); \ |
| 400 \ | |
| 401 builtin_assert ("cpu=mips"); \ | |
| 402 builtin_define ("__mips__"); \ | |
| 403 builtin_define ("_mips"); \ | |
| 404 \ | |
| 405 /* We do this here because __mips is defined below and so we \ | |
| 406 can't use builtin_define_std. We don't ever want to define \ | |
| 407 "mips" for VxWorks because some of the VxWorks headers \ | |
| 408 construct include filenames from a root directory macro, \ | |
| 409 an architecture macro and a filename, where the architecture \ | |
| 410 macro expands to 'mips'. If we define 'mips' to 1, the \ | |
| 411 architecture macro expands to 1 as well. */ \ | |
| 412 if (!flag_iso && !TARGET_VXWORKS) \ | |
| 413 builtin_define ("mips"); \ | |
| 414 \ | |
| 415 if (TARGET_64BIT) \ | |
| 416 builtin_define ("__mips64"); \ | |
| 417 \ | |
|
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418 if (!TARGET_IRIX6) \ |
| 0 | 419 { \ |
| 420 /* Treat _R3000 and _R4000 like register-size \ | |
| 421 defines, which is how they've historically \ | |
| 422 been used. */ \ | |
| 423 if (TARGET_64BIT) \ | |
| 424 { \ | |
| 425 builtin_define_std ("R4000"); \ | |
| 426 builtin_define ("_R4000"); \ | |
| 427 } \ | |
| 428 else \ | |
| 429 { \ | |
| 430 builtin_define_std ("R3000"); \ | |
| 431 builtin_define ("_R3000"); \ | |
| 432 } \ | |
| 433 } \ | |
| 434 if (TARGET_FLOAT64) \ | |
| 435 builtin_define ("__mips_fpr=64"); \ | |
| 436 else \ | |
| 437 builtin_define ("__mips_fpr=32"); \ | |
| 438 \ | |
| 439 if (mips_base_mips16) \ | |
| 440 builtin_define ("__mips16"); \ | |
| 441 \ | |
| 442 if (TARGET_MIPS3D) \ | |
| 443 builtin_define ("__mips3d"); \ | |
| 444 \ | |
| 445 if (TARGET_SMARTMIPS) \ | |
| 446 builtin_define ("__mips_smartmips"); \ | |
| 447 \ | |
| 448 if (TARGET_DSP) \ | |
| 449 { \ | |
| 450 builtin_define ("__mips_dsp"); \ | |
| 451 if (TARGET_DSPR2) \ | |
| 452 { \ | |
| 453 builtin_define ("__mips_dspr2"); \ | |
| 454 builtin_define ("__mips_dsp_rev=2"); \ | |
| 455 } \ | |
| 456 else \ | |
| 457 builtin_define ("__mips_dsp_rev=1"); \ | |
| 458 } \ | |
| 459 \ | |
| 460 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \ | |
| 461 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \ | |
| 462 \ | |
| 463 if (ISA_MIPS1) \ | |
| 464 { \ | |
| 465 builtin_define ("__mips=1"); \ | |
| 466 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \ | |
| 467 } \ | |
| 468 else if (ISA_MIPS2) \ | |
| 469 { \ | |
| 470 builtin_define ("__mips=2"); \ | |
| 471 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \ | |
| 472 } \ | |
| 473 else if (ISA_MIPS3) \ | |
| 474 { \ | |
| 475 builtin_define ("__mips=3"); \ | |
| 476 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \ | |
| 477 } \ | |
| 478 else if (ISA_MIPS4) \ | |
| 479 { \ | |
| 480 builtin_define ("__mips=4"); \ | |
| 481 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \ | |
| 482 } \ | |
| 483 else if (ISA_MIPS32) \ | |
| 484 { \ | |
| 485 builtin_define ("__mips=32"); \ | |
| 486 builtin_define ("__mips_isa_rev=1"); \ | |
| 487 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ | |
| 488 } \ | |
| 489 else if (ISA_MIPS32R2) \ | |
| 490 { \ | |
| 491 builtin_define ("__mips=32"); \ | |
| 492 builtin_define ("__mips_isa_rev=2"); \ | |
| 493 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ | |
| 494 } \ | |
| 495 else if (ISA_MIPS64) \ | |
| 496 { \ | |
| 497 builtin_define ("__mips=64"); \ | |
| 498 builtin_define ("__mips_isa_rev=1"); \ | |
| 499 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ | |
| 500 } \ | |
| 501 else if (ISA_MIPS64R2) \ | |
| 502 { \ | |
| 503 builtin_define ("__mips=64"); \ | |
| 504 builtin_define ("__mips_isa_rev=2"); \ | |
| 505 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ | |
| 506 } \ | |
| 507 \ | |
| 508 switch (mips_abi) \ | |
| 509 { \ | |
| 510 case ABI_32: \ | |
| 511 builtin_define ("_ABIO32=1"); \ | |
| 512 builtin_define ("_MIPS_SIM=_ABIO32"); \ | |
| 513 break; \ | |
| 514 \ | |
| 515 case ABI_N32: \ | |
| 516 builtin_define ("_ABIN32=2"); \ | |
| 517 builtin_define ("_MIPS_SIM=_ABIN32"); \ | |
| 518 break; \ | |
| 519 \ | |
| 520 case ABI_64: \ | |
| 521 builtin_define ("_ABI64=3"); \ | |
| 522 builtin_define ("_MIPS_SIM=_ABI64"); \ | |
| 523 break; \ | |
| 524 \ | |
| 525 case ABI_O64: \ | |
| 526 builtin_define ("_ABIO64=4"); \ | |
| 527 builtin_define ("_MIPS_SIM=_ABIO64"); \ | |
| 528 break; \ | |
| 529 } \ | |
| 530 \ | |
| 531 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \ | |
| 532 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \ | |
| 533 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \ | |
| 534 builtin_define_with_int_value ("_MIPS_FPSET", \ | |
| 535 32 / MAX_FPRS_PER_FMT); \ | |
| 536 \ | |
| 537 /* These defines reflect the ABI in use, not whether the \ | |
| 538 FPU is directly accessible. */ \ | |
|
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539 if (TARGET_NO_FLOAT) \ |
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540 builtin_define ("__mips_no_float"); \ |
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541 else if (TARGET_HARD_FLOAT_ABI) \ |
| 0 | 542 builtin_define ("__mips_hard_float"); \ |
| 543 else \ | |
| 544 builtin_define ("__mips_soft_float"); \ | |
| 545 \ | |
| 546 if (TARGET_SINGLE_FLOAT) \ | |
| 547 builtin_define ("__mips_single_float"); \ | |
| 548 \ | |
| 549 if (TARGET_PAIRED_SINGLE_FLOAT) \ | |
| 550 builtin_define ("__mips_paired_single_float"); \ | |
| 551 \ | |
| 552 if (TARGET_BIG_ENDIAN) \ | |
| 553 { \ | |
| 554 builtin_define_std ("MIPSEB"); \ | |
| 555 builtin_define ("_MIPSEB"); \ | |
| 556 } \ | |
| 557 else \ | |
| 558 { \ | |
| 559 builtin_define_std ("MIPSEL"); \ | |
| 560 builtin_define ("_MIPSEL"); \ | |
| 561 } \ | |
| 562 \ | |
| 563 /* Whether calls should go through $25. The separate __PIC__ \ | |
| 564 macro indicates whether abicalls code might use a GOT. */ \ | |
| 565 if (TARGET_ABICALLS) \ | |
| 566 builtin_define ("__mips_abicalls"); \ | |
| 567 \ | |
| 568 /* Whether Loongson vector modes are enabled. */ \ | |
| 569 if (TARGET_LOONGSON_VECTORS) \ | |
| 570 builtin_define ("__mips_loongson_vector_rev"); \ | |
| 571 \ | |
| 572 /* Historical Octeon macro. */ \ | |
| 573 if (TARGET_OCTEON) \ | |
| 574 builtin_define ("__OCTEON__"); \ | |
| 575 \ | |
| 576 /* Macros dependent on the C dialect. */ \ | |
| 577 if (preprocessing_asm_p ()) \ | |
| 578 { \ | |
| 579 builtin_define_std ("LANGUAGE_ASSEMBLY"); \ | |
| 580 builtin_define ("_LANGUAGE_ASSEMBLY"); \ | |
| 581 } \ | |
| 582 else if (c_dialect_cxx ()) \ | |
| 583 { \ | |
| 584 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \ | |
| 585 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ | |
| 586 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ | |
| 587 } \ | |
| 588 else \ | |
| 589 { \ | |
| 590 builtin_define_std ("LANGUAGE_C"); \ | |
| 591 builtin_define ("_LANGUAGE_C"); \ | |
| 592 } \ | |
| 593 if (c_dialect_objc ()) \ | |
| 594 { \ | |
| 595 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \ | |
| 596 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ | |
| 597 /* Bizarre, but needed at least for Irix. */ \ | |
| 598 builtin_define_std ("LANGUAGE_C"); \ | |
| 599 builtin_define ("_LANGUAGE_C"); \ | |
| 600 } \ | |
| 601 \ | |
| 602 if (mips_abi == ABI_EABI) \ | |
| 603 builtin_define ("__mips_eabi"); \ | |
| 604 \ | |
| 605 if (TARGET_CACHE_BUILTIN) \ | |
| 606 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \ | |
| 607 } \ | |
| 608 while (0) | |
| 609 | |
| 610 /* Default target_flags if no switches are specified */ | |
| 611 | |
| 612 #ifndef TARGET_DEFAULT | |
| 613 #define TARGET_DEFAULT 0 | |
| 614 #endif | |
| 615 | |
| 616 #ifndef TARGET_CPU_DEFAULT | |
| 617 #define TARGET_CPU_DEFAULT 0 | |
| 618 #endif | |
| 619 | |
| 620 #ifndef TARGET_ENDIAN_DEFAULT | |
| 621 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN | |
| 622 #endif | |
| 623 | |
| 624 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT | |
| 625 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS | |
| 626 #endif | |
| 627 | |
| 628 /* 'from-abi' makes a good default: you get whatever the ABI requires. */ | |
| 629 #ifndef MIPS_ISA_DEFAULT | |
| 630 #ifndef MIPS_CPU_STRING_DEFAULT | |
| 631 #define MIPS_CPU_STRING_DEFAULT "from-abi" | |
| 632 #endif | |
| 633 #endif | |
| 634 | |
| 635 #ifdef IN_LIBGCC2 | |
| 636 #undef TARGET_64BIT | |
| 637 /* Make this compile time constant for libgcc2 */ | |
| 638 #ifdef __mips64 | |
| 639 #define TARGET_64BIT 1 | |
| 640 #else | |
| 641 #define TARGET_64BIT 0 | |
| 642 #endif | |
| 643 #endif /* IN_LIBGCC2 */ | |
| 644 | |
| 645 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code | |
| 646 when compiled with hardware floating point. This is because MIPS16 | |
| 647 code cannot save and restore the floating-point registers, which is | |
| 648 important if in a mixed MIPS16/non-MIPS16 environment. */ | |
| 649 | |
| 650 #ifdef IN_LIBGCC2 | |
| 651 #if __mips_hard_float | |
| 652 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__)) | |
| 653 #endif | |
| 654 #endif /* IN_LIBGCC2 */ | |
| 655 | |
| 656 #define TARGET_LIBGCC_SDATA_SECTION ".sdata" | |
| 657 | |
| 658 #ifndef MULTILIB_ENDIAN_DEFAULT | |
| 659 #if TARGET_ENDIAN_DEFAULT == 0 | |
| 660 #define MULTILIB_ENDIAN_DEFAULT "EL" | |
| 661 #else | |
| 662 #define MULTILIB_ENDIAN_DEFAULT "EB" | |
| 663 #endif | |
| 664 #endif | |
| 665 | |
| 666 #ifndef MULTILIB_ISA_DEFAULT | |
| 667 # if MIPS_ISA_DEFAULT == 1 | |
| 668 # define MULTILIB_ISA_DEFAULT "mips1" | |
| 669 # else | |
| 670 # if MIPS_ISA_DEFAULT == 2 | |
| 671 # define MULTILIB_ISA_DEFAULT "mips2" | |
| 672 # else | |
| 673 # if MIPS_ISA_DEFAULT == 3 | |
| 674 # define MULTILIB_ISA_DEFAULT "mips3" | |
| 675 # else | |
| 676 # if MIPS_ISA_DEFAULT == 4 | |
| 677 # define MULTILIB_ISA_DEFAULT "mips4" | |
| 678 # else | |
| 679 # if MIPS_ISA_DEFAULT == 32 | |
| 680 # define MULTILIB_ISA_DEFAULT "mips32" | |
| 681 # else | |
| 682 # if MIPS_ISA_DEFAULT == 33 | |
| 683 # define MULTILIB_ISA_DEFAULT "mips32r2" | |
| 684 # else | |
| 685 # if MIPS_ISA_DEFAULT == 64 | |
| 686 # define MULTILIB_ISA_DEFAULT "mips64" | |
| 687 # else | |
| 688 # if MIPS_ISA_DEFAULT == 65 | |
| 689 # define MULTILIB_ISA_DEFAULT "mips64r2" | |
| 690 # else | |
| 691 # define MULTILIB_ISA_DEFAULT "mips1" | |
| 692 # endif | |
| 693 # endif | |
| 694 # endif | |
| 695 # endif | |
| 696 # endif | |
| 697 # endif | |
| 698 # endif | |
| 699 # endif | |
| 700 #endif | |
| 701 | |
|
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702 #ifndef MIPS_ABI_DEFAULT |
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703 #define MIPS_ABI_DEFAULT ABI_32 |
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704 #endif |
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705 |
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706 /* Use the most portable ABI flag for the ASM specs. */ |
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707 |
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708 #if MIPS_ABI_DEFAULT == ABI_32 |
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709 #define MULTILIB_ABI_DEFAULT "mabi=32" |
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710 #endif |
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711 |
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712 #if MIPS_ABI_DEFAULT == ABI_O64 |
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713 #define MULTILIB_ABI_DEFAULT "mabi=o64" |
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714 #endif |
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715 |
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716 #if MIPS_ABI_DEFAULT == ABI_N32 |
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717 #define MULTILIB_ABI_DEFAULT "mabi=n32" |
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718 #endif |
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719 |
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720 #if MIPS_ABI_DEFAULT == ABI_64 |
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721 #define MULTILIB_ABI_DEFAULT "mabi=64" |
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722 #endif |
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723 |
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724 #if MIPS_ABI_DEFAULT == ABI_EABI |
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725 #define MULTILIB_ABI_DEFAULT "mabi=eabi" |
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726 #endif |
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727 |
| 0 | 728 #ifndef MULTILIB_DEFAULTS |
| 729 #define MULTILIB_DEFAULTS \ | |
| 730 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT } | |
| 731 #endif | |
| 732 | |
| 733 /* We must pass -EL to the linker by default for little endian embedded | |
| 734 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the | |
| 735 linker will default to using big-endian output files. The OUTPUT_FORMAT | |
| 736 line must be in the linker script, otherwise -EB/-EL will not work. */ | |
| 737 | |
| 738 #ifndef ENDIAN_SPEC | |
| 739 #if TARGET_ENDIAN_DEFAULT == 0 | |
| 740 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}" | |
| 741 #else | |
| 742 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}" | |
| 743 #endif | |
| 744 #endif | |
| 745 | |
| 746 /* A spec condition that matches all non-mips16 -mips arguments. */ | |
| 747 | |
| 748 #define MIPS_ISA_LEVEL_OPTION_SPEC \ | |
| 749 "mips1|mips2|mips3|mips4|mips32*|mips64*" | |
| 750 | |
| 751 /* A spec condition that matches all non-mips16 architecture arguments. */ | |
| 752 | |
| 753 #define MIPS_ARCH_OPTION_SPEC \ | |
| 754 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*" | |
| 755 | |
| 756 /* A spec that infers a -mips argument from an -march argument, | |
| 757 or injects the default if no architecture is specified. */ | |
| 758 | |
| 759 #define MIPS_ISA_LEVEL_SPEC \ | |
| 760 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \ | |
| 761 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \ | |
| 762 %{march=mips2|march=r6000:-mips2} \ | |
| 763 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \ | |
| 764 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \ | |
| 765 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \ | |
| 766 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \ | |
| 767 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \ | |
|
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768 |march=34k*|march=74k*|march=1004k*: -mips32r2} \ |
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769 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |
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770 |march=xlr: -mips64} \ |
| 0 | 771 %{march=mips64r2|march=octeon: -mips64r2} \ |
| 772 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}" | |
| 773 | |
| 774 /* A spec that infers a -mhard-float or -msoft-float setting from an | |
| 775 -march argument. Note that soft-float and hard-float code are not | |
| 776 link-compatible. */ | |
| 777 | |
| 778 #define MIPS_ARCH_FLOAT_SPEC \ | |
| 779 "%{mhard-float|msoft-float|march=mips*:; \ | |
| 780 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \ | |
|
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781 |march=34kc|march=74kc|march=1004kc|march=5kc \ |
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782 |march=octeon|march=xlr: -msoft-float; \ |
| 0 | 783 march=*: -mhard-float}" |
| 784 | |
| 785 /* A spec condition that matches 32-bit options. It only works if | |
| 786 MIPS_ISA_LEVEL_SPEC has been applied. */ | |
| 787 | |
| 788 #define MIPS_32BIT_OPTION_SPEC \ | |
| 789 "mips1|mips2|mips32*|mgp32" | |
| 790 | |
|
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791 #if MIPS_ABI_DEFAULT == ABI_O64 \ |
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792 || MIPS_ABI_DEFAULT == ABI_N32 \ |
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793 || MIPS_ABI_DEFAULT == ABI_64 |
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794 #define OPT_ARCH64 "mabi=32|mgp32:;" |
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795 #define OPT_ARCH32 "mabi=32|mgp32" |
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796 #else |
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797 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64" |
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798 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;" |
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799 #endif |
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800 |
| 0 | 801 /* Support for a compile-time default CPU, et cetera. The rules are: |
| 802 --with-arch is ignored if -march is specified or a -mips is specified | |
|
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803 (other than -mips16); likewise --with-arch-32 and --with-arch-64. |
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804 --with-tune is ignored if -mtune is specified; likewise |
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805 --with-tune-32 and --with-tune-64. |
| 0 | 806 --with-abi is ignored if -mabi is specified. |
| 807 --with-float is ignored if -mhard-float or -msoft-float are | |
| 808 specified. | |
| 809 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are | |
| 810 specified. */ | |
| 811 #define OPTION_DEFAULT_SPECS \ | |
| 812 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \ | |
|
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813 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \ |
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814 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \ |
| 0 | 815 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ |
|
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816 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \ |
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817 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \ |
| 0 | 818 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \ |
| 819 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \ | |
| 820 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \ | |
| 821 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \ | |
|
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822 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \ |
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823 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" } |
| 0 | 824 |
| 825 | |
| 826 /* A spec that infers the -mdsp setting from an -march argument. */ | |
| 827 #define BASE_DRIVER_SELF_SPECS \ | |
|
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828 "%{!mno-dsp:%{march=24ke*|march=34k*|march=74k*|march=1004k*: -mdsp}}" |
| 0 | 829 |
| 830 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS | |
| 831 | |
| 832 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \ | |
| 833 && ISA_HAS_COND_TRAP) | |
| 834 | |
| 835 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16) | |
| 836 | |
| 837 /* True if the ABI can only work with 64-bit integer registers. We | |
| 838 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but | |
| 839 otherwise floating-point registers must also be 64-bit. */ | |
| 840 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64) | |
| 841 | |
| 842 /* Likewise for 32-bit regs. */ | |
| 843 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32) | |
| 844 | |
| 845 /* True if the file format uses 64-bit symbols. At present, this is | |
| 846 only true for n64, which uses 64-bit ELF. */ | |
| 847 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64) | |
| 848 | |
| 849 /* True if symbols are 64 bits wide. This is usually determined by | |
| 850 the ABI's file format, but it can be overridden by -msym32. Note that | |
| 851 overriding the size with -msym32 changes the ABI of relocatable objects, | |
| 852 although it doesn't change the ABI of a fully-linked object. */ | |
| 853 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS && !TARGET_SYM32) | |
| 854 | |
| 855 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */ | |
| 856 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \ | |
| 857 || ISA_MIPS4 \ | |
| 858 || ISA_MIPS64 \ | |
| 859 || ISA_MIPS64R2) | |
| 860 | |
| 861 /* ISA has branch likely instructions (e.g. mips2). */ | |
| 862 /* Disable branchlikely for tx39 until compare rewrite. They haven't | |
| 863 been generated up to this point. */ | |
| 864 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1) | |
| 865 | |
| 866 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */ | |
| 867 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \ | |
| 868 || TARGET_MIPS5400 \ | |
| 869 || TARGET_MIPS5500 \ | |
| 870 || TARGET_MIPS7000 \ | |
| 871 || TARGET_MIPS9000 \ | |
| 872 || TARGET_MAD \ | |
| 873 || ISA_MIPS32 \ | |
| 874 || ISA_MIPS32R2 \ | |
| 875 || ISA_MIPS64 \ | |
| 876 || ISA_MIPS64R2) \ | |
| 877 && !TARGET_MIPS16) | |
| 878 | |
| 879 /* ISA has a three-operand multiplication instruction. */ | |
| 880 #define ISA_HAS_DMUL3 (TARGET_64BIT \ | |
| 881 && TARGET_OCTEON \ | |
| 882 && !TARGET_MIPS16) | |
| 883 | |
| 884 /* ISA has the floating-point conditional move instructions introduced | |
| 885 in mips4. */ | |
| 886 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \ | |
| 887 || ISA_MIPS32 \ | |
| 888 || ISA_MIPS32R2 \ | |
| 889 || ISA_MIPS64 \ | |
| 890 || ISA_MIPS64R2) \ | |
| 891 && !TARGET_MIPS5500 \ | |
| 892 && !TARGET_MIPS16) | |
| 893 | |
| 894 /* ISA has the integer conditional move instructions introduced in mips4 and | |
| 895 ST Loongson 2E/2F. */ | |
| 896 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF) | |
| 897 | |
| 898 /* ISA has LDC1 and SDC1. */ | |
| 899 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16) | |
| 900 | |
| 901 /* ISA has the mips4 FP condition code instructions: FP-compare to CC, | |
| 902 branch on CC, and move (both FP and non-FP) on CC. */ | |
| 903 #define ISA_HAS_8CC (ISA_MIPS4 \ | |
| 904 || ISA_MIPS32 \ | |
| 905 || ISA_MIPS32R2 \ | |
| 906 || ISA_MIPS64 \ | |
| 907 || ISA_MIPS64R2) | |
| 908 | |
| 909 /* This is a catch all for other mips4 instructions: indexed load, the | |
| 910 FP madd and msub instructions, and the FP recip and recip sqrt | |
| 911 instructions. */ | |
| 912 #define ISA_HAS_FP4 ((ISA_MIPS4 \ | |
| 913 || (ISA_MIPS32R2 && TARGET_FLOAT64) \ | |
| 914 || ISA_MIPS64 \ | |
| 915 || ISA_MIPS64R2) \ | |
| 916 && !TARGET_MIPS16) | |
| 917 | |
| 918 /* ISA has paired-single instructions. */ | |
| 919 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2) | |
| 920 | |
| 921 /* ISA has conditional trap instructions. */ | |
| 922 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \ | |
| 923 && !TARGET_MIPS16) | |
| 924 | |
| 925 /* ISA has integer multiply-accumulate instructions, madd and msub. */ | |
| 926 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \ | |
| 927 || ISA_MIPS32R2 \ | |
| 928 || ISA_MIPS64 \ | |
| 929 || ISA_MIPS64R2) \ | |
| 930 && !TARGET_MIPS16) | |
| 931 | |
| 932 /* Integer multiply-accumulate instructions should be generated. */ | |
| 933 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K) | |
| 934 | |
| 935 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */ | |
| 936 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4 | |
| 937 | |
| 938 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */ | |
| 939 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF | |
| 940 | |
| 941 /* ISA has floating-point nmadd and nmsub instructions | |
| 942 'd = -((a * b) [+-] c)'. */ | |
| 943 #define ISA_HAS_NMADD4_NMSUB4(MODE) \ | |
| 944 ((ISA_MIPS4 \ | |
| 945 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \ | |
| 946 || ISA_MIPS64 \ | |
| 947 || ISA_MIPS64R2) \ | |
| 948 && (!TARGET_MIPS5400 || TARGET_MAD) \ | |
| 949 && !TARGET_MIPS16) | |
| 950 | |
| 951 /* ISA has floating-point nmadd and nmsub instructions | |
| 952 'c = -((a * b) [+-] c)'. */ | |
| 953 #define ISA_HAS_NMADD3_NMSUB3(MODE) \ | |
| 954 TARGET_LOONGSON_2EF | |
| 955 | |
| 956 /* ISA has count leading zeroes/ones instruction (not implemented). */ | |
| 957 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ | |
| 958 || ISA_MIPS32R2 \ | |
| 959 || ISA_MIPS64 \ | |
| 960 || ISA_MIPS64R2) \ | |
| 961 && !TARGET_MIPS16) | |
| 962 | |
| 963 /* ISA has three operand multiply instructions that put | |
| 964 the high part in an accumulator: mulhi or mulhiu. */ | |
| 965 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \ | |
| 966 || TARGET_MIPS5500 \ | |
| 967 || TARGET_SR71K) \ | |
| 968 && !TARGET_MIPS16) | |
| 969 | |
| 970 /* ISA has three operand multiply instructions that | |
| 971 negates the result and puts the result in an accumulator. */ | |
| 972 #define ISA_HAS_MULS ((TARGET_MIPS5400 \ | |
| 973 || TARGET_MIPS5500 \ | |
| 974 || TARGET_SR71K) \ | |
| 975 && !TARGET_MIPS16) | |
| 976 | |
| 977 /* ISA has three operand multiply instructions that subtracts the | |
| 978 result from a 4th operand and puts the result in an accumulator. */ | |
| 979 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \ | |
| 980 || TARGET_MIPS5500 \ | |
| 981 || TARGET_SR71K) \ | |
| 982 && !TARGET_MIPS16) | |
| 983 | |
| 984 /* ISA has three operand multiply instructions that the result | |
| 985 from a 4th operand and puts the result in an accumulator. */ | |
| 986 #define ISA_HAS_MACC ((TARGET_MIPS4120 \ | |
| 987 || TARGET_MIPS4130 \ | |
| 988 || TARGET_MIPS5400 \ | |
| 989 || TARGET_MIPS5500 \ | |
| 990 || TARGET_SR71K) \ | |
| 991 && !TARGET_MIPS16) | |
| 992 | |
| 993 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */ | |
| 994 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \ | |
| 995 || TARGET_MIPS4130) \ | |
| 996 && !TARGET_MIPS16) | |
| 997 | |
| 998 /* ISA has the "ror" (rotate right) instructions. */ | |
| 999 #define ISA_HAS_ROR ((ISA_MIPS32R2 \ | |
| 1000 || ISA_MIPS64R2 \ | |
| 1001 || TARGET_MIPS5400 \ | |
| 1002 || TARGET_MIPS5500 \ | |
| 1003 || TARGET_SR71K \ | |
| 1004 || TARGET_SMARTMIPS) \ | |
| 1005 && !TARGET_MIPS16) | |
| 1006 | |
| 1007 /* ISA has data prefetch instructions. This controls use of 'pref'. */ | |
| 1008 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ | |
| 1009 || TARGET_LOONGSON_2EF \ | |
| 1010 || ISA_MIPS32 \ | |
| 1011 || ISA_MIPS32R2 \ | |
| 1012 || ISA_MIPS64 \ | |
| 1013 || ISA_MIPS64R2) \ | |
| 1014 && !TARGET_MIPS16) | |
| 1015 | |
| 1016 /* ISA has data indexed prefetch instructions. This controls use of | |
| 1017 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. | |
| 1018 (prefx is a cop1x instruction, so can only be used if FP is | |
| 1019 enabled.) */ | |
| 1020 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \ | |
| 1021 || ISA_MIPS32R2 \ | |
| 1022 || ISA_MIPS64 \ | |
| 1023 || ISA_MIPS64R2) \ | |
| 1024 && !TARGET_MIPS16) | |
| 1025 | |
| 1026 /* True if trunc.w.s and trunc.w.d are real (not synthetic) | |
| 1027 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d | |
| 1028 also requires TARGET_DOUBLE_FLOAT. */ | |
| 1029 #define ISA_HAS_TRUNC_W (!ISA_MIPS1) | |
| 1030 | |
| 1031 /* ISA includes the MIPS32r2 seb and seh instructions. */ | |
| 1032 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \ | |
| 1033 || ISA_MIPS64R2) \ | |
| 1034 && !TARGET_MIPS16) | |
| 1035 | |
| 1036 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */ | |
| 1037 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \ | |
| 1038 || ISA_MIPS64R2) \ | |
| 1039 && !TARGET_MIPS16) | |
| 1040 | |
| 1041 /* ISA has instructions for accessing top part of 64-bit fp regs. */ | |
| 1042 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \ | |
| 1043 && (ISA_MIPS32R2 \ | |
| 1044 || ISA_MIPS64R2)) | |
| 1045 | |
| 1046 /* ISA has lwxs instruction (load w/scaled index address. */ | |
| 1047 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16) | |
| 1048 | |
| 1049 /* The DSP ASE is available. */ | |
| 1050 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16) | |
| 1051 | |
| 1052 /* Revision 2 of the DSP ASE is available. */ | |
| 1053 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16) | |
| 1054 | |
| 1055 /* True if the result of a load is not available to the next instruction. | |
| 1056 A nop will then be needed between instructions like "lw $4,..." | |
| 1057 and "addiu $4,$4,1". */ | |
| 1058 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \ | |
| 1059 && !TARGET_MIPS3900 \ | |
| 1060 && !TARGET_MIPS16) | |
| 1061 | |
| 1062 /* Likewise mtc1 and mfc1. */ | |
| 1063 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \ | |
| 1064 && !TARGET_LOONGSON_2EF) | |
| 1065 | |
| 1066 /* Likewise floating-point comparisons. */ | |
| 1067 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \ | |
| 1068 && !TARGET_LOONGSON_2EF) | |
| 1069 | |
| 1070 /* True if mflo and mfhi can be immediately followed by instructions | |
| 1071 which write to the HI and LO registers. | |
| 1072 | |
| 1073 According to MIPS specifications, MIPS ISAs I, II, and III need | |
| 1074 (at least) two instructions between the reads of HI/LO and | |
| 1075 instructions which write them, and later ISAs do not. Contradicting | |
| 1076 the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
| 1077 the UM for the NEC Vr5000) document needing the instructions between | |
| 1078 HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
| 1079 MIPS64 and later ISAs to have the interlocks, plus any specific | |
| 1080 earlier-ISA CPUs for which CPU documentation declares that the | |
| 1081 instructions are really interlocked. */ | |
| 1082 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \ | |
| 1083 || ISA_MIPS32R2 \ | |
| 1084 || ISA_MIPS64 \ | |
| 1085 || ISA_MIPS64R2 \ | |
| 1086 || TARGET_MIPS5500 \ | |
| 1087 || TARGET_LOONGSON_2EF) | |
| 1088 | |
| 1089 /* ISA includes synci, jr.hb and jalr.hb. */ | |
| 1090 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \ | |
| 1091 || ISA_MIPS64R2) \ | |
| 1092 && !TARGET_MIPS16) | |
| 1093 | |
| 1094 /* ISA includes sync. */ | |
| 1095 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16) | |
| 1096 #define GENERATE_SYNC \ | |
| 1097 (target_flags_explicit & MASK_LLSC \ | |
| 1098 ? TARGET_LLSC && !TARGET_MIPS16 \ | |
| 1099 : ISA_HAS_SYNC) | |
| 1100 | |
| 1101 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC | |
| 1102 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC | |
| 1103 instructions. */ | |
| 1104 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16) | |
| 1105 #define GENERATE_LL_SC \ | |
| 1106 (target_flags_explicit & MASK_LLSC \ | |
| 1107 ? TARGET_LLSC && !TARGET_MIPS16 \ | |
| 1108 : ISA_HAS_LL_SC) | |
| 1109 | |
| 1110 /* ISA includes the baddu instruction. */ | |
| 1111 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16) | |
| 1112 | |
| 1113 /* ISA includes the bbit* instructions. */ | |
| 1114 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16) | |
| 1115 | |
| 1116 /* ISA includes the cins instruction. */ | |
| 1117 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16) | |
| 1118 | |
| 1119 /* ISA includes the exts instruction. */ | |
| 1120 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16) | |
| 1121 | |
| 1122 /* ISA includes the seq and sne instructions. */ | |
| 1123 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16) | |
| 1124 | |
| 1125 /* ISA includes the pop instruction. */ | |
| 1126 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16) | |
| 1127 | |
| 1128 /* The CACHE instruction is available in non-MIPS16 code. */ | |
| 1129 #define TARGET_CACHE_BUILTIN (mips_isa >= 3) | |
| 1130 | |
| 1131 /* The CACHE instruction is available. */ | |
| 1132 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16) | |
| 1133 | |
| 1134 /* Add -G xx support. */ | |
| 1135 | |
| 1136 #undef SWITCH_TAKES_ARG | |
| 1137 #define SWITCH_TAKES_ARG(CHAR) \ | |
| 1138 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G') | |
| 1139 | |
| 1140 #define OVERRIDE_OPTIONS mips_override_options () | |
| 1141 | |
| 1142 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage () | |
| 1143 | |
| 1144 /* Show we can debug even without a frame pointer. */ | |
| 1145 #define CAN_DEBUG_WITHOUT_FP | |
| 1146 | |
| 1147 /* Tell collect what flags to pass to nm. */ | |
| 1148 #ifndef NM_FLAGS | |
| 1149 #define NM_FLAGS "-Bn" | |
| 1150 #endif | |
| 1151 | |
| 1152 | |
| 1153 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options | |
| 1154 to the assembler. It may be overridden by subtargets. */ | |
| 1155 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC | |
| 1156 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\ | |
| 1157 %{noasmopt:-O0} \ | |
| 1158 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}" | |
| 1159 #endif | |
| 1160 | |
| 1161 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to | |
| 1162 the assembler. It may be overridden by subtargets. | |
| 1163 | |
| 1164 Beginning with gas 2.13, -mdebug must be passed to correctly handle | |
| 1165 COFF debugging info. */ | |
| 1166 | |
| 1167 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC | |
| 1168 #define SUBTARGET_ASM_DEBUGGING_SPEC "\ | |
| 1169 %{g} %{g0} %{g1} %{g2} %{g3} \ | |
| 1170 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \ | |
| 1171 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \ | |
| 1172 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \ | |
| 1173 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \ | |
| 1174 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}" | |
| 1175 #endif | |
| 1176 | |
| 1177 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be | |
| 1178 overridden by subtargets. */ | |
| 1179 | |
| 1180 #ifndef SUBTARGET_ASM_SPEC | |
| 1181 #define SUBTARGET_ASM_SPEC "" | |
| 1182 #endif | |
| 1183 | |
| 1184 #undef ASM_SPEC | |
| 1185 #define ASM_SPEC "\ | |
| 1186 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \ | |
| 1187 %{mips32*} %{mips64*} \ | |
| 1188 %{mips16} %{mno-mips16:-no-mips16} \ | |
| 1189 %{mips3d} %{mno-mips3d:-no-mips3d} \ | |
| 1190 %{mdmx} %{mno-mdmx:-no-mdmx} \ | |
| 1191 %{mdsp} %{mno-dsp} \ | |
| 1192 %{mdspr2} %{mno-dspr2} \ | |
| 1193 %{msmartmips} %{mno-smartmips} \ | |
| 1194 %{mmt} %{mno-mt} \ | |
| 1195 %{mfix-vr4120} %{mfix-vr4130} \ | |
| 1196 %(subtarget_asm_optimizing_spec) \ | |
| 1197 %(subtarget_asm_debugging_spec) \ | |
| 1198 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \ | |
| 1199 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \ | |
| 1200 %{mfp32} %{mfp64} \ | |
| 1201 %{mshared} %{mno-shared} \ | |
| 1202 %{msym32} %{mno-sym32} \ | |
| 1203 %{mtune=*} %{v} \ | |
| 1204 %(subtarget_asm_spec)" | |
| 1205 | |
| 1206 /* Extra switches sometimes passed to the linker. */ | |
| 1207 /* ??? The bestGnum will never be passed to the linker, because the gcc driver | |
| 1208 will interpret it as a -b option. */ | |
| 1209 | |
| 1210 #ifndef LINK_SPEC | |
| 1211 #define LINK_SPEC "\ | |
| 1212 %(endian_spec) \ | |
| 1213 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \ | |
| 1214 %{bestGnum} %{shared} %{non_shared}" | |
| 1215 #endif /* LINK_SPEC defined */ | |
| 1216 | |
| 1217 | |
| 1218 /* Specs for the compiler proper */ | |
| 1219 | |
| 1220 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be | |
| 1221 overridden by subtargets. */ | |
| 1222 #ifndef SUBTARGET_CC1_SPEC | |
| 1223 #define SUBTARGET_CC1_SPEC "" | |
| 1224 #endif | |
| 1225 | |
| 1226 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */ | |
| 1227 | |
| 1228 #undef CC1_SPEC | |
| 1229 #define CC1_SPEC "\ | |
| 1230 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \ | |
| 1231 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \ | |
| 1232 %{save-temps: } \ | |
| 1233 %(subtarget_cc1_spec)" | |
| 1234 | |
| 1235 /* Preprocessor specs. */ | |
| 1236 | |
| 1237 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be | |
| 1238 overridden by subtargets. */ | |
| 1239 #ifndef SUBTARGET_CPP_SPEC | |
| 1240 #define SUBTARGET_CPP_SPEC "" | |
| 1241 #endif | |
| 1242 | |
| 1243 #define CPP_SPEC "%(subtarget_cpp_spec)" | |
| 1244 | |
| 1245 /* This macro defines names of additional specifications to put in the specs | |
| 1246 that can be used in various specifications like CC1_SPEC. Its definition | |
| 1247 is an initializer with a subgrouping for each command option. | |
| 1248 | |
| 1249 Each subgrouping contains a string constant, that defines the | |
| 1250 specification name, and a string constant that used by the GCC driver | |
| 1251 program. | |
| 1252 | |
| 1253 Do not define this macro if it does not need to do anything. */ | |
| 1254 | |
| 1255 #define EXTRA_SPECS \ | |
| 1256 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \ | |
| 1257 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ | |
| 1258 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \ | |
| 1259 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \ | |
| 1260 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ | |
| 1261 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \ | |
| 1262 { "endian_spec", ENDIAN_SPEC }, \ | |
| 1263 SUBTARGET_EXTRA_SPECS | |
| 1264 | |
| 1265 #ifndef SUBTARGET_EXTRA_SPECS | |
| 1266 #define SUBTARGET_EXTRA_SPECS | |
| 1267 #endif | |
| 1268 | |
| 1269 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */ | |
| 1270 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */ | |
| 1271 | |
| 1272 #ifndef PREFERRED_DEBUGGING_TYPE | |
| 1273 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG | |
| 1274 #endif | |
| 1275 | |
| 1276 /* The size of DWARF addresses should be the same as the size of symbols | |
| 1277 in the target file format. They shouldn't depend on things like -msym32, | |
| 1278 because many DWARF consumers do not allow the mixture of address sizes | |
| 1279 that one would then get from linking -msym32 code with -msym64 code. | |
| 1280 | |
| 1281 Note that the default POINTER_SIZE test is not appropriate for MIPS. | |
| 1282 EABI64 has 64-bit pointers but uses 32-bit ELF. */ | |
| 1283 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4) | |
| 1284 | |
| 1285 /* By default, turn on GDB extensions. */ | |
| 1286 #define DEFAULT_GDB_EXTENSIONS 1 | |
| 1287 | |
| 1288 /* Local compiler-generated symbols must have a prefix that the assembler | |
| 1289 understands. By default, this is $, although some targets (e.g., | |
| 1290 NetBSD-ELF) need to override this. */ | |
| 1291 | |
| 1292 #ifndef LOCAL_LABEL_PREFIX | |
| 1293 #define LOCAL_LABEL_PREFIX "$" | |
| 1294 #endif | |
| 1295 | |
| 1296 /* By default on the mips, external symbols do not have an underscore | |
| 1297 prepended, but some targets (e.g., NetBSD) require this. */ | |
| 1298 | |
| 1299 #ifndef USER_LABEL_PREFIX | |
| 1300 #define USER_LABEL_PREFIX "" | |
| 1301 #endif | |
| 1302 | |
| 1303 /* On Sun 4, this limit is 2048. We use 1500 to be safe, | |
| 1304 since the length can run past this up to a continuation point. */ | |
| 1305 #undef DBX_CONTIN_LENGTH | |
| 1306 #define DBX_CONTIN_LENGTH 1500 | |
| 1307 | |
| 1308 /* How to renumber registers for dbx and gdb. */ | |
| 1309 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO] | |
| 1310 | |
| 1311 /* The mapping from gcc register number to DWARF 2 CFA column number. */ | |
| 1312 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO] | |
| 1313 | |
| 1314 /* The DWARF 2 CFA column which tracks the return address. */ | |
|
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1315 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM |
| 0 | 1316 |
| 1317 /* Before the prologue, RA lives in r31. */ | |
|
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1318 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM) |
| 0 | 1319 |
| 1320 /* Describe how we implement __builtin_eh_return. */ | |
| 1321 #define EH_RETURN_DATA_REGNO(N) \ | |
| 1322 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM) | |
| 1323 | |
| 1324 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3) | |
| 1325 | |
|
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1326 #define EH_USES(N) mips_eh_uses (N) |
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1327 |
| 0 | 1328 /* Offsets recorded in opcodes are a multiple of this alignment factor. |
| 1329 The default for this in 64-bit mode is 8, which causes problems with | |
| 1330 SFmode register saves. */ | |
| 1331 #define DWARF_CIE_DATA_ALIGNMENT -4 | |
| 1332 | |
| 1333 /* Correct the offset of automatic variables and arguments. Note that | |
| 1334 the MIPS debug format wants all automatic variables and arguments | |
| 1335 to be in terms of the virtual frame pointer (stack pointer before | |
| 1336 any adjustment in the function), while the MIPS 3.0 linker wants | |
| 1337 the frame pointer to be the stack pointer after the initial | |
| 1338 adjustment. */ | |
| 1339 | |
| 1340 #define DEBUGGER_AUTO_OFFSET(X) \ | |
| 1341 mips_debugger_offset (X, (HOST_WIDE_INT) 0) | |
| 1342 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \ | |
| 1343 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET) | |
| 1344 | |
| 1345 /* Target machine storage layout */ | |
| 1346 | |
| 1347 #define BITS_BIG_ENDIAN 0 | |
| 1348 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) | |
| 1349 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) | |
| 1350 | |
| 1351 /* Define this to set the endianness to use in libgcc2.c, which can | |
| 1352 not depend on target_flags. */ | |
| 1353 #if !defined(MIPSEL) && !defined(__MIPSEL__) | |
| 1354 #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
| 1355 #else | |
| 1356 #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
| 1357 #endif | |
| 1358 | |
| 1359 #define MAX_BITS_PER_WORD 64 | |
| 1360 | |
| 1361 /* Width of a word, in units (bytes). */ | |
| 1362 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) | |
| 1363 #ifndef IN_LIBGCC2 | |
| 1364 #define MIN_UNITS_PER_WORD 4 | |
| 1365 #endif | |
| 1366 | |
| 1367 /* For MIPS, width of a floating point register. */ | |
| 1368 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4) | |
| 1369 | |
| 1370 /* The number of consecutive floating-point registers needed to store the | |
| 1371 largest format supported by the FPU. */ | |
| 1372 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2) | |
| 1373 | |
| 1374 /* The number of consecutive floating-point registers needed to store the | |
| 1375 smallest format supported by the FPU. */ | |
| 1376 #define MIN_FPRS_PER_FMT \ | |
| 1377 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \ | |
| 1378 ? 1 : MAX_FPRS_PER_FMT) | |
| 1379 | |
| 1380 /* The largest size of value that can be held in floating-point | |
| 1381 registers and moved with a single instruction. */ | |
| 1382 #define UNITS_PER_HWFPVALUE \ | |
| 1383 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG) | |
| 1384 | |
| 1385 /* The largest size of value that can be held in floating-point | |
| 1386 registers. */ | |
| 1387 #define UNITS_PER_FPVALUE \ | |
| 1388 (TARGET_SOFT_FLOAT_ABI ? 0 \ | |
| 1389 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \ | |
| 1390 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT) | |
| 1391 | |
| 1392 /* The number of bytes in a double. */ | |
| 1393 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT) | |
| 1394 | |
| 1395 #define UNITS_PER_SIMD_WORD(MODE) \ | |
| 1396 (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD) | |
| 1397 | |
| 1398 /* Set the sizes of the core types. */ | |
| 1399 #define SHORT_TYPE_SIZE 16 | |
| 1400 #define INT_TYPE_SIZE 32 | |
| 1401 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) | |
| 1402 #define LONG_LONG_TYPE_SIZE 64 | |
| 1403 | |
| 1404 #define FLOAT_TYPE_SIZE 32 | |
| 1405 #define DOUBLE_TYPE_SIZE 64 | |
| 1406 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64) | |
| 1407 | |
| 1408 /* Define the sizes of fixed-point types. */ | |
| 1409 #define SHORT_FRACT_TYPE_SIZE 8 | |
| 1410 #define FRACT_TYPE_SIZE 16 | |
| 1411 #define LONG_FRACT_TYPE_SIZE 32 | |
| 1412 #define LONG_LONG_FRACT_TYPE_SIZE 64 | |
| 1413 | |
| 1414 #define SHORT_ACCUM_TYPE_SIZE 16 | |
| 1415 #define ACCUM_TYPE_SIZE 32 | |
| 1416 #define LONG_ACCUM_TYPE_SIZE 64 | |
| 1417 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC | |
| 1418 doesn't support 128-bit integers for MIPS32 currently. */ | |
| 1419 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64) | |
| 1420 | |
| 1421 /* long double is not a fixed mode, but the idea is that, if we | |
| 1422 support long double, we also want a 128-bit integer type. */ | |
| 1423 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE | |
| 1424 | |
| 1425 #ifdef IN_LIBGCC2 | |
| 1426 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \ | |
| 1427 || (defined _ABI64 && _MIPS_SIM == _ABI64) | |
| 1428 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 | |
| 1429 # else | |
| 1430 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 | |
| 1431 # endif | |
| 1432 #endif | |
| 1433 | |
| 1434 /* Width in bits of a pointer. */ | |
| 1435 #ifndef POINTER_SIZE | |
| 1436 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32) | |
| 1437 #endif | |
| 1438 | |
| 1439 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
| 1440 #define PARM_BOUNDARY BITS_PER_WORD | |
| 1441 | |
| 1442 /* Allocation boundary (in *bits*) for the code of a function. */ | |
| 1443 #define FUNCTION_BOUNDARY 32 | |
| 1444 | |
| 1445 /* Alignment of field after `int : 0' in a structure. */ | |
| 1446 #define EMPTY_FIELD_BOUNDARY 32 | |
| 1447 | |
| 1448 /* Every structure's size must be a multiple of this. */ | |
| 1449 /* 8 is observed right on a DECstation and on riscos 4.02. */ | |
| 1450 #define STRUCTURE_SIZE_BOUNDARY 8 | |
| 1451 | |
| 1452 /* There is no point aligning anything to a rounder boundary than this. */ | |
| 1453 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE | |
| 1454 | |
| 1455 /* All accesses must be aligned. */ | |
| 1456 #define STRICT_ALIGNMENT 1 | |
| 1457 | |
| 1458 /* Define this if you wish to imitate the way many other C compilers | |
| 1459 handle alignment of bitfields and the structures that contain | |
| 1460 them. | |
| 1461 | |
| 1462 The behavior is that the type written for a bit-field (`int', | |
| 1463 `short', or other integer type) imposes an alignment for the | |
| 1464 entire structure, as if the structure really did contain an | |
| 1465 ordinary field of that type. In addition, the bit-field is placed | |
| 1466 within the structure so that it would fit within such a field, | |
| 1467 not crossing a boundary for it. | |
| 1468 | |
| 1469 Thus, on most machines, a bit-field whose type is written as `int' | |
| 1470 would not cross a four-byte boundary, and would force four-byte | |
| 1471 alignment for the whole structure. (The alignment used may not | |
| 1472 be four bytes; it is controlled by the other alignment | |
| 1473 parameters.) | |
| 1474 | |
| 1475 If the macro is defined, its definition should be a C expression; | |
| 1476 a nonzero value for the expression enables this behavior. */ | |
| 1477 | |
| 1478 #define PCC_BITFIELD_TYPE_MATTERS 1 | |
| 1479 | |
| 1480 /* If defined, a C expression to compute the alignment given to a | |
| 1481 constant that is being placed in memory. CONSTANT is the constant | |
| 1482 and ALIGN is the alignment that the object would ordinarily have. | |
| 1483 The value of this macro is used instead of that alignment to align | |
| 1484 the object. | |
| 1485 | |
| 1486 If this macro is not defined, then ALIGN is used. | |
| 1487 | |
| 1488 The typical use of this macro is to increase alignment for string | |
| 1489 constants to be word aligned so that `strcpy' calls that copy | |
| 1490 constants can be done inline. */ | |
| 1491 | |
| 1492 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
| 1493 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ | |
| 1494 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
| 1495 | |
| 1496 /* If defined, a C expression to compute the alignment for a static | |
| 1497 variable. TYPE is the data type, and ALIGN is the alignment that | |
| 1498 the object would ordinarily have. The value of this macro is used | |
| 1499 instead of that alignment to align the object. | |
| 1500 | |
| 1501 If this macro is not defined, then ALIGN is used. | |
| 1502 | |
| 1503 One use of this macro is to increase alignment of medium-size | |
| 1504 data to make it all fit in fewer cache lines. Another is to | |
| 1505 cause character arrays to be word-aligned so that `strcpy' calls | |
| 1506 that copy constants to character arrays can be done inline. */ | |
| 1507 | |
| 1508 #undef DATA_ALIGNMENT | |
| 1509 #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
| 1510 ((((ALIGN) < BITS_PER_WORD) \ | |
| 1511 && (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
| 1512 || TREE_CODE (TYPE) == UNION_TYPE \ | |
| 1513 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
| 1514 | |
| 1515 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause | |
| 1516 character arrays to be word-aligned so that `strcpy' calls that copy | |
| 1517 constants to character arrays can be done inline, and 'strcmp' can be | |
| 1518 optimised to use word loads. */ | |
| 1519 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
| 1520 DATA_ALIGNMENT (TYPE, ALIGN) | |
| 1521 | |
| 1522 #define PAD_VARARGS_DOWN \ | |
| 1523 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) | |
| 1524 | |
| 1525 /* Define if operations between registers always perform the operation | |
| 1526 on the full register even if a narrower mode is specified. */ | |
| 1527 #define WORD_REGISTER_OPERATIONS | |
| 1528 | |
| 1529 /* When in 64-bit mode, move insns will sign extend SImode and CCmode | |
| 1530 moves. All other references are zero extended. */ | |
| 1531 #define LOAD_EXTEND_OP(MODE) \ | |
| 1532 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \ | |
| 1533 ? SIGN_EXTEND : ZERO_EXTEND) | |
| 1534 | |
| 1535 /* Define this macro if it is advisable to hold scalars in registers | |
| 1536 in a wider mode than that declared by the program. In such cases, | |
| 1537 the value is constrained to be within the bounds of the declared | |
| 1538 type, but kept valid in the wider mode. The signedness of the | |
| 1539 extension may differ from that of the type. */ | |
| 1540 | |
| 1541 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
| 1542 if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
| 1543 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
| 1544 { \ | |
| 1545 if ((MODE) == SImode) \ | |
| 1546 (UNSIGNEDP) = 0; \ | |
| 1547 (MODE) = Pmode; \ | |
| 1548 } | |
| 1549 | |
| 1550 /* Pmode is always the same as ptr_mode, but not always the same as word_mode. | |
| 1551 Extensions of pointers to word_mode must be signed. */ | |
| 1552 #define POINTERS_EXTEND_UNSIGNED false | |
| 1553 | |
| 1554 /* Define if loading short immediate values into registers sign extends. */ | |
| 1555 #define SHORT_IMMEDIATES_SIGN_EXTEND | |
| 1556 | |
| 1557 /* The [d]clz instructions have the natural values at 0. */ | |
| 1558 | |
| 1559 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
| 1560 ((VALUE) = GET_MODE_BITSIZE (MODE), 2) | |
| 1561 | |
| 1562 /* Standard register usage. */ | |
| 1563 | |
| 1564 /* Number of hardware registers. We have: | |
| 1565 | |
| 1566 - 32 integer registers | |
| 1567 - 32 floating point registers | |
| 1568 - 8 condition code registers | |
| 1569 - 2 accumulator registers (hi and lo) | |
| 1570 - 32 registers each for coprocessors 0, 2 and 3 | |
|
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1571 - 4 fake registers: |
| 0 | 1572 - ARG_POINTER_REGNUM |
| 1573 - FRAME_POINTER_REGNUM | |
| 1574 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details) | |
|
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1575 - CPRESTORE_SLOT_REGNUM |
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1576 - 2 dummy entries that were used at various times in the past. |
| 0 | 1577 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE |
| 1578 - 6 DSP control registers */ | |
| 1579 | |
| 1580 #define FIRST_PSEUDO_REGISTER 188 | |
| 1581 | |
| 1582 /* By default, fix the kernel registers ($26 and $27), the global | |
| 1583 pointer ($28) and the stack pointer ($29). This can change | |
| 1584 depending on the command-line options. | |
| 1585 | |
| 1586 Regarding coprocessor registers: without evidence to the contrary, | |
| 1587 it's best to assume that each coprocessor register has a unique | |
| 1588 use. This can be overridden, in, e.g., mips_override_options or | |
| 1589 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate | |
| 1590 for a particular target. */ | |
| 1591 | |
| 1592 #define FIXED_REGISTERS \ | |
| 1593 { \ | |
| 1594 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1595 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \ | |
| 1596 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1597 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1598 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \ | |
| 1599 /* COP0 registers */ \ | |
| 1600 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1601 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1602 /* COP2 registers */ \ | |
| 1603 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1604 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1605 /* COP3 registers */ \ | |
| 1606 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1607 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1608 /* 6 DSP accumulator registers & 6 control registers */ \ | |
| 1609 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \ | |
| 1610 } | |
| 1611 | |
| 1612 | |
| 1613 /* Set up this array for o32 by default. | |
| 1614 | |
| 1615 Note that we don't mark $31 as a call-clobbered register. The idea is | |
| 1616 that it's really the call instructions themselves which clobber $31. | |
| 1617 We don't care what the called function does with it afterwards. | |
| 1618 | |
| 1619 This approach makes it easier to implement sibcalls. Unlike normal | |
| 1620 calls, sibcalls don't clobber $31, so the register reaches the | |
| 1621 called function in tact. EPILOGUE_USES says that $31 is useful | |
| 1622 to the called function. */ | |
| 1623 | |
| 1624 #define CALL_USED_REGISTERS \ | |
| 1625 { \ | |
| 1626 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1627 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
| 1628 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1629 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1630 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1631 /* COP0 registers */ \ | |
| 1632 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1633 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1634 /* COP2 registers */ \ | |
| 1635 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1636 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1637 /* COP3 registers */ \ | |
| 1638 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1639 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1640 /* 6 DSP accumulator registers & 6 control registers */ \ | |
| 1641 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ | |
| 1642 } | |
| 1643 | |
| 1644 | |
| 1645 /* Define this since $28, though fixed, is call-saved in many ABIs. */ | |
| 1646 | |
| 1647 #define CALL_REALLY_USED_REGISTERS \ | |
| 1648 { /* General registers. */ \ | |
| 1649 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1650 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \ | |
| 1651 /* Floating-point registers. */ \ | |
| 1652 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
| 1653 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1654 /* Others. */ \ | |
| 1655 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \ | |
| 1656 /* COP0 registers */ \ | |
| 1657 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1658 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1659 /* COP2 registers */ \ | |
| 1660 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1661 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1662 /* COP3 registers */ \ | |
| 1663 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1664 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1665 /* 6 DSP accumulator registers & 6 control registers */ \ | |
| 1666 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \ | |
| 1667 } | |
| 1668 | |
| 1669 /* Internal macros to classify a register number as to whether it's a | |
| 1670 general purpose register, a floating point register, a | |
| 1671 multiply/divide register, or a status register. */ | |
| 1672 | |
| 1673 #define GP_REG_FIRST 0 | |
| 1674 #define GP_REG_LAST 31 | |
| 1675 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) | |
| 1676 #define GP_DBX_FIRST 0 | |
|
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1677 #define K0_REG_NUM (GP_REG_FIRST + 26) |
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1678 #define K1_REG_NUM (GP_REG_FIRST + 27) |
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1679 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM)) |
| 0 | 1680 |
| 1681 #define FP_REG_FIRST 32 | |
| 1682 #define FP_REG_LAST 63 | |
| 1683 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) | |
| 1684 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32) | |
| 1685 | |
| 1686 #define MD_REG_FIRST 64 | |
| 1687 #define MD_REG_LAST 65 | |
| 1688 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1) | |
| 1689 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM) | |
| 1690 | |
| 1691 /* The DWARF 2 CFA column which tracks the return address from a | |
| 1692 signal handler context. This means that to maintain backwards | |
| 1693 compatibility, no hard register can be assigned this column if it | |
| 1694 would need to be handled by the DWARF unwinder. */ | |
| 1695 #define DWARF_ALT_FRAME_RETURN_COLUMN 66 | |
| 1696 | |
| 1697 #define ST_REG_FIRST 67 | |
| 1698 #define ST_REG_LAST 74 | |
| 1699 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1) | |
| 1700 | |
| 1701 | |
| 1702 /* FIXME: renumber. */ | |
| 1703 #define COP0_REG_FIRST 80 | |
| 1704 #define COP0_REG_LAST 111 | |
| 1705 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1) | |
| 1706 | |
|
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1707 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12) |
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1708 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13) |
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1709 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14) |
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1710 |
| 0 | 1711 #define COP2_REG_FIRST 112 |
| 1712 #define COP2_REG_LAST 143 | |
| 1713 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1) | |
| 1714 | |
| 1715 #define COP3_REG_FIRST 144 | |
| 1716 #define COP3_REG_LAST 175 | |
| 1717 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1) | |
| 1718 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */ | |
| 1719 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1) | |
| 1720 | |
| 1721 #define DSP_ACC_REG_FIRST 176 | |
| 1722 #define DSP_ACC_REG_LAST 181 | |
| 1723 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1) | |
| 1724 | |
| 1725 #define AT_REGNUM (GP_REG_FIRST + 1) | |
| 1726 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1) | |
| 1727 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST) | |
| 1728 | |
|
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1729 /* A few bitfield locations for the coprocessor registers. */ |
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1730 /* Request Interrupt Priority Level is from bit 10 to bit 15 of |
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1731 the cause register for the EIC interrupt mode. */ |
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1732 #define CAUSE_IPL 10 |
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1733 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */ |
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1734 #define SR_IPL 10 |
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1735 /* Exception Level is at bit 1 of the status register. */ |
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1736 #define SR_EXL 1 |
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1737 /* Interrupt Enable is at bit 0 of the status register. */ |
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1738 #define SR_IE 0 |
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1739 |
| 0 | 1740 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC. |
| 1741 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG | |
| 1742 should be used instead. */ | |
| 1743 #define FPSW_REGNUM ST_REG_FIRST | |
| 1744 | |
| 1745 #define GP_REG_P(REGNO) \ | |
| 1746 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) | |
| 1747 #define M16_REG_P(REGNO) \ | |
| 1748 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17) | |
| 1749 #define FP_REG_P(REGNO) \ | |
| 1750 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) | |
| 1751 #define MD_REG_P(REGNO) \ | |
| 1752 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM) | |
| 1753 #define ST_REG_P(REGNO) \ | |
| 1754 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM) | |
| 1755 #define COP0_REG_P(REGNO) \ | |
| 1756 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM) | |
| 1757 #define COP2_REG_P(REGNO) \ | |
| 1758 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM) | |
| 1759 #define COP3_REG_P(REGNO) \ | |
| 1760 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM) | |
| 1761 #define ALL_COP_REG_P(REGNO) \ | |
| 1762 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM) | |
| 1763 /* Test if REGNO is one of the 6 new DSP accumulators. */ | |
| 1764 #define DSP_ACC_REG_P(REGNO) \ | |
| 1765 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM) | |
| 1766 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */ | |
| 1767 #define ACC_REG_P(REGNO) \ | |
| 1768 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO)) | |
| 1769 | |
| 1770 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) | |
| 1771 | |
| 1772 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used | |
| 1773 to initialize the mips16 gp pseudo register. */ | |
| 1774 #define CONST_GP_P(X) \ | |
| 1775 (GET_CODE (X) == CONST \ | |
| 1776 && GET_CODE (XEXP (X, 0)) == UNSPEC \ | |
| 1777 && XINT (XEXP (X, 0), 1) == UNSPEC_GP) | |
| 1778 | |
| 1779 /* Return coprocessor number from register number. */ | |
| 1780 | |
| 1781 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \ | |
| 1782 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \ | |
| 1783 : COP3_REG_P (REGNO) ? '3' : '?') | |
| 1784 | |
| 1785 | |
| 1786 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE) | |
| 1787 | |
| 1788 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
| 1789 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ] | |
| 1790 | |
| 1791 #define MODES_TIEABLE_P mips_modes_tieable_p | |
| 1792 | |
| 1793 /* Register to use for pushing function arguments. */ | |
| 1794 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29) | |
| 1795 | |
| 1796 /* These two registers don't really exist: they get eliminated to either | |
| 1797 the stack or hard frame pointer. */ | |
| 1798 #define ARG_POINTER_REGNUM 77 | |
| 1799 #define FRAME_POINTER_REGNUM 78 | |
| 1800 | |
| 1801 /* $30 is not available on the mips16, so we use $17 as the frame | |
| 1802 pointer. */ | |
| 1803 #define HARD_FRAME_POINTER_REGNUM \ | |
| 1804 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30) | |
| 1805 | |
| 1806 /* Register in which static-chain is passed to a function. */ | |
| 1807 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15) | |
| 1808 | |
| 1809 /* Registers used as temporaries in prologue/epilogue code: | |
| 1810 | |
| 1811 - If a MIPS16 PIC function needs access to _gp, it first loads | |
| 1812 the value into MIPS16_PIC_TEMP and then copies it to $gp. | |
| 1813 | |
| 1814 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary | |
| 1815 register. The register must not conflict with MIPS16_PIC_TEMP. | |
| 1816 | |
| 1817 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary | |
| 1818 register. | |
| 1819 | |
| 1820 If we're generating MIPS16 code, these registers must come from the | |
| 1821 core set of 8. The prologue registers mustn't conflict with any | |
| 1822 incoming arguments, the static chain pointer, or the frame pointer. | |
| 1823 The epilogue temporary mustn't conflict with the return registers, | |
| 1824 the PIC call register ($25), the frame pointer, the EH stack adjustment, | |
|
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1825 or the EH data registers. |
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1826 |
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1827 If we're generating interrupt handlers, we use K0 as a temporary register |
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1828 in prologue/epilogue code. */ |
| 0 | 1829 |
| 1830 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2) | |
|
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1831 #define MIPS_PROLOGUE_TEMP_REGNUM \ |
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1832 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3) |
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1833 #define MIPS_EPILOGUE_TEMP_REGNUM \ |
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1834 (cfun->machine->interrupt_handler_p \ |
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1835 ? K0_REG_NUM \ |
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1836 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8)) |
| 0 | 1837 |
| 1838 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM) | |
| 1839 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM) | |
| 1840 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM) | |
| 1841 | |
| 1842 /* Define this macro if it is as good or better to call a constant | |
| 1843 function address than to call an address kept in a register. */ | |
| 1844 #define NO_FUNCTION_CSE 1 | |
| 1845 | |
| 1846 /* The ABI-defined global pointer. Sometimes we use a different | |
| 1847 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */ | |
| 1848 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28) | |
| 1849 | |
| 1850 /* We normally use $28 as the global pointer. However, when generating | |
| 1851 n32/64 PIC, it is better for leaf functions to use a call-clobbered | |
| 1852 register instead. They can then avoid saving and restoring $28 | |
| 1853 and perhaps avoid using a frame at all. | |
| 1854 | |
| 1855 When a leaf function uses something other than $28, mips_expand_prologue | |
| 1856 will modify pic_offset_table_rtx in place. Take the register number | |
| 1857 from there after reload. */ | |
| 1858 #define PIC_OFFSET_TABLE_REGNUM \ | |
| 1859 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM) | |
| 1860 | |
| 1861 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25) | |
| 1862 | |
| 1863 /* Define the classes of registers for register constraints in the | |
| 1864 machine description. Also define ranges of constants. | |
| 1865 | |
| 1866 One of the classes must always be named ALL_REGS and include all hard regs. | |
| 1867 If there is more than one class, another class must be named NO_REGS | |
| 1868 and contain no registers. | |
| 1869 | |
| 1870 The name GENERAL_REGS must be the name of a class (or an alias for | |
| 1871 another name such as ALL_REGS). This is the class of registers | |
| 1872 that is allowed by "g" or "r" in a register constraint. | |
| 1873 Also, registers outside this class are allocated only when | |
| 1874 instructions express preferences for them. | |
| 1875 | |
| 1876 The classes must be numbered in nondecreasing order; that is, | |
| 1877 a larger-numbered class must never be contained completely | |
| 1878 in a smaller-numbered class. | |
| 1879 | |
| 1880 For any two classes, it is very desirable that there be another | |
| 1881 class that represents their union. */ | |
| 1882 | |
| 1883 enum reg_class | |
| 1884 { | |
| 1885 NO_REGS, /* no registers in set */ | |
| 1886 M16_REGS, /* mips16 directly accessible registers */ | |
| 1887 T_REG, /* mips16 T register ($24) */ | |
| 1888 M16_T_REGS, /* mips16 registers plus T register */ | |
| 1889 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */ | |
| 1890 V1_REG, /* Register $v1 ($3) used for TLS access. */ | |
| 1891 LEA_REGS, /* Every GPR except $25 */ | |
| 1892 GR_REGS, /* integer registers */ | |
| 1893 FP_REGS, /* floating point registers */ | |
| 1894 MD0_REG, /* first multiply/divide register */ | |
| 1895 MD1_REG, /* second multiply/divide register */ | |
| 1896 MD_REGS, /* multiply/divide registers (hi/lo) */ | |
| 1897 COP0_REGS, /* generic coprocessor classes */ | |
| 1898 COP2_REGS, | |
| 1899 COP3_REGS, | |
| 1900 ST_REGS, /* status registers (fp status) */ | |
| 1901 DSP_ACC_REGS, /* DSP accumulator registers */ | |
| 1902 ACC_REGS, /* Hi/Lo and DSP accumulator registers */ | |
| 1903 FRAME_REGS, /* $arg and $frame */ | |
| 1904 GR_AND_MD0_REGS, /* union classes */ | |
| 1905 GR_AND_MD1_REGS, | |
| 1906 GR_AND_MD_REGS, | |
| 1907 GR_AND_ACC_REGS, | |
| 1908 ALL_REGS, /* all registers */ | |
| 1909 LIM_REG_CLASSES /* max value + 1 */ | |
| 1910 }; | |
| 1911 | |
| 1912 #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
| 1913 | |
| 1914 #define GENERAL_REGS GR_REGS | |
| 1915 | |
| 1916 /* An initializer containing the names of the register classes as C | |
| 1917 string constants. These names are used in writing some of the | |
| 1918 debugging dumps. */ | |
| 1919 | |
| 1920 #define REG_CLASS_NAMES \ | |
| 1921 { \ | |
| 1922 "NO_REGS", \ | |
| 1923 "M16_REGS", \ | |
| 1924 "T_REG", \ | |
| 1925 "M16_T_REGS", \ | |
| 1926 "PIC_FN_ADDR_REG", \ | |
| 1927 "V1_REG", \ | |
| 1928 "LEA_REGS", \ | |
| 1929 "GR_REGS", \ | |
| 1930 "FP_REGS", \ | |
| 1931 "MD0_REG", \ | |
| 1932 "MD1_REG", \ | |
| 1933 "MD_REGS", \ | |
| 1934 /* coprocessor registers */ \ | |
| 1935 "COP0_REGS", \ | |
| 1936 "COP2_REGS", \ | |
| 1937 "COP3_REGS", \ | |
| 1938 "ST_REGS", \ | |
| 1939 "DSP_ACC_REGS", \ | |
| 1940 "ACC_REGS", \ | |
| 1941 "FRAME_REGS", \ | |
| 1942 "GR_AND_MD0_REGS", \ | |
| 1943 "GR_AND_MD1_REGS", \ | |
| 1944 "GR_AND_MD_REGS", \ | |
| 1945 "GR_AND_ACC_REGS", \ | |
| 1946 "ALL_REGS" \ | |
| 1947 } | |
| 1948 | |
| 1949 /* An initializer containing the contents of the register classes, | |
| 1950 as integers which are bit masks. The Nth integer specifies the | |
| 1951 contents of class N. The way the integer MASK is interpreted is | |
| 1952 that register R is in the class if `MASK & (1 << R)' is 1. | |
| 1953 | |
| 1954 When the machine has more than 32 registers, an integer does not | |
| 1955 suffice. Then the integers are replaced by sub-initializers, | |
| 1956 braced groupings containing several integers. Each | |
| 1957 sub-initializer must be suitable as an initializer for the type | |
| 1958 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ | |
| 1959 | |
| 1960 #define REG_CLASS_CONTENTS \ | |
| 1961 { \ | |
| 1962 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
| 1963 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \ | |
| 1964 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \ | |
| 1965 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \ | |
| 1966 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \ | |
| 1967 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \ | |
| 1968 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \ | |
| 1969 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \ | |
| 1970 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \ | |
| 1971 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \ | |
| 1972 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \ | |
| 1973 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \ | |
| 1974 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \ | |
| 1975 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \ | |
| 1976 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \ | |
| 1977 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \ | |
| 1978 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \ | |
| 1979 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \ | |
| 1980 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \ | |
| 1981 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \ | |
| 1982 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \ | |
| 1983 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \ | |
| 1984 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \ | |
| 1985 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \ | |
| 1986 } | |
| 1987 | |
| 1988 | |
| 1989 /* A C expression whose value is a register class containing hard | |
| 1990 register REGNO. In general there is more that one such class; | |
| 1991 choose a class which is "minimal", meaning that no smaller class | |
| 1992 also contains the register. */ | |
| 1993 | |
| 1994 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ] | |
| 1995 | |
| 1996 /* A macro whose definition is the name of the class to which a | |
| 1997 valid base register must belong. A base register is one used in | |
| 1998 an address which is the register value plus a displacement. */ | |
| 1999 | |
| 2000 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS) | |
| 2001 | |
| 2002 /* A macro whose definition is the name of the class to which a | |
| 2003 valid index register must belong. An index register is one used | |
| 2004 in an address where its value is either multiplied by a scale | |
| 2005 factor or added to another register (as well as added to a | |
| 2006 displacement). */ | |
| 2007 | |
| 2008 #define INDEX_REG_CLASS NO_REGS | |
| 2009 | |
| 2010 /* We generally want to put call-clobbered registers ahead of | |
| 2011 call-saved ones. (IRA expects this.) */ | |
| 2012 | |
| 2013 #define REG_ALLOC_ORDER \ | |
| 2014 { /* Accumulator registers. When GPRs and accumulators have equal \ | |
| 2015 cost, we generally prefer to use accumulators. For example, \ | |
| 2016 a division of multiplication result is better allocated to LO, \ | |
| 2017 so that we put the MFLO at the point of use instead of at the \ | |
| 2018 point of definition. It's also needed if we're to take advantage \ | |
| 2019 of the extra accumulators available with -mdspr2. In some cases, \ | |
| 2020 it can also help to reduce register pressure. */ \ | |
| 2021 64, 65,176,177,178,179,180,181, \ | |
| 2022 /* Call-clobbered GPRs. */ \ | |
| 2023 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ | |
| 2024 24, 25, 31, \ | |
| 2025 /* The global pointer. This is call-clobbered for o32 and o64 \ | |
| 2026 abicalls, call-saved for n32 and n64 abicalls, and a program \ | |
| 2027 invariant otherwise. Putting it between the call-clobbered \ | |
| 2028 and call-saved registers should cope with all eventualities. */ \ | |
| 2029 28, \ | |
| 2030 /* Call-saved GPRs. */ \ | |
| 2031 16, 17, 18, 19, 20, 21, 22, 23, 30, \ | |
| 2032 /* GPRs that can never be exposed to the register allocator. */ \ | |
| 2033 0, 26, 27, 29, \ | |
| 2034 /* Call-clobbered FPRs. */ \ | |
| 2035 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
| 2036 48, 49, 50, 51, \ | |
| 2037 /* FPRs that are usually call-saved. The odd ones are actually \ | |
| 2038 call-clobbered for n32, but listing them ahead of the even \ | |
| 2039 registers might encourage the register allocator to fragment \ | |
| 2040 the available FPR pairs. We need paired FPRs to store long \ | |
| 2041 doubles, so it isn't clear that using a different order \ | |
| 2042 for n32 would be a win. */ \ | |
| 2043 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ | |
| 2044 /* None of the remaining classes have defined call-saved \ | |
| 2045 registers. */ \ | |
| 2046 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ | |
| 2047 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \ | |
| 2048 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \ | |
| 2049 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \ | |
| 2050 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \ | |
| 2051 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \ | |
| 2052 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \ | |
| 2053 182,183,184,185,186,187 \ | |
| 2054 } | |
| 2055 | |
|
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2056 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order |
| 0 | 2057 to be rearranged based on a particular function. On the mips16, we |
| 2058 want to allocate $24 (T_REG) before other registers for | |
| 2059 instructions for which it is possible. */ | |
| 2060 | |
|
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2061 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc () |
| 0 | 2062 |
| 2063 /* True if VALUE is an unsigned 6-bit number. */ | |
| 2064 | |
| 2065 #define UIMM6_OPERAND(VALUE) \ | |
| 2066 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0) | |
| 2067 | |
| 2068 /* True if VALUE is a signed 10-bit number. */ | |
| 2069 | |
| 2070 #define IMM10_OPERAND(VALUE) \ | |
| 2071 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400) | |
| 2072 | |
| 2073 /* True if VALUE is a signed 16-bit number. */ | |
| 2074 | |
| 2075 #define SMALL_OPERAND(VALUE) \ | |
| 2076 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000) | |
| 2077 | |
| 2078 /* True if VALUE is an unsigned 16-bit number. */ | |
| 2079 | |
| 2080 #define SMALL_OPERAND_UNSIGNED(VALUE) \ | |
| 2081 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0) | |
| 2082 | |
| 2083 /* True if VALUE can be loaded into a register using LUI. */ | |
| 2084 | |
| 2085 #define LUI_OPERAND(VALUE) \ | |
| 2086 (((VALUE) | 0x7fff0000) == 0x7fff0000 \ | |
| 2087 || ((VALUE) | 0x7fff0000) + 0x10000 == 0) | |
| 2088 | |
| 2089 /* Return a value X with the low 16 bits clear, and such that | |
| 2090 VALUE - X is a signed 16-bit value. */ | |
| 2091 | |
| 2092 #define CONST_HIGH_PART(VALUE) \ | |
| 2093 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff) | |
| 2094 | |
| 2095 #define CONST_LOW_PART(VALUE) \ | |
| 2096 ((VALUE) - CONST_HIGH_PART (VALUE)) | |
| 2097 | |
| 2098 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X)) | |
| 2099 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X)) | |
| 2100 #define LUI_INT(X) LUI_OPERAND (INTVAL (X)) | |
| 2101 | |
| 2102 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
| 2103 mips_preferred_reload_class (X, CLASS) | |
| 2104 | |
| 2105 /* The HI and LO registers can only be reloaded via the general | |
| 2106 registers. Condition code registers can only be loaded to the | |
| 2107 general registers, and from the floating point registers. */ | |
| 2108 | |
| 2109 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
| 2110 mips_secondary_reload_class (CLASS, MODE, X, true) | |
| 2111 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
| 2112 mips_secondary_reload_class (CLASS, MODE, X, false) | |
| 2113 | |
| 2114 /* Return the maximum number of consecutive registers | |
| 2115 needed to represent mode MODE in a register of class CLASS. */ | |
| 2116 | |
| 2117 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE) | |
| 2118 | |
| 2119 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
| 2120 mips_cannot_change_mode_class (FROM, TO, CLASS) | |
| 2121 | |
| 2122 /* Stack layout; function entry, exit and calling. */ | |
| 2123 | |
| 2124 #define STACK_GROWS_DOWNWARD | |
| 2125 | |
|
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2126 #define FRAME_GROWS_DOWNWARD flag_stack_protect |
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2127 |
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2128 /* Size of the area allocated in the frame to save the GP. */ |
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2129 |
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2130 #define MIPS_GP_SAVE_AREA_SIZE \ |
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2131 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0) |
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2132 |
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2133 /* The offset of the first local variable from the frame pointer. See |
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2134 mips_compute_frame_info for details about the frame layout. */ |
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2135 |
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2136 #define STARTING_FRAME_OFFSET \ |
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2137 (FRAME_GROWS_DOWNWARD \ |
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2138 ? 0 \ |
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2139 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE) |
| 0 | 2140 |
| 2141 #define RETURN_ADDR_RTX mips_return_addr | |
| 2142 | |
| 2143 /* Mask off the MIPS16 ISA bit in unwind addresses. | |
| 2144 | |
| 2145 The reason for this is a little subtle. When unwinding a call, | |
| 2146 we are given the call's return address, which on most targets | |
| 2147 is the address of the following instruction. However, what we | |
| 2148 actually want to find is the EH region for the call itself. | |
| 2149 The target-independent unwind code therefore searches for "RA - 1". | |
| 2150 | |
| 2151 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address. | |
| 2152 RA - 1 is therefore the real (even-valued) start of the return | |
| 2153 instruction. EH region labels are usually odd-valued MIPS16 symbols | |
| 2154 too, so a search for an even address within a MIPS16 region would | |
| 2155 usually work. | |
| 2156 | |
| 2157 However, there is an exception. If the end of an EH region is also | |
| 2158 the end of a function, the end label is allowed to be even. This is | |
| 2159 necessary because a following non-MIPS16 function may also need EH | |
| 2160 information for its first instruction. | |
| 2161 | |
| 2162 Thus a MIPS16 region may be terminated by an ISA-encoded or a | |
| 2163 non-ISA-encoded address. This probably isn't ideal, but it is | |
| 2164 the traditional (legacy) behavior. It is therefore only safe | |
| 2165 to search MIPS EH regions for an _odd-valued_ address. | |
| 2166 | |
| 2167 Masking off the ISA bit means that the target-independent code | |
| 2168 will search for "(RA & -2) - 1", which is guaranteed to be odd. */ | |
| 2169 #define MASK_RETURN_ADDR GEN_INT (-2) | |
| 2170 | |
| 2171 | |
| 2172 /* Similarly, don't use the least-significant bit to tell pointers to | |
| 2173 code from vtable index. */ | |
| 2174 | |
| 2175 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
| 2176 | |
| 2177 /* The eliminations to $17 are only used for mips16 code. See the | |
| 2178 definition of HARD_FRAME_POINTER_REGNUM. */ | |
| 2179 | |
| 2180 #define ELIMINABLE_REGS \ | |
| 2181 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 2182 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \ | |
| 2183 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \ | |
| 2184 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 2185 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \ | |
| 2186 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}} | |
| 2187 | |
| 2188 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
| 2189 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO)) | |
| 2190 | |
| 2191 /* Allocate stack space for arguments at the beginning of each function. */ | |
| 2192 #define ACCUMULATE_OUTGOING_ARGS 1 | |
| 2193 | |
| 2194 /* The argument pointer always points to the first argument. */ | |
| 2195 #define FIRST_PARM_OFFSET(FNDECL) 0 | |
| 2196 | |
| 2197 /* o32 and o64 reserve stack space for all argument registers. */ | |
| 2198 #define REG_PARM_STACK_SPACE(FNDECL) \ | |
| 2199 (TARGET_OLDABI \ | |
| 2200 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \ | |
| 2201 : 0) | |
| 2202 | |
| 2203 /* Define this if it is the responsibility of the caller to | |
| 2204 allocate the area reserved for arguments passed in registers. | |
| 2205 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect | |
| 2206 of this macro is to determine whether the space is included in | |
| 2207 `crtl->outgoing_args_size'. */ | |
| 2208 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 | |
| 2209 | |
| 2210 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64) | |
| 2211 | |
| 2212 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 | |
| 2213 | |
| 2214 /* Symbolic macros for the registers used to return integer and floating | |
| 2215 point values. */ | |
| 2216 | |
| 2217 #define GP_RETURN (GP_REG_FIRST + 2) | |
| 2218 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0)) | |
| 2219 | |
| 2220 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8) | |
| 2221 | |
| 2222 /* Symbolic macros for the first/last argument registers. */ | |
| 2223 | |
| 2224 #define GP_ARG_FIRST (GP_REG_FIRST + 4) | |
| 2225 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) | |
| 2226 #define FP_ARG_FIRST (FP_REG_FIRST + 12) | |
| 2227 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) | |
| 2228 | |
| 2229 #define LIBCALL_VALUE(MODE) \ | |
|
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2230 mips_function_value (NULL_TREE, NULL_TREE, MODE) |
| 0 | 2231 |
| 2232 #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
|
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2233 mips_function_value (VALTYPE, FUNC, VOIDmode) |
| 0 | 2234 |
| 2235 /* 1 if N is a possible register number for a function value. | |
| 2236 On the MIPS, R2 R3 and F0 F2 are the only register thus used. | |
| 2237 Currently, R2 and F0 are only implemented here (C has no complex type) */ | |
| 2238 | |
| 2239 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \ | |
| 2240 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \ | |
| 2241 && (N) == FP_RETURN + 2)) | |
| 2242 | |
| 2243 /* 1 if N is a possible register number for function argument passing. | |
| 2244 We have no FP argument registers when soft-float. When FP registers | |
| 2245 are 32 bits, we can't directly reference the odd numbered ones. */ | |
| 2246 | |
| 2247 #define FUNCTION_ARG_REGNO_P(N) \ | |
| 2248 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \ | |
| 2249 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \ | |
| 2250 && !fixed_regs[N]) | |
| 2251 | |
| 2252 /* This structure has to cope with two different argument allocation | |
| 2253 schemes. Most MIPS ABIs view the arguments as a structure, of which | |
| 2254 the first N words go in registers and the rest go on the stack. If I | |
| 2255 < N, the Ith word might go in Ith integer argument register or in a | |
| 2256 floating-point register. For these ABIs, we only need to remember | |
| 2257 the offset of the current argument into the structure. | |
| 2258 | |
| 2259 The EABI instead allocates the integer and floating-point arguments | |
| 2260 separately. The first N words of FP arguments go in FP registers, | |
| 2261 the rest go on the stack. Likewise, the first N words of the other | |
| 2262 arguments go in integer registers, and the rest go on the stack. We | |
| 2263 need to maintain three counts: the number of integer registers used, | |
| 2264 the number of floating-point registers used, and the number of words | |
| 2265 passed on the stack. | |
| 2266 | |
| 2267 We could keep separate information for the two ABIs (a word count for | |
| 2268 the standard ABIs, and three separate counts for the EABI). But it | |
| 2269 seems simpler to view the standard ABIs as forms of EABI that do not | |
| 2270 allocate floating-point registers. | |
| 2271 | |
| 2272 So for the standard ABIs, the first N words are allocated to integer | |
| 2273 registers, and mips_function_arg decides on an argument-by-argument | |
| 2274 basis whether that argument should really go in an integer register, | |
| 2275 or in a floating-point one. */ | |
| 2276 | |
| 2277 typedef struct mips_args { | |
| 2278 /* Always true for varargs functions. Otherwise true if at least | |
| 2279 one argument has been passed in an integer register. */ | |
| 2280 int gp_reg_found; | |
| 2281 | |
| 2282 /* The number of arguments seen so far. */ | |
| 2283 unsigned int arg_number; | |
| 2284 | |
| 2285 /* The number of integer registers used so far. For all ABIs except | |
| 2286 EABI, this is the number of words that have been added to the | |
| 2287 argument structure, limited to MAX_ARGS_IN_REGISTERS. */ | |
| 2288 unsigned int num_gprs; | |
| 2289 | |
| 2290 /* For EABI, the number of floating-point registers used so far. */ | |
| 2291 unsigned int num_fprs; | |
| 2292 | |
| 2293 /* The number of words passed on the stack. */ | |
| 2294 unsigned int stack_words; | |
| 2295 | |
| 2296 /* On the mips16, we need to keep track of which floating point | |
| 2297 arguments were passed in general registers, but would have been | |
| 2298 passed in the FP regs if this were a 32-bit function, so that we | |
| 2299 can move them to the FP regs if we wind up calling a 32-bit | |
| 2300 function. We record this information in fp_code, encoded in base | |
| 2301 four. A zero digit means no floating point argument, a one digit | |
| 2302 means an SFmode argument, and a two digit means a DFmode argument, | |
| 2303 and a three digit is not used. The low order digit is the first | |
| 2304 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by | |
| 2305 an SFmode argument. ??? A more sophisticated approach will be | |
| 2306 needed if MIPS_ABI != ABI_32. */ | |
| 2307 int fp_code; | |
| 2308 | |
| 2309 /* True if the function has a prototype. */ | |
| 2310 int prototype; | |
| 2311 } CUMULATIVE_ARGS; | |
| 2312 | |
| 2313 /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
| 2314 for a call to a function whose data type is FNTYPE. | |
| 2315 For a library call, FNTYPE is 0. */ | |
| 2316 | |
| 2317 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ | |
| 2318 mips_init_cumulative_args (&CUM, FNTYPE) | |
| 2319 | |
| 2320 /* Update the data in CUM to advance over an argument | |
| 2321 of mode MODE and data type TYPE. | |
| 2322 (TYPE is null for libcalls where that information may not be available.) */ | |
| 2323 | |
| 2324 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
| 2325 mips_function_arg_advance (&CUM, MODE, TYPE, NAMED) | |
| 2326 | |
| 2327 /* Determine where to put an argument to a function. | |
| 2328 Value is zero to push the argument on the stack, | |
| 2329 or a hard register in which to store the argument. | |
| 2330 | |
| 2331 MODE is the argument's machine mode. | |
| 2332 TYPE is the data type of the argument (as a tree). | |
| 2333 This is null for libcalls where that information may | |
| 2334 not be available. | |
| 2335 CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
| 2336 the preceding args and about the function being called. | |
| 2337 NAMED is nonzero if this argument is a named parameter | |
| 2338 (otherwise it is an extra parameter matching an ellipsis). */ | |
| 2339 | |
| 2340 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
| 2341 mips_function_arg (&CUM, MODE, TYPE, NAMED) | |
| 2342 | |
| 2343 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary | |
| 2344 | |
| 2345 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ | |
| 2346 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward) | |
| 2347 | |
| 2348 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ | |
| 2349 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward) | |
| 2350 | |
| 2351 /* True if using EABI and varargs can be passed in floating-point | |
| 2352 registers. Under these conditions, we need a more complex form | |
| 2353 of va_list, which tracks GPR, FPR and stack arguments separately. */ | |
| 2354 #define EABI_FLOAT_VARARGS_P \ | |
| 2355 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE) | |
| 2356 | |
| 2357 | |
|
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2358 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO) |
| 0 | 2359 |
| 2360 /* Treat LOC as a byte offset from the stack pointer and round it up | |
| 2361 to the next fully-aligned offset. */ | |
| 2362 #define MIPS_STACK_ALIGN(LOC) \ | |
| 2363 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8) | |
| 2364 | |
| 2365 | |
| 2366 /* Output assembler code to FILE to increment profiler label # LABELNO | |
| 2367 for profiling a function entry. */ | |
| 2368 | |
|
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2369 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE)) |
| 0 | 2370 |
| 2371 /* The profiler preserves all interesting registers, including $31. */ | |
| 2372 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false | |
| 2373 | |
| 2374 /* No mips port has ever used the profiler counter word, so don't emit it | |
| 2375 or the label for it. */ | |
| 2376 | |
| 2377 #define NO_PROFILE_COUNTERS 1 | |
| 2378 | |
| 2379 /* Define this macro if the code for function profiling should come | |
| 2380 before the function prologue. Normally, the profiling code comes | |
| 2381 after. */ | |
| 2382 | |
| 2383 /* #define PROFILE_BEFORE_PROLOGUE */ | |
| 2384 | |
| 2385 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
| 2386 the stack pointer does not matter. The value is tested only in | |
| 2387 functions that have frame pointers. | |
| 2388 No definition is equivalent to always zero. */ | |
| 2389 | |
| 2390 #define EXIT_IGNORE_STACK 1 | |
| 2391 | |
| 2392 | |
|
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2393 /* Trampolines are a block of code followed by two pointers. */ |
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2394 |
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2395 #define TRAMPOLINE_SIZE \ |
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2396 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2) |
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2397 |
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2398 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two |
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2399 pointers from a single LUI base. */ |
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2400 |
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2401 #define TRAMPOLINE_ALIGNMENT 64 |
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2402 |
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2403 /* mips_trampoline_init calls this library function to flush |
| 0 | 2404 program and data caches. */ |
| 2405 | |
| 2406 #ifndef CACHE_FLUSH_FUNC | |
| 2407 #define CACHE_FLUSH_FUNC "_flush_cache" | |
| 2408 #endif | |
| 2409 | |
| 2410 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \ | |
| 2411 /* Flush both caches. We need to flush the data cache in case \ | |
| 2412 the system has a write-back cache. */ \ | |
| 2413 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \ | |
|
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2414 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \ |
| 0 | 2415 GEN_INT (3), TYPE_MODE (integer_type_node)) |
| 2416 | |
| 2417 | |
| 2418 /* Addressing modes, and classification of registers for them. */ | |
| 2419 | |
| 2420 #define REGNO_OK_FOR_INDEX_P(REGNO) 0 | |
| 2421 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
| 2422 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1) | |
| 2423 | |
| 2424 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
| 2425 and check its validity for a certain class. | |
| 2426 We have two alternate definitions for each of them. | |
| 2427 The usual definition accepts all pseudo regs; the other rejects them all. | |
| 2428 The symbol REG_OK_STRICT causes the latter definition to be used. | |
| 2429 | |
| 2430 Most source files want to accept pseudo regs in the hope that | |
| 2431 they will get allocated to the class that the insn wants them to be in. | |
| 2432 Some source files that are used after register allocation | |
| 2433 need to be strict. */ | |
| 2434 | |
| 2435 #ifndef REG_OK_STRICT | |
| 2436 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
| 2437 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0) | |
| 2438 #else | |
| 2439 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
| 2440 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1) | |
| 2441 #endif | |
| 2442 | |
| 2443 #define REG_OK_FOR_INDEX_P(X) 0 | |
| 2444 | |
| 2445 | |
| 2446 /* Maximum number of registers that can appear in a valid memory address. */ | |
| 2447 | |
| 2448 #define MAX_REGS_PER_ADDRESS 1 | |
| 2449 | |
| 2450 /* Check for constness inline but use mips_legitimate_address_p | |
| 2451 to check whether a constant really is an address. */ | |
| 2452 | |
| 2453 #define CONSTANT_ADDRESS_P(X) \ | |
|
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2454 (CONSTANT_P (X) && memory_address_p (SImode, X)) |
| 0 | 2455 |
| 2456 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0) | |
| 2457 | |
| 2458 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means | |
| 2459 'the start of the function that this code is output in'. */ | |
| 2460 | |
| 2461 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ | |
| 2462 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ | |
| 2463 asm_fprintf ((FILE), "%U%s", \ | |
| 2464 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \ | |
| 2465 else \ | |
| 2466 asm_fprintf ((FILE), "%U%s", (NAME)) | |
| 2467 | |
| 2468 /* Flag to mark a function decl symbol that requires a long call. */ | |
| 2469 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0) | |
| 2470 #define SYMBOL_REF_LONG_CALL_P(X) \ | |
| 2471 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0) | |
| 2472 | |
| 2473 /* This flag marks functions that cannot be lazily bound. */ | |
| 2474 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1) | |
| 2475 #define SYMBOL_REF_BIND_NOW_P(RTX) \ | |
| 2476 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0) | |
| 2477 | |
| 2478 /* True if we're generating a form of MIPS16 code in which jump tables | |
| 2479 are stored in the text section and encoded as 16-bit PC-relative | |
| 2480 offsets. This is only possible when general text loads are allowed, | |
| 2481 since the table access itself will be an "lh" instruction. */ | |
| 2482 /* ??? 16-bit offsets can overflow in large functions. */ | |
| 2483 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS | |
| 2484 | |
| 2485 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES | |
| 2486 | |
| 2487 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode) | |
| 2488 | |
| 2489 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES | |
| 2490 | |
| 2491 /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
| 2492 #ifndef DEFAULT_SIGNED_CHAR | |
| 2493 #define DEFAULT_SIGNED_CHAR 1 | |
| 2494 #endif | |
| 2495 | |
| 2496 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets, | |
| 2497 we generally don't want to use them for copying arbitrary data. | |
| 2498 A single N-word move is usually the same cost as N single-word moves. */ | |
| 2499 #define MOVE_MAX UNITS_PER_WORD | |
| 2500 #define MAX_MOVE_MAX 8 | |
| 2501 | |
| 2502 /* Define this macro as a C expression which is nonzero if | |
| 2503 accessing less than a word of memory (i.e. a `char' or a | |
| 2504 `short') is no faster than accessing a word of memory, i.e., if | |
| 2505 such access require more than one instruction or if there is no | |
| 2506 difference in cost between byte and (aligned) word loads. | |
| 2507 | |
| 2508 On RISC machines, it tends to generate better code to define | |
| 2509 this as 1, since it avoids making a QI or HI mode register. | |
| 2510 | |
| 2511 But, generating word accesses for -mips16 is generally bad as shifts | |
| 2512 (often extended) would be needed for byte accesses. */ | |
| 2513 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16) | |
| 2514 | |
| 2515 /* Define this to be nonzero if shift instructions ignore all but the low-order | |
| 2516 few bits. */ | |
| 2517 #define SHIFT_COUNT_TRUNCATED 1 | |
| 2518 | |
| 2519 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
| 2520 is done just by pretending it is already truncated. */ | |
| 2521 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \ | |
| 2522 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1) | |
| 2523 | |
| 2524 | |
| 2525 /* Specify the machine mode that pointers have. | |
| 2526 After generation of rtl, the compiler makes no further distinction | |
| 2527 between pointers and any other objects of this machine mode. */ | |
| 2528 | |
| 2529 #ifndef Pmode | |
| 2530 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode) | |
| 2531 #endif | |
| 2532 | |
| 2533 /* Give call MEMs SImode since it is the "most permissive" mode | |
| 2534 for both 32-bit and 64-bit targets. */ | |
| 2535 | |
| 2536 #define FUNCTION_MODE SImode | |
| 2537 | |
| 2538 | |
| 2539 /* A C expression for the cost of moving data from a register in | |
| 2540 class FROM to one in class TO. The classes are expressed using | |
| 2541 the enumeration values such as `GENERAL_REGS'. A value of 2 is | |
| 2542 the default; other values are interpreted relative to that. | |
| 2543 | |
| 2544 It is not required that the cost always equal 2 when FROM is the | |
| 2545 same as TO; on some machines it is expensive to move between | |
| 2546 registers if they are not general registers. | |
| 2547 | |
| 2548 If reload sees an insn consisting of a single `set' between two | |
| 2549 hard registers, and if `REGISTER_MOVE_COST' applied to their | |
| 2550 classes returns a value of 2, reload does not check to ensure | |
| 2551 that the constraints of the insn are met. Setting a cost of | |
| 2552 other than 2 will allow reload to verify that the constraints are | |
| 2553 met. You should do this if the `movM' pattern's constraints do | |
| 2554 not allow such copying. */ | |
| 2555 | |
| 2556 #define REGISTER_MOVE_COST(MODE, FROM, TO) \ | |
| 2557 mips_register_move_cost (MODE, FROM, TO) | |
| 2558 | |
| 2559 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \ | |
| 2560 (mips_cost->memory_latency \ | |
| 2561 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P))) | |
| 2562 | |
| 2563 /* Define if copies to/from condition code registers should be avoided. | |
| 2564 | |
| 2565 This is needed for the MIPS because reload_outcc is not complete; | |
| 2566 it needs to handle cases where the source is a general or another | |
| 2567 condition code register. */ | |
| 2568 #define AVOID_CCMODE_COPIES | |
| 2569 | |
| 2570 /* A C expression for the cost of a branch instruction. A value of | |
| 2571 1 is the default; other values are interpreted relative to that. */ | |
| 2572 | |
| 2573 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost | |
| 2574 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 | |
| 2575 | |
| 2576 /* If defined, modifies the length assigned to instruction INSN as a | |
| 2577 function of the context in which it is used. LENGTH is an lvalue | |
| 2578 that contains the initially computed length of the insn and should | |
| 2579 be updated with the correct length of the insn. */ | |
| 2580 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ | |
| 2581 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH))) | |
| 2582 | |
| 2583 /* Return the asm template for a non-MIPS16 conditional branch instruction. | |
| 2584 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for | |
| 2585 its operands. */ | |
| 2586 #define MIPS_BRANCH(OPCODE, OPERANDS) \ | |
| 2587 "%*" OPCODE "%?\t" OPERANDS "%/" | |
| 2588 | |
|
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2589 /* Return an asm string that forces INSN to be treated as an absolute |
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2590 J or JAL instruction instead of an assembler macro. */ |
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2591 #define MIPS_ABSOLUTE_JUMP(INSN) \ |
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2592 (TARGET_ABICALLS_PIC2 \ |
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2593 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \ |
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2594 : INSN) |
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2595 |
| 0 | 2596 /* Return the asm template for a call. INSN is the instruction's mnemonic |
|
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2597 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand |
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2598 number of the target. SIZE_OPNO is the operand number of the argument size |
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2599 operand that can optionally hold the call attributes. If SIZE_OPNO is not |
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2600 -1 and the call is indirect, use the function symbol from the call |
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2601 attributes to attach a R_MIPS_JALR relocation to the call. |
| 0 | 2602 |
| 2603 When generating GOT code without explicit relocation operators, | |
| 2604 all calls should use assembly macros. Otherwise, all indirect | |
| 2605 calls should use "jr" or "jalr"; we will arrange to restore $gp | |
| 2606 afterwards if necessary. Finally, we can only generate direct | |
| 2607 calls for -mabicalls by temporarily switching to non-PIC mode. */ | |
|
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2608 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \ |
| 0 | 2609 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \ |
|
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2610 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \ |
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2611 : (REG_P (OPERANDS[TARGET_OPNO]) \ |
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2612 && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \ |
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2613 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \ |
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2614 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \ |
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2615 : REG_P (OPERANDS[TARGET_OPNO]) \ |
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2616 ? "%*" INSN "r\t%" #TARGET_OPNO "%/" \ |
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2617 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/")) |
| 0 | 2618 |
| 2619 /* Control the assembler format that we output. */ | |
| 2620 | |
| 2621 /* Output to assembler file text saying following lines | |
| 2622 may contain character constants, extra white space, comments, etc. */ | |
| 2623 | |
| 2624 #ifndef ASM_APP_ON | |
| 2625 #define ASM_APP_ON " #APP\n" | |
| 2626 #endif | |
| 2627 | |
| 2628 /* Output to assembler file text saying following lines | |
| 2629 no longer contain unusual constructs. */ | |
| 2630 | |
| 2631 #ifndef ASM_APP_OFF | |
| 2632 #define ASM_APP_OFF " #NO_APP\n" | |
| 2633 #endif | |
| 2634 | |
| 2635 #define REGISTER_NAMES \ | |
| 2636 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \ | |
| 2637 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ | |
| 2638 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ | |
| 2639 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \ | |
| 2640 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \ | |
| 2641 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ | |
| 2642 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \ | |
| 2643 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \ | |
| 2644 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \ | |
|
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2645 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \ |
| 0 | 2646 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \ |
| 2647 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \ | |
| 2648 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \ | |
| 2649 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \ | |
| 2650 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \ | |
| 2651 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \ | |
| 2652 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \ | |
| 2653 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \ | |
| 2654 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \ | |
| 2655 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \ | |
| 2656 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \ | |
| 2657 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \ | |
| 2658 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \ | |
| 2659 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" } | |
| 2660 | |
| 2661 /* List the "software" names for each register. Also list the numerical | |
| 2662 names for $fp and $sp. */ | |
| 2663 | |
| 2664 #define ADDITIONAL_REGISTER_NAMES \ | |
| 2665 { \ | |
| 2666 { "$29", 29 + GP_REG_FIRST }, \ | |
| 2667 { "$30", 30 + GP_REG_FIRST }, \ | |
| 2668 { "at", 1 + GP_REG_FIRST }, \ | |
| 2669 { "v0", 2 + GP_REG_FIRST }, \ | |
| 2670 { "v1", 3 + GP_REG_FIRST }, \ | |
| 2671 { "a0", 4 + GP_REG_FIRST }, \ | |
| 2672 { "a1", 5 + GP_REG_FIRST }, \ | |
| 2673 { "a2", 6 + GP_REG_FIRST }, \ | |
| 2674 { "a3", 7 + GP_REG_FIRST }, \ | |
| 2675 { "t0", 8 + GP_REG_FIRST }, \ | |
| 2676 { "t1", 9 + GP_REG_FIRST }, \ | |
| 2677 { "t2", 10 + GP_REG_FIRST }, \ | |
| 2678 { "t3", 11 + GP_REG_FIRST }, \ | |
| 2679 { "t4", 12 + GP_REG_FIRST }, \ | |
| 2680 { "t5", 13 + GP_REG_FIRST }, \ | |
| 2681 { "t6", 14 + GP_REG_FIRST }, \ | |
| 2682 { "t7", 15 + GP_REG_FIRST }, \ | |
| 2683 { "s0", 16 + GP_REG_FIRST }, \ | |
| 2684 { "s1", 17 + GP_REG_FIRST }, \ | |
| 2685 { "s2", 18 + GP_REG_FIRST }, \ | |
| 2686 { "s3", 19 + GP_REG_FIRST }, \ | |
| 2687 { "s4", 20 + GP_REG_FIRST }, \ | |
| 2688 { "s5", 21 + GP_REG_FIRST }, \ | |
| 2689 { "s6", 22 + GP_REG_FIRST }, \ | |
| 2690 { "s7", 23 + GP_REG_FIRST }, \ | |
| 2691 { "t8", 24 + GP_REG_FIRST }, \ | |
| 2692 { "t9", 25 + GP_REG_FIRST }, \ | |
| 2693 { "k0", 26 + GP_REG_FIRST }, \ | |
| 2694 { "k1", 27 + GP_REG_FIRST }, \ | |
| 2695 { "gp", 28 + GP_REG_FIRST }, \ | |
| 2696 { "sp", 29 + GP_REG_FIRST }, \ | |
| 2697 { "fp", 30 + GP_REG_FIRST }, \ | |
| 2698 { "ra", 31 + GP_REG_FIRST }, \ | |
| 2699 ALL_COP_ADDITIONAL_REGISTER_NAMES \ | |
| 2700 } | |
| 2701 | |
| 2702 /* This is meant to be redefined in the host dependent files. It is a | |
| 2703 set of alternative names and regnums for mips coprocessors. */ | |
| 2704 | |
| 2705 #define ALL_COP_ADDITIONAL_REGISTER_NAMES | |
| 2706 | |
| 2707 #define PRINT_OPERAND mips_print_operand | |
| 2708 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE] | |
| 2709 #define PRINT_OPERAND_ADDRESS mips_print_operand_address | |
| 2710 | |
| 2711 #define DBR_OUTPUT_SEQEND(STREAM) \ | |
| 2712 do \ | |
| 2713 { \ | |
|
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2714 /* Undo the effect of '%*'. */ \ |
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2715 mips_pop_asm_switch (&mips_nomacro); \ |
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2716 mips_pop_asm_switch (&mips_noreorder); \ |
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2717 /* Emit a blank line after the delay slot for emphasis. */ \ |
| 0 | 2718 fputs ("\n", STREAM); \ |
| 2719 } \ | |
| 2720 while (0) | |
| 2721 | |
| 2722 /* How to tell the debugger about changes of source files. */ | |
| 2723 #define ASM_OUTPUT_SOURCE_FILENAME mips_output_filename | |
| 2724 | |
| 2725 /* mips-tfile does not understand .stabd directives. */ | |
| 2726 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \ | |
| 2727 dbxout_begin_stabn_sline (LINE); \ | |
| 2728 dbxout_stab_value_internal_label ("LM", &COUNTER); \ | |
| 2729 } while (0) | |
| 2730 | |
| 2731 /* Use .loc directives for SDB line numbers. */ | |
| 2732 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \ | |
| 2733 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE) | |
| 2734 | |
| 2735 /* The MIPS implementation uses some labels for its own purpose. The | |
| 2736 following lists what labels are created, and are all formed by the | |
| 2737 pattern $L[a-z].*. The machine independent portion of GCC creates | |
| 2738 labels matching: $L[A-Z][0-9]+ and $L[0-9]+. | |
| 2739 | |
| 2740 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt. | |
| 2741 $Lb[0-9]+ Begin blocks for MIPS debug support | |
| 2742 $Lc[0-9]+ Label for use in s<xx> operation. | |
| 2743 $Le[0-9]+ End blocks for MIPS debug support */ | |
| 2744 | |
| 2745 #undef ASM_DECLARE_OBJECT_NAME | |
| 2746 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ | |
| 2747 mips_declare_object (STREAM, NAME, "", ":\n") | |
| 2748 | |
| 2749 /* Globalizing directive for a label. */ | |
| 2750 #define GLOBAL_ASM_OP "\t.globl\t" | |
| 2751 | |
| 2752 /* This says how to define a global common symbol. */ | |
| 2753 | |
| 2754 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common | |
| 2755 | |
| 2756 /* This says how to define a local common symbol (i.e., not visible to | |
| 2757 linker). */ | |
| 2758 | |
| 2759 #ifndef ASM_OUTPUT_ALIGNED_LOCAL | |
| 2760 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \ | |
| 2761 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false) | |
| 2762 #endif | |
| 2763 | |
| 2764 /* This says how to output an external. It would be possible not to | |
| 2765 output anything and let undefined symbol become external. However | |
| 2766 the assembler uses length information on externals to allocate in | |
| 2767 data/sdata bss/sbss, thereby saving exec time. */ | |
| 2768 | |
| 2769 #undef ASM_OUTPUT_EXTERNAL | |
| 2770 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \ | |
| 2771 mips_output_external(STREAM,DECL,NAME) | |
| 2772 | |
| 2773 /* This is how to declare a function name. The actual work of | |
| 2774 emitting the label is moved to function_prologue, so that we can | |
| 2775 get the line number correctly emitted before the .ent directive, | |
| 2776 and after any .file directives. Define as empty so that the function | |
| 2777 is not declared before the .ent directive elsewhere. */ | |
| 2778 | |
| 2779 #undef ASM_DECLARE_FUNCTION_NAME | |
| 2780 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) | |
| 2781 | |
| 2782 /* This is how to store into the string LABEL | |
| 2783 the symbol_ref name of an internal numbered label where | |
| 2784 PREFIX is the class of label and NUM is the number within the class. | |
| 2785 This is suitable for output with `assemble_name'. */ | |
| 2786 | |
| 2787 #undef ASM_GENERATE_INTERNAL_LABEL | |
| 2788 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
| 2789 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) | |
| 2790 | |
| 2791 /* Print debug labels as "foo = ." rather than "foo:" because they should | |
| 2792 represent a byte pointer rather than an ISA-encoded address. This is | |
| 2793 particularly important for code like: | |
| 2794 | |
| 2795 $LFBxxx = . | |
| 2796 .cfi_startproc | |
| 2797 ... | |
| 2798 .section .gcc_except_table,... | |
| 2799 ... | |
| 2800 .uleb128 foo-$LFBxxx | |
| 2801 | |
| 2802 The .uleb128 requies $LFBxxx to match the FDE start address, which is | |
| 2803 likewise a byte pointer rather than an ISA-encoded address. | |
| 2804 | |
| 2805 At the time of writing, this hook is not used for the function end | |
| 2806 label: | |
| 2807 | |
| 2808 $LFExxx: | |
| 2809 .end foo | |
| 2810 | |
| 2811 But this doesn't matter, because GAS doesn't treat a pre-.end label | |
| 2812 as a MIPS16 one anyway. */ | |
| 2813 | |
| 2814 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ | |
| 2815 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM) | |
| 2816 | |
| 2817 /* This is how to output an element of a case-vector that is absolute. */ | |
| 2818 | |
| 2819 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ | |
| 2820 fprintf (STREAM, "\t%s\t%sL%d\n", \ | |
| 2821 ptr_mode == DImode ? ".dword" : ".word", \ | |
| 2822 LOCAL_LABEL_PREFIX, \ | |
| 2823 VALUE) | |
| 2824 | |
| 2825 /* This is how to output an element of a case-vector. We can make the | |
| 2826 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word | |
| 2827 is supported. */ | |
| 2828 | |
| 2829 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ | |
| 2830 do { \ | |
| 2831 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \ | |
| 2832 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \ | |
| 2833 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ | |
| 2834 else if (TARGET_GPWORD) \ | |
| 2835 fprintf (STREAM, "\t%s\t%sL%d\n", \ | |
| 2836 ptr_mode == DImode ? ".gpdword" : ".gpword", \ | |
| 2837 LOCAL_LABEL_PREFIX, VALUE); \ | |
| 2838 else if (TARGET_RTP_PIC) \ | |
| 2839 { \ | |
| 2840 /* Make the entry relative to the start of the function. */ \ | |
| 2841 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \ | |
| 2842 fprintf (STREAM, "\t%s\t%sL%d-", \ | |
| 2843 Pmode == DImode ? ".dword" : ".word", \ | |
| 2844 LOCAL_LABEL_PREFIX, VALUE); \ | |
| 2845 assemble_name (STREAM, XSTR (fnsym, 0)); \ | |
| 2846 fprintf (STREAM, "\n"); \ | |
| 2847 } \ | |
| 2848 else \ | |
| 2849 fprintf (STREAM, "\t%s\t%sL%d\n", \ | |
| 2850 ptr_mode == DImode ? ".dword" : ".word", \ | |
| 2851 LOCAL_LABEL_PREFIX, VALUE); \ | |
| 2852 } while (0) | |
| 2853 | |
| 2854 /* This is how to output an assembler line | |
| 2855 that says to advance the location counter | |
| 2856 to a multiple of 2**LOG bytes. */ | |
| 2857 | |
| 2858 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ | |
| 2859 fprintf (STREAM, "\t.align\t%d\n", (LOG)) | |
| 2860 | |
| 2861 /* This is how to output an assembler line to advance the location | |
| 2862 counter by SIZE bytes. */ | |
| 2863 | |
| 2864 #undef ASM_OUTPUT_SKIP | |
| 2865 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \ | |
| 2866 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) | |
| 2867 | |
| 2868 /* This is how to output a string. */ | |
| 2869 #undef ASM_OUTPUT_ASCII | |
| 2870 #define ASM_OUTPUT_ASCII mips_output_ascii | |
| 2871 | |
| 2872 /* Output #ident as a in the read-only data section. */ | |
| 2873 #undef ASM_OUTPUT_IDENT | |
| 2874 #define ASM_OUTPUT_IDENT(FILE, STRING) \ | |
| 2875 { \ | |
| 2876 const char *p = STRING; \ | |
| 2877 int size = strlen (p) + 1; \ | |
| 2878 switch_to_section (readonly_data_section); \ | |
| 2879 assemble_string (p, size); \ | |
| 2880 } | |
| 2881 | |
| 2882 /* Default to -G 8 */ | |
| 2883 #ifndef MIPS_DEFAULT_GVALUE | |
| 2884 #define MIPS_DEFAULT_GVALUE 8 | |
| 2885 #endif | |
| 2886 | |
| 2887 /* Define the strings to put out for each section in the object file. */ | |
| 2888 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ | |
| 2889 #define DATA_SECTION_ASM_OP "\t.data" /* large data */ | |
| 2890 | |
| 2891 #undef READONLY_DATA_SECTION_ASM_OP | |
| 2892 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */ | |
| 2893 | |
| 2894 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ | |
| 2895 do \ | |
| 2896 { \ | |
| 2897 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \ | |
| 2898 TARGET_64BIT ? "daddiu" : "addiu", \ | |
| 2899 reg_names[STACK_POINTER_REGNUM], \ | |
| 2900 reg_names[STACK_POINTER_REGNUM], \ | |
| 2901 TARGET_64BIT ? "sd" : "sw", \ | |
| 2902 reg_names[REGNO], \ | |
| 2903 reg_names[STACK_POINTER_REGNUM]); \ | |
| 2904 } \ | |
| 2905 while (0) | |
| 2906 | |
| 2907 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ | |
| 2908 do \ | |
| 2909 { \ | |
|
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2910 mips_push_asm_switch (&mips_noreorder); \ |
| 0 | 2911 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \ |
| 2912 TARGET_64BIT ? "ld" : "lw", \ | |
| 2913 reg_names[REGNO], \ | |
| 2914 reg_names[STACK_POINTER_REGNUM], \ | |
| 2915 TARGET_64BIT ? "daddu" : "addu", \ | |
| 2916 reg_names[STACK_POINTER_REGNUM], \ | |
| 2917 reg_names[STACK_POINTER_REGNUM]); \ | |
|
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2918 mips_pop_asm_switch (&mips_noreorder); \ |
| 0 | 2919 } \ |
| 2920 while (0) | |
| 2921 | |
| 2922 /* How to start an assembler comment. | |
| 2923 The leading space is important (the mips native assembler requires it). */ | |
| 2924 #ifndef ASM_COMMENT_START | |
| 2925 #define ASM_COMMENT_START " #" | |
| 2926 #endif | |
| 2927 | |
| 2928 /* Default definitions for size_t and ptrdiff_t. We must override the | |
| 2929 definitions from ../svr4.h on mips-*-linux-gnu. */ | |
| 2930 | |
| 2931 #undef SIZE_TYPE | |
| 2932 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") | |
| 2933 | |
| 2934 #undef PTRDIFF_TYPE | |
| 2935 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") | |
| 2936 | |
| 2937 /* The maximum number of bytes that can be copied by one iteration of | |
| 2938 a movmemsi loop; see mips_block_move_loop. */ | |
| 2939 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \ | |
| 2940 (UNITS_PER_WORD * 4) | |
| 2941 | |
| 2942 /* The maximum number of bytes that can be copied by a straight-line | |
| 2943 implementation of movmemsi; see mips_block_move_straight. We want | |
| 2944 to make sure that any loop-based implementation will iterate at | |
| 2945 least twice. */ | |
| 2946 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \ | |
| 2947 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2) | |
| 2948 | |
| 2949 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These | |
| 2950 values were determined experimentally by benchmarking with CSiBE. | |
| 2951 In theory, the call overhead is higher for TARGET_ABICALLS (especially | |
| 2952 for o32 where we have to restore $gp afterwards as well as make an | |
| 2953 indirect call), but in practice, bumping this up higher for | |
| 2954 TARGET_ABICALLS doesn't make much difference to code size. */ | |
| 2955 | |
| 2956 #define MIPS_CALL_RATIO 8 | |
| 2957 | |
| 2958 /* Any loop-based implementation of movmemsi will have at least | |
| 2959 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory | |
| 2960 moves, so allow individual copies of fewer elements. | |
| 2961 | |
| 2962 When movmemsi is not available, use a value approximating | |
| 2963 the length of a memcpy call sequence, so that move_by_pieces | |
| 2964 will generate inline code if it is shorter than a function call. | |
| 2965 Since move_by_pieces_ninsns counts memory-to-memory moves, but | |
| 2966 we'll have to generate a load/store pair for each, halve the | |
| 2967 value of MIPS_CALL_RATIO to take that into account. */ | |
| 2968 | |
| 2969 #define MOVE_RATIO(speed) \ | |
| 2970 (HAVE_movmemsi \ | |
| 2971 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \ | |
| 2972 : MIPS_CALL_RATIO / 2) | |
| 2973 | |
| 2974 /* movmemsi is meant to generate code that is at least as good as | |
| 2975 move_by_pieces. However, movmemsi effectively uses a by-pieces | |
| 2976 implementation both for moves smaller than a word and for word-aligned | |
| 2977 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should | |
| 2978 allow the tree-level optimisers to do such moves by pieces, as it | |
| 2979 often exposes other optimization opportunities. We might as well | |
| 2980 continue to use movmemsi at the rtl level though, as it produces | |
| 2981 better code when scheduling is disabled (such as at -O). */ | |
| 2982 | |
| 2983 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ | |
| 2984 (HAVE_movmemsi \ | |
| 2985 ? (!currently_expanding_to_rtl \ | |
| 2986 && ((ALIGN) < BITS_PER_WORD \ | |
| 2987 ? (SIZE) < UNITS_PER_WORD \ | |
| 2988 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \ | |
| 2989 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \ | |
| 2990 < (unsigned int) MOVE_RATIO (false))) | |
| 2991 | |
| 2992 /* For CLEAR_RATIO, when optimizing for size, give a better estimate | |
| 2993 of the length of a memset call, but use the default otherwise. */ | |
| 2994 | |
| 2995 #define CLEAR_RATIO(speed)\ | |
| 2996 ((speed) ? 15 : MIPS_CALL_RATIO) | |
| 2997 | |
| 2998 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when | |
| 2999 optimizing for size adjust the ratio to account for the overhead of | |
| 3000 loading the constant and replicating it across the word. */ | |
| 3001 | |
| 3002 #define SET_RATIO(speed) \ | |
| 3003 ((speed) ? 15 : MIPS_CALL_RATIO - 2) | |
| 3004 | |
| 3005 /* STORE_BY_PIECES_P can be used when copying a constant string, but | |
| 3006 in that case each word takes 3 insns (lui, ori, sw), or more in | |
| 3007 64-bit mode, instead of 2 (lw, sw). For now we always fail this | |
| 3008 and let the move_by_pieces code copy the string from read-only | |
| 3009 memory. In the future, this could be tuned further for multi-issue | |
| 3010 CPUs that can issue stores down one pipe and arithmetic instructions | |
| 3011 down another; in that case, the lui/ori/sw combination would be a | |
| 3012 win for long enough strings. */ | |
| 3013 | |
| 3014 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0 | |
| 3015 | |
| 3016 #ifndef __mips16 | |
| 3017 /* Since the bits of the _init and _fini function is spread across | |
| 3018 many object files, each potentially with its own GP, we must assume | |
| 3019 we need to load our GP. We don't preserve $gp or $ra, since each | |
| 3020 init/fini chunk is supposed to initialize $gp, and crti/crtn | |
| 3021 already take care of preserving $ra and, when appropriate, $gp. */ | |
| 3022 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32) | |
| 3023 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
| 3024 asm (SECTION_OP "\n\ | |
| 3025 .set noreorder\n\ | |
| 3026 bal 1f\n\ | |
| 3027 nop\n\ | |
| 3028 1: .cpload $31\n\ | |
| 3029 .set reorder\n\ | |
| 3030 jal " USER_LABEL_PREFIX #FUNC "\n\ | |
| 3031 " TEXT_SECTION_ASM_OP); | |
| 3032 #endif /* Switch to #elif when we're no longer limited by K&R C. */ | |
| 3033 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \ | |
| 3034 || (defined _ABI64 && _MIPS_SIM == _ABI64) | |
| 3035 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
| 3036 asm (SECTION_OP "\n\ | |
| 3037 .set noreorder\n\ | |
| 3038 bal 1f\n\ | |
| 3039 nop\n\ | |
| 3040 1: .set reorder\n\ | |
| 3041 .cpsetup $31, $2, 1b\n\ | |
| 3042 jal " USER_LABEL_PREFIX #FUNC "\n\ | |
| 3043 " TEXT_SECTION_ASM_OP); | |
| 3044 #endif | |
| 3045 #endif | |
| 3046 | |
| 3047 #ifndef HAVE_AS_TLS | |
| 3048 #define HAVE_AS_TLS 0 | |
| 3049 #endif | |
| 3050 | |
| 3051 #ifndef USED_FOR_TARGET | |
|
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3052 /* Information about ".set noFOO; ...; .set FOO" blocks. */ |
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3053 struct mips_asm_switch { |
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3054 /* The FOO in the description above. */ |
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3055 const char *name; |
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3056 |
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3057 /* The current block nesting level, or 0 if we aren't in a block. */ |
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3058 int nesting_level; |
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3059 }; |
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3060 |
| 0 | 3061 extern const enum reg_class mips_regno_to_class[]; |
| 3062 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; | |
| 3063 extern bool mips_print_operand_punct[256]; | |
| 3064 extern const char *current_function_file; /* filename current function is in */ | |
| 3065 extern int num_source_filenames; /* current .file # */ | |
|
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3066 extern struct mips_asm_switch mips_noreorder; |
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3067 extern struct mips_asm_switch mips_nomacro; |
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3068 extern struct mips_asm_switch mips_noat; |
| 0 | 3069 extern int mips_dbx_regno[]; |
| 3070 extern int mips_dwarf_regno[]; | |
| 3071 extern bool mips_split_p[]; | |
| 3072 extern bool mips_split_hi_p[]; | |
| 3073 extern enum processor_type mips_arch; /* which cpu to codegen for */ | |
| 3074 extern enum processor_type mips_tune; /* which cpu to schedule for */ | |
| 3075 extern int mips_isa; /* architectural level */ | |
| 3076 extern int mips_abi; /* which ABI to use */ | |
| 3077 extern const struct mips_cpu_info *mips_arch_info; | |
| 3078 extern const struct mips_cpu_info *mips_tune_info; | |
| 3079 extern const struct mips_rtx_cost_data *mips_cost; | |
| 3080 extern bool mips_base_mips16; | |
| 3081 extern enum mips_code_readable_setting mips_code_readable; | |
| 3082 #endif | |
| 3083 | |
| 3084 /* Enable querying of DFA units. */ | |
| 3085 #define CPU_UNITS_QUERY 1 | |
|
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3086 |
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3087 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ |
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3088 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS) |
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3089 |
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3090 /* This is necessary to avoid a warning about comparing different enum |
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3091 types. */ |
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3092 #define mips_tune_attr ((enum attr_cpu) mips_tune) |
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3093 |
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3094 /* As on most targets, we want the .eh_frame section to be read-only where |
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3095 possible. And as on most targets, this means two things: |
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3096 |
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3097 (a) Non-locally-binding pointers must have an indirect encoding, |
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3098 so that the addresses in the .eh_frame section itself become |
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3099 locally-binding. |
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3100 |
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3101 (b) A shared library's .eh_frame section must encode locally-binding |
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3102 pointers in a relative (relocation-free) form. |
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3103 |
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3104 However, MIPS has traditionally not allowed directives like: |
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3105 |
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3106 .long x-. |
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3107 |
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3108 in cases where "x" is in a different section, or is not defined in the |
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3109 same assembly file. We are therefore unable to emit the PC-relative |
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3110 form required by (b) at assembly time. |
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3111 |
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3112 Fortunately, the linker is able to convert absolute addresses into |
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3113 PC-relative addresses on our behalf. Unfortunately, only certain |
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3114 versions of the linker know how to do this for indirect pointers, |
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3115 and for personality data. We must fall back on using writable |
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3116 .eh_frame sections for shared libraries if the linker does not |
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3117 support this feature. */ |
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3118 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ |
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3119 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr) |