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annotate gcc/config/mips/sync.md @ 63:b7f97abdc517 gcc-4.6-20100522

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update gcc from gcc-4.5.0 to gcc-4.6
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Mon, 24 May 2010 12:47:05 +0900
parents 77e2b8dfacca
children f6334be47118
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1 ;; Machine Description for MIPS based processor synchronization
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2 ;; instructions.
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3 ;; Copyright (C) 2007, 2008, 2009
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4 ;; Free Software Foundation, Inc.
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5
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6 ;; This file is part of GCC.
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7
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8 ;; GCC is free software; you can redistribute it and/or modify
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9 ;; it under the terms of the GNU General Public License as published by
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10 ;; the Free Software Foundation; either version 3, or (at your option)
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11 ;; any later version.
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12
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13 ;; GCC is distributed in the hope that it will be useful,
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14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 ;; GNU General Public License for more details.
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17
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 ;; Atomic fetch bitwise operations.
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23 (define_code_iterator fetchop_bit [ior xor and])
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24
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25 ;; Atomic HI and QI operations
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26 (define_code_iterator atomic_hiqi_op [plus minus ior xor and])
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27
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28 ;; Atomic memory operations.
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29
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30 (define_expand "memory_barrier"
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31 [(set (match_dup 0)
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32 (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))]
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33 "GENERATE_SYNC"
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34 {
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35 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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36 MEM_VOLATILE_P (operands[0]) = 1;
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37 })
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38
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39 (define_insn "*memory_barrier"
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40 [(set (match_operand:BLK 0 "" "")
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41 (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))]
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42 "GENERATE_SYNC"
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43 { return mips_output_sync (); })
0
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44
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45 (define_insn "sync_compare_and_swap<mode>"
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46 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
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47 (match_operand:GPR 1 "memory_operand" "+R,R"))
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48 (set (match_dup 1)
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49 (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "dJ,dJ")
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50 (match_operand:GPR 3 "arith_operand" "I,d")]
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51 UNSPEC_COMPARE_AND_SWAP))]
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52 "GENERATE_LL_SC"
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53 { return mips_output_sync_loop (insn, operands); }
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54 [(set_attr "sync_insn1" "li,move")
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55 (set_attr "sync_oldval" "0")
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56 (set_attr "sync_mem" "1")
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57 (set_attr "sync_required_oldval" "2")
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58 (set_attr "sync_insn1_op2" "3")])
0
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59
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60 (define_expand "sync_compare_and_swap<mode>"
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61 [(match_operand:SHORT 0 "register_operand")
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62 (match_operand:SHORT 1 "memory_operand")
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63 (match_operand:SHORT 2 "general_operand")
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64 (match_operand:SHORT 3 "general_operand")]
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65 "GENERATE_LL_SC"
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66 {
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67 union mips_gen_fn_ptrs generator;
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68 generator.fn_6 = gen_compare_and_swap_12;
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69 mips_expand_atomic_qihi (generator,
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70 operands[0], operands[1], operands[2], operands[3]);
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71 DONE;
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72 })
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73
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74 ;; Helper insn for mips_expand_atomic_qihi.
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75 (define_insn "compare_and_swap_12"
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76 [(set (match_operand:SI 0 "register_operand" "=&d,&d")
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77 (match_operand:SI 1 "memory_operand" "+R,R"))
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78 (set (match_dup 1)
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79 (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d,d")
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80 (match_operand:SI 3 "register_operand" "d,d")
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81 (match_operand:SI 4 "reg_or_0_operand" "dJ,dJ")
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82 (match_operand:SI 5 "reg_or_0_operand" "d,J")]
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83 UNSPEC_COMPARE_AND_SWAP_12))]
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84 "GENERATE_LL_SC"
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85 { return mips_output_sync_loop (insn, operands); }
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86 [(set_attr "sync_oldval" "0")
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87 (set_attr "sync_mem" "1")
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88 (set_attr "sync_inclusive_mask" "2")
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89 (set_attr "sync_exclusive_mask" "3")
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90 (set_attr "sync_required_oldval" "4")
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91 (set_attr "sync_insn1_op2" "5")])
0
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92
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93 (define_insn "sync_add<mode>"
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94 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
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95 (unspec_volatile:GPR
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96 [(plus:GPR (match_dup 0)
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97 (match_operand:GPR 1 "arith_operand" "I,d"))]
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98 UNSPEC_SYNC_OLD_OP))]
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99 "GENERATE_LL_SC"
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100 { return mips_output_sync_loop (insn, operands); }
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101 [(set_attr "sync_insn1" "addiu,addu")
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102 (set_attr "sync_mem" "0")
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103 (set_attr "sync_insn1_op2" "1")])
0
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104
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105 (define_expand "sync_<optab><mode>"
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106 [(set (match_operand:SHORT 0 "memory_operand")
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107 (unspec_volatile:SHORT
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108 [(atomic_hiqi_op:SHORT (match_dup 0)
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109 (match_operand:SHORT 1 "general_operand"))]
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110 UNSPEC_SYNC_OLD_OP))]
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111 "GENERATE_LL_SC"
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112 {
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113 union mips_gen_fn_ptrs generator;
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114 generator.fn_4 = gen_sync_<optab>_12;
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115 mips_expand_atomic_qihi (generator,
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116 NULL, operands[0], operands[1], NULL);
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117 DONE;
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118 })
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119
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120 ;; Helper insn for sync_<optab><mode>
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121 (define_insn "sync_<optab>_12"
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122 [(set (match_operand:SI 0 "memory_operand" "+R")
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123 (unspec_volatile:SI
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124 [(match_operand:SI 1 "register_operand" "d")
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125 (match_operand:SI 2 "register_operand" "d")
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126 (atomic_hiqi_op:SI (match_dup 0)
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127 (match_operand:SI 3 "register_operand" "dJ"))]
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128 UNSPEC_SYNC_OLD_OP_12))
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129 (clobber (match_scratch:SI 4 "=&d"))]
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130 "GENERATE_LL_SC"
55
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131 { return mips_output_sync_loop (insn, operands); }
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132 [(set_attr "sync_insn1" "<insn>")
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133 (set_attr "sync_insn2" "and")
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134 (set_attr "sync_mem" "0")
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135 (set_attr "sync_inclusive_mask" "1")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
136 (set_attr "sync_exclusive_mask" "2")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
137 (set_attr "sync_insn1_op2" "3")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
138 (set_attr "sync_oldval" "4")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
139 (set_attr "sync_newval" "4")])
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
140
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
141 (define_expand "sync_old_<optab><mode>"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
142 [(parallel [
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
143 (set (match_operand:SHORT 0 "register_operand")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
144 (match_operand:SHORT 1 "memory_operand"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
145 (set (match_dup 1)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
146 (unspec_volatile:SHORT [(atomic_hiqi_op:SHORT
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
147 (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
148 (match_operand:SHORT 2 "general_operand"))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
149 UNSPEC_SYNC_OLD_OP))])]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
150 "GENERATE_LL_SC"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
151 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
152 union mips_gen_fn_ptrs generator;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
153 generator.fn_5 = gen_sync_old_<optab>_12;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
154 mips_expand_atomic_qihi (generator,
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
155 operands[0], operands[1], operands[2], NULL);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
156 DONE;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
157 })
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
158
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
159 ;; Helper insn for sync_old_<optab><mode>
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
160 (define_insn "sync_old_<optab>_12"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
161 [(set (match_operand:SI 0 "register_operand" "=&d")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
162 (match_operand:SI 1 "memory_operand" "+R"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
163 (set (match_dup 1)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
164 (unspec_volatile:SI
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
165 [(match_operand:SI 2 "register_operand" "d")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
166 (match_operand:SI 3 "register_operand" "d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
167 (atomic_hiqi_op:SI (match_dup 0)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
168 (match_operand:SI 4 "register_operand" "dJ"))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
169 UNSPEC_SYNC_OLD_OP_12))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
170 (clobber (match_scratch:SI 5 "=&d"))]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
171 "GENERATE_LL_SC"
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
172 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
173 [(set_attr "sync_insn1" "<insn>")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
174 (set_attr "sync_insn2" "and")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
175 (set_attr "sync_oldval" "0")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
176 (set_attr "sync_mem" "1")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
177 (set_attr "sync_inclusive_mask" "2")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
178 (set_attr "sync_exclusive_mask" "3")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
179 (set_attr "sync_insn1_op2" "4")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
180 (set_attr "sync_newval" "5")])
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
181
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
182 (define_expand "sync_new_<optab><mode>"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
183 [(parallel [
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
184 (set (match_operand:SHORT 0 "register_operand")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
185 (unspec_volatile:SHORT [(atomic_hiqi_op:SHORT
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
186 (match_operand:SHORT 1 "memory_operand")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
187 (match_operand:SHORT 2 "general_operand"))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
188 UNSPEC_SYNC_NEW_OP))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
189 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
190 (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
191 UNSPEC_SYNC_NEW_OP))])]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
192 "GENERATE_LL_SC"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
193 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
194 union mips_gen_fn_ptrs generator;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
195 generator.fn_5 = gen_sync_new_<optab>_12;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
196 mips_expand_atomic_qihi (generator,
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
197 operands[0], operands[1], operands[2], NULL);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
198 DONE;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
199 })
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
200
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
201 ;; Helper insn for sync_new_<optab><mode>
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
202 (define_insn "sync_new_<optab>_12"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
203 [(set (match_operand:SI 0 "register_operand" "=&d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
204 (unspec_volatile:SI
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
205 [(match_operand:SI 1 "memory_operand" "+R")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
206 (match_operand:SI 2 "register_operand" "d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
207 (match_operand:SI 3 "register_operand" "d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
208 (atomic_hiqi_op:SI (match_dup 0)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
209 (match_operand:SI 4 "register_operand" "dJ"))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
210 UNSPEC_SYNC_NEW_OP_12))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
211 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
212 (unspec_volatile:SI
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
213 [(match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
214 (match_dup 2)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
215 (match_dup 3)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
216 (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
217 "GENERATE_LL_SC"
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
218 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
219 [(set_attr "sync_insn1" "<insn>")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
220 (set_attr "sync_insn2" "and")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
221 (set_attr "sync_oldval" "0")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
222 (set_attr "sync_newval" "0")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
223 (set_attr "sync_mem" "1")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
224 (set_attr "sync_inclusive_mask" "2")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
225 (set_attr "sync_exclusive_mask" "3")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
226 (set_attr "sync_insn1_op2" "4")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
227
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
228 (define_expand "sync_nand<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
229 [(set (match_operand:SHORT 0 "memory_operand")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
230 (unspec_volatile:SHORT
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
231 [(match_dup 0)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
232 (match_operand:SHORT 1 "general_operand")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
233 UNSPEC_SYNC_OLD_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
234 "GENERATE_LL_SC"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
235 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
236 union mips_gen_fn_ptrs generator;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
237 generator.fn_4 = gen_sync_nand_12;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
238 mips_expand_atomic_qihi (generator,
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
239 NULL, operands[0], operands[1], NULL);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
240 DONE;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
241 })
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
242
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
243 ;; Helper insn for sync_nand<mode>
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
244 (define_insn "sync_nand_12"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
245 [(set (match_operand:SI 0 "memory_operand" "+R")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
246 (unspec_volatile:SI
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
247 [(match_operand:SI 1 "register_operand" "d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
248 (match_operand:SI 2 "register_operand" "d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
249 (match_dup 0)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
250 (match_operand:SI 3 "register_operand" "dJ")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
251 UNSPEC_SYNC_OLD_OP_12))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
252 (clobber (match_scratch:SI 4 "=&d"))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
253 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
254 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
255 [(set_attr "sync_insn1" "and")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
256 (set_attr "sync_insn2" "xor")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
257 (set_attr "sync_mem" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
258 (set_attr "sync_inclusive_mask" "1")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
259 (set_attr "sync_exclusive_mask" "2")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
260 (set_attr "sync_insn1_op2" "3")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
261 (set_attr "sync_oldval" "4")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
262 (set_attr "sync_newval" "4")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
263
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
264 (define_expand "sync_old_nand<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
265 [(parallel [
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
266 (set (match_operand:SHORT 0 "register_operand")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
267 (match_operand:SHORT 1 "memory_operand"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
268 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
269 (unspec_volatile:SHORT [(match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
270 (match_operand:SHORT 2 "general_operand")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
271 UNSPEC_SYNC_OLD_OP))])]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
272 "GENERATE_LL_SC"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
273 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
274 union mips_gen_fn_ptrs generator;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
275 generator.fn_5 = gen_sync_old_nand_12;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
276 mips_expand_atomic_qihi (generator,
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
277 operands[0], operands[1], operands[2], NULL);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
278 DONE;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
279 })
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
280
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
281 ;; Helper insn for sync_old_nand<mode>
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
282 (define_insn "sync_old_nand_12"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
283 [(set (match_operand:SI 0 "register_operand" "=&d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
284 (match_operand:SI 1 "memory_operand" "+R"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
285 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
286 (unspec_volatile:SI
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
287 [(match_operand:SI 2 "register_operand" "d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
288 (match_operand:SI 3 "register_operand" "d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
289 (match_operand:SI 4 "register_operand" "dJ")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
290 UNSPEC_SYNC_OLD_OP_12))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
291 (clobber (match_scratch:SI 5 "=&d"))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
292 "GENERATE_LL_SC"
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
293 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
294 [(set_attr "sync_insn1" "and")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
295 (set_attr "sync_insn2" "xor")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
296 (set_attr "sync_oldval" "0")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
297 (set_attr "sync_mem" "1")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
298 (set_attr "sync_inclusive_mask" "2")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
299 (set_attr "sync_exclusive_mask" "3")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
300 (set_attr "sync_insn1_op2" "4")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
301 (set_attr "sync_newval" "5")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
302
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
303 (define_expand "sync_new_nand<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
304 [(parallel [
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
305 (set (match_operand:SHORT 0 "register_operand")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
306 (unspec_volatile:SHORT [(match_operand:SHORT 1 "memory_operand")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
307 (match_operand:SHORT 2 "general_operand")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
308 UNSPEC_SYNC_NEW_OP))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
309 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
310 (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
311 UNSPEC_SYNC_NEW_OP))])]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
312 "GENERATE_LL_SC"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
313 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
314 union mips_gen_fn_ptrs generator;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
315 generator.fn_5 = gen_sync_new_nand_12;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
316 mips_expand_atomic_qihi (generator,
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
317 operands[0], operands[1], operands[2], NULL);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
318 DONE;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
319 })
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
320
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
321 ;; Helper insn for sync_new_nand<mode>
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
322 (define_insn "sync_new_nand_12"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
323 [(set (match_operand:SI 0 "register_operand" "=&d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
324 (unspec_volatile:SI
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
325 [(match_operand:SI 1 "memory_operand" "+R")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
326 (match_operand:SI 2 "register_operand" "d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
327 (match_operand:SI 3 "register_operand" "d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
328 (match_operand:SI 4 "register_operand" "dJ")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
329 UNSPEC_SYNC_NEW_OP_12))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
330 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
331 (unspec_volatile:SI
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
332 [(match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
333 (match_dup 2)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
334 (match_dup 3)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
335 (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
336 "GENERATE_LL_SC"
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
337 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
338 [(set_attr "sync_insn1" "and")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
339 (set_attr "sync_insn2" "xor")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
340 (set_attr "sync_oldval" "0")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
341 (set_attr "sync_newval" "0")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
342 (set_attr "sync_mem" "1")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
343 (set_attr "sync_inclusive_mask" "2")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
344 (set_attr "sync_exclusive_mask" "3")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
345 (set_attr "sync_insn1_op2" "4")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
346
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
347 (define_insn "sync_sub<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
348 [(set (match_operand:GPR 0 "memory_operand" "+R")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
349 (unspec_volatile:GPR
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
350 [(minus:GPR (match_dup 0)
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
351 (match_operand:GPR 1 "register_operand" "d"))]
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
352 UNSPEC_SYNC_OLD_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
353 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
354 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
355 [(set_attr "sync_insn1" "subu")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
356 (set_attr "sync_mem" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
357 (set_attr "sync_insn1_op2" "1")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
358
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
359 (define_insn "sync_old_add<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
360 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
361 (match_operand:GPR 1 "memory_operand" "+R,R"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
362 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
363 (unspec_volatile:GPR
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
364 [(plus:GPR (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
365 (match_operand:GPR 2 "arith_operand" "I,d"))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
366 UNSPEC_SYNC_OLD_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
367 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
368 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
369 [(set_attr "sync_insn1" "addiu,addu")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
370 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
371 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
372 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
373
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
374 (define_insn "sync_old_sub<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
375 [(set (match_operand:GPR 0 "register_operand" "=&d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
376 (match_operand:GPR 1 "memory_operand" "+R"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
377 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
378 (unspec_volatile:GPR
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
379 [(minus:GPR (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
380 (match_operand:GPR 2 "register_operand" "d"))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
381 UNSPEC_SYNC_OLD_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
382 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
383 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
384 [(set_attr "sync_insn1" "subu")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
385 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
386 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
387 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
388
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
389 (define_insn "sync_new_add<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
390 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
391 (plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
392 (match_operand:GPR 2 "arith_operand" "I,d")))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
393 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
394 (unspec_volatile:GPR
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
395 [(plus:GPR (match_dup 1) (match_dup 2))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
396 UNSPEC_SYNC_NEW_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
397 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
398 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
399 [(set_attr "sync_insn1" "addiu,addu")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
400 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
401 (set_attr "sync_newval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
402 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
403 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
404
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
405 (define_insn "sync_new_sub<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
406 [(set (match_operand:GPR 0 "register_operand" "=&d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
407 (minus:GPR (match_operand:GPR 1 "memory_operand" "+R")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
408 (match_operand:GPR 2 "register_operand" "d")))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
409 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
410 (unspec_volatile:GPR
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
411 [(minus:GPR (match_dup 1) (match_dup 2))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
412 UNSPEC_SYNC_NEW_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
413 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
414 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
415 [(set_attr "sync_insn1" "subu")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
416 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
417 (set_attr "sync_newval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
418 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
419 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
420
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
421 (define_insn "sync_<optab><mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
422 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
423 (unspec_volatile:GPR
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
424 [(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
425 (match_dup 0))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
426 UNSPEC_SYNC_OLD_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
427 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
428 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
429 [(set_attr "sync_insn1" "<immediate_insn>,<insn>")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
430 (set_attr "sync_mem" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
431 (set_attr "sync_insn1_op2" "1")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
432
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
433 (define_insn "sync_old_<optab><mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
434 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
435 (match_operand:GPR 1 "memory_operand" "+R,R"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
436 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
437 (unspec_volatile:GPR
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
438 [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
439 (match_dup 1))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
440 UNSPEC_SYNC_OLD_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
441 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
442 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
443 [(set_attr "sync_insn1" "<immediate_insn>,<insn>")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
444 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
445 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
446 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
447
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
448 (define_insn "sync_new_<optab><mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
449 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
450 (match_operand:GPR 1 "memory_operand" "+R,R"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
451 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
452 (unspec_volatile:GPR
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
453 [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
454 (match_dup 1))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
455 UNSPEC_SYNC_NEW_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
456 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
457 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
458 [(set_attr "sync_insn1" "<immediate_insn>,<insn>")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
459 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
460 (set_attr "sync_newval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
461 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
462 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
463
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
464 (define_insn "sync_nand<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
465 [(set (match_operand:GPR 0 "memory_operand" "+R,R")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
466 (unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
467 UNSPEC_SYNC_OLD_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
468 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
469 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
470 [(set_attr "sync_insn1" "andi,and")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
471 (set_attr "sync_insn2" "not")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
472 (set_attr "sync_mem" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
473 (set_attr "sync_insn1_op2" "1")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
474
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
475 (define_insn "sync_old_nand<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
476 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
477 (match_operand:GPR 1 "memory_operand" "+R,R"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
478 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
479 (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
480 UNSPEC_SYNC_OLD_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
481 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
482 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
483 [(set_attr "sync_insn1" "andi,and")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
484 (set_attr "sync_insn2" "not")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
485 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
486 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
487 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
488
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
489 (define_insn "sync_new_nand<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
490 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
491 (match_operand:GPR 1 "memory_operand" "+R,R"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
492 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
493 (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
494 UNSPEC_SYNC_NEW_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
495 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
496 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
497 [(set_attr "sync_insn1" "andi,and")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
498 (set_attr "sync_insn2" "not")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
499 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
500 (set_attr "sync_newval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
501 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
502 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
503
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
504 (define_insn "sync_lock_test_and_set<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
505 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
506 (match_operand:GPR 1 "memory_operand" "+R,R"))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
507 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
508 (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
509 UNSPEC_SYNC_EXCHANGE))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
510 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
511 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
512 [(set_attr "sync_release_barrier" "no")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
513 (set_attr "sync_insn1" "li,move")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
514 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
515 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
516 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
517
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
518 (define_expand "sync_lock_test_and_set<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
519 [(match_operand:SHORT 0 "register_operand")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
520 (match_operand:SHORT 1 "memory_operand")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
521 (match_operand:SHORT 2 "general_operand")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
522 "GENERATE_LL_SC"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
523 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
524 union mips_gen_fn_ptrs generator;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
525 generator.fn_5 = gen_test_and_set_12;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
526 mips_expand_atomic_qihi (generator,
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
527 operands[0], operands[1], operands[2], NULL);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
528 DONE;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
529 })
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
530
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
531 (define_insn "test_and_set_12"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
532 [(set (match_operand:SI 0 "register_operand" "=&d")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
533 (match_operand:SI 1 "memory_operand" "+R"))
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
534 (set (match_dup 1)
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
535 (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
536 (match_operand:SI 3 "register_operand" "d")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
537 (match_operand:SI 4 "arith_operand" "dJ")]
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
538 UNSPEC_SYNC_EXCHANGE_12))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
539 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
540 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
541 [(set_attr "sync_release_barrier" "no")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
542 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
543 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
544 ;; Unused, but needed to give the number of operands expected by
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
545 ;; the expander.
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
546 (set_attr "sync_inclusive_mask" "2")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
547 (set_attr "sync_exclusive_mask" "3")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
548 (set_attr "sync_insn1_op2" "4")])