Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/pdp11/pdp11.h @ 63:b7f97abdc517 gcc-4.6-20100522
update gcc from gcc-4.5.0 to gcc-4.6
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Mon, 24 May 2010 12:47:05 +0900 |
| parents | 77e2b8dfacca |
| children | f6334be47118 |
| rev | line source |
|---|---|
| 0 | 1 /* Definitions of target machine for GNU compiler, for the pdp-11 |
| 2 Copyright (C) 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2002, 2004, 2005, | |
| 3 2006, 2007, 2008 Free Software Foundation, Inc. | |
| 4 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). | |
| 5 | |
| 6 This file is part of GCC. | |
| 7 | |
| 8 GCC is free software; you can redistribute it and/or modify | |
| 9 it under the terms of the GNU General Public License as published by | |
| 10 the Free Software Foundation; either version 3, or (at your option) | |
| 11 any later version. | |
| 12 | |
| 13 GCC is distributed in the hope that it will be useful, | |
| 14 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 GNU General Public License for more details. | |
| 17 | |
| 18 You should have received a copy of the GNU General Public License | |
| 19 along with GCC; see the file COPYING3. If not see | |
| 20 <http://www.gnu.org/licenses/>. */ | |
| 21 | |
| 22 #define CONSTANT_POOL_BEFORE_FUNCTION 0 | |
| 23 | |
| 24 /* check whether load_fpu_reg or not */ | |
| 25 #define LOAD_FPU_REG_P(x) ((x)>=8 && (x)<=11) | |
| 26 #define NO_LOAD_FPU_REG_P(x) ((x)==12 || (x)==13) | |
| 27 #define FPU_REG_P(x) (LOAD_FPU_REG_P(x) || NO_LOAD_FPU_REG_P(x)) | |
| 28 #define CPU_REG_P(x) ((x)<8) | |
| 29 | |
| 30 /* Names to predefine in the preprocessor for this target machine. */ | |
| 31 | |
| 32 #define TARGET_CPU_CPP_BUILTINS() \ | |
| 33 do \ | |
| 34 { \ | |
| 35 builtin_define_std ("pdp11"); \ | |
| 36 } \ | |
| 37 while (0) | |
| 38 | |
| 39 /* Print subsidiary information on the compiler version in use. */ | |
| 40 #define TARGET_VERSION fprintf (stderr, " (pdp11)"); | |
| 41 | |
| 42 | |
| 43 /* Generate DBX debugging information. */ | |
| 44 | |
| 45 /* #define DBX_DEBUGGING_INFO */ | |
| 46 | |
| 47 #define TARGET_40_PLUS (TARGET_40 || TARGET_45) | |
| 48 #define TARGET_10 (! TARGET_40_PLUS) | |
| 49 | |
| 50 #define TARGET_UNIX_ASM_DEFAULT 0 | |
| 51 | |
| 52 #define ASSEMBLER_DIALECT (TARGET_UNIX_ASM ? 1 : 0) | |
| 53 | |
| 54 | |
| 55 | |
| 56 /* TYPE SIZES */ | |
| 57 #define SHORT_TYPE_SIZE 16 | |
| 58 #define INT_TYPE_SIZE (TARGET_INT16 ? 16 : 32) | |
| 59 #define LONG_TYPE_SIZE 32 | |
| 60 #define LONG_LONG_TYPE_SIZE 64 | |
| 61 | |
| 62 /* if we set FLOAT_TYPE_SIZE to 32, we could have the benefit | |
| 63 of saving core for huge arrays - the definitions are | |
| 64 already in md - but floats can never reside in | |
| 65 an FPU register - we keep the FPU in double float mode | |
| 66 all the time !! */ | |
| 67 #define FLOAT_TYPE_SIZE (TARGET_FLOAT32 ? 32 : 64) | |
| 68 #define DOUBLE_TYPE_SIZE 64 | |
| 69 #define LONG_DOUBLE_TYPE_SIZE 64 | |
| 70 | |
| 71 /* machine types from ansi */ | |
| 72 #define SIZE_TYPE "unsigned int" /* definition of size_t */ | |
| 73 #define WCHAR_TYPE "int" /* or long int???? */ | |
| 74 #define WCHAR_TYPE_SIZE 16 | |
| 75 | |
| 76 #define PTRDIFF_TYPE "int" | |
| 77 | |
| 78 /* target machine storage layout */ | |
| 79 | |
| 80 /* Define this if most significant bit is lowest numbered | |
| 81 in instructions that operate on numbered bit-fields. */ | |
| 82 #define BITS_BIG_ENDIAN 0 | |
| 83 | |
| 84 /* Define this if most significant byte of a word is the lowest numbered. */ | |
| 85 #define BYTES_BIG_ENDIAN 0 | |
| 86 | |
| 87 /* Define this if most significant word of a multiword number is first. */ | |
| 88 #define WORDS_BIG_ENDIAN 1 | |
| 89 | |
| 90 /* Define that floats are in VAX order, not high word first as for ints. */ | |
| 91 #define FLOAT_WORDS_BIG_ENDIAN 0 | |
| 92 | |
| 93 /* Width of a word, in units (bytes). | |
| 94 | |
| 95 UNITS OR BYTES - seems like units */ | |
| 96 #define UNITS_PER_WORD 2 | |
| 97 | |
| 98 /* This machine doesn't use IEEE floats. */ | |
| 99 /* Because the pdp11 (at least Unix) convention for 32-bit ints is | |
| 100 big endian, opposite for what you need for float, the vax float | |
| 101 conversion routines aren't actually used directly. But the underlying | |
| 102 format is indeed the vax/pdp11 float format. */ | |
| 103 extern const struct real_format pdp11_f_format; | |
| 104 extern const struct real_format pdp11_d_format; | |
| 105 | |
| 106 /* Maximum sized of reasonable data type | |
| 107 DImode or Dfmode ...*/ | |
| 108 #define MAX_FIXED_MODE_SIZE 64 | |
| 109 | |
| 110 /* Allocation boundary (in *bits*) for storing pointers in memory. */ | |
| 111 #define POINTER_BOUNDARY 16 | |
| 112 | |
| 113 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
| 114 #define PARM_BOUNDARY 16 | |
| 115 | |
| 116 /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
| 117 #define STACK_BOUNDARY 16 | |
| 118 | |
| 119 /* Allocation boundary (in *bits*) for the code of a function. */ | |
| 120 #define FUNCTION_BOUNDARY 16 | |
| 121 | |
| 122 /* Alignment of field after `int : 0' in a structure. */ | |
| 123 #define EMPTY_FIELD_BOUNDARY 16 | |
| 124 | |
| 125 /* No data type wants to be aligned rounder than this. */ | |
| 126 #define BIGGEST_ALIGNMENT 16 | |
| 127 | |
| 128 /* Define this if move instructions will actually fail to work | |
| 129 when given unaligned data. */ | |
| 130 #define STRICT_ALIGNMENT 1 | |
| 131 | |
| 132 /* Standard register usage. */ | |
| 133 | |
| 134 /* Number of actual hardware registers. | |
| 135 The hardware registers are assigned numbers for the compiler | |
| 136 from 0 to just below FIRST_PSEUDO_REGISTER. | |
| 137 All registers that the compiler knows about must be given numbers, | |
| 138 even those that are not normally considered general registers. | |
| 139 | |
| 140 we have 8 integer registers, plus 6 float | |
| 141 (don't use scratch float !) */ | |
| 142 | |
| 143 #define FIRST_PSEUDO_REGISTER 14 | |
| 144 | |
| 145 /* 1 for registers that have pervasive standard uses | |
| 146 and are not available for the register allocator. | |
| 147 | |
| 148 On the pdp, these are: | |
| 149 Reg 7 = pc; | |
| 150 reg 6 = sp; | |
| 151 reg 5 = fp; not necessarily! | |
| 152 */ | |
| 153 | |
| 154 /* don't let them touch fp regs for the time being !*/ | |
| 155 | |
| 156 #define FIXED_REGISTERS \ | |
| 157 {0, 0, 0, 0, 0, 0, 1, 1, \ | |
| 158 0, 0, 0, 0, 0, 0 } | |
| 159 | |
| 160 | |
| 161 | |
| 162 /* 1 for registers not available across function calls. | |
| 163 These must include the FIXED_REGISTERS and also any | |
| 164 registers that can be used without being saved. | |
| 165 The latter must include the registers where values are returned | |
| 166 and the register where structure-value addresses are passed. | |
| 167 Aside from that, you can include as many other registers as you like. */ | |
| 168 | |
| 169 /* don't know about fp */ | |
| 170 #define CALL_USED_REGISTERS \ | |
| 171 {1, 1, 0, 0, 0, 0, 1, 1, \ | |
| 172 0, 0, 0, 0, 0, 0 } | |
| 173 | |
| 174 | |
| 175 /* Make sure everything's fine if we *don't* have an FPU. | |
| 176 This assumes that putting a register in fixed_regs will keep the | |
| 177 compiler's mitts completely off it. We don't bother to zero it out | |
| 178 of register classes. Also fix incompatible register naming with | |
| 179 the UNIX assembler. | |
| 180 */ | |
| 181 #define CONDITIONAL_REGISTER_USAGE \ | |
| 182 { \ | |
| 183 int i; \ | |
| 184 HARD_REG_SET x; \ | |
| 185 if (!TARGET_FPU) \ | |
| 186 { \ | |
| 187 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPU_REGS]); \ | |
| 188 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ | |
| 189 if (TEST_HARD_REG_BIT (x, i)) \ | |
| 190 fixed_regs[i] = call_used_regs[i] = 1; \ | |
| 191 } \ | |
| 192 \ | |
| 193 if (TARGET_AC0) \ | |
| 194 call_used_regs[8] = 1; \ | |
| 195 if (TARGET_UNIX_ASM) \ | |
| 196 { \ | |
| 197 /* Change names of FPU registers for the UNIX assembler. */ \ | |
| 198 reg_names[8] = "fr0"; \ | |
| 199 reg_names[9] = "fr1"; \ | |
| 200 reg_names[10] = "fr2"; \ | |
| 201 reg_names[11] = "fr3"; \ | |
| 202 reg_names[12] = "fr4"; \ | |
| 203 reg_names[13] = "fr5"; \ | |
| 204 } \ | |
| 205 } | |
| 206 | |
| 207 /* Return number of consecutive hard regs needed starting at reg REGNO | |
| 208 to hold something of mode MODE. | |
| 209 This is ordinarily the length in words of a value of mode MODE | |
| 210 but can be less for certain modes in special long registers. | |
| 211 */ | |
| 212 | |
| 213 #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
| 214 ((REGNO < 8)? \ | |
| 215 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \ | |
| 216 :1) | |
| 217 | |
| 218 | |
| 219 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
| 220 On the pdp, the cpu registers can hold any mode - check alignment | |
| 221 | |
| 222 FPU can only hold DF - simplifies life! | |
| 223 */ | |
| 224 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
| 225 (((REGNO) < 8)? \ | |
| 226 ((GET_MODE_BITSIZE(MODE) <= 16) \ | |
| 227 || (GET_MODE_BITSIZE(MODE) == 32 && !((REGNO) & 1))) \ | |
| 228 :(MODE) == DFmode) | |
| 229 | |
| 230 | |
| 231 /* Value is 1 if it is a good idea to tie two pseudo registers | |
| 232 when one has mode MODE1 and one has mode MODE2. | |
| 233 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
| 234 for any hard reg, then this must be 0 for correct output. */ | |
| 235 #define MODES_TIEABLE_P(MODE1, MODE2) 0 | |
| 236 | |
| 237 /* Specify the registers used for certain standard purposes. | |
| 238 The values of these macros are register numbers. */ | |
| 239 | |
| 240 /* the pdp11 pc overloaded on a register that the compiler knows about. */ | |
| 241 #define PC_REGNUM 7 | |
| 242 | |
| 243 /* Register to use for pushing function arguments. */ | |
| 244 #define STACK_POINTER_REGNUM 6 | |
| 245 | |
| 246 /* Base register for access to local variables of the function. */ | |
| 247 #define FRAME_POINTER_REGNUM 5 | |
| 248 | |
| 249 /* Base register for access to arguments of the function. */ | |
| 250 #define ARG_POINTER_REGNUM 5 | |
| 251 | |
| 252 /* Register in which static-chain is passed to a function. */ | |
| 253 /* ??? - i don't want to give up a reg for this! */ | |
| 254 #define STATIC_CHAIN_REGNUM 4 | |
| 255 | |
| 256 /* Define the classes of registers for register constraints in the | |
| 257 machine description. Also define ranges of constants. | |
| 258 | |
| 259 One of the classes must always be named ALL_REGS and include all hard regs. | |
| 260 If there is more than one class, another class must be named NO_REGS | |
| 261 and contain no registers. | |
| 262 | |
| 263 The name GENERAL_REGS must be the name of a class (or an alias for | |
| 264 another name such as ALL_REGS). This is the class of registers | |
| 265 that is allowed by "g" or "r" in a register constraint. | |
| 266 Also, registers outside this class are allocated only when | |
| 267 instructions express preferences for them. | |
| 268 | |
| 269 The classes must be numbered in nondecreasing order; that is, | |
| 270 a larger-numbered class must never be contained completely | |
| 271 in a smaller-numbered class. | |
| 272 | |
| 273 For any two classes, it is very desirable that there be another | |
| 274 class that represents their union. */ | |
| 275 | |
| 276 /* The pdp has a couple of classes: | |
| 277 | |
| 278 MUL_REGS are used for odd numbered regs, to use in 16-bit multiplication | |
| 279 (even numbered do 32-bit multiply) | |
| 280 LMUL_REGS long multiply registers (even numbered regs ) | |
| 281 (don't need them, all 32-bit regs are even numbered!) | |
| 282 GENERAL_REGS is all cpu | |
| 283 LOAD_FPU_REGS is the first four cpu regs, they are easier to load | |
| 284 NO_LOAD_FPU_REGS is ac4 and ac5, currently - difficult to load them | |
| 285 FPU_REGS is all fpu regs | |
| 286 */ | |
| 287 | |
| 288 enum reg_class { NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS, FPU_REGS, ALL_REGS, LIM_REG_CLASSES }; | |
| 289 | |
| 290 #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
| 291 | |
| 292 /* have to allow this till cmpsi/tstsi are fixed in a better way !! */ | |
|
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b7f97abdc517
update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
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293 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true |
| 0 | 294 |
| 295 /* Since GENERAL_REGS is the same class as ALL_REGS, | |
| 296 don't give it a different class number; just make it an alias. */ | |
| 297 | |
| 298 /* #define GENERAL_REGS ALL_REGS */ | |
| 299 | |
| 300 /* Give names of register classes as strings for dump file. */ | |
| 301 | |
| 302 #define REG_CLASS_NAMES {"NO_REGS", "MUL_REGS", "GENERAL_REGS", "LOAD_FPU_REGS", "NO_LOAD_FPU_REGS", "FPU_REGS", "ALL_REGS" } | |
| 303 | |
| 304 /* Define which registers fit in which classes. | |
| 305 This is an initializer for a vector of HARD_REG_SET | |
| 306 of length N_REG_CLASSES. */ | |
| 307 | |
| 308 #define REG_CLASS_CONTENTS {{0}, {0x00aa}, {0x00ff}, {0x0f00}, {0x3000}, {0x3f00}, {0x3fff}} | |
| 309 | |
| 310 /* The same information, inverted: | |
| 311 Return the class number of the smallest class containing | |
| 312 reg number REGNO. This could be a conditional expression | |
| 313 or could index an array. */ | |
| 314 | |
| 315 #define REGNO_REG_CLASS(REGNO) \ | |
| 316 ((REGNO)>=8?((REGNO)<=11?LOAD_FPU_REGS:NO_LOAD_FPU_REGS):(((REGNO)&1)?MUL_REGS:GENERAL_REGS)) | |
| 317 | |
| 318 | |
| 319 /* The class value for index registers, and the one for base regs. */ | |
| 320 #define INDEX_REG_CLASS GENERAL_REGS | |
| 321 #define BASE_REG_CLASS GENERAL_REGS | |
| 322 | |
| 323 /* Get reg_class from a letter such as appears in the machine description. */ | |
| 324 | |
| 325 #define REG_CLASS_FROM_LETTER(C) \ | |
| 326 ((C) == 'f' ? FPU_REGS : \ | |
| 327 ((C) == 'd' ? MUL_REGS : \ | |
| 328 ((C) == 'a' ? LOAD_FPU_REGS : NO_REGS))) | |
| 329 | |
| 330 | |
| 331 /* The letters I, J, K, L and M in a register constraint string | |
| 332 can be used to stand for particular ranges of immediate operands. | |
| 333 This macro defines what the ranges are. | |
| 334 C is the letter, and VALUE is a constant value. | |
| 335 Return 1 if VALUE is in the range specified by C. | |
| 336 | |
| 337 I bits 31-16 0000 | |
| 338 J bits 15-00 0000 | |
| 339 K completely random 32 bit | |
| 340 L,M,N -1,1,0 respectively | |
| 341 O where doing shifts in sequence is faster than | |
| 342 one big shift | |
| 343 */ | |
| 344 | |
| 345 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
| 346 ((C) == 'I' ? ((VALUE) & 0xffff0000) == 0 \ | |
| 347 : (C) == 'J' ? ((VALUE) & 0x0000ffff) == 0 \ | |
| 348 : (C) == 'K' ? (((VALUE) & 0xffff0000) != 0 \ | |
| 349 && ((VALUE) & 0x0000ffff) != 0) \ | |
| 350 : (C) == 'L' ? ((VALUE) == 1) \ | |
| 351 : (C) == 'M' ? ((VALUE) == -1) \ | |
| 352 : (C) == 'N' ? ((VALUE) == 0) \ | |
| 353 : (C) == 'O' ? (abs(VALUE) >1 && abs(VALUE) <= 4) \ | |
| 354 : 0) | |
| 355 | |
| 356 /* Similar, but for floating constants, and defining letters G and H. | |
| 357 Here VALUE is the CONST_DOUBLE rtx itself. */ | |
| 358 | |
| 359 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
| 360 ((C) == 'G' && XINT (VALUE, 0) == 0 && XINT (VALUE, 1) == 0) | |
| 361 | |
| 362 | |
| 363 /* Letters in the range `Q' through `U' may be defined in a | |
| 364 machine-dependent fashion to stand for arbitrary operand types. | |
| 365 The machine description macro `EXTRA_CONSTRAINT' is passed the | |
| 366 operand as its first argument and the constraint letter as its | |
| 367 second operand. | |
| 368 | |
| 369 `Q' is for memory references that require an extra word after the opcode. | |
| 370 `R' is for memory references which are encoded within the opcode. */ | |
| 371 | |
| 372 #define EXTRA_CONSTRAINT(OP,CODE) \ | |
| 373 ((GET_CODE (OP) != MEM) ? 0 \ | |
|
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77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
374 : !memory_address_p (GET_MODE (OP), XEXP (OP, 0)) ? 0 \ |
| 0 | 375 : ((CODE) == 'Q') ? !simple_memory_operand (OP, GET_MODE (OP)) \ |
| 376 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \ | |
| 377 : 0) | |
| 378 | |
| 379 /* Given an rtx X being reloaded into a reg required to be | |
| 380 in class CLASS, return the class of reg to actually use. | |
| 381 In general this is just CLASS; but on some machines | |
| 382 in some cases it is preferable to use a more restrictive class. | |
| 383 | |
| 384 loading is easier into LOAD_FPU_REGS than FPU_REGS! */ | |
| 385 | |
| 386 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
| 387 (((CLASS) != FPU_REGS)?(CLASS):LOAD_FPU_REGS) | |
| 388 | |
| 389 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,x) \ | |
| 390 (((CLASS) == NO_LOAD_FPU_REGS && !(REG_P(x) && LOAD_FPU_REG_P(REGNO(x))))?LOAD_FPU_REGS:NO_REGS) | |
| 391 | |
| 392 /* Return the maximum number of consecutive registers | |
| 393 needed to represent mode MODE in a register of class CLASS. */ | |
| 394 #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
| 395 ((CLASS == GENERAL_REGS || CLASS == MUL_REGS)? \ | |
| 396 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD): \ | |
| 397 1 \ | |
| 398 ) | |
| 399 | |
| 400 | |
| 401 /* Stack layout; function entry, exit and calling. */ | |
| 402 | |
| 403 /* Define this if pushing a word on the stack | |
| 404 makes the stack pointer a smaller address. */ | |
| 405 #define STACK_GROWS_DOWNWARD | |
| 406 | |
| 407 /* Define this to nonzero if the nominal address of the stack frame | |
| 408 is at the high-address end of the local variables; | |
| 409 that is, each additional local variable allocated | |
| 410 goes at a more negative offset in the frame. | |
| 411 */ | |
| 412 #define FRAME_GROWS_DOWNWARD 1 | |
| 413 | |
| 414 /* Offset within stack frame to start allocating local variables at. | |
| 415 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
| 416 first local allocated. Otherwise, it is the offset to the BEGINNING | |
| 417 of the first local allocated. */ | |
| 418 #define STARTING_FRAME_OFFSET 0 | |
| 419 | |
| 420 /* If we generate an insn to push BYTES bytes, | |
| 421 this says how many the stack pointer really advances by. | |
| 422 On the pdp11, the stack is on an even boundary */ | |
| 423 #define PUSH_ROUNDING(BYTES) ((BYTES + 1) & ~1) | |
| 424 | |
| 425 /* current_first_parm_offset stores the # of registers pushed on the | |
| 426 stack */ | |
| 427 extern int current_first_parm_offset; | |
| 428 | |
| 429 /* Offset of first parameter from the argument pointer register value. | |
| 430 For the pdp11, this is nonzero to account for the return address. | |
| 431 1 - return address | |
| 432 2 - frame pointer (always saved, even when not used!!!!) | |
| 433 -- change some day !!!:q! | |
| 434 | |
| 435 */ | |
| 436 #define FIRST_PARM_OFFSET(FNDECL) 4 | |
| 437 | |
| 438 /* Value is 1 if returning from a function call automatically | |
| 439 pops the arguments described by the number-of-args field in the call. | |
| 440 FUNDECL is the declaration node of the function (as a tree), | |
| 441 FUNTYPE is the data type of the function (as a tree), | |
| 442 or for a library call it is an identifier node for the subroutine name. */ | |
| 443 | |
| 444 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 | |
| 445 | |
| 446 /* Define how to find the value returned by a function. | |
| 447 VALTYPE is the data type of the value (as a tree). | |
| 448 If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
| 449 otherwise, FUNC is 0. */ | |
| 450 #define BASE_RETURN_VALUE_REG(MODE) \ | |
| 451 ((MODE) == DFmode ? 8 : 0) | |
| 452 | |
| 453 /* On the pdp11 the value is found in R0 (or ac0??? | |
| 454 not without FPU!!!! ) */ | |
| 455 | |
| 456 #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
| 457 gen_rtx_REG (TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG(TYPE_MODE(VALTYPE))) | |
| 458 | |
| 459 /* and the called function leaves it in the first register. | |
| 460 Difference only on machines with register windows. */ | |
| 461 | |
| 462 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ | |
| 463 gen_rtx_REG (TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG(TYPE_MODE(VALTYPE))) | |
| 464 | |
| 465 /* Define how to find the value returned by a library function | |
| 466 assuming the value has mode MODE. */ | |
| 467 | |
| 468 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, BASE_RETURN_VALUE_REG(MODE)) | |
| 469 | |
| 470 /* 1 if N is a possible register number for a function value | |
| 471 as seen by the caller. | |
| 472 On the pdp, the first "output" reg is the only register thus used. | |
| 473 | |
| 474 maybe ac0 ? - as option someday! */ | |
| 475 | |
| 476 #define FUNCTION_VALUE_REGNO_P(N) (((N) == 0) || (TARGET_AC0 && (N) == 8)) | |
| 477 | |
| 478 /* 1 if N is a possible register number for function argument passing. | |
| 479 - not used on pdp */ | |
| 480 | |
| 481 #define FUNCTION_ARG_REGNO_P(N) 0 | |
| 482 | |
| 483 /* Define a data type for recording info about an argument list | |
| 484 during the scan of that argument list. This data type should | |
| 485 hold all necessary information about the function itself | |
| 486 and about the args processed so far, enough to enable macros | |
| 487 such as FUNCTION_ARG to determine where the next arg should go. | |
| 488 | |
| 489 */ | |
| 490 | |
| 491 #define CUMULATIVE_ARGS int | |
| 492 | |
| 493 /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
| 494 for a call to a function whose data type is FNTYPE. | |
| 495 For a library call, FNTYPE is 0. | |
| 496 | |
| 497 ...., the offset normally starts at 0, but starts at 1 word | |
| 498 when the function gets a structure-value-address as an | |
| 499 invisible first argument. */ | |
| 500 | |
| 501 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ | |
| 502 ((CUM) = 0) | |
| 503 | |
| 504 /* Update the data in CUM to advance over an argument | |
| 505 of mode MODE and data type TYPE. | |
| 506 (TYPE is null for libcalls where that information may not be available.) | |
| 507 | |
| 508 */ | |
| 509 | |
| 510 | |
| 511 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
| 512 ((CUM) += ((MODE) != BLKmode \ | |
| 513 ? (GET_MODE_SIZE (MODE)) \ | |
| 514 : (int_size_in_bytes (TYPE)))) | |
| 515 | |
| 516 /* Determine where to put an argument to a function. | |
| 517 Value is zero to push the argument on the stack, | |
| 518 or a hard register in which to store the argument. | |
| 519 | |
| 520 MODE is the argument's machine mode. | |
| 521 TYPE is the data type of the argument (as a tree). | |
| 522 This is null for libcalls where that information may | |
| 523 not be available. | |
| 524 CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
| 525 the preceding args and about the function being called. | |
| 526 NAMED is nonzero if this argument is a named parameter | |
| 527 (otherwise it is an extra parameter matching an ellipsis). */ | |
| 528 | |
| 529 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0 | |
| 530 | |
| 531 /* Define where a function finds its arguments. | |
| 532 This would be different from FUNCTION_ARG if we had register windows. */ | |
| 533 /* | |
| 534 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ | |
| 535 FUNCTION_ARG (CUM, MODE, TYPE, NAMED) | |
| 536 */ | |
| 537 | |
| 538 /* Output assembler code to FILE to increment profiler label # LABELNO | |
| 539 for profiling a function entry. */ | |
| 540 | |
| 541 #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
| 542 gcc_unreachable (); | |
| 543 | |
| 544 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
| 545 the stack pointer does not matter. The value is tested only in | |
| 546 functions that have frame pointers. | |
| 547 No definition is equivalent to always zero. */ | |
| 548 | |
| 549 extern int may_call_alloca; | |
| 550 | |
| 551 #define EXIT_IGNORE_STACK 1 | |
| 552 | |
| 553 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR) \ | |
| 554 { \ | |
| 555 int offset, regno; \ | |
| 556 offset = get_frame_size(); \ | |
| 557 for (regno = 0; regno < 8; regno++) \ | |
| 558 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) \ | |
| 559 offset += 2; \ | |
| 560 for (regno = 8; regno < 14; regno++) \ | |
| 561 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) \ | |
| 562 offset += 8; \ | |
| 563 /* offset -= 2; no fp on stack frame */ \ | |
| 564 (DEPTH_VAR) = offset; \ | |
| 565 } | |
| 566 | |
| 567 | |
| 568 /* Addressing modes, and classification of registers for them. */ | |
| 569 | |
| 570 #define HAVE_POST_INCREMENT 1 | |
| 571 | |
| 572 #define HAVE_PRE_DECREMENT 1 | |
| 573 | |
| 574 /* Macros to check register numbers against specific register classes. */ | |
| 575 | |
| 576 /* These assume that REGNO is a hard or pseudo reg number. | |
| 577 They give nonzero only if REGNO is a hard reg of the suitable class | |
| 578 or a pseudo reg currently allocated to a suitable hard reg. | |
| 579 Since they use reg_renumber, they are safe only once reg_renumber | |
| 580 has been allocated, which happens in local-alloc.c. */ | |
| 581 | |
| 582 #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
| 583 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) | |
| 584 #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
| 585 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) | |
| 586 | |
| 587 /* Now macros that check whether X is a register and also, | |
| 588 strictly, whether it is in a specified class. | |
| 589 */ | |
| 590 | |
| 591 | |
| 592 | |
| 593 /* Maximum number of registers that can appear in a valid memory address. */ | |
| 594 | |
| 595 #define MAX_REGS_PER_ADDRESS 1 | |
| 596 | |
| 597 /* Nonzero if the constant value X is a legitimate general operand. | |
| 598 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
| 599 | |
| 600 #define LEGITIMATE_CONSTANT_P(X) \ | |
| 601 (GET_CODE (X) != CONST_DOUBLE || legitimate_const_double_p (X)) | |
| 602 | |
| 603 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
| 604 and check its validity for a certain class. | |
| 605 We have two alternate definitions for each of them. | |
| 606 The usual definition accepts all pseudo regs; the other rejects | |
| 607 them unless they have been allocated suitable hard regs. | |
| 608 The symbol REG_OK_STRICT causes the latter definition to be used. | |
| 609 | |
| 610 Most source files want to accept pseudo regs in the hope that | |
| 611 they will get allocated to the class that the insn wants them to be in. | |
| 612 Source files for reload pass need to be strict. | |
| 613 After reload, it makes no difference, since pseudo regs have | |
| 614 been eliminated by then. */ | |
| 615 | |
| 616 #ifndef REG_OK_STRICT | |
| 617 | |
| 618 /* Nonzero if X is a hard reg that can be used as an index | |
| 619 or if it is a pseudo reg. */ | |
| 620 #define REG_OK_FOR_INDEX_P(X) (1) | |
| 621 /* Nonzero if X is a hard reg that can be used as a base reg | |
| 622 or if it is a pseudo reg. */ | |
| 623 #define REG_OK_FOR_BASE_P(X) (1) | |
| 624 | |
| 625 #else | |
| 626 | |
| 627 /* Nonzero if X is a hard reg that can be used as an index. */ | |
| 628 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
| 629 /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
| 630 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
| 631 | |
| 632 #endif | |
| 633 | |
| 634 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
| 635 that is a valid memory address for an instruction. | |
| 636 The MODE argument is the machine mode for the MEM expression | |
| 637 that wants to use this address. | |
| 638 | |
| 639 */ | |
| 640 | |
| 641 #define GO_IF_LEGITIMATE_ADDRESS(mode, operand, ADDR) \ | |
| 642 { \ | |
| 643 rtx xfoob; \ | |
| 644 \ | |
| 645 /* accept (R0) */ \ | |
| 646 if (GET_CODE (operand) == REG \ | |
| 647 && REG_OK_FOR_BASE_P(operand)) \ | |
| 648 goto ADDR; \ | |
| 649 \ | |
| 650 /* accept @#address */ \ | |
| 651 if (CONSTANT_ADDRESS_P (operand)) \ | |
| 652 goto ADDR; \ | |
| 653 \ | |
| 654 /* accept X(R0) */ \ | |
| 655 if (GET_CODE (operand) == PLUS \ | |
| 656 && GET_CODE (XEXP (operand, 0)) == REG \ | |
| 657 && REG_OK_FOR_BASE_P (XEXP (operand, 0)) \ | |
| 658 && CONSTANT_ADDRESS_P (XEXP (operand, 1))) \ | |
| 659 goto ADDR; \ | |
| 660 \ | |
| 661 /* accept -(R0) */ \ | |
| 662 if (GET_CODE (operand) == PRE_DEC \ | |
| 663 && GET_CODE (XEXP (operand, 0)) == REG \ | |
| 664 && REG_OK_FOR_BASE_P (XEXP (operand, 0))) \ | |
| 665 goto ADDR; \ | |
| 666 \ | |
| 667 /* accept (R0)+ */ \ | |
| 668 if (GET_CODE (operand) == POST_INC \ | |
| 669 && GET_CODE (XEXP (operand, 0)) == REG \ | |
| 670 && REG_OK_FOR_BASE_P (XEXP (operand, 0))) \ | |
| 671 goto ADDR; \ | |
| 672 \ | |
| 673 /* accept -(SP) -- which uses PRE_MODIFY for byte mode */ \ | |
| 674 if (GET_CODE (operand) == PRE_MODIFY \ | |
| 675 && GET_CODE (XEXP (operand, 0)) == REG \ | |
| 676 && REGNO (XEXP (operand, 0)) == 6 \ | |
| 677 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS \ | |
| 678 && GET_CODE (XEXP (xfoob, 0)) == REG \ | |
| 679 && REGNO (XEXP (xfoob, 0)) == 6 \ | |
| 680 && CONSTANT_P (XEXP (xfoob, 1)) \ | |
| 681 && INTVAL (XEXP (xfoob,1)) == -2) \ | |
| 682 goto ADDR; \ | |
| 683 \ | |
| 684 /* accept (SP)+ -- which uses POST_MODIFY for byte mode */ \ | |
| 685 if (GET_CODE (operand) == POST_MODIFY \ | |
| 686 && GET_CODE (XEXP (operand, 0)) == REG \ | |
| 687 && REGNO (XEXP (operand, 0)) == 6 \ | |
| 688 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS \ | |
| 689 && GET_CODE (XEXP (xfoob, 0)) == REG \ | |
| 690 && REGNO (XEXP (xfoob, 0)) == 6 \ | |
| 691 && CONSTANT_P (XEXP (xfoob, 1)) \ | |
| 692 && INTVAL (XEXP (xfoob,1)) == 2) \ | |
| 693 goto ADDR; \ | |
| 694 \ | |
| 695 \ | |
| 696 /* handle another level of indirection ! */ \ | |
| 697 if (GET_CODE(operand) != MEM) \ | |
| 698 goto fail; \ | |
| 699 \ | |
| 700 xfoob = XEXP (operand, 0); \ | |
| 701 \ | |
| 702 /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently */ \ | |
| 703 /* also forbidden for float, because we have to handle this */ \ | |
| 704 /* in output_move_double and/or output_move_quad() - we could */ \ | |
| 705 /* do it, but currently it's not worth it!!! */ \ | |
| 706 /* now that DFmode cannot go into CPU register file, */ \ | |
| 707 /* maybe I should allow float ... */ \ | |
| 708 /* but then I have to handle memory-to-memory moves in movdf ?? */ \ | |
| 709 \ | |
| 710 if (GET_MODE_BITSIZE(mode) > 16) \ | |
| 711 goto fail; \ | |
| 712 \ | |
| 713 /* accept @(R0) - which is @0(R0) */ \ | |
| 714 if (GET_CODE (xfoob) == REG \ | |
| 715 && REG_OK_FOR_BASE_P(xfoob)) \ | |
| 716 goto ADDR; \ | |
| 717 \ | |
| 718 /* accept @address */ \ | |
| 719 if (CONSTANT_ADDRESS_P (xfoob)) \ | |
| 720 goto ADDR; \ | |
| 721 \ | |
| 722 /* accept @X(R0) */ \ | |
| 723 if (GET_CODE (xfoob) == PLUS \ | |
| 724 && GET_CODE (XEXP (xfoob, 0)) == REG \ | |
| 725 && REG_OK_FOR_BASE_P (XEXP (xfoob, 0)) \ | |
| 726 && CONSTANT_ADDRESS_P (XEXP (xfoob, 1))) \ | |
| 727 goto ADDR; \ | |
| 728 \ | |
| 729 /* accept @-(R0) */ \ | |
| 730 if (GET_CODE (xfoob) == PRE_DEC \ | |
| 731 && GET_CODE (XEXP (xfoob, 0)) == REG \ | |
| 732 && REG_OK_FOR_BASE_P (XEXP (xfoob, 0))) \ | |
| 733 goto ADDR; \ | |
| 734 \ | |
| 735 /* accept @(R0)+ */ \ | |
| 736 if (GET_CODE (xfoob) == POST_INC \ | |
| 737 && GET_CODE (XEXP (xfoob, 0)) == REG \ | |
| 738 && REG_OK_FOR_BASE_P (XEXP (xfoob, 0))) \ | |
| 739 goto ADDR; \ | |
| 740 \ | |
| 741 /* anything else is invalid */ \ | |
| 742 fail: ; \ | |
| 743 } | |
| 744 | |
| 745 | |
| 746 /* Specify the machine mode that this machine uses | |
| 747 for the index in the tablejump instruction. */ | |
| 748 #define CASE_VECTOR_MODE HImode | |
| 749 | |
| 750 /* Define this if a raw index is all that is needed for a | |
| 751 `tablejump' insn. */ | |
| 752 #define CASE_TAKES_INDEX_RAW | |
| 753 | |
| 754 /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
| 755 #define DEFAULT_SIGNED_CHAR 1 | |
| 756 | |
| 757 /* Max number of bytes we can move from memory to memory | |
| 758 in one reasonably fast instruction. | |
| 759 */ | |
| 760 | |
| 761 #define MOVE_MAX 2 | |
| 762 | |
| 763 /* Nonzero if access to memory by byte is slow and undesirable. - | |
| 764 */ | |
| 765 #define SLOW_BYTE_ACCESS 0 | |
| 766 | |
| 767 /* Do not break .stabs pseudos into continuations. */ | |
| 768 #define DBX_CONTIN_LENGTH 0 | |
| 769 | |
| 770 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
| 771 is done just by pretending it is already truncated. */ | |
| 772 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
| 773 | |
| 774 /* Give a comparison code (EQ, NE etc) and the first operand of a COMPARE, | |
| 775 return the mode to be used for the comparison. For floating-point, CCFPmode | |
| 776 should be used. */ | |
| 777 | |
| 778 #define SELECT_CC_MODE(OP,X,Y) \ | |
| 779 (GET_MODE_CLASS(GET_MODE(X)) == MODE_FLOAT? CCFPmode : CCmode) | |
| 780 | |
| 781 /* Specify the machine mode that pointers have. | |
| 782 After generation of rtl, the compiler makes no further distinction | |
| 783 between pointers and any other objects of this machine mode. */ | |
| 784 #define Pmode HImode | |
| 785 | |
| 786 /* A function address in a call instruction | |
| 787 is a word address (for indexing purposes) | |
| 788 so give the MEM rtx a word's mode. */ | |
| 789 #define FUNCTION_MODE HImode | |
| 790 | |
| 791 /* Define this if addresses of constant functions | |
| 792 shouldn't be put through pseudo regs where they can be cse'd. | |
| 793 Desirable on machines where ordinary constants are expensive | |
| 794 but a CALL with constant address is cheap. */ | |
| 795 /* #define NO_FUNCTION_CSE */ | |
| 796 | |
| 797 | |
| 798 /* cost of moving one register class to another */ | |
| 799 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ | |
| 800 register_move_cost (CLASS1, CLASS2) | |
| 801 | |
| 802 /* Tell emit-rtl.c how to initialize special values on a per-function base. */ | |
| 803 extern int optimize; | |
| 804 extern struct rtx_def *cc0_reg_rtx; | |
| 805 | |
| 806 #define CC_STATUS_MDEP rtx | |
| 807 | |
| 808 #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0) | |
| 809 | |
| 810 /* Tell final.c how to eliminate redundant test instructions. */ | |
| 811 | |
| 812 /* Here we define machine-dependent flags and fields in cc_status | |
| 813 (see `conditions.h'). */ | |
| 814 | |
| 815 #define CC_IN_FPU 04000 | |
| 816 | |
| 817 /* Do UPDATE_CC if EXP is a set, used in | |
| 818 NOTICE_UPDATE_CC | |
| 819 | |
| 820 floats only do compare correctly, else nullify ... | |
| 821 | |
| 822 get cc0 out soon ... | |
| 823 */ | |
| 824 | |
| 825 /* Store in cc_status the expressions | |
| 826 that the condition codes will describe | |
| 827 after execution of an instruction whose pattern is EXP. | |
| 828 Do not alter them if the instruction would not alter the cc's. */ | |
| 829 | |
| 830 #define NOTICE_UPDATE_CC(EXP, INSN) \ | |
| 831 { if (GET_CODE (EXP) == SET) \ | |
| 832 { \ | |
| 833 notice_update_cc_on_set(EXP, INSN); \ | |
| 834 } \ | |
| 835 else if (GET_CODE (EXP) == PARALLEL \ | |
| 836 && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \ | |
| 837 { \ | |
| 838 notice_update_cc_on_set(XVECEXP (EXP, 0, 0), INSN); \ | |
| 839 } \ | |
| 840 else if (GET_CODE (EXP) == CALL) \ | |
| 841 { /* all bets are off */ CC_STATUS_INIT; } \ | |
| 842 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \ | |
| 843 && cc_status.value2 \ | |
| 844 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \ | |
| 845 { \ | |
| 846 printf ("here!\n"); \ | |
| 847 cc_status.value2 = 0; \ | |
| 848 } \ | |
| 849 } | |
| 850 | |
| 851 /* Control the assembler format that we output. */ | |
| 852 | |
| 853 /* Output to assembler file text saying following lines | |
| 854 may contain character constants, extra white space, comments, etc. */ | |
| 855 | |
| 856 #define ASM_APP_ON "" | |
| 857 | |
| 858 /* Output to assembler file text saying following lines | |
| 859 no longer contain unusual constructs. */ | |
| 860 | |
| 861 #define ASM_APP_OFF "" | |
| 862 | |
| 863 /* Output before read-only data. */ | |
| 864 | |
| 865 #define TEXT_SECTION_ASM_OP "\t.text\n" | |
| 866 | |
| 867 /* Output before writable data. */ | |
| 868 | |
| 869 #define DATA_SECTION_ASM_OP "\t.data\n" | |
| 870 | |
| 871 /* How to refer to registers in assembler output. | |
| 872 This sequence is indexed by compiler's hard-register-number (see above). */ | |
| 873 | |
| 874 #define REGISTER_NAMES \ | |
| 875 {"r0", "r1", "r2", "r3", "r4", "r5", "sp", "pc", \ | |
| 876 "ac0", "ac1", "ac2", "ac3", "ac4", "ac5" } | |
| 877 | |
| 878 /* Globalizing directive for a label. */ | |
| 879 #define GLOBAL_ASM_OP "\t.globl " | |
| 880 | |
| 881 /* The prefix to add to user-visible assembler symbols. */ | |
| 882 | |
| 883 #define USER_LABEL_PREFIX "_" | |
| 884 | |
| 885 /* This is how to store into the string LABEL | |
| 886 the symbol_ref name of an internal numbered label where | |
| 887 PREFIX is the class of label and NUM is the number within the class. | |
| 888 This is suitable for output with `assemble_name'. */ | |
| 889 | |
| 890 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
| 891 sprintf (LABEL, "*%s_%lu", PREFIX, (unsigned long)(NUM)) | |
| 892 | |
| 893 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \ | |
| 894 output_ascii (FILE, P, SIZE) | |
| 895 | |
| 896 /* This is how to output an element of a case-vector that is absolute. */ | |
| 897 | |
| 898 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
| 899 fprintf (FILE, "\t%sL_%d\n", TARGET_UNIX_ASM ? "" : ".word ", VALUE) | |
| 900 | |
| 901 /* This is how to output an element of a case-vector that is relative. | |
| 902 Don't define this if it is not supported. */ | |
| 903 | |
| 904 /* #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) */ | |
| 905 | |
| 906 /* This is how to output an assembler line | |
| 907 that says to advance the location counter | |
| 908 to a multiple of 2**LOG bytes. | |
| 909 | |
| 910 who needs this???? | |
| 911 */ | |
| 912 | |
| 913 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
| 914 switch (LOG) \ | |
| 915 { \ | |
| 916 case 0: \ | |
| 917 break; \ | |
| 918 case 1: \ | |
| 919 fprintf (FILE, "\t.even\n"); \ | |
| 920 break; \ | |
| 921 default: \ | |
| 922 gcc_unreachable (); \ | |
| 923 } | |
| 924 | |
| 925 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
| 926 fprintf (FILE, "\t.=.+ %#ho\n", (unsigned short)(SIZE)) | |
| 927 | |
| 928 /* This says how to output an assembler line | |
| 929 to define a global common symbol. */ | |
| 930 | |
| 931 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
| 932 ( fprintf ((FILE), ".globl "), \ | |
| 933 assemble_name ((FILE), (NAME)), \ | |
| 934 fprintf ((FILE), "\n"), \ | |
| 935 assemble_name ((FILE), (NAME)), \ | |
| 936 fprintf ((FILE), ": .=.+ %#ho\n", (unsigned short)(ROUNDED)) \ | |
| 937 ) | |
| 938 | |
| 939 /* This says how to output an assembler line | |
| 940 to define a local common symbol. */ | |
| 941 | |
| 942 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ | |
| 943 ( assemble_name ((FILE), (NAME)), \ | |
| 944 fprintf ((FILE), ":\t.=.+ %#ho\n", (unsigned short)(ROUNDED))) | |
| 945 | |
| 946 /* Print operand X (an rtx) in assembler syntax to file FILE. | |
| 947 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
| 948 For `%' followed by punctuation, CODE is the punctuation and X is null. | |
| 949 | |
| 950 */ | |
| 951 | |
| 952 | |
| 953 #define PRINT_OPERAND(FILE, X, CODE) \ | |
| 954 { if (CODE == '#') fprintf (FILE, "#"); \ | |
| 955 else if (GET_CODE (X) == REG) \ | |
| 956 fprintf (FILE, "%s", reg_names[REGNO (X)]); \ | |
| 957 else if (GET_CODE (X) == MEM) \ | |
| 958 output_address (XEXP (X, 0)); \ | |
| 959 else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != SImode) \ | |
| 960 { REAL_VALUE_TYPE r; \ | |
| 961 long sval[2]; \ | |
| 962 REAL_VALUE_FROM_CONST_DOUBLE (r, X); \ | |
| 963 REAL_VALUE_TO_TARGET_DOUBLE (r, sval); \ | |
| 964 fprintf (FILE, "$%#lo", sval[0] >> 16); } \ | |
| 965 else { putc ('$', FILE); output_addr_const_pdp11 (FILE, X); }} | |
| 966 | |
| 967 /* Print a memory address as an operand to reference that memory location. */ | |
| 968 | |
| 969 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
| 970 print_operand_address (FILE, ADDR) | |
| 971 | |
| 972 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ | |
| 973 ( \ | |
| 974 fprintf (FILE, "\tmov %s, -(sp)\n", reg_names[REGNO]) \ | |
| 975 ) | |
| 976 | |
| 977 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
| 978 ( \ | |
| 979 fprintf (FILE, "\tmov (sp)+, %s\n", reg_names[REGNO]) \ | |
| 980 ) | |
| 981 | |
| 982 #define TRAMPOLINE_SIZE 8 | |
| 983 #define TRAMPOLINE_ALIGNMENT 16 | |
| 984 | |
| 985 /* Some machines may desire to change what optimizations are | |
| 986 performed for various optimization levels. This macro, if | |
| 987 defined, is executed once just after the optimization level is | |
| 988 determined and before the remainder of the command options have | |
| 989 been parsed. Values set in this macro are used as the default | |
| 990 values for the other command line options. | |
| 991 | |
| 992 LEVEL is the optimization level specified; 2 if -O2 is | |
| 993 specified, 1 if -O is specified, and 0 if neither is specified. */ | |
| 994 | |
| 995 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ | |
| 996 { \ | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
997 flag_finite_math_only = 0; \ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
998 flag_trapping_math = 0; \ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
999 flag_signaling_nans = 0; \ |
| 0 | 1000 if (LEVEL >= 3) \ |
| 1001 { \ | |
| 1002 flag_omit_frame_pointer = 1; \ | |
| 1003 /* flag_unroll_loops = 1; */ \ | |
| 1004 } \ | |
| 1005 } | |
| 1006 | |
| 1007 /* there is no point in avoiding branches on a pdp, | |
| 1008 since branches are really cheap - I just want to find out | |
| 1009 how much difference the BRANCH_COST macro makes in code */ | |
| 1010 #define BRANCH_COST(speed_p, predictable_p) (TARGET_BRANCH_CHEAP ? 0 : 1) | |
| 1011 | |
| 1012 | |
| 1013 #define COMPARE_FLAG_MODE HImode |