Mercurial > hg > CbC > CbC_gcc
annotate gcc/reginfo.c @ 132:d34655255c78
update gcc-8.2
| author | mir3636 |
|---|---|
| date | Thu, 25 Oct 2018 10:21:07 +0900 |
| parents | 84e7813d76e9 |
| children | 1830386684a0 |
| rev | line source |
|---|---|
| 0 | 1 /* Compute different info about registers. |
| 131 | 2 Copyright (C) 1987-2018 Free Software Foundation, Inc. |
| 0 | 3 |
| 4 This file is part of GCC. | |
| 5 | |
| 6 GCC is free software; you can redistribute it and/or modify it under | |
| 7 the terms of the GNU General Public License as published by the Free | |
| 8 Software Foundation; either version 3, or (at your option) any later | |
| 9 version. | |
| 10 | |
| 11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 12 WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 14 for more details. | |
| 15 | |
| 16 You should have received a copy of the GNU General Public License | |
| 17 along with GCC; see the file COPYING3. If not see | |
| 18 <http://www.gnu.org/licenses/>. */ | |
| 19 | |
| 20 | |
| 21 /* This file contains regscan pass of the compiler and passes for | |
| 22 dealing with info about modes of pseudo-registers inside | |
| 23 subregisters. It also defines some tables of information about the | |
| 24 hardware registers, function init_reg_sets to initialize the | |
| 25 tables, and other auxiliary functions to deal with info about | |
| 26 registers and their classes. */ | |
| 27 | |
| 28 #include "config.h" | |
| 29 #include "system.h" | |
| 30 #include "coretypes.h" | |
| 111 | 31 #include "backend.h" |
| 32 #include "target.h" | |
| 0 | 33 #include "rtl.h" |
| 111 | 34 #include "tree.h" |
| 35 #include "df.h" | |
| 36 #include "memmodel.h" | |
| 0 | 37 #include "tm_p.h" |
| 38 #include "insn-config.h" | |
| 111 | 39 #include "regs.h" |
| 40 #include "ira.h" | |
| 0 | 41 #include "recog.h" |
| 111 | 42 #include "diagnostic-core.h" |
| 0 | 43 #include "reload.h" |
| 44 #include "output.h" | |
| 45 #include "tree-pass.h" | |
| 46 | |
| 47 /* Maximum register number used in this function, plus one. */ | |
| 48 | |
| 49 int max_regno; | |
| 50 | |
| 111 | 51 /* Used to cache the results of simplifiable_subregs. SHAPE is the input |
| 52 parameter and SIMPLIFIABLE_REGS is the result. */ | |
| 53 struct simplifiable_subreg | |
| 54 { | |
| 55 simplifiable_subreg (const subreg_shape &); | |
| 56 | |
| 57 subreg_shape shape; | |
| 58 HARD_REG_SET simplifiable_regs; | |
| 59 }; | |
| 0 | 60 |
|
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61 struct target_hard_regs default_target_hard_regs; |
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62 struct target_regs default_target_regs; |
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63 #if SWITCHABLE_TARGET |
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64 struct target_hard_regs *this_target_hard_regs = &default_target_hard_regs; |
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65 struct target_regs *this_target_regs = &default_target_regs; |
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66 #endif |
| 0 | 67 |
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68 /* Data for initializing fixed_regs. */ |
| 0 | 69 static const char initial_fixed_regs[] = FIXED_REGISTERS; |
| 70 | |
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71 /* Data for initializing call_used_regs. */ |
| 0 | 72 static const char initial_call_used_regs[] = CALL_USED_REGISTERS; |
| 73 | |
| 74 #ifdef CALL_REALLY_USED_REGISTERS | |
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75 /* Data for initializing call_really_used_regs. */ |
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76 static const char initial_call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; |
| 0 | 77 #endif |
| 78 | |
| 79 #ifdef CALL_REALLY_USED_REGISTERS | |
| 80 #define CALL_REALLY_USED_REGNO_P(X) call_really_used_regs[X] | |
| 81 #else | |
| 82 #define CALL_REALLY_USED_REGNO_P(X) call_used_regs[X] | |
| 83 #endif | |
| 84 | |
| 85 /* Indexed by hard register number, contains 1 for registers | |
| 86 that are being used for global register decls. | |
| 87 These must be exempt from ordinary flow analysis | |
| 88 and are also considered fixed. */ | |
| 89 char global_regs[FIRST_PSEUDO_REGISTER]; | |
| 90 | |
| 111 | 91 /* Declaration for the global register. */ |
| 92 tree global_regs_decl[FIRST_PSEUDO_REGISTER]; | |
| 93 | |
| 0 | 94 /* Same information as REGS_INVALIDATED_BY_CALL but in regset form to be used |
| 95 in dataflow more conveniently. */ | |
| 96 regset regs_invalidated_by_call_regset; | |
| 97 | |
| 111 | 98 /* Same information as FIXED_REG_SET but in regset form. */ |
| 99 regset fixed_reg_set_regset; | |
| 100 | |
| 0 | 101 /* The bitmap_obstack is used to hold some static variables that |
| 102 should not be reset after each function is compiled. */ | |
| 103 static bitmap_obstack persistent_obstack; | |
| 104 | |
|
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105 /* Used to initialize reg_alloc_order. */ |
| 0 | 106 #ifdef REG_ALLOC_ORDER |
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107 static int initial_reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; |
| 0 | 108 #endif |
| 109 | |
| 110 /* The same information, but as an array of unsigned ints. We copy from | |
| 111 these unsigned ints to the table above. We do this so the tm.h files | |
| 112 do not have to be aware of the wordsize for machines with <= 64 regs. | |
| 113 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ | |
| 114 #define N_REG_INTS \ | |
| 115 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32) | |
| 116 | |
| 117 static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] | |
| 118 = REG_CLASS_CONTENTS; | |
| 119 | |
| 120 /* Array containing all of the register names. */ | |
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121 static const char *const initial_reg_names[] = REGISTER_NAMES; |
| 0 | 122 |
| 123 /* Array containing all of the register class names. */ | |
| 124 const char * reg_class_names[] = REG_CLASS_NAMES; | |
| 125 | |
| 126 /* No more global register variables may be declared; true once | |
| 127 reginfo has been initialized. */ | |
| 128 static int no_global_reg_vars = 0; | |
| 129 | |
| 130 /* Given a register bitmap, turn on the bits in a HARD_REG_SET that | |
| 131 correspond to the hard registers, if any, set in that map. This | |
| 132 could be done far more efficiently by having all sorts of special-cases | |
| 133 with moving single words, but probably isn't worth the trouble. */ | |
| 134 void | |
| 135 reg_set_to_hard_reg_set (HARD_REG_SET *to, const_bitmap from) | |
| 136 { | |
| 137 unsigned i; | |
| 138 bitmap_iterator bi; | |
| 139 | |
| 140 EXECUTE_IF_SET_IN_BITMAP (from, 0, i, bi) | |
| 141 { | |
| 142 if (i >= FIRST_PSEUDO_REGISTER) | |
| 143 return; | |
| 144 SET_HARD_REG_BIT (*to, i); | |
| 145 } | |
| 146 } | |
| 147 | |
|
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148 /* Function called only once per target_globals to initialize the |
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149 target_hard_regs structure. Once this is done, various switches |
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150 may override. */ |
| 0 | 151 void |
| 152 init_reg_sets (void) | |
| 153 { | |
| 154 int i, j; | |
| 155 | |
| 156 /* First copy the register information from the initial int form into | |
| 157 the regsets. */ | |
| 158 | |
| 159 for (i = 0; i < N_REG_CLASSES; i++) | |
| 160 { | |
| 161 CLEAR_HARD_REG_SET (reg_class_contents[i]); | |
| 162 | |
| 163 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ | |
| 164 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
| 165 if (int_reg_class_contents[i][j / 32] | |
| 166 & ((unsigned) 1 << (j % 32))) | |
| 167 SET_HARD_REG_BIT (reg_class_contents[i], j); | |
| 168 } | |
| 169 | |
| 170 /* Sanity check: make sure the target macros FIXED_REGISTERS and | |
| 171 CALL_USED_REGISTERS had the right number of initializers. */ | |
| 172 gcc_assert (sizeof fixed_regs == sizeof initial_fixed_regs); | |
| 173 gcc_assert (sizeof call_used_regs == sizeof initial_call_used_regs); | |
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174 #ifdef CALL_REALLY_USED_REGISTERS |
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175 gcc_assert (sizeof call_really_used_regs |
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176 == sizeof initial_call_really_used_regs); |
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177 #endif |
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178 #ifdef REG_ALLOC_ORDER |
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179 gcc_assert (sizeof reg_alloc_order == sizeof initial_reg_alloc_order); |
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180 #endif |
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181 gcc_assert (sizeof reg_names == sizeof initial_reg_names); |
| 0 | 182 |
| 183 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs); | |
| 184 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs); | |
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185 #ifdef CALL_REALLY_USED_REGISTERS |
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186 memcpy (call_really_used_regs, initial_call_really_used_regs, |
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187 sizeof call_really_used_regs); |
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188 #endif |
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189 #ifdef REG_ALLOC_ORDER |
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190 memcpy (reg_alloc_order, initial_reg_alloc_order, sizeof reg_alloc_order); |
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191 #endif |
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192 memcpy (reg_names, initial_reg_names, sizeof reg_names); |
| 0 | 193 |
| 111 | 194 SET_HARD_REG_SET (accessible_reg_set); |
| 195 SET_HARD_REG_SET (operand_reg_set); | |
| 0 | 196 } |
| 197 | |
| 198 /* We need to save copies of some of the register information which | |
| 199 can be munged by command-line switches so we can restore it during | |
| 200 subsequent back-end reinitialization. */ | |
| 201 static char saved_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
| 202 static char saved_call_used_regs[FIRST_PSEUDO_REGISTER]; | |
| 203 #ifdef CALL_REALLY_USED_REGISTERS | |
| 204 static char saved_call_really_used_regs[FIRST_PSEUDO_REGISTER]; | |
| 205 #endif | |
| 206 static const char *saved_reg_names[FIRST_PSEUDO_REGISTER]; | |
| 111 | 207 static HARD_REG_SET saved_accessible_reg_set; |
| 208 static HARD_REG_SET saved_operand_reg_set; | |
| 0 | 209 |
| 210 /* Save the register information. */ | |
| 211 void | |
| 212 save_register_info (void) | |
| 213 { | |
| 214 /* Sanity check: make sure the target macros FIXED_REGISTERS and | |
| 215 CALL_USED_REGISTERS had the right number of initializers. */ | |
| 216 gcc_assert (sizeof fixed_regs == sizeof saved_fixed_regs); | |
| 217 gcc_assert (sizeof call_used_regs == sizeof saved_call_used_regs); | |
| 218 memcpy (saved_fixed_regs, fixed_regs, sizeof fixed_regs); | |
| 219 memcpy (saved_call_used_regs, call_used_regs, sizeof call_used_regs); | |
| 220 | |
| 221 /* Likewise for call_really_used_regs. */ | |
| 222 #ifdef CALL_REALLY_USED_REGISTERS | |
| 223 gcc_assert (sizeof call_really_used_regs | |
| 224 == sizeof saved_call_really_used_regs); | |
| 225 memcpy (saved_call_really_used_regs, call_really_used_regs, | |
| 226 sizeof call_really_used_regs); | |
| 227 #endif | |
| 228 | |
| 229 /* And similarly for reg_names. */ | |
| 230 gcc_assert (sizeof reg_names == sizeof saved_reg_names); | |
| 231 memcpy (saved_reg_names, reg_names, sizeof reg_names); | |
| 111 | 232 COPY_HARD_REG_SET (saved_accessible_reg_set, accessible_reg_set); |
| 233 COPY_HARD_REG_SET (saved_operand_reg_set, operand_reg_set); | |
| 0 | 234 } |
| 235 | |
| 236 /* Restore the register information. */ | |
| 237 static void | |
| 238 restore_register_info (void) | |
| 239 { | |
| 240 memcpy (fixed_regs, saved_fixed_regs, sizeof fixed_regs); | |
| 241 memcpy (call_used_regs, saved_call_used_regs, sizeof call_used_regs); | |
| 242 | |
| 243 #ifdef CALL_REALLY_USED_REGISTERS | |
| 244 memcpy (call_really_used_regs, saved_call_really_used_regs, | |
| 245 sizeof call_really_used_regs); | |
| 246 #endif | |
| 247 | |
| 248 memcpy (reg_names, saved_reg_names, sizeof reg_names); | |
| 111 | 249 COPY_HARD_REG_SET (accessible_reg_set, saved_accessible_reg_set); |
| 250 COPY_HARD_REG_SET (operand_reg_set, saved_operand_reg_set); | |
| 0 | 251 } |
| 252 | |
| 253 /* After switches have been processed, which perhaps alter | |
| 254 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
| 255 static void | |
| 256 init_reg_sets_1 (void) | |
| 257 { | |
| 258 unsigned int i, j; | |
| 111 | 259 unsigned int /* machine_mode */ m; |
| 0 | 260 |
| 261 restore_register_info (); | |
| 262 | |
| 263 #ifdef REG_ALLOC_ORDER | |
| 264 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
| 265 inv_reg_alloc_order[reg_alloc_order[i]] = i; | |
| 266 #endif | |
| 267 | |
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268 /* Let the target tweak things if necessary. */ |
| 0 | 269 |
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270 targetm.conditional_register_usage (); |
| 0 | 271 |
| 272 /* Compute number of hard regs in each class. */ | |
| 273 | |
| 274 memset (reg_class_size, 0, sizeof reg_class_size); | |
| 275 for (i = 0; i < N_REG_CLASSES; i++) | |
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276 { |
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277 bool any_nonfixed = false; |
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278 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
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279 if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) |
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280 { |
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281 reg_class_size[i]++; |
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282 if (!fixed_regs[j]) |
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283 any_nonfixed = true; |
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284 } |
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285 class_only_fixed_regs[i] = !any_nonfixed; |
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286 } |
| 0 | 287 |
| 288 /* Initialize the table of subunions. | |
| 289 reg_class_subunion[I][J] gets the largest-numbered reg-class | |
| 290 that is contained in the union of classes I and J. */ | |
| 291 | |
| 292 memset (reg_class_subunion, 0, sizeof reg_class_subunion); | |
| 293 for (i = 0; i < N_REG_CLASSES; i++) | |
| 294 { | |
| 295 for (j = 0; j < N_REG_CLASSES; j++) | |
| 296 { | |
| 297 HARD_REG_SET c; | |
| 298 int k; | |
| 299 | |
| 300 COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
| 301 IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
| 302 for (k = 0; k < N_REG_CLASSES; k++) | |
| 303 if (hard_reg_set_subset_p (reg_class_contents[k], c) | |
| 304 && !hard_reg_set_subset_p (reg_class_contents[k], | |
| 305 reg_class_contents | |
| 306 [(int) reg_class_subunion[i][j]])) | |
| 307 reg_class_subunion[i][j] = (enum reg_class) k; | |
| 308 } | |
| 309 } | |
| 310 | |
| 311 /* Initialize the table of superunions. | |
| 312 reg_class_superunion[I][J] gets the smallest-numbered reg-class | |
| 313 containing the union of classes I and J. */ | |
| 314 | |
| 315 memset (reg_class_superunion, 0, sizeof reg_class_superunion); | |
| 316 for (i = 0; i < N_REG_CLASSES; i++) | |
| 317 { | |
| 318 for (j = 0; j < N_REG_CLASSES; j++) | |
| 319 { | |
| 320 HARD_REG_SET c; | |
| 321 int k; | |
| 322 | |
| 323 COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
| 324 IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
| 325 for (k = 0; k < N_REG_CLASSES; k++) | |
| 326 if (hard_reg_set_subset_p (c, reg_class_contents[k])) | |
| 327 break; | |
| 328 | |
| 329 reg_class_superunion[i][j] = (enum reg_class) k; | |
| 330 } | |
| 331 } | |
| 332 | |
| 333 /* Initialize the tables of subclasses and superclasses of each reg class. | |
| 334 First clear the whole table, then add the elements as they are found. */ | |
| 335 | |
| 336 for (i = 0; i < N_REG_CLASSES; i++) | |
| 337 { | |
| 338 for (j = 0; j < N_REG_CLASSES; j++) | |
| 339 reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
| 340 } | |
| 341 | |
| 342 for (i = 0; i < N_REG_CLASSES; i++) | |
| 343 { | |
| 344 if (i == (int) NO_REGS) | |
| 345 continue; | |
| 346 | |
| 347 for (j = i + 1; j < N_REG_CLASSES; j++) | |
| 348 if (hard_reg_set_subset_p (reg_class_contents[i], | |
| 349 reg_class_contents[j])) | |
| 350 { | |
| 351 /* Reg class I is a subclass of J. | |
| 352 Add J to the table of superclasses of I. */ | |
| 353 enum reg_class *p; | |
| 354 | |
| 355 /* Add I to the table of superclasses of J. */ | |
| 356 p = ®_class_subclasses[j][0]; | |
| 357 while (*p != LIM_REG_CLASSES) p++; | |
| 358 *p = (enum reg_class) i; | |
| 359 } | |
| 360 } | |
| 361 | |
| 362 /* Initialize "constant" tables. */ | |
| 363 | |
| 364 CLEAR_HARD_REG_SET (fixed_reg_set); | |
| 365 CLEAR_HARD_REG_SET (call_used_reg_set); | |
| 366 CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
| 367 CLEAR_HARD_REG_SET (regs_invalidated_by_call); | |
| 368 if (!regs_invalidated_by_call_regset) | |
| 369 { | |
| 370 bitmap_obstack_initialize (&persistent_obstack); | |
| 371 regs_invalidated_by_call_regset = ALLOC_REG_SET (&persistent_obstack); | |
| 372 } | |
| 373 else | |
| 374 CLEAR_REG_SET (regs_invalidated_by_call_regset); | |
| 111 | 375 if (!fixed_reg_set_regset) |
| 376 fixed_reg_set_regset = ALLOC_REG_SET (&persistent_obstack); | |
| 377 else | |
| 378 CLEAR_REG_SET (fixed_reg_set_regset); | |
| 0 | 379 |
| 111 | 380 AND_HARD_REG_SET (operand_reg_set, accessible_reg_set); |
| 0 | 381 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
| 382 { | |
| 111 | 383 /* As a special exception, registers whose class is NO_REGS are |
| 384 not accepted by `register_operand'. The reason for this change | |
| 385 is to allow the representation of special architecture artifacts | |
| 386 (such as a condition code register) without extending the rtl | |
| 387 definitions. Since registers of class NO_REGS cannot be used | |
| 388 as registers in any case where register classes are examined, | |
| 389 it is better to apply this exception in a target-independent way. */ | |
| 390 if (REGNO_REG_CLASS (i) == NO_REGS) | |
| 391 CLEAR_HARD_REG_BIT (operand_reg_set, i); | |
| 392 | |
| 393 /* If a register is too limited to be treated as a register operand, | |
| 394 then it should never be allocated to a pseudo. */ | |
| 395 if (!TEST_HARD_REG_BIT (operand_reg_set, i)) | |
| 396 { | |
| 397 fixed_regs[i] = 1; | |
| 398 call_used_regs[i] = 1; | |
| 399 } | |
| 400 | |
| 0 | 401 /* call_used_regs must include fixed_regs. */ |
| 402 gcc_assert (!fixed_regs[i] || call_used_regs[i]); | |
| 403 #ifdef CALL_REALLY_USED_REGISTERS | |
| 404 /* call_used_regs must include call_really_used_regs. */ | |
| 405 gcc_assert (!call_really_used_regs[i] || call_used_regs[i]); | |
| 406 #endif | |
| 407 | |
| 408 if (fixed_regs[i]) | |
| 111 | 409 { |
| 410 SET_HARD_REG_BIT (fixed_reg_set, i); | |
| 411 SET_REGNO_REG_SET (fixed_reg_set_regset, i); | |
| 412 } | |
| 0 | 413 |
| 414 if (call_used_regs[i]) | |
| 415 SET_HARD_REG_BIT (call_used_reg_set, i); | |
| 416 | |
| 417 /* There are a couple of fixed registers that we know are safe to | |
| 418 exclude from being clobbered by calls: | |
| 419 | |
|
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420 The frame pointer is always preserved across calls. The arg |
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421 pointer is if it is fixed. The stack pointer usually is, |
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422 unless TARGET_RETURN_POPS_ARGS, in which case an explicit |
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423 CLOBBER will be present. If we are generating PIC code, the |
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424 PIC offset table register is preserved across calls, though the |
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425 target can override that. */ |
| 0 | 426 |
| 427 if (i == STACK_POINTER_REGNUM) | |
| 428 ; | |
| 429 else if (global_regs[i]) | |
| 430 { | |
| 431 SET_HARD_REG_BIT (regs_invalidated_by_call, i); | |
| 432 SET_REGNO_REG_SET (regs_invalidated_by_call_regset, i); | |
| 433 } | |
| 434 else if (i == FRAME_POINTER_REGNUM) | |
| 435 ; | |
| 111 | 436 else if (!HARD_FRAME_POINTER_IS_FRAME_POINTER |
| 437 && i == HARD_FRAME_POINTER_REGNUM) | |
| 0 | 438 ; |
| 111 | 439 else if (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM |
| 440 && i == ARG_POINTER_REGNUM && fixed_regs[i]) | |
| 0 | 441 ; |
|
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442 else if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED |
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443 && i == (unsigned) PIC_OFFSET_TABLE_REGNUM && fixed_regs[i]) |
| 0 | 444 ; |
| 445 else if (CALL_REALLY_USED_REGNO_P (i)) | |
| 446 { | |
| 447 SET_HARD_REG_BIT (regs_invalidated_by_call, i); | |
| 448 SET_REGNO_REG_SET (regs_invalidated_by_call_regset, i); | |
| 449 } | |
| 450 } | |
| 451 | |
| 111 | 452 COPY_HARD_REG_SET (call_fixed_reg_set, fixed_reg_set); |
| 453 COPY_HARD_REG_SET (fixed_nonglobal_reg_set, fixed_reg_set); | |
|
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454 |
| 0 | 455 /* Preserve global registers if called more than once. */ |
| 456 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
| 457 { | |
| 458 if (global_regs[i]) | |
| 459 { | |
|
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460 fixed_regs[i] = call_used_regs[i] = 1; |
| 0 | 461 SET_HARD_REG_BIT (fixed_reg_set, i); |
| 462 SET_HARD_REG_BIT (call_used_reg_set, i); | |
| 463 SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
| 464 } | |
| 465 } | |
| 466 | |
| 467 memset (have_regs_of_mode, 0, sizeof (have_regs_of_mode)); | |
| 468 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode)); | |
| 469 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) | |
| 470 { | |
| 111 | 471 HARD_REG_SET ok_regs, ok_regs2; |
| 0 | 472 CLEAR_HARD_REG_SET (ok_regs); |
| 111 | 473 CLEAR_HARD_REG_SET (ok_regs2); |
| 0 | 474 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) |
| 111 | 475 if (!TEST_HARD_REG_BIT (fixed_nonglobal_reg_set, j) |
| 476 && targetm.hard_regno_mode_ok (j, (machine_mode) m)) | |
| 477 { | |
| 478 SET_HARD_REG_BIT (ok_regs, j); | |
| 479 if (!fixed_regs[j]) | |
| 480 SET_HARD_REG_BIT (ok_regs2, j); | |
| 481 } | |
|
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482 |
| 0 | 483 for (i = 0; i < N_REG_CLASSES; i++) |
| 111 | 484 if ((targetm.class_max_nregs ((reg_class_t) i, (machine_mode) m) |
|
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485 <= reg_class_size[i]) |
| 0 | 486 && hard_reg_set_intersect_p (ok_regs, reg_class_contents[i])) |
| 487 { | |
| 111 | 488 contains_reg_of_mode[i][m] = 1; |
| 489 if (hard_reg_set_intersect_p (ok_regs2, reg_class_contents[i])) | |
| 490 { | |
| 491 have_regs_of_mode[m] = 1; | |
| 492 contains_allocatable_reg_of_mode[i][m] = 1; | |
| 493 } | |
| 0 | 494 } |
| 495 } | |
| 496 } | |
| 497 | |
| 498 /* Compute the table of register modes. | |
| 499 These values are used to record death information for individual registers | |
| 500 (as opposed to a multi-register mode). | |
| 501 This function might be invoked more than once, if the target has support | |
| 502 for changing register usage conventions on a per-function basis. | |
| 503 */ | |
| 504 void | |
| 505 init_reg_modes_target (void) | |
| 506 { | |
| 507 int i, j; | |
| 508 | |
| 509 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
| 510 for (j = 0; j < MAX_MACHINE_MODE; j++) | |
| 111 | 511 this_target_regs->x_hard_regno_nregs[i][j] |
| 512 = targetm.hard_regno_nregs (i, (machine_mode) j); | |
| 0 | 513 |
| 514 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
| 515 { | |
| 516 reg_raw_mode[i] = choose_hard_reg_mode (i, 1, false); | |
| 517 | |
| 111 | 518 /* If we couldn't find a valid mode, just use the previous mode |
| 519 if it is suitable, otherwise fall back on word_mode. */ | |
| 0 | 520 if (reg_raw_mode[i] == VOIDmode) |
| 111 | 521 { |
| 522 if (i > 0 && hard_regno_nregs (i, reg_raw_mode[i - 1]) == 1) | |
| 523 reg_raw_mode[i] = reg_raw_mode[i - 1]; | |
| 524 else | |
| 525 reg_raw_mode[i] = word_mode; | |
| 526 } | |
| 0 | 527 } |
| 528 } | |
| 529 | |
| 530 /* Finish initializing the register sets and initialize the register modes. | |
| 531 This function might be invoked more than once, if the target has support | |
| 532 for changing register usage conventions on a per-function basis. | |
| 533 */ | |
| 534 void | |
| 535 init_regs (void) | |
| 536 { | |
| 537 /* This finishes what was started by init_reg_sets, but couldn't be done | |
| 538 until after register usage was specified. */ | |
| 539 init_reg_sets_1 (); | |
| 540 } | |
| 541 | |
| 542 /* The same as previous function plus initializing IRA. */ | |
| 543 void | |
| 544 reinit_regs (void) | |
| 545 { | |
| 546 init_regs (); | |
|
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547 /* caller_save needs to be re-initialized. */ |
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548 caller_save_initialized_p = false; |
| 111 | 549 if (this_target_rtl->target_specific_initialized) |
| 550 { | |
| 551 ira_init (); | |
| 552 recog_init (); | |
| 553 } | |
| 0 | 554 } |
| 555 | |
| 556 /* Initialize some fake stack-frame MEM references for use in | |
| 557 memory_move_secondary_cost. */ | |
| 558 void | |
| 559 init_fake_stack_mems (void) | |
| 560 { | |
| 561 int i; | |
|
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562 |
| 0 | 563 for (i = 0; i < MAX_MACHINE_MODE; i++) |
| 111 | 564 top_of_stack[i] = gen_rtx_MEM ((machine_mode) i, stack_pointer_rtx); |
| 0 | 565 } |
| 566 | |
| 567 | |
|
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568 /* Compute cost of moving data from a register of class FROM to one of |
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569 TO, using MODE. */ |
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570 |
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571 int |
| 111 | 572 register_move_cost (machine_mode mode, reg_class_t from, reg_class_t to) |
|
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573 { |
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574 return targetm.register_move_cost (mode, from, to); |
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575 } |
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576 |
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577 /* Compute cost of moving registers to/from memory. */ |
| 111 | 578 |
|
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579 int |
| 111 | 580 memory_move_cost (machine_mode mode, reg_class_t rclass, bool in) |
|
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581 { |
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582 return targetm.memory_move_cost (mode, rclass, in); |
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583 } |
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584 |
| 0 | 585 /* Compute extra cost of moving registers to/from memory due to reloads. |
| 586 Only needed if secondary reloads are required for memory moves. */ | |
| 587 int | |
| 111 | 588 memory_move_secondary_cost (machine_mode mode, reg_class_t rclass, |
|
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589 bool in) |
| 0 | 590 { |
|
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591 reg_class_t altclass; |
| 0 | 592 int partial_cost = 0; |
| 593 /* We need a memory reference to feed to SECONDARY... macros. */ | |
| 594 /* mem may be unused even if the SECONDARY_ macros are defined. */ | |
| 595 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode]; | |
| 596 | |
| 597 altclass = secondary_reload_class (in ? 1 : 0, rclass, mode, mem); | |
| 598 | |
| 599 if (altclass == NO_REGS) | |
| 600 return 0; | |
| 601 | |
| 602 if (in) | |
|
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603 partial_cost = register_move_cost (mode, altclass, rclass); |
| 0 | 604 else |
|
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605 partial_cost = register_move_cost (mode, rclass, altclass); |
| 0 | 606 |
| 607 if (rclass == altclass) | |
| 608 /* This isn't simply a copy-to-temporary situation. Can't guess | |
|
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609 what it is, so TARGET_MEMORY_MOVE_COST really ought not to be |
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610 calling here in that case. |
| 0 | 611 |
| 612 I'm tempted to put in an assert here, but returning this will | |
| 613 probably only give poor estimates, which is what we would've | |
| 614 had before this code anyways. */ | |
| 615 return partial_cost; | |
| 616 | |
| 617 /* Check if the secondary reload register will also need a | |
| 618 secondary reload. */ | |
| 619 return memory_move_secondary_cost (mode, altclass, in) + partial_cost; | |
| 620 } | |
| 621 | |
| 622 /* Return a machine mode that is legitimate for hard reg REGNO and large | |
| 623 enough to save nregs. If we can't find one, return VOIDmode. | |
| 624 If CALL_SAVED is true, only consider modes that are call saved. */ | |
| 111 | 625 machine_mode |
| 0 | 626 choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED, |
| 627 unsigned int nregs, bool call_saved) | |
| 628 { | |
| 111 | 629 unsigned int /* machine_mode */ m; |
| 630 machine_mode found_mode = VOIDmode, mode; | |
| 0 | 631 |
| 632 /* We first look for the largest integer mode that can be validly | |
| 633 held in REGNO. If none, we look for the largest floating-point mode. | |
| 131 | 634 If we still didn't find a valid mode, try CCmode. |
| 0 | 635 |
| 131 | 636 The tests use maybe_gt rather than known_gt because we want (for example) |
| 637 N V4SFs to win over plain V4SF even though N might be 1. */ | |
| 111 | 638 FOR_EACH_MODE_IN_CLASS (mode, MODE_INT) |
| 639 if (hard_regno_nregs (regno, mode) == nregs | |
| 640 && targetm.hard_regno_mode_ok (regno, mode) | |
| 641 && (!call_saved | |
| 642 || !targetm.hard_regno_call_part_clobbered (regno, mode)) | |
| 131 | 643 && maybe_gt (GET_MODE_SIZE (mode), GET_MODE_SIZE (found_mode))) |
| 0 | 644 found_mode = mode; |
| 645 | |
| 111 | 646 FOR_EACH_MODE_IN_CLASS (mode, MODE_FLOAT) |
| 647 if (hard_regno_nregs (regno, mode) == nregs | |
| 648 && targetm.hard_regno_mode_ok (regno, mode) | |
| 649 && (!call_saved | |
| 650 || !targetm.hard_regno_call_part_clobbered (regno, mode)) | |
| 131 | 651 && maybe_gt (GET_MODE_SIZE (mode), GET_MODE_SIZE (found_mode))) |
| 0 | 652 found_mode = mode; |
| 653 | |
| 111 | 654 FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_FLOAT) |
| 655 if (hard_regno_nregs (regno, mode) == nregs | |
| 656 && targetm.hard_regno_mode_ok (regno, mode) | |
| 657 && (!call_saved | |
| 658 || !targetm.hard_regno_call_part_clobbered (regno, mode)) | |
| 131 | 659 && maybe_gt (GET_MODE_SIZE (mode), GET_MODE_SIZE (found_mode))) |
| 111 | 660 found_mode = mode; |
| 0 | 661 |
| 111 | 662 FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_INT) |
| 663 if (hard_regno_nregs (regno, mode) == nregs | |
| 664 && targetm.hard_regno_mode_ok (regno, mode) | |
| 665 && (!call_saved | |
| 666 || !targetm.hard_regno_call_part_clobbered (regno, mode)) | |
| 131 | 667 && maybe_gt (GET_MODE_SIZE (mode), GET_MODE_SIZE (found_mode))) |
| 0 | 668 found_mode = mode; |
| 669 | |
| 670 if (found_mode != VOIDmode) | |
| 671 return found_mode; | |
| 672 | |
| 673 /* Iterate over all of the CCmodes. */ | |
| 674 for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m) | |
| 675 { | |
| 111 | 676 mode = (machine_mode) m; |
| 677 if (hard_regno_nregs (regno, mode) == nregs | |
| 678 && targetm.hard_regno_mode_ok (regno, mode) | |
| 679 && (!call_saved | |
| 680 || !targetm.hard_regno_call_part_clobbered (regno, mode))) | |
| 0 | 681 return mode; |
| 682 } | |
| 683 | |
| 684 /* We can't find a mode valid for this register. */ | |
| 685 return VOIDmode; | |
| 686 } | |
| 687 | |
| 688 /* Specify the usage characteristics of the register named NAME. | |
| 689 It should be a fixed register if FIXED and a | |
| 690 call-used register if CALL_USED. */ | |
| 691 void | |
| 692 fix_register (const char *name, int fixed, int call_used) | |
| 693 { | |
| 694 int i; | |
|
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695 int reg, nregs; |
| 0 | 696 |
| 697 /* Decode the name and update the primary form of | |
| 698 the register info. */ | |
| 699 | |
|
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700 if ((reg = decode_reg_name_and_count (name, &nregs)) >= 0) |
| 0 | 701 { |
|
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702 gcc_assert (nregs >= 1); |
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703 for (i = reg; i < reg + nregs; i++) |
| 0 | 704 { |
|
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705 if ((i == STACK_POINTER_REGNUM |
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706 #ifdef HARD_FRAME_POINTER_REGNUM |
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707 || i == HARD_FRAME_POINTER_REGNUM |
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708 #else |
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709 || i == FRAME_POINTER_REGNUM |
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710 #endif |
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711 ) |
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712 && (fixed == 0 || call_used == 0)) |
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713 { |
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714 switch (fixed) |
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715 { |
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716 case 0: |
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717 switch (call_used) |
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718 { |
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719 case 0: |
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720 error ("can%'t use %qs as a call-saved register", name); |
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721 break; |
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722 |
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723 case 1: |
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724 error ("can%'t use %qs as a call-used register", name); |
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725 break; |
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726 |
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727 default: |
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728 gcc_unreachable (); |
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729 } |
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730 break; |
| 0 | 731 |
|
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732 case 1: |
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733 switch (call_used) |
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734 { |
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735 case 1: |
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736 error ("can%'t use %qs as a fixed register", name); |
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737 break; |
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738 |
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739 case 0: |
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740 default: |
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741 gcc_unreachable (); |
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742 } |
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743 break; |
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744 |
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745 default: |
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746 gcc_unreachable (); |
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747 } |
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748 } |
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749 else |
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750 { |
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751 fixed_regs[i] = fixed; |
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752 call_used_regs[i] = call_used; |
| 0 | 753 #ifdef CALL_REALLY_USED_REGISTERS |
|
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754 if (fixed == 0) |
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755 call_really_used_regs[i] = call_used; |
| 0 | 756 #endif |
|
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757 } |
| 0 | 758 } |
| 759 } | |
| 760 else | |
| 761 { | |
| 762 warning (0, "unknown register name: %s", name); | |
| 763 } | |
| 764 } | |
| 765 | |
| 766 /* Mark register number I as global. */ | |
| 767 void | |
| 111 | 768 globalize_reg (tree decl, int i) |
| 0 | 769 { |
| 111 | 770 location_t loc = DECL_SOURCE_LOCATION (decl); |
| 771 | |
|
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772 #ifdef STACK_REGS |
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773 if (IN_RANGE (i, FIRST_STACK_REG, LAST_STACK_REG)) |
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774 { |
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775 error ("stack register used for global register variable"); |
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776 return; |
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777 } |
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778 #endif |
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779 |
| 0 | 780 if (fixed_regs[i] == 0 && no_global_reg_vars) |
| 111 | 781 error_at (loc, "global register variable follows a function definition"); |
| 0 | 782 |
| 783 if (global_regs[i]) | |
| 784 { | |
| 131 | 785 auto_diagnostic_group d; |
| 111 | 786 warning_at (loc, 0, |
| 787 "register of %qD used for multiple global register variables", | |
| 788 decl); | |
| 789 inform (DECL_SOURCE_LOCATION (global_regs_decl[i]), | |
| 790 "conflicts with %qD", global_regs_decl[i]); | |
| 0 | 791 return; |
| 792 } | |
| 793 | |
| 794 if (call_used_regs[i] && ! fixed_regs[i]) | |
| 111 | 795 warning_at (loc, 0, "call-clobbered register used for global register variable"); |
| 0 | 796 |
| 797 global_regs[i] = 1; | |
| 111 | 798 global_regs_decl[i] = decl; |
| 0 | 799 |
| 800 /* If we're globalizing the frame pointer, we need to set the | |
| 801 appropriate regs_invalidated_by_call bit, even if it's already | |
| 802 set in fixed_regs. */ | |
| 803 if (i != STACK_POINTER_REGNUM) | |
| 804 { | |
| 805 SET_HARD_REG_BIT (regs_invalidated_by_call, i); | |
| 806 SET_REGNO_REG_SET (regs_invalidated_by_call_regset, i); | |
| 807 } | |
| 808 | |
| 809 /* If already fixed, nothing else to do. */ | |
| 810 if (fixed_regs[i]) | |
| 811 return; | |
| 812 | |
|
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813 fixed_regs[i] = call_used_regs[i] = 1; |
| 0 | 814 #ifdef CALL_REALLY_USED_REGISTERS |
| 815 call_really_used_regs[i] = 1; | |
| 816 #endif | |
| 817 | |
| 818 SET_HARD_REG_BIT (fixed_reg_set, i); | |
| 819 SET_HARD_REG_BIT (call_used_reg_set, i); | |
| 820 SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
| 821 | |
| 822 reinit_regs (); | |
| 823 } | |
| 824 | |
| 825 | |
| 826 /* Structure used to record preferences of given pseudo. */ | |
| 827 struct reg_pref | |
| 828 { | |
| 829 /* (enum reg_class) prefclass is the preferred class. May be | |
| 830 NO_REGS if no class is better than memory. */ | |
| 831 char prefclass; | |
| 832 | |
| 833 /* altclass is a register class that we should use for allocating | |
| 834 pseudo if no register in the preferred class is available. | |
| 835 If no register in this class is available, memory is preferred. | |
| 836 | |
| 837 It might appear to be more general to have a bitmask of classes here, | |
| 838 but since it is recommended that there be a class corresponding to the | |
| 839 union of most major pair of classes, that generality is not required. */ | |
| 840 char altclass; | |
|
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841 |
| 111 | 842 /* allocnoclass is a register class that IRA uses for allocating |
|
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843 the pseudo. */ |
| 111 | 844 char allocnoclass; |
| 0 | 845 }; |
| 846 | |
| 847 /* Record preferences of each pseudo. This is available after RA is | |
| 848 run. */ | |
| 849 static struct reg_pref *reg_pref; | |
| 850 | |
|
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851 /* Current size of reg_info. */ |
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852 static int reg_info_size; |
| 111 | 853 /* Max_reg_num still last resize_reg_info call. */ |
| 854 static int max_regno_since_last_resize; | |
|
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855 |
| 0 | 856 /* Return the reg_class in which pseudo reg number REGNO is best allocated. |
| 857 This function is sometimes called before the info has been computed. | |
| 858 When that happens, just return GENERAL_REGS, which is innocuous. */ | |
| 859 enum reg_class | |
| 860 reg_preferred_class (int regno) | |
| 861 { | |
| 862 if (reg_pref == 0) | |
| 863 return GENERAL_REGS; | |
| 864 | |
| 111 | 865 gcc_assert (regno < reg_info_size); |
| 0 | 866 return (enum reg_class) reg_pref[regno].prefclass; |
| 867 } | |
| 868 | |
| 869 enum reg_class | |
| 870 reg_alternate_class (int regno) | |
| 871 { | |
| 872 if (reg_pref == 0) | |
| 873 return ALL_REGS; | |
| 874 | |
| 111 | 875 gcc_assert (regno < reg_info_size); |
| 0 | 876 return (enum reg_class) reg_pref[regno].altclass; |
| 877 } | |
| 878 | |
|
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879 /* Return the reg_class which is used by IRA for its allocation. */ |
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880 enum reg_class |
| 111 | 881 reg_allocno_class (int regno) |
| 0 | 882 { |
|
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883 if (reg_pref == 0) |
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884 return NO_REGS; |
| 0 | 885 |
| 111 | 886 gcc_assert (regno < reg_info_size); |
| 887 return (enum reg_class) reg_pref[regno].allocnoclass; | |
|
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888 } |
| 0 | 889 |
| 890 | |
| 891 | |
| 111 | 892 /* Allocate space for reg info and initilize it. */ |
|
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893 static void |
| 0 | 894 allocate_reg_info (void) |
| 895 { | |
| 111 | 896 int i; |
| 897 | |
| 898 max_regno_since_last_resize = max_reg_num (); | |
| 899 reg_info_size = max_regno_since_last_resize * 3 / 2 + 1; | |
| 0 | 900 gcc_assert (! reg_pref && ! reg_renumber); |
|
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901 reg_renumber = XNEWVEC (short, reg_info_size); |
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902 reg_pref = XCNEWVEC (struct reg_pref, reg_info_size); |
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903 memset (reg_renumber, -1, reg_info_size * sizeof (short)); |
| 111 | 904 for (i = 0; i < reg_info_size; i++) |
| 905 { | |
| 906 reg_pref[i].prefclass = GENERAL_REGS; | |
| 907 reg_pref[i].altclass = ALL_REGS; | |
| 908 reg_pref[i].allocnoclass = GENERAL_REGS; | |
| 909 } | |
| 0 | 910 } |
| 911 | |
| 912 | |
| 111 | 913 /* Resize reg info. The new elements will be initialized. Return TRUE |
| 914 if new pseudos were added since the last call. */ | |
|
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915 bool |
| 0 | 916 resize_reg_info (void) |
| 917 { | |
| 111 | 918 int old, i; |
| 919 bool change_p; | |
| 0 | 920 |
|
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921 if (reg_pref == NULL) |
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922 { |
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923 allocate_reg_info (); |
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924 return true; |
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925 } |
| 111 | 926 change_p = max_regno_since_last_resize != max_reg_num (); |
| 927 max_regno_since_last_resize = max_reg_num (); | |
| 928 if (reg_info_size >= max_reg_num ()) | |
| 929 return change_p; | |
|
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930 old = reg_info_size; |
| 111 | 931 reg_info_size = max_reg_num () * 3 / 2 + 1; |
| 0 | 932 gcc_assert (reg_pref && reg_renumber); |
|
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933 reg_renumber = XRESIZEVEC (short, reg_renumber, reg_info_size); |
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934 reg_pref = XRESIZEVEC (struct reg_pref, reg_pref, reg_info_size); |
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935 memset (reg_pref + old, -1, |
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936 (reg_info_size - old) * sizeof (struct reg_pref)); |
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937 memset (reg_renumber + old, -1, (reg_info_size - old) * sizeof (short)); |
| 111 | 938 for (i = old; i < reg_info_size; i++) |
| 939 { | |
| 940 reg_pref[i].prefclass = GENERAL_REGS; | |
| 941 reg_pref[i].altclass = ALL_REGS; | |
| 942 reg_pref[i].allocnoclass = GENERAL_REGS; | |
| 943 } | |
|
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944 return true; |
| 0 | 945 } |
| 946 | |
| 947 | |
| 948 /* Free up the space allocated by allocate_reg_info. */ | |
| 949 void | |
| 950 free_reg_info (void) | |
| 951 { | |
| 952 if (reg_pref) | |
| 953 { | |
| 954 free (reg_pref); | |
| 955 reg_pref = NULL; | |
| 956 } | |
| 957 | |
| 958 if (reg_renumber) | |
| 959 { | |
| 960 free (reg_renumber); | |
| 961 reg_renumber = NULL; | |
| 962 } | |
| 963 } | |
| 964 | |
|
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965 /* Initialize some global data for this pass. */ |
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966 static unsigned int |
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967 reginfo_init (void) |
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968 { |
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969 if (df) |
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970 df_compute_regs_ever_live (true); |
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971 |
| 111 | 972 /* This prevents dump_reg_info from losing if called |
|
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973 before reginfo is run. */ |
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974 reg_pref = NULL; |
| 111 | 975 reg_info_size = max_regno_since_last_resize = 0; |
|
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976 /* No more global register variables may be declared. */ |
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977 no_global_reg_vars = 1; |
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978 return 1; |
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979 } |
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980 |
| 111 | 981 namespace { |
| 982 | |
| 983 const pass_data pass_data_reginfo_init = | |
| 984 { | |
| 985 RTL_PASS, /* type */ | |
| 986 "reginfo", /* name */ | |
| 987 OPTGROUP_NONE, /* optinfo_flags */ | |
| 988 TV_NONE, /* tv_id */ | |
| 989 0, /* properties_required */ | |
| 990 0, /* properties_provided */ | |
| 991 0, /* properties_destroyed */ | |
| 992 0, /* todo_flags_start */ | |
| 993 0, /* todo_flags_finish */ | |
| 994 }; | |
| 995 | |
| 996 class pass_reginfo_init : public rtl_opt_pass | |
|
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997 { |
| 111 | 998 public: |
| 999 pass_reginfo_init (gcc::context *ctxt) | |
| 1000 : rtl_opt_pass (pass_data_reginfo_init, ctxt) | |
| 1001 {} | |
| 1002 | |
| 1003 /* opt_pass methods: */ | |
| 1004 virtual unsigned int execute (function *) { return reginfo_init (); } | |
| 1005 | |
| 1006 }; // class pass_reginfo_init | |
| 1007 | |
| 1008 } // anon namespace | |
| 1009 | |
| 1010 rtl_opt_pass * | |
| 1011 make_pass_reginfo_init (gcc::context *ctxt) | |
| 1012 { | |
| 1013 return new pass_reginfo_init (ctxt); | |
| 1014 } | |
| 0 | 1015 |
| 1016 | |
| 1017 | |
| 111 | 1018 /* Set up preferred, alternate, and allocno classes for REGNO as |
| 1019 PREFCLASS, ALTCLASS, and ALLOCNOCLASS. */ | |
| 0 | 1020 void |
| 1021 setup_reg_classes (int regno, | |
|
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1022 enum reg_class prefclass, enum reg_class altclass, |
| 111 | 1023 enum reg_class allocnoclass) |
| 0 | 1024 { |
| 1025 if (reg_pref == NULL) | |
| 1026 return; | |
| 111 | 1027 gcc_assert (reg_info_size >= max_reg_num ()); |
| 0 | 1028 reg_pref[regno].prefclass = prefclass; |
| 1029 reg_pref[regno].altclass = altclass; | |
| 111 | 1030 reg_pref[regno].allocnoclass = allocnoclass; |
| 0 | 1031 } |
| 1032 | |
| 1033 | |
| 1034 /* This is the `regscan' pass of the compiler, run just before cse and | |
| 1035 again just before loop. It finds the first and last use of each | |
| 1036 pseudo-register. */ | |
| 1037 | |
| 111 | 1038 static void reg_scan_mark_refs (rtx, rtx_insn *); |
| 0 | 1039 |
| 1040 void | |
| 111 | 1041 reg_scan (rtx_insn *f, unsigned int nregs ATTRIBUTE_UNUSED) |
| 0 | 1042 { |
| 111 | 1043 rtx_insn *insn; |
| 0 | 1044 |
| 1045 timevar_push (TV_REG_SCAN); | |
| 1046 | |
| 1047 for (insn = f; insn; insn = NEXT_INSN (insn)) | |
| 1048 if (INSN_P (insn)) | |
| 1049 { | |
| 1050 reg_scan_mark_refs (PATTERN (insn), insn); | |
| 1051 if (REG_NOTES (insn)) | |
| 1052 reg_scan_mark_refs (REG_NOTES (insn), insn); | |
| 1053 } | |
| 1054 | |
| 1055 timevar_pop (TV_REG_SCAN); | |
| 1056 } | |
| 1057 | |
| 1058 | |
| 1059 /* X is the expression to scan. INSN is the insn it appears in. | |
| 1060 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. | |
| 1061 We should only record information for REGs with numbers | |
| 1062 greater than or equal to MIN_REGNO. */ | |
| 1063 static void | |
| 111 | 1064 reg_scan_mark_refs (rtx x, rtx_insn *insn) |
| 0 | 1065 { |
| 1066 enum rtx_code code; | |
| 1067 rtx dest; | |
| 1068 rtx note; | |
| 1069 | |
| 1070 if (!x) | |
| 1071 return; | |
| 1072 code = GET_CODE (x); | |
| 1073 switch (code) | |
| 1074 { | |
| 1075 case CONST: | |
| 111 | 1076 CASE_CONST_ANY: |
| 0 | 1077 case CC0: |
| 1078 case PC: | |
| 1079 case SYMBOL_REF: | |
| 1080 case LABEL_REF: | |
| 1081 case ADDR_VEC: | |
| 1082 case ADDR_DIFF_VEC: | |
| 1083 case REG: | |
| 1084 return; | |
| 1085 | |
| 1086 case EXPR_LIST: | |
| 1087 if (XEXP (x, 0)) | |
| 1088 reg_scan_mark_refs (XEXP (x, 0), insn); | |
| 1089 if (XEXP (x, 1)) | |
| 1090 reg_scan_mark_refs (XEXP (x, 1), insn); | |
| 1091 break; | |
| 1092 | |
| 1093 case INSN_LIST: | |
| 111 | 1094 case INT_LIST: |
| 0 | 1095 if (XEXP (x, 1)) |
| 1096 reg_scan_mark_refs (XEXP (x, 1), insn); | |
| 1097 break; | |
| 1098 | |
| 1099 case CLOBBER: | |
| 1100 if (MEM_P (XEXP (x, 0))) | |
| 1101 reg_scan_mark_refs (XEXP (XEXP (x, 0), 0), insn); | |
| 1102 break; | |
| 1103 | |
| 131 | 1104 case CLOBBER_HIGH: |
| 1105 gcc_assert (!(MEM_P (XEXP (x, 0)))); | |
| 1106 break; | |
| 1107 | |
| 0 | 1108 case SET: |
| 1109 /* Count a set of the destination if it is a register. */ | |
| 1110 for (dest = SET_DEST (x); | |
| 1111 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART | |
| 111 | 1112 || GET_CODE (dest) == ZERO_EXTRACT; |
| 0 | 1113 dest = XEXP (dest, 0)) |
| 1114 ; | |
| 1115 | |
| 1116 /* If this is setting a pseudo from another pseudo or the sum of a | |
| 1117 pseudo and a constant integer and the other pseudo is known to be | |
| 1118 a pointer, set the destination to be a pointer as well. | |
| 1119 | |
| 1120 Likewise if it is setting the destination from an address or from a | |
| 1121 value equivalent to an address or to the sum of an address and | |
| 1122 something else. | |
| 1123 | |
| 1124 But don't do any of this if the pseudo corresponds to a user | |
| 1125 variable since it should have already been set as a pointer based | |
| 1126 on the type. */ | |
| 1127 | |
| 1128 if (REG_P (SET_DEST (x)) | |
| 1129 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER | |
| 1130 /* If the destination pseudo is set more than once, then other | |
| 1131 sets might not be to a pointer value (consider access to a | |
| 1132 union in two threads of control in the presence of global | |
| 1133 optimizations). So only set REG_POINTER on the destination | |
| 1134 pseudo if this is the only set of that pseudo. */ | |
| 1135 && DF_REG_DEF_COUNT (REGNO (SET_DEST (x))) == 1 | |
| 1136 && ! REG_USERVAR_P (SET_DEST (x)) | |
| 1137 && ! REG_POINTER (SET_DEST (x)) | |
| 1138 && ((REG_P (SET_SRC (x)) | |
| 1139 && REG_POINTER (SET_SRC (x))) | |
| 1140 || ((GET_CODE (SET_SRC (x)) == PLUS | |
| 1141 || GET_CODE (SET_SRC (x)) == LO_SUM) | |
|
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1142 && CONST_INT_P (XEXP (SET_SRC (x), 1)) |
| 0 | 1143 && REG_P (XEXP (SET_SRC (x), 0)) |
| 1144 && REG_POINTER (XEXP (SET_SRC (x), 0))) | |
| 1145 || GET_CODE (SET_SRC (x)) == CONST | |
| 1146 || GET_CODE (SET_SRC (x)) == SYMBOL_REF | |
| 1147 || GET_CODE (SET_SRC (x)) == LABEL_REF | |
| 1148 || (GET_CODE (SET_SRC (x)) == HIGH | |
| 1149 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST | |
| 1150 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF | |
| 1151 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) | |
| 1152 || ((GET_CODE (SET_SRC (x)) == PLUS | |
| 1153 || GET_CODE (SET_SRC (x)) == LO_SUM) | |
| 1154 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST | |
| 1155 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF | |
| 1156 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) | |
| 1157 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 | |
| 1158 && (GET_CODE (XEXP (note, 0)) == CONST | |
| 1159 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF | |
| 1160 || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) | |
| 1161 REG_POINTER (SET_DEST (x)) = 1; | |
| 1162 | |
| 1163 /* If this is setting a register from a register or from a simple | |
| 1164 conversion of a register, propagate REG_EXPR. */ | |
| 1165 if (REG_P (dest) && !REG_ATTRS (dest)) | |
| 111 | 1166 set_reg_attrs_from_value (dest, SET_SRC (x)); |
| 0 | 1167 |
| 111 | 1168 /* fall through */ |
| 0 | 1169 |
| 1170 default: | |
| 1171 { | |
| 1172 const char *fmt = GET_RTX_FORMAT (code); | |
| 1173 int i; | |
| 1174 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
| 1175 { | |
| 1176 if (fmt[i] == 'e') | |
| 1177 reg_scan_mark_refs (XEXP (x, i), insn); | |
| 1178 else if (fmt[i] == 'E' && XVEC (x, i) != 0) | |
| 1179 { | |
| 1180 int j; | |
| 1181 for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
| 1182 reg_scan_mark_refs (XVECEXP (x, i, j), insn); | |
| 1183 } | |
| 1184 } | |
| 1185 } | |
| 1186 } | |
| 1187 } | |
| 1188 | |
| 1189 | |
| 1190 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 | |
| 1191 is also in C2. */ | |
| 1192 int | |
|
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1193 reg_class_subset_p (reg_class_t c1, reg_class_t c2) |
| 0 | 1194 { |
| 1195 return (c1 == c2 | |
| 1196 || c2 == ALL_REGS | |
| 1197 || hard_reg_set_subset_p (reg_class_contents[(int) c1], | |
| 1198 reg_class_contents[(int) c2])); | |
| 1199 } | |
| 1200 | |
| 1201 /* Return nonzero if there is a register that is in both C1 and C2. */ | |
| 1202 int | |
|
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1203 reg_classes_intersect_p (reg_class_t c1, reg_class_t c2) |
| 0 | 1204 { |
| 1205 return (c1 == c2 | |
| 1206 || c1 == ALL_REGS | |
| 1207 || c2 == ALL_REGS | |
| 1208 || hard_reg_set_intersect_p (reg_class_contents[(int) c1], | |
| 1209 reg_class_contents[(int) c2])); | |
| 1210 } | |
| 1211 | |
| 1212 | |
| 111 | 1213 inline hashval_t |
| 1214 simplifiable_subregs_hasher::hash (const simplifiable_subreg *value) | |
| 1215 { | |
| 131 | 1216 inchash::hash h; |
| 1217 h.add_hwi (value->shape.unique_id ()); | |
| 1218 return h.end (); | |
| 111 | 1219 } |
| 1220 | |
| 1221 inline bool | |
| 1222 simplifiable_subregs_hasher::equal (const simplifiable_subreg *value, | |
| 1223 const subreg_shape *compare) | |
| 1224 { | |
| 1225 return value->shape == *compare; | |
| 1226 } | |
| 1227 | |
| 1228 inline simplifiable_subreg::simplifiable_subreg (const subreg_shape &shape_in) | |
| 1229 : shape (shape_in) | |
| 1230 { | |
| 1231 CLEAR_HARD_REG_SET (simplifiable_regs); | |
| 1232 } | |
| 1233 | |
| 1234 /* Return the set of hard registers that are able to form the subreg | |
| 1235 described by SHAPE. */ | |
| 1236 | |
| 1237 const HARD_REG_SET & | |
| 1238 simplifiable_subregs (const subreg_shape &shape) | |
| 1239 { | |
| 1240 if (!this_target_hard_regs->x_simplifiable_subregs) | |
| 1241 this_target_hard_regs->x_simplifiable_subregs | |
| 1242 = new hash_table <simplifiable_subregs_hasher> (30); | |
| 131 | 1243 inchash::hash h; |
| 1244 h.add_hwi (shape.unique_id ()); | |
| 111 | 1245 simplifiable_subreg **slot |
| 1246 = (this_target_hard_regs->x_simplifiable_subregs | |
| 131 | 1247 ->find_slot_with_hash (&shape, h.end (), INSERT)); |
| 111 | 1248 |
| 1249 if (!*slot) | |
| 1250 { | |
| 1251 simplifiable_subreg *info = new simplifiable_subreg (shape); | |
| 1252 for (unsigned int i = 0; i < FIRST_PSEUDO_REGISTER; ++i) | |
| 1253 if (targetm.hard_regno_mode_ok (i, shape.inner_mode) | |
| 1254 && simplify_subreg_regno (i, shape.inner_mode, shape.offset, | |
| 1255 shape.outer_mode) >= 0) | |
| 1256 SET_HARD_REG_BIT (info->simplifiable_regs, i); | |
| 1257 *slot = info; | |
| 1258 } | |
| 1259 return (*slot)->simplifiable_regs; | |
| 1260 } | |
| 0 | 1261 |
| 1262 /* Passes for keeping and updating info about modes of registers | |
| 1263 inside subregisters. */ | |
| 1264 | |
| 111 | 1265 static HARD_REG_SET **valid_mode_changes; |
| 1266 static obstack valid_mode_changes_obstack; | |
| 0 | 1267 |
| 111 | 1268 /* Restrict the choice of register for SUBREG_REG (SUBREG) based |
| 1269 on information about SUBREG. | |
| 1270 | |
| 1271 If PARTIAL_DEF, SUBREG is a partial definition of a multipart inner | |
| 1272 register and we want to ensure that the other parts of the inner | |
| 1273 register are correctly preserved. If !PARTIAL_DEF we need to | |
| 1274 ensure that SUBREG itself can be formed. */ | |
| 0 | 1275 |
| 1276 static void | |
| 111 | 1277 record_subregs_of_mode (rtx subreg, bool partial_def) |
| 0 | 1278 { |
| 1279 unsigned int regno; | |
| 1280 | |
| 1281 if (!REG_P (SUBREG_REG (subreg))) | |
| 1282 return; | |
| 1283 | |
| 1284 regno = REGNO (SUBREG_REG (subreg)); | |
| 1285 if (regno < FIRST_PSEUDO_REGISTER) | |
| 1286 return; | |
| 1287 | |
| 111 | 1288 subreg_shape shape (shape_of_subreg (subreg)); |
| 1289 if (partial_def) | |
| 0 | 1290 { |
| 111 | 1291 /* The number of independently-accessible SHAPE.outer_mode values |
| 1292 in SHAPE.inner_mode is GET_MODE_SIZE (SHAPE.inner_mode) / SIZE. | |
| 1293 We need to check that the assignment will preserve all the other | |
| 1294 SIZE-byte chunks in the inner register besides the one that | |
| 1295 includes SUBREG. | |
| 1296 | |
| 1297 In practice it is enough to check whether an equivalent | |
| 1298 SHAPE.inner_mode value in an adjacent SIZE-byte chunk can be formed. | |
| 1299 If the underlying registers are small enough, both subregs will | |
| 1300 be valid. If the underlying registers are too large, one of the | |
| 1301 subregs will be invalid. | |
| 1302 | |
| 1303 This relies on the fact that we've already been passed | |
| 131 | 1304 SUBREG with PARTIAL_DEF set to false. |
| 1305 | |
| 1306 The size of the outer mode must ordered wrt the size of the | |
| 1307 inner mode's registers, since otherwise we wouldn't know at | |
| 1308 compile time how many registers the outer mode occupies. */ | |
| 1309 poly_uint64 size = ordered_max (REGMODE_NATURAL_SIZE (shape.inner_mode), | |
| 1310 GET_MODE_SIZE (shape.outer_mode)); | |
| 1311 gcc_checking_assert (known_lt (size, GET_MODE_SIZE (shape.inner_mode))); | |
| 1312 if (known_ge (shape.offset, size)) | |
| 111 | 1313 shape.offset -= size; |
| 1314 else | |
| 1315 shape.offset += size; | |
| 1316 } | |
| 1317 | |
| 1318 if (valid_mode_changes[regno]) | |
| 1319 AND_HARD_REG_SET (*valid_mode_changes[regno], | |
| 1320 simplifiable_subregs (shape)); | |
| 1321 else | |
| 1322 { | |
| 1323 valid_mode_changes[regno] | |
| 1324 = XOBNEW (&valid_mode_changes_obstack, HARD_REG_SET); | |
| 1325 COPY_HARD_REG_SET (*valid_mode_changes[regno], | |
| 1326 simplifiable_subregs (shape)); | |
| 0 | 1327 } |
| 1328 } | |
| 1329 | |
| 1330 /* Call record_subregs_of_mode for all the subregs in X. */ | |
|
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1331 static void |
| 111 | 1332 find_subregs_of_mode (rtx x) |
| 0 | 1333 { |
| 1334 enum rtx_code code = GET_CODE (x); | |
| 1335 const char * const fmt = GET_RTX_FORMAT (code); | |
| 1336 int i; | |
| 1337 | |
| 1338 if (code == SUBREG) | |
| 111 | 1339 record_subregs_of_mode (x, false); |
|
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1340 |
| 0 | 1341 /* Time for some deep diving. */ |
| 1342 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
| 1343 { | |
| 1344 if (fmt[i] == 'e') | |
| 111 | 1345 find_subregs_of_mode (XEXP (x, i)); |
| 0 | 1346 else if (fmt[i] == 'E') |
| 1347 { | |
| 1348 int j; | |
| 1349 for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
| 111 | 1350 find_subregs_of_mode (XVECEXP (x, i, j)); |
| 0 | 1351 } |
| 1352 } | |
| 1353 } | |
| 1354 | |
|
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1355 void |
| 0 | 1356 init_subregs_of_mode (void) |
| 1357 { | |
| 1358 basic_block bb; | |
| 111 | 1359 rtx_insn *insn; |
| 0 | 1360 |
| 111 | 1361 gcc_obstack_init (&valid_mode_changes_obstack); |
| 1362 valid_mode_changes = XCNEWVEC (HARD_REG_SET *, max_reg_num ()); | |
| 0 | 1363 |
| 111 | 1364 FOR_EACH_BB_FN (bb, cfun) |
| 0 | 1365 FOR_BB_INSNS (bb, insn) |
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1366 if (NONDEBUG_INSN_P (insn)) |
| 111 | 1367 { |
| 1368 find_subregs_of_mode (PATTERN (insn)); | |
| 1369 df_ref def; | |
| 1370 FOR_EACH_INSN_DEF (def, insn) | |
| 1371 if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL) | |
| 1372 && read_modify_subreg_p (DF_REF_REG (def))) | |
| 1373 record_subregs_of_mode (DF_REF_REG (def), true); | |
| 1374 } | |
| 0 | 1375 } |
| 1376 | |
| 111 | 1377 const HARD_REG_SET * |
| 1378 valid_mode_changes_for_regno (unsigned int regno) | |
| 0 | 1379 { |
| 111 | 1380 return valid_mode_changes[regno]; |
| 0 | 1381 } |
| 1382 | |
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1383 void |
| 0 | 1384 finish_subregs_of_mode (void) |
| 1385 { | |
| 111 | 1386 XDELETEVEC (valid_mode_changes); |
| 1387 obstack_free (&valid_mode_changes_obstack, NULL); | |
| 0 | 1388 } |
| 1389 | |
| 111 | 1390 /* Free all data attached to the structure. This isn't a destructor because |
| 1391 we don't want to run on exit. */ | |
| 1392 | |
| 1393 void | |
| 1394 target_hard_regs::finalize () | |
| 1395 { | |
| 1396 delete x_simplifiable_subregs; | |
| 1397 } |