Mercurial > hg > CbC > CbC_gcc
annotate gcc/postreload.c @ 88:f214c1d5b862
merge 89
| author | Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 20 Dec 2011 18:53:46 +0900 |
| parents | f6334be47118 |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 /* Perform simple optimizations to clean up the result of reload. |
| 2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, | |
|
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3 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
|
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4 2010, 2011 Free Software Foundation, Inc. |
| 0 | 5 |
| 6 This file is part of GCC. | |
| 7 | |
| 8 GCC is free software; you can redistribute it and/or modify it under | |
| 9 the terms of the GNU General Public License as published by the Free | |
| 10 Software Foundation; either version 3, or (at your option) any later | |
| 11 version. | |
| 12 | |
| 13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 14 WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 16 for more details. | |
| 17 | |
| 18 You should have received a copy of the GNU General Public License | |
| 19 along with GCC; see the file COPYING3. If not see | |
| 20 <http://www.gnu.org/licenses/>. */ | |
| 21 | |
| 22 #include "config.h" | |
| 23 #include "system.h" | |
| 24 #include "coretypes.h" | |
| 25 #include "tm.h" | |
| 26 | |
| 27 #include "machmode.h" | |
| 28 #include "hard-reg-set.h" | |
| 29 #include "rtl.h" | |
| 30 #include "tm_p.h" | |
| 31 #include "obstack.h" | |
| 32 #include "insn-config.h" | |
| 33 #include "flags.h" | |
| 34 #include "function.h" | |
| 35 #include "expr.h" | |
| 36 #include "optabs.h" | |
| 37 #include "regs.h" | |
| 38 #include "basic-block.h" | |
| 39 #include "reload.h" | |
| 40 #include "recog.h" | |
| 41 #include "output.h" | |
| 42 #include "cselib.h" | |
|
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43 #include "diagnostic-core.h" |
| 0 | 44 #include "except.h" |
| 45 #include "tree.h" | |
|
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46 #include "target.h" |
| 0 | 47 #include "timevar.h" |
| 48 #include "tree-pass.h" | |
| 49 #include "df.h" | |
| 50 #include "dbgcnt.h" | |
| 51 | |
| 52 static int reload_cse_noop_set_p (rtx); | |
| 53 static void reload_cse_simplify (rtx, rtx); | |
| 54 static void reload_cse_regs_1 (rtx); | |
| 55 static int reload_cse_simplify_set (rtx, rtx); | |
| 56 static int reload_cse_simplify_operands (rtx, rtx); | |
| 57 | |
| 58 static void reload_combine (void); | |
|
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59 static void reload_combine_note_use (rtx *, rtx, int, rtx); |
| 0 | 60 static void reload_combine_note_store (rtx, const_rtx, void *); |
| 61 | |
|
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62 static bool reload_cse_move2add (rtx); |
| 0 | 63 static void move2add_note_store (rtx, const_rtx, void *); |
| 64 | |
| 65 /* Call cse / combine like post-reload optimization phases. | |
| 66 FIRST is the first instruction. */ | |
| 67 void | |
| 68 reload_cse_regs (rtx first ATTRIBUTE_UNUSED) | |
| 69 { | |
|
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70 bool moves_converted; |
| 0 | 71 reload_cse_regs_1 (first); |
| 72 reload_combine (); | |
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73 moves_converted = reload_cse_move2add (first); |
| 0 | 74 if (flag_expensive_optimizations) |
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75 { |
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76 if (moves_converted) |
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77 reload_combine (); |
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78 reload_cse_regs_1 (first); |
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79 } |
| 0 | 80 } |
| 81 | |
| 82 /* See whether a single set SET is a noop. */ | |
| 83 static int | |
| 84 reload_cse_noop_set_p (rtx set) | |
| 85 { | |
| 86 if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set))) | |
| 87 return 0; | |
| 88 | |
| 89 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set)); | |
| 90 } | |
| 91 | |
| 92 /* Try to simplify INSN. */ | |
| 93 static void | |
| 94 reload_cse_simplify (rtx insn, rtx testreg) | |
| 95 { | |
| 96 rtx body = PATTERN (insn); | |
| 97 | |
| 98 if (GET_CODE (body) == SET) | |
| 99 { | |
| 100 int count = 0; | |
| 101 | |
| 102 /* Simplify even if we may think it is a no-op. | |
| 103 We may think a memory load of a value smaller than WORD_SIZE | |
| 104 is redundant because we haven't taken into account possible | |
| 105 implicit extension. reload_cse_simplify_set() will bring | |
| 106 this out, so it's safer to simplify before we delete. */ | |
| 107 count += reload_cse_simplify_set (body, insn); | |
| 108 | |
| 109 if (!count && reload_cse_noop_set_p (body)) | |
| 110 { | |
| 111 rtx value = SET_DEST (body); | |
| 112 if (REG_P (value) | |
| 113 && ! REG_FUNCTION_VALUE_P (value)) | |
| 114 value = 0; | |
|
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115 check_for_inc_dec (insn); |
| 0 | 116 delete_insn_and_edges (insn); |
| 117 return; | |
| 118 } | |
| 119 | |
| 120 if (count > 0) | |
| 121 apply_change_group (); | |
| 122 else | |
| 123 reload_cse_simplify_operands (insn, testreg); | |
| 124 } | |
| 125 else if (GET_CODE (body) == PARALLEL) | |
| 126 { | |
| 127 int i; | |
| 128 int count = 0; | |
| 129 rtx value = NULL_RTX; | |
| 130 | |
| 131 /* Registers mentioned in the clobber list for an asm cannot be reused | |
| 132 within the body of the asm. Invalidate those registers now so that | |
| 133 we don't try to substitute values for them. */ | |
| 134 if (asm_noperands (body) >= 0) | |
| 135 { | |
| 136 for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
| 137 { | |
| 138 rtx part = XVECEXP (body, 0, i); | |
| 139 if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0))) | |
| 140 cselib_invalidate_rtx (XEXP (part, 0)); | |
| 141 } | |
| 142 } | |
| 143 | |
| 144 /* If every action in a PARALLEL is a noop, we can delete | |
| 145 the entire PARALLEL. */ | |
| 146 for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
| 147 { | |
| 148 rtx part = XVECEXP (body, 0, i); | |
| 149 if (GET_CODE (part) == SET) | |
| 150 { | |
| 151 if (! reload_cse_noop_set_p (part)) | |
| 152 break; | |
| 153 if (REG_P (SET_DEST (part)) | |
| 154 && REG_FUNCTION_VALUE_P (SET_DEST (part))) | |
| 155 { | |
| 156 if (value) | |
| 157 break; | |
| 158 value = SET_DEST (part); | |
| 159 } | |
| 160 } | |
| 161 else if (GET_CODE (part) != CLOBBER) | |
| 162 break; | |
| 163 } | |
| 164 | |
| 165 if (i < 0) | |
| 166 { | |
|
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167 check_for_inc_dec (insn); |
| 0 | 168 delete_insn_and_edges (insn); |
| 169 /* We're done with this insn. */ | |
| 170 return; | |
| 171 } | |
| 172 | |
| 173 /* It's not a no-op, but we can try to simplify it. */ | |
| 174 for (i = XVECLEN (body, 0) - 1; i >= 0; --i) | |
| 175 if (GET_CODE (XVECEXP (body, 0, i)) == SET) | |
| 176 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); | |
| 177 | |
| 178 if (count > 0) | |
| 179 apply_change_group (); | |
| 180 else | |
| 181 reload_cse_simplify_operands (insn, testreg); | |
| 182 } | |
| 183 } | |
| 184 | |
| 185 /* Do a very simple CSE pass over the hard registers. | |
| 186 | |
| 187 This function detects no-op moves where we happened to assign two | |
| 188 different pseudo-registers to the same hard register, and then | |
| 189 copied one to the other. Reload will generate a useless | |
| 190 instruction copying a register to itself. | |
| 191 | |
| 192 This function also detects cases where we load a value from memory | |
| 193 into two different registers, and (if memory is more expensive than | |
| 194 registers) changes it to simply copy the first register into the | |
| 195 second register. | |
| 196 | |
| 197 Another optimization is performed that scans the operands of each | |
| 198 instruction to see whether the value is already available in a | |
| 199 hard register. It then replaces the operand with the hard register | |
| 200 if possible, much like an optional reload would. */ | |
| 201 | |
| 202 static void | |
| 203 reload_cse_regs_1 (rtx first) | |
| 204 { | |
| 205 rtx insn; | |
| 206 rtx testreg = gen_rtx_REG (VOIDmode, -1); | |
| 207 | |
|
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208 cselib_init (CSELIB_RECORD_MEMORY); |
| 0 | 209 init_alias_analysis (); |
| 210 | |
| 211 for (insn = first; insn; insn = NEXT_INSN (insn)) | |
| 212 { | |
| 213 if (INSN_P (insn)) | |
| 214 reload_cse_simplify (insn, testreg); | |
| 215 | |
| 216 cselib_process_insn (insn); | |
| 217 } | |
| 218 | |
| 219 /* Clean up. */ | |
| 220 end_alias_analysis (); | |
| 221 cselib_finish (); | |
| 222 } | |
| 223 | |
| 224 /* Try to simplify a single SET instruction. SET is the set pattern. | |
| 225 INSN is the instruction it came from. | |
| 226 This function only handles one case: if we set a register to a value | |
| 227 which is not a register, we try to find that value in some other register | |
| 228 and change the set into a register copy. */ | |
| 229 | |
| 230 static int | |
| 231 reload_cse_simplify_set (rtx set, rtx insn) | |
| 232 { | |
| 233 int did_change = 0; | |
| 234 int dreg; | |
| 235 rtx src; | |
| 236 enum reg_class dclass; | |
| 237 int old_cost; | |
| 238 cselib_val *val; | |
| 239 struct elt_loc_list *l; | |
| 240 #ifdef LOAD_EXTEND_OP | |
| 241 enum rtx_code extend_op = UNKNOWN; | |
| 242 #endif | |
| 243 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | |
| 244 | |
| 245 dreg = true_regnum (SET_DEST (set)); | |
| 246 if (dreg < 0) | |
| 247 return 0; | |
| 248 | |
| 249 src = SET_SRC (set); | |
| 250 if (side_effects_p (src) || true_regnum (src) >= 0) | |
| 251 return 0; | |
| 252 | |
| 253 dclass = REGNO_REG_CLASS (dreg); | |
| 254 | |
| 255 #ifdef LOAD_EXTEND_OP | |
| 256 /* When replacing a memory with a register, we need to honor assumptions | |
| 257 that combine made wrt the contents of sign bits. We'll do this by | |
| 258 generating an extend instruction instead of a reg->reg copy. Thus | |
| 259 the destination must be a register that we can widen. */ | |
| 260 if (MEM_P (src) | |
| 261 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD | |
| 262 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != UNKNOWN | |
| 263 && !REG_P (SET_DEST (set))) | |
| 264 return 0; | |
| 265 #endif | |
| 266 | |
|
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267 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0, VOIDmode); |
| 0 | 268 if (! val) |
| 269 return 0; | |
| 270 | |
| 271 /* If memory loads are cheaper than register copies, don't change them. */ | |
| 272 if (MEM_P (src)) | |
|
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273 old_cost = memory_move_cost (GET_MODE (src), dclass, true); |
| 0 | 274 else if (REG_P (src)) |
|
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275 old_cost = register_move_cost (GET_MODE (src), |
| 0 | 276 REGNO_REG_CLASS (REGNO (src)), dclass); |
| 277 else | |
| 278 old_cost = rtx_cost (src, SET, speed); | |
| 279 | |
| 280 for (l = val->locs; l; l = l->next) | |
| 281 { | |
| 282 rtx this_rtx = l->loc; | |
| 283 int this_cost; | |
| 284 | |
| 285 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0)) | |
| 286 { | |
| 287 #ifdef LOAD_EXTEND_OP | |
| 288 if (extend_op != UNKNOWN) | |
| 289 { | |
| 290 HOST_WIDE_INT this_val; | |
| 291 | |
| 292 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other | |
| 293 constants, such as SYMBOL_REF, cannot be extended. */ | |
|
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294 if (!CONST_INT_P (this_rtx)) |
| 0 | 295 continue; |
| 296 | |
| 297 this_val = INTVAL (this_rtx); | |
| 298 switch (extend_op) | |
| 299 { | |
| 300 case ZERO_EXTEND: | |
| 301 this_val &= GET_MODE_MASK (GET_MODE (src)); | |
| 302 break; | |
| 303 case SIGN_EXTEND: | |
| 304 /* ??? In theory we're already extended. */ | |
| 305 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src))) | |
| 306 break; | |
| 307 default: | |
| 308 gcc_unreachable (); | |
| 309 } | |
| 310 this_rtx = GEN_INT (this_val); | |
| 311 } | |
| 312 #endif | |
| 313 this_cost = rtx_cost (this_rtx, SET, speed); | |
| 314 } | |
| 315 else if (REG_P (this_rtx)) | |
| 316 { | |
| 317 #ifdef LOAD_EXTEND_OP | |
| 318 if (extend_op != UNKNOWN) | |
| 319 { | |
| 320 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx); | |
| 321 this_cost = rtx_cost (this_rtx, SET, speed); | |
| 322 } | |
| 323 else | |
| 324 #endif | |
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325 this_cost = register_move_cost (GET_MODE (this_rtx), |
| 0 | 326 REGNO_REG_CLASS (REGNO (this_rtx)), |
| 327 dclass); | |
| 328 } | |
| 329 else | |
| 330 continue; | |
| 331 | |
| 332 /* If equal costs, prefer registers over anything else. That | |
| 333 tends to lead to smaller instructions on some machines. */ | |
| 334 if (this_cost < old_cost | |
| 335 || (this_cost == old_cost | |
| 336 && REG_P (this_rtx) | |
| 337 && !REG_P (SET_SRC (set)))) | |
| 338 { | |
| 339 #ifdef LOAD_EXTEND_OP | |
| 340 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD | |
| 341 && extend_op != UNKNOWN | |
| 342 #ifdef CANNOT_CHANGE_MODE_CLASS | |
| 343 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)), | |
| 344 word_mode, | |
| 345 REGNO_REG_CLASS (REGNO (SET_DEST (set)))) | |
| 346 #endif | |
| 347 ) | |
| 348 { | |
| 349 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set))); | |
| 350 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set)); | |
| 351 validate_change (insn, &SET_DEST (set), wide_dest, 1); | |
| 352 } | |
| 353 #endif | |
| 354 | |
| 355 validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1); | |
| 356 old_cost = this_cost, did_change = 1; | |
| 357 } | |
| 358 } | |
| 359 | |
| 360 return did_change; | |
| 361 } | |
| 362 | |
| 363 /* Try to replace operands in INSN with equivalent values that are already | |
| 364 in registers. This can be viewed as optional reloading. | |
| 365 | |
| 366 For each non-register operand in the insn, see if any hard regs are | |
| 367 known to be equivalent to that operand. Record the alternatives which | |
| 368 can accept these hard registers. Among all alternatives, select the | |
| 369 ones which are better or equal to the one currently matching, where | |
| 370 "better" is in terms of '?' and '!' constraints. Among the remaining | |
| 371 alternatives, select the one which replaces most operands with | |
| 372 hard registers. */ | |
| 373 | |
| 374 static int | |
| 375 reload_cse_simplify_operands (rtx insn, rtx testreg) | |
| 376 { | |
| 377 int i, j; | |
| 378 | |
| 379 /* For each operand, all registers that are equivalent to it. */ | |
| 380 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS]; | |
| 381 | |
| 382 const char *constraints[MAX_RECOG_OPERANDS]; | |
| 383 | |
| 384 /* Vector recording how bad an alternative is. */ | |
| 385 int *alternative_reject; | |
| 386 /* Vector recording how many registers can be introduced by choosing | |
| 387 this alternative. */ | |
| 388 int *alternative_nregs; | |
| 389 /* Array of vectors recording, for each operand and each alternative, | |
| 390 which hard register to substitute, or -1 if the operand should be | |
| 391 left as it is. */ | |
| 392 int *op_alt_regno[MAX_RECOG_OPERANDS]; | |
| 393 /* Array of alternatives, sorted in order of decreasing desirability. */ | |
| 394 int *alternative_order; | |
| 395 | |
| 396 extract_insn (insn); | |
| 397 | |
| 398 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0) | |
| 399 return 0; | |
| 400 | |
| 401 /* Figure out which alternative currently matches. */ | |
| 402 if (! constrain_operands (1)) | |
| 403 fatal_insn_not_found (insn); | |
| 404 | |
| 405 alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives); | |
| 406 alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives); | |
| 407 alternative_order = XALLOCAVEC (int, recog_data.n_alternatives); | |
| 408 memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int)); | |
| 409 memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int)); | |
| 410 | |
| 411 /* For each operand, find out which regs are equivalent. */ | |
| 412 for (i = 0; i < recog_data.n_operands; i++) | |
| 413 { | |
| 414 cselib_val *v; | |
| 415 struct elt_loc_list *l; | |
| 416 rtx op; | |
| 417 | |
| 418 CLEAR_HARD_REG_SET (equiv_regs[i]); | |
| 419 | |
| 420 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem | |
| 421 right, so avoid the problem here. Likewise if we have a constant | |
| 422 and the insn pattern doesn't tell us the mode we need. */ | |
| 423 if (LABEL_P (recog_data.operand[i]) | |
| 424 || (CONSTANT_P (recog_data.operand[i]) | |
| 425 && recog_data.operand_mode[i] == VOIDmode)) | |
| 426 continue; | |
| 427 | |
| 428 op = recog_data.operand[i]; | |
| 429 #ifdef LOAD_EXTEND_OP | |
| 430 if (MEM_P (op) | |
|
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431 && GET_MODE_BITSIZE (GET_MODE (op)) < BITS_PER_WORD |
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432 && LOAD_EXTEND_OP (GET_MODE (op)) != UNKNOWN) |
| 0 | 433 { |
| 434 rtx set = single_set (insn); | |
| 435 | |
| 436 /* We might have multiple sets, some of which do implicit | |
| 437 extension. Punt on this for now. */ | |
| 438 if (! set) | |
| 439 continue; | |
| 440 /* If the destination is also a MEM or a STRICT_LOW_PART, no | |
| 441 extension applies. | |
| 442 Also, if there is an explicit extension, we don't have to | |
| 443 worry about an implicit one. */ | |
| 444 else if (MEM_P (SET_DEST (set)) | |
| 445 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART | |
| 446 || GET_CODE (SET_SRC (set)) == ZERO_EXTEND | |
| 447 || GET_CODE (SET_SRC (set)) == SIGN_EXTEND) | |
| 448 ; /* Continue ordinary processing. */ | |
| 449 #ifdef CANNOT_CHANGE_MODE_CLASS | |
| 450 /* If the register cannot change mode to word_mode, it follows that | |
| 451 it cannot have been used in word_mode. */ | |
| 452 else if (REG_P (SET_DEST (set)) | |
| 453 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)), | |
| 454 word_mode, | |
| 455 REGNO_REG_CLASS (REGNO (SET_DEST (set))))) | |
| 456 ; /* Continue ordinary processing. */ | |
| 457 #endif | |
| 458 /* If this is a straight load, make the extension explicit. */ | |
| 459 else if (REG_P (SET_DEST (set)) | |
| 460 && recog_data.n_operands == 2 | |
| 461 && SET_SRC (set) == op | |
| 462 && SET_DEST (set) == recog_data.operand[1-i]) | |
| 463 { | |
| 464 validate_change (insn, recog_data.operand_loc[i], | |
|
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465 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op)), |
| 0 | 466 word_mode, op), |
| 467 1); | |
| 468 validate_change (insn, recog_data.operand_loc[1-i], | |
| 469 gen_rtx_REG (word_mode, REGNO (SET_DEST (set))), | |
| 470 1); | |
| 471 if (! apply_change_group ()) | |
| 472 return 0; | |
| 473 return reload_cse_simplify_operands (insn, testreg); | |
| 474 } | |
| 475 else | |
| 476 /* ??? There might be arithmetic operations with memory that are | |
| 477 safe to optimize, but is it worth the trouble? */ | |
| 478 continue; | |
| 479 } | |
| 480 #endif /* LOAD_EXTEND_OP */ | |
|
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481 if (side_effects_p (op)) |
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482 continue; |
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483 v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode); |
| 0 | 484 if (! v) |
| 485 continue; | |
| 486 | |
| 487 for (l = v->locs; l; l = l->next) | |
| 488 if (REG_P (l->loc)) | |
| 489 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc)); | |
| 490 } | |
| 491 | |
| 492 for (i = 0; i < recog_data.n_operands; i++) | |
| 493 { | |
| 494 enum machine_mode mode; | |
| 495 int regno; | |
| 496 const char *p; | |
| 497 | |
| 498 op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives); | |
| 499 for (j = 0; j < recog_data.n_alternatives; j++) | |
| 500 op_alt_regno[i][j] = -1; | |
| 501 | |
| 502 p = constraints[i] = recog_data.constraints[i]; | |
| 503 mode = recog_data.operand_mode[i]; | |
| 504 | |
| 505 /* Add the reject values for each alternative given by the constraints | |
| 506 for this operand. */ | |
| 507 j = 0; | |
| 508 while (*p != '\0') | |
| 509 { | |
| 510 char c = *p++; | |
| 511 if (c == ',') | |
| 512 j++; | |
| 513 else if (c == '?') | |
| 514 alternative_reject[j] += 3; | |
| 515 else if (c == '!') | |
| 516 alternative_reject[j] += 300; | |
| 517 } | |
| 518 | |
| 519 /* We won't change operands which are already registers. We | |
| 520 also don't want to modify output operands. */ | |
| 521 regno = true_regnum (recog_data.operand[i]); | |
| 522 if (regno >= 0 | |
| 523 || constraints[i][0] == '=' | |
| 524 || constraints[i][0] == '+') | |
| 525 continue; | |
| 526 | |
| 527 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
| 528 { | |
|
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529 enum reg_class rclass = NO_REGS; |
| 0 | 530 |
| 531 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) | |
| 532 continue; | |
| 533 | |
|
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534 SET_REGNO_RAW (testreg, regno); |
| 0 | 535 PUT_MODE (testreg, mode); |
| 536 | |
| 537 /* We found a register equal to this operand. Now look for all | |
| 538 alternatives that can accept this register and have not been | |
| 539 assigned a register they can use yet. */ | |
| 540 j = 0; | |
| 541 p = constraints[i]; | |
| 542 for (;;) | |
| 543 { | |
| 544 char c = *p; | |
| 545 | |
| 546 switch (c) | |
| 547 { | |
| 548 case '=': case '+': case '?': | |
| 549 case '#': case '&': case '!': | |
| 550 case '*': case '%': | |
| 551 case '0': case '1': case '2': case '3': case '4': | |
| 552 case '5': case '6': case '7': case '8': case '9': | |
| 553 case '<': case '>': case 'V': case 'o': | |
| 554 case 'E': case 'F': case 'G': case 'H': | |
| 555 case 's': case 'i': case 'n': | |
| 556 case 'I': case 'J': case 'K': case 'L': | |
| 557 case 'M': case 'N': case 'O': case 'P': | |
| 558 case 'p': case 'X': case TARGET_MEM_CONSTRAINT: | |
| 559 /* These don't say anything we care about. */ | |
| 560 break; | |
| 561 | |
| 562 case 'g': case 'r': | |
| 563 rclass = reg_class_subunion[(int) rclass][(int) GENERAL_REGS]; | |
| 564 break; | |
| 565 | |
| 566 default: | |
| 567 rclass | |
| 568 = (reg_class_subunion | |
| 569 [(int) rclass] | |
| 570 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]); | |
| 571 break; | |
| 572 | |
| 573 case ',': case '\0': | |
| 574 /* See if REGNO fits this alternative, and set it up as the | |
| 575 replacement register if we don't have one for this | |
| 576 alternative yet and the operand being replaced is not | |
| 577 a cheap CONST_INT. */ | |
| 578 if (op_alt_regno[i][j] == -1 | |
|
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579 && recog_data.alternative_enabled_p[j] |
| 0 | 580 && reg_fits_class_p (testreg, rclass, 0, mode) |
|
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581 && (!CONST_INT_P (recog_data.operand[i]) |
| 0 | 582 || (rtx_cost (recog_data.operand[i], SET, |
| 583 optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn))) | |
| 584 > rtx_cost (testreg, SET, | |
| 585 optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)))))) | |
| 586 { | |
| 587 alternative_nregs[j]++; | |
| 588 op_alt_regno[i][j] = regno; | |
| 589 } | |
| 590 j++; | |
|
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591 rclass = NO_REGS; |
| 0 | 592 break; |
| 593 } | |
| 594 p += CONSTRAINT_LEN (c, p); | |
| 595 | |
| 596 if (c == '\0') | |
| 597 break; | |
| 598 } | |
| 599 } | |
| 600 } | |
| 601 | |
| 602 /* Record all alternatives which are better or equal to the currently | |
| 603 matching one in the alternative_order array. */ | |
| 604 for (i = j = 0; i < recog_data.n_alternatives; i++) | |
| 605 if (alternative_reject[i] <= alternative_reject[which_alternative]) | |
| 606 alternative_order[j++] = i; | |
| 607 recog_data.n_alternatives = j; | |
| 608 | |
| 609 /* Sort it. Given a small number of alternatives, a dumb algorithm | |
| 610 won't hurt too much. */ | |
| 611 for (i = 0; i < recog_data.n_alternatives - 1; i++) | |
| 612 { | |
| 613 int best = i; | |
| 614 int best_reject = alternative_reject[alternative_order[i]]; | |
| 615 int best_nregs = alternative_nregs[alternative_order[i]]; | |
| 616 int tmp; | |
| 617 | |
| 618 for (j = i + 1; j < recog_data.n_alternatives; j++) | |
| 619 { | |
| 620 int this_reject = alternative_reject[alternative_order[j]]; | |
| 621 int this_nregs = alternative_nregs[alternative_order[j]]; | |
| 622 | |
| 623 if (this_reject < best_reject | |
| 624 || (this_reject == best_reject && this_nregs > best_nregs)) | |
| 625 { | |
| 626 best = j; | |
| 627 best_reject = this_reject; | |
| 628 best_nregs = this_nregs; | |
| 629 } | |
| 630 } | |
| 631 | |
| 632 tmp = alternative_order[best]; | |
| 633 alternative_order[best] = alternative_order[i]; | |
| 634 alternative_order[i] = tmp; | |
| 635 } | |
| 636 | |
| 637 /* Substitute the operands as determined by op_alt_regno for the best | |
| 638 alternative. */ | |
| 639 j = alternative_order[0]; | |
| 640 | |
| 641 for (i = 0; i < recog_data.n_operands; i++) | |
| 642 { | |
| 643 enum machine_mode mode = recog_data.operand_mode[i]; | |
| 644 if (op_alt_regno[i][j] == -1) | |
| 645 continue; | |
| 646 | |
| 647 validate_change (insn, recog_data.operand_loc[i], | |
| 648 gen_rtx_REG (mode, op_alt_regno[i][j]), 1); | |
| 649 } | |
| 650 | |
| 651 for (i = recog_data.n_dups - 1; i >= 0; i--) | |
| 652 { | |
| 653 int op = recog_data.dup_num[i]; | |
| 654 enum machine_mode mode = recog_data.operand_mode[op]; | |
| 655 | |
| 656 if (op_alt_regno[op][j] == -1) | |
| 657 continue; | |
| 658 | |
| 659 validate_change (insn, recog_data.dup_loc[i], | |
| 660 gen_rtx_REG (mode, op_alt_regno[op][j]), 1); | |
| 661 } | |
| 662 | |
| 663 return apply_change_group (); | |
| 664 } | |
| 665 | |
| 666 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg | |
| 667 addressing now. | |
| 668 This code might also be useful when reload gave up on reg+reg addressing | |
| 669 because of clashes between the return register and INDEX_REG_CLASS. */ | |
| 670 | |
| 671 /* The maximum number of uses of a register we can keep track of to | |
| 672 replace them with reg+reg addressing. */ | |
|
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673 #define RELOAD_COMBINE_MAX_USES 16 |
| 0 | 674 |
|
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675 /* Describes a recorded use of a register. */ |
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676 struct reg_use |
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677 { |
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678 /* The insn where a register has been used. */ |
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679 rtx insn; |
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680 /* Points to the memory reference enclosing the use, if any, NULL_RTX |
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681 otherwise. */ |
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682 rtx containing_mem; |
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683 /* Location of the register withing INSN. */ |
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684 rtx *usep; |
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685 /* The reverse uid of the insn. */ |
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686 int ruid; |
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687 }; |
| 0 | 688 |
| 689 /* If the register is used in some unknown fashion, USE_INDEX is negative. | |
| 690 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID | |
|
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691 indicates where it is first set or clobbered. |
| 0 | 692 Otherwise, USE_INDEX is the index of the last encountered use of the |
|
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693 register (which is first among these we have seen since we scan backwards). |
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694 USE_RUID indicates the first encountered, i.e. last, of these uses. |
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695 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS |
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696 with a constant offset; OFFSET contains this constant in that case. |
| 0 | 697 STORE_RUID is always meaningful if we only want to use a value in a |
| 698 register in a different place: it denotes the next insn in the insn | |
|
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699 stream (i.e. the last encountered) that sets or clobbers the register. |
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700 REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */ |
| 0 | 701 static struct |
| 702 { | |
| 703 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; | |
|
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704 rtx offset; |
| 0 | 705 int use_index; |
| 706 int store_ruid; | |
|
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707 int real_store_ruid; |
| 0 | 708 int use_ruid; |
|
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709 bool all_offsets_match; |
| 0 | 710 } reg_state[FIRST_PSEUDO_REGISTER]; |
| 711 | |
| 712 /* Reverse linear uid. This is increased in reload_combine while scanning | |
| 713 the instructions from last to first. It is used to set last_label_ruid | |
| 714 and the store_ruid / use_ruid fields in reg_state. */ | |
| 715 static int reload_combine_ruid; | |
| 716 | |
|
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717 /* The RUID of the last label we encountered in reload_combine. */ |
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718 static int last_label_ruid; |
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719 |
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720 /* The RUID of the last jump we encountered in reload_combine. */ |
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721 static int last_jump_ruid; |
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722 |
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723 /* The register numbers of the first and last index register. A value of |
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724 -1 in LAST_INDEX_REG indicates that we've previously computed these |
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725 values and found no suitable index registers. */ |
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726 static int first_index_reg = -1; |
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727 static int last_index_reg; |
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728 |
| 0 | 729 #define LABEL_LIVE(LABEL) \ |
| 730 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) | |
| 731 | |
|
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732 /* Subroutine of reload_combine_split_ruids, called to fix up a single |
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733 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */ |
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734 |
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735 static inline void |
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736 reload_combine_split_one_ruid (int *pruid, int split_ruid) |
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737 { |
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738 if (*pruid > split_ruid) |
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739 (*pruid)++; |
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740 } |
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741 |
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742 /* Called when we insert a new insn in a position we've already passed in |
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743 the scan. Examine all our state, increasing all ruids that are higher |
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744 than SPLIT_RUID by one in order to make room for a new insn. */ |
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745 |
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746 static void |
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747 reload_combine_split_ruids (int split_ruid) |
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748 { |
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749 unsigned i; |
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750 |
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751 reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid); |
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752 reload_combine_split_one_ruid (&last_label_ruid, split_ruid); |
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753 reload_combine_split_one_ruid (&last_jump_ruid, split_ruid); |
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754 |
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755 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
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756 { |
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757 int j, idx = reg_state[i].use_index; |
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758 reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid); |
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759 reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid); |
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760 reload_combine_split_one_ruid (®_state[i].real_store_ruid, |
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761 split_ruid); |
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762 if (idx < 0) |
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763 continue; |
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764 for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++) |
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765 { |
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766 reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid, |
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767 split_ruid); |
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768 } |
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769 } |
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770 } |
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771 |
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772 /* Called when we are about to rescan a previously encountered insn with |
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773 reload_combine_note_use after modifying some part of it. This clears all |
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774 information about uses in that particular insn. */ |
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775 |
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776 static void |
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777 reload_combine_purge_insn_uses (rtx insn) |
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778 { |
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779 unsigned i; |
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780 |
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781 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
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782 { |
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783 int j, k, idx = reg_state[i].use_index; |
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784 if (idx < 0) |
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785 continue; |
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786 j = k = RELOAD_COMBINE_MAX_USES; |
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787 while (j-- > idx) |
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788 { |
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789 if (reg_state[i].reg_use[j].insn != insn) |
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790 { |
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791 k--; |
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792 if (k != j) |
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793 reg_state[i].reg_use[k] = reg_state[i].reg_use[j]; |
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794 } |
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795 } |
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796 reg_state[i].use_index = k; |
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797 } |
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798 } |
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799 |
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800 /* Called when we need to forget about all uses of REGNO after an insn |
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801 which is identified by RUID. */ |
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802 |
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803 static void |
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804 reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid) |
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805 { |
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806 int j, k, idx = reg_state[regno].use_index; |
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807 if (idx < 0) |
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808 return; |
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809 j = k = RELOAD_COMBINE_MAX_USES; |
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810 while (j-- > idx) |
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811 { |
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812 if (reg_state[regno].reg_use[j].ruid >= ruid) |
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813 { |
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814 k--; |
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815 if (k != j) |
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816 reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j]; |
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817 } |
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818 } |
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819 reg_state[regno].use_index = k; |
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820 } |
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821 |
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822 /* Find the use of REGNO with the ruid that is highest among those |
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823 lower than RUID_LIMIT, and return it if it is the only use of this |
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824 reg in the insn. Return NULL otherwise. */ |
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825 |
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826 static struct reg_use * |
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827 reload_combine_closest_single_use (unsigned regno, int ruid_limit) |
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828 { |
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829 int i, best_ruid = 0; |
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830 int use_idx = reg_state[regno].use_index; |
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831 struct reg_use *retval; |
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832 |
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833 if (use_idx < 0) |
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834 return NULL; |
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835 retval = NULL; |
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836 for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++) |
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837 { |
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838 struct reg_use *use = reg_state[regno].reg_use + i; |
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839 int this_ruid = use->ruid; |
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840 if (this_ruid >= ruid_limit) |
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841 continue; |
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842 if (this_ruid > best_ruid) |
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843 { |
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844 best_ruid = this_ruid; |
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845 retval = use; |
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846 } |
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847 else if (this_ruid == best_ruid) |
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848 retval = NULL; |
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849 } |
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850 if (last_label_ruid >= best_ruid) |
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851 return NULL; |
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852 return retval; |
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853 } |
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854 |
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855 /* After we've moved an add insn, fix up any debug insns that occur |
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856 between the old location of the add and the new location. REG is |
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857 the destination register of the add insn; REPLACEMENT is the |
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858 SET_SRC of the add. FROM and TO specify the range in which we |
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859 should make this change on debug insns. */ |
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860 |
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861 static void |
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862 fixup_debug_insns (rtx reg, rtx replacement, rtx from, rtx to) |
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863 { |
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864 rtx insn; |
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865 for (insn = from; insn != to; insn = NEXT_INSN (insn)) |
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866 { |
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867 rtx t; |
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868 |
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869 if (!DEBUG_INSN_P (insn)) |
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870 continue; |
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871 |
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872 t = INSN_VAR_LOCATION_LOC (insn); |
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873 t = simplify_replace_rtx (t, reg, replacement); |
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874 validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0); |
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875 } |
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876 } |
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877 |
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878 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG |
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879 with SRC in the insn described by USE, taking costs into account. Return |
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880 true if we made the replacement. */ |
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881 |
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882 static bool |
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883 try_replace_in_use (struct reg_use *use, rtx reg, rtx src) |
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884 { |
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885 rtx use_insn = use->insn; |
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886 rtx mem = use->containing_mem; |
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887 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn)); |
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888 |
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889 if (mem != NULL_RTX) |
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890 { |
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891 addr_space_t as = MEM_ADDR_SPACE (mem); |
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892 rtx oldaddr = XEXP (mem, 0); |
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893 rtx newaddr = NULL_RTX; |
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894 int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed); |
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895 int new_cost; |
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896 |
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897 newaddr = simplify_replace_rtx (oldaddr, reg, src); |
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898 if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as)) |
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899 { |
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900 XEXP (mem, 0) = newaddr; |
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901 new_cost = address_cost (newaddr, GET_MODE (mem), as, speed); |
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902 XEXP (mem, 0) = oldaddr; |
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903 if (new_cost <= old_cost |
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904 && validate_change (use_insn, |
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905 &XEXP (mem, 0), newaddr, 0)) |
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906 return true; |
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907 } |
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908 } |
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909 else |
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910 { |
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911 rtx new_set = single_set (use_insn); |
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912 if (new_set |
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|
913 && REG_P (SET_DEST (new_set)) |
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914 && GET_CODE (SET_SRC (new_set)) == PLUS |
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915 && REG_P (XEXP (SET_SRC (new_set), 0)) |
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916 && CONSTANT_P (XEXP (SET_SRC (new_set), 1))) |
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|
917 { |
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918 rtx new_src; |
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919 int old_cost = rtx_cost (SET_SRC (new_set), SET, speed); |
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920 |
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921 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg)); |
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922 new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src); |
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923 |
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924 if (rtx_cost (new_src, SET, speed) <= old_cost |
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925 && validate_change (use_insn, &SET_SRC (new_set), |
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926 new_src, 0)) |
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927 return true; |
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928 } |
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929 } |
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930 return false; |
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931 } |
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932 |
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933 /* Called by reload_combine when scanning INSN. This function tries to detect |
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934 patterns where a constant is added to a register, and the result is used |
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935 in an address. |
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936 Return true if no further processing is needed on INSN; false if it wasn't |
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937 recognized and should be handled normally. */ |
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938 |
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939 static bool |
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940 reload_combine_recognize_const_pattern (rtx insn) |
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941 { |
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942 int from_ruid = reload_combine_ruid; |
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943 rtx set, pat, reg, src, addreg; |
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944 unsigned int regno; |
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945 struct reg_use *use; |
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946 bool must_move_add; |
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947 rtx add_moved_after_insn = NULL_RTX; |
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948 int add_moved_after_ruid = 0; |
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949 int clobbered_regno = -1; |
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950 |
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951 set = single_set (insn); |
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952 if (set == NULL_RTX) |
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953 return false; |
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954 |
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955 reg = SET_DEST (set); |
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956 src = SET_SRC (set); |
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957 if (!REG_P (reg) |
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958 || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1 |
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959 || GET_MODE (reg) != Pmode |
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960 || reg == stack_pointer_rtx) |
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961 return false; |
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962 |
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963 regno = REGNO (reg); |
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964 |
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965 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either |
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966 uses of REG1 inside an address, or inside another add insn. If |
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967 possible and profitable, merge the addition into subsequent |
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968 uses. */ |
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969 if (GET_CODE (src) != PLUS |
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970 || !REG_P (XEXP (src, 0)) |
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971 || !CONSTANT_P (XEXP (src, 1))) |
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972 return false; |
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973 |
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974 addreg = XEXP (src, 0); |
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975 must_move_add = rtx_equal_p (reg, addreg); |
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976 |
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977 pat = PATTERN (insn); |
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978 if (must_move_add && set != pat) |
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979 { |
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980 /* We have to be careful when moving the add; apart from the |
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981 single_set there may also be clobbers. Recognize one special |
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982 case, that of one clobber alongside the set (likely a clobber |
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983 of the CC register). */ |
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984 gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL); |
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985 if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set |
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986 || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER |
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987 || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0))) |
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988 return false; |
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989 clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0)); |
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990 } |
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991 |
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992 do |
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993 { |
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994 use = reload_combine_closest_single_use (regno, from_ruid); |
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995 |
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996 if (use) |
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997 /* Start the search for the next use from here. */ |
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998 from_ruid = use->ruid; |
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999 |
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1000 if (use && GET_MODE (*use->usep) == Pmode) |
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1001 { |
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1002 bool delete_add = false; |
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1003 rtx use_insn = use->insn; |
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1004 int use_ruid = use->ruid; |
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1005 |
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1006 /* Avoid moving the add insn past a jump. */ |
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1007 if (must_move_add && use_ruid <= last_jump_ruid) |
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1008 break; |
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1009 |
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1010 /* If the add clobbers another hard reg in parallel, don't move |
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1011 it past a real set of this hard reg. */ |
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1012 if (must_move_add && clobbered_regno >= 0 |
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1013 && reg_state[clobbered_regno].real_store_ruid >= use_ruid) |
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1014 break; |
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1015 |
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1016 #ifdef HAVE_cc0 |
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1017 /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */ |
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1018 if (must_move_add && sets_cc0_p (PATTERN (use_insn))) |
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1019 break; |
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1020 #endif |
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1021 |
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1022 gcc_assert (reg_state[regno].store_ruid <= use_ruid); |
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1023 /* Avoid moving a use of ADDREG past a point where it is stored. */ |
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1024 if (reg_state[REGNO (addreg)].store_ruid > use_ruid) |
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1025 break; |
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1026 |
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1027 /* We also must not move the addition past an insn that sets |
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1028 the same register, unless we can combine two add insns. */ |
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1029 if (must_move_add && reg_state[regno].store_ruid == use_ruid) |
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1030 { |
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1031 if (use->containing_mem == NULL_RTX) |
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1032 delete_add = true; |
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1033 else |
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1034 break; |
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1035 } |
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1036 |
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1037 if (try_replace_in_use (use, reg, src)) |
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1038 { |
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1039 reload_combine_purge_insn_uses (use_insn); |
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1040 reload_combine_note_use (&PATTERN (use_insn), use_insn, |
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1041 use_ruid, NULL_RTX); |
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1042 |
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1043 if (delete_add) |
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1044 { |
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1045 fixup_debug_insns (reg, src, insn, use_insn); |
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1046 delete_insn (insn); |
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1047 return true; |
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1048 } |
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1049 if (must_move_add) |
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1050 { |
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1051 add_moved_after_insn = use_insn; |
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1052 add_moved_after_ruid = use_ruid; |
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1053 } |
|
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|
1054 continue; |
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1055 } |
|
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1056 } |
|
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1057 /* If we get here, we couldn't handle this use. */ |
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1058 if (must_move_add) |
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|
1059 break; |
|
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1060 } |
|
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|
1061 while (use); |
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1062 |
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1063 if (!must_move_add || add_moved_after_insn == NULL_RTX) |
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|
1064 /* Process the add normally. */ |
|
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|
1065 return false; |
|
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|
1066 |
|
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|
1067 fixup_debug_insns (reg, src, insn, add_moved_after_insn); |
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|
1068 |
|
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|
1069 reorder_insns (insn, insn, add_moved_after_insn); |
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1070 reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid); |
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1071 reload_combine_split_ruids (add_moved_after_ruid - 1); |
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|
1072 reload_combine_note_use (&PATTERN (insn), insn, |
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1073 add_moved_after_ruid, NULL_RTX); |
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1074 reg_state[regno].store_ruid = add_moved_after_ruid; |
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1075 |
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|
1076 return true; |
|
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1077 } |
|
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1078 |
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1079 /* Called by reload_combine when scanning INSN. Try to detect a pattern we |
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1080 can handle and improve. Return true if no further processing is needed on |
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1081 INSN; false if it wasn't recognized and should be handled normally. */ |
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1082 |
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|
1083 static bool |
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1084 reload_combine_recognize_pattern (rtx insn) |
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1085 { |
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1086 rtx set, reg, src; |
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1087 unsigned int regno; |
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1088 |
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1089 set = single_set (insn); |
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1090 if (set == NULL_RTX) |
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|
1091 return false; |
|
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1092 |
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1093 reg = SET_DEST (set); |
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1094 src = SET_SRC (set); |
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1095 if (!REG_P (reg) |
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1096 || hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] != 1) |
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1097 return false; |
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1098 |
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1099 regno = REGNO (reg); |
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1100 |
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1101 /* Look for (set (REGX) (CONST_INT)) |
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1102 (set (REGX) (PLUS (REGX) (REGY))) |
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1103 ... |
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1104 ... (MEM (REGX)) ... |
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1105 and convert it to |
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1106 (set (REGZ) (CONST_INT)) |
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1107 ... |
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1108 ... (MEM (PLUS (REGZ) (REGY)))... . |
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1109 |
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1110 First, check that we have (set (REGX) (PLUS (REGX) (REGY))) |
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1111 and that we know all uses of REGX before it dies. |
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1112 Also, explicitly check that REGX != REGY; our life information |
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1113 does not yet show whether REGY changes in this insn. */ |
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1114 |
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1115 if (GET_CODE (src) == PLUS |
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1116 && reg_state[regno].all_offsets_match |
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1117 && last_index_reg != -1 |
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1118 && REG_P (XEXP (src, 1)) |
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1119 && rtx_equal_p (XEXP (src, 0), reg) |
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1120 && !rtx_equal_p (XEXP (src, 1), reg) |
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1121 && reg_state[regno].use_index >= 0 |
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1122 && reg_state[regno].use_index < RELOAD_COMBINE_MAX_USES |
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1123 && last_label_ruid < reg_state[regno].use_ruid) |
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1124 { |
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1125 rtx base = XEXP (src, 1); |
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1126 rtx prev = prev_nonnote_nondebug_insn (insn); |
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1127 rtx prev_set = prev ? single_set (prev) : NULL_RTX; |
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1128 rtx index_reg = NULL_RTX; |
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1129 rtx reg_sum = NULL_RTX; |
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1130 int i; |
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1131 |
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1132 /* Now we need to set INDEX_REG to an index register (denoted as |
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1133 REGZ in the illustration above) and REG_SUM to the expression |
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1134 register+register that we want to use to substitute uses of REG |
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1135 (typically in MEMs) with. First check REG and BASE for being |
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1136 index registers; we can use them even if they are not dead. */ |
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1137 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) |
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1138 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], |
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1139 REGNO (base))) |
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1140 { |
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1141 index_reg = reg; |
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1142 reg_sum = src; |
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1143 } |
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1144 else |
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1145 { |
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1146 /* Otherwise, look for a free index register. Since we have |
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1147 checked above that neither REG nor BASE are index registers, |
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1148 if we find anything at all, it will be different from these |
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1149 two registers. */ |
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1150 for (i = first_index_reg; i <= last_index_reg; i++) |
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1151 { |
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1152 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i) |
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1153 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES |
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1154 && reg_state[i].store_ruid <= reg_state[regno].use_ruid |
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1155 && (call_used_regs[i] || df_regs_ever_live_p (i)) |
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1156 && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM) |
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1157 && !fixed_regs[i] && !global_regs[i] |
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1158 && hard_regno_nregs[i][GET_MODE (reg)] == 1 |
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1159 && targetm.hard_regno_scratch_ok (i)) |
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1160 { |
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1161 index_reg = gen_rtx_REG (GET_MODE (reg), i); |
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1162 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); |
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1163 break; |
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1164 } |
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1165 } |
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1166 } |
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1167 |
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1168 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that |
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1169 (REGY), i.e. BASE, is not clobbered before the last use we'll |
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1170 create. */ |
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1171 if (reg_sum |
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1172 && prev_set |
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1173 && CONST_INT_P (SET_SRC (prev_set)) |
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1174 && rtx_equal_p (SET_DEST (prev_set), reg) |
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1175 && (reg_state[REGNO (base)].store_ruid |
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1176 <= reg_state[regno].use_ruid)) |
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1177 { |
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1178 /* Change destination register and, if necessary, the constant |
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1179 value in PREV, the constant loading instruction. */ |
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1180 validate_change (prev, &SET_DEST (prev_set), index_reg, 1); |
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1181 if (reg_state[regno].offset != const0_rtx) |
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1182 validate_change (prev, |
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1183 &SET_SRC (prev_set), |
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1184 GEN_INT (INTVAL (SET_SRC (prev_set)) |
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1185 + INTVAL (reg_state[regno].offset)), |
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1186 1); |
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1187 |
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1188 /* Now for every use of REG that we have recorded, replace REG |
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1189 with REG_SUM. */ |
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1190 for (i = reg_state[regno].use_index; |
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1191 i < RELOAD_COMBINE_MAX_USES; i++) |
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1192 validate_unshare_change (reg_state[regno].reg_use[i].insn, |
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1193 reg_state[regno].reg_use[i].usep, |
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1194 /* Each change must have its own |
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1195 replacement. */ |
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1196 reg_sum, 1); |
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1197 |
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1198 if (apply_change_group ()) |
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1199 { |
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1200 struct reg_use *lowest_ruid = NULL; |
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1201 |
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1202 /* For every new use of REG_SUM, we have to record the use |
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1203 of BASE therein, i.e. operand 1. */ |
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1204 for (i = reg_state[regno].use_index; |
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1205 i < RELOAD_COMBINE_MAX_USES; i++) |
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1206 { |
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1207 struct reg_use *use = reg_state[regno].reg_use + i; |
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1208 reload_combine_note_use (&XEXP (*use->usep, 1), use->insn, |
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1209 use->ruid, use->containing_mem); |
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1210 if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid) |
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1211 lowest_ruid = use; |
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1212 } |
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1213 |
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1214 fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn); |
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1215 |
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1216 /* Delete the reg-reg addition. */ |
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1217 delete_insn (insn); |
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1218 |
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1219 if (reg_state[regno].offset != const0_rtx) |
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1220 /* Previous REG_EQUIV / REG_EQUAL notes for PREV |
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1221 are now invalid. */ |
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1222 remove_reg_equal_equiv_notes (prev); |
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1223 |
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1224 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; |
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1225 return true; |
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1226 } |
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1227 } |
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1228 } |
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1229 return false; |
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1230 } |
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1231 |
| 0 | 1232 static void |
| 1233 reload_combine (void) | |
| 1234 { | |
|
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1235 rtx insn, prev; |
| 0 | 1236 basic_block bb; |
| 1237 unsigned int r; | |
| 1238 int min_labelno, n_labels; | |
| 1239 HARD_REG_SET ever_live_at_start, *label_live; | |
| 1240 | |
| 1241 /* To avoid wasting too much time later searching for an index register, | |
| 1242 determine the minimum and maximum index register numbers. */ | |
|
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1243 if (INDEX_REG_CLASS == NO_REGS) |
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1244 last_index_reg = -1; |
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1245 else if (first_index_reg == -1 && last_index_reg == 0) |
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1246 { |
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1247 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
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1248 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) |
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1249 { |
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1250 if (first_index_reg == -1) |
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1251 first_index_reg = r; |
| 0 | 1252 |
|
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1253 last_index_reg = r; |
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1254 } |
| 0 | 1255 |
|
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1256 /* If no index register is available, we can quit now. Set LAST_INDEX_REG |
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1257 to -1 so we'll know to quit early the next time we get here. */ |
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1258 if (first_index_reg == -1) |
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1259 { |
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1260 last_index_reg = -1; |
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1261 return; |
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1262 } |
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1263 } |
| 0 | 1264 |
| 1265 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime | |
| 1266 information is a bit fuzzy immediately after reload, but it's | |
| 1267 still good enough to determine which registers are live at a jump | |
| 1268 destination. */ | |
| 1269 min_labelno = get_first_label_num (); | |
| 1270 n_labels = max_label_num () - min_labelno; | |
| 1271 label_live = XNEWVEC (HARD_REG_SET, n_labels); | |
| 1272 CLEAR_HARD_REG_SET (ever_live_at_start); | |
| 1273 | |
| 1274 FOR_EACH_BB_REVERSE (bb) | |
| 1275 { | |
| 1276 insn = BB_HEAD (bb); | |
| 1277 if (LABEL_P (insn)) | |
| 1278 { | |
| 1279 HARD_REG_SET live; | |
| 1280 bitmap live_in = df_get_live_in (bb); | |
| 1281 | |
| 1282 REG_SET_TO_HARD_REG_SET (live, live_in); | |
| 1283 compute_use_by_pseudos (&live, live_in); | |
| 1284 COPY_HARD_REG_SET (LABEL_LIVE (insn), live); | |
| 1285 IOR_HARD_REG_SET (ever_live_at_start, live); | |
| 1286 } | |
| 1287 } | |
| 1288 | |
| 1289 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ | |
|
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1290 last_label_ruid = last_jump_ruid = reload_combine_ruid = 0; |
| 0 | 1291 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
| 1292 { | |
|
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1293 reg_state[r].store_ruid = 0; |
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1294 reg_state[r].real_store_ruid = 0; |
| 0 | 1295 if (fixed_regs[r]) |
| 1296 reg_state[r].use_index = -1; | |
| 1297 else | |
| 1298 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
| 1299 } | |
| 1300 | |
|
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1301 for (insn = get_last_insn (); insn; insn = prev) |
| 0 | 1302 { |
|
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1303 bool control_flow_insn; |
| 0 | 1304 rtx note; |
| 1305 | |
|
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1306 prev = PREV_INSN (insn); |
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1307 |
| 0 | 1308 /* We cannot do our optimization across labels. Invalidating all the use |
| 1309 information we have would be costly, so we just note where the label | |
| 1310 is and then later disable any optimization that would cross it. */ | |
| 1311 if (LABEL_P (insn)) | |
| 1312 last_label_ruid = reload_combine_ruid; | |
| 1313 else if (BARRIER_P (insn)) | |
| 1314 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
| 1315 if (! fixed_regs[r]) | |
| 1316 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
| 1317 | |
|
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1318 if (! NONDEBUG_INSN_P (insn)) |
| 0 | 1319 continue; |
| 1320 | |
| 1321 reload_combine_ruid++; | |
| 1322 | |
|
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1323 control_flow_insn = control_flow_insn_p (insn); |
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1324 if (control_flow_insn) |
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1325 last_jump_ruid = reload_combine_ruid; |
| 0 | 1326 |
|
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1327 if (reload_combine_recognize_const_pattern (insn) |
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1328 || reload_combine_recognize_pattern (insn)) |
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1329 continue; |
| 0 | 1330 |
| 1331 note_stores (PATTERN (insn), reload_combine_note_store, NULL); | |
| 1332 | |
| 1333 if (CALL_P (insn)) | |
| 1334 { | |
| 1335 rtx link; | |
| 1336 | |
| 1337 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) | |
| 1338 if (call_used_regs[r]) | |
| 1339 { | |
| 1340 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; | |
| 1341 reg_state[r].store_ruid = reload_combine_ruid; | |
| 1342 } | |
| 1343 | |
| 1344 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; | |
| 1345 link = XEXP (link, 1)) | |
| 1346 { | |
| 1347 rtx usage_rtx = XEXP (XEXP (link, 0), 0); | |
| 1348 if (REG_P (usage_rtx)) | |
| 1349 { | |
| 1350 unsigned int i; | |
| 1351 unsigned int start_reg = REGNO (usage_rtx); | |
|
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1352 unsigned int num_regs |
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1353 = hard_regno_nregs[start_reg][GET_MODE (usage_rtx)]; |
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1354 unsigned int end_reg = start_reg + num_regs - 1; |
| 0 | 1355 for (i = start_reg; i <= end_reg; i++) |
| 1356 if (GET_CODE (XEXP (link, 0)) == CLOBBER) | |
| 1357 { | |
| 1358 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; | |
| 1359 reg_state[i].store_ruid = reload_combine_ruid; | |
| 1360 } | |
| 1361 else | |
| 1362 reg_state[i].use_index = -1; | |
| 1363 } | |
| 1364 } | |
|
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1365 } |
| 0 | 1366 |
|
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1367 if (control_flow_insn && GET_CODE (PATTERN (insn)) != RETURN) |
| 0 | 1368 { |
| 1369 /* Non-spill registers might be used at the call destination in | |
| 1370 some unknown fashion, so we have to mark the unknown use. */ | |
| 1371 HARD_REG_SET *live; | |
| 1372 | |
| 1373 if ((condjump_p (insn) || condjump_in_parallel_p (insn)) | |
| 1374 && JUMP_LABEL (insn)) | |
| 1375 live = &LABEL_LIVE (JUMP_LABEL (insn)); | |
| 1376 else | |
| 1377 live = &ever_live_at_start; | |
| 1378 | |
|
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1379 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) |
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1380 if (TEST_HARD_REG_BIT (*live, r)) |
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1381 reg_state[r].use_index = -1; |
| 0 | 1382 } |
| 1383 | |
|
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1384 reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid, |
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1385 NULL_RTX); |
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1386 |
| 0 | 1387 for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) |
| 1388 { | |
|
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1389 if (REG_NOTE_KIND (note) == REG_INC && REG_P (XEXP (note, 0))) |
| 0 | 1390 { |
| 1391 int regno = REGNO (XEXP (note, 0)); | |
| 1392 reg_state[regno].store_ruid = reload_combine_ruid; | |
|
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1393 reg_state[regno].real_store_ruid = reload_combine_ruid; |
| 0 | 1394 reg_state[regno].use_index = -1; |
| 1395 } | |
| 1396 } | |
| 1397 } | |
| 1398 | |
| 1399 free (label_live); | |
| 1400 } | |
| 1401 | |
| 1402 /* Check if DST is a register or a subreg of a register; if it is, | |
|
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1403 update store_ruid, real_store_ruid and use_index in the reg_state |
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1404 structure accordingly. Called via note_stores from reload_combine. */ |
| 0 | 1405 |
| 1406 static void | |
| 1407 reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED) | |
| 1408 { | |
| 1409 int regno = 0; | |
| 1410 int i; | |
| 1411 enum machine_mode mode = GET_MODE (dst); | |
| 1412 | |
| 1413 if (GET_CODE (dst) == SUBREG) | |
| 1414 { | |
| 1415 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), | |
| 1416 GET_MODE (SUBREG_REG (dst)), | |
| 1417 SUBREG_BYTE (dst), | |
| 1418 GET_MODE (dst)); | |
| 1419 dst = SUBREG_REG (dst); | |
| 1420 } | |
|
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1421 |
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1422 /* Some targets do argument pushes without adding REG_INC notes. */ |
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1423 |
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1424 if (MEM_P (dst)) |
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1425 { |
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1426 dst = XEXP (dst, 0); |
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1427 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC |
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1428 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC |
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1429 || GET_CODE (dst) == PRE_MODIFY || GET_CODE (dst) == POST_MODIFY) |
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1430 { |
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1431 regno = REGNO (XEXP (dst, 0)); |
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1432 mode = GET_MODE (XEXP (dst, 0)); |
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1433 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) |
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1434 { |
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1435 /* We could probably do better, but for now mark the register |
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1436 as used in an unknown fashion and set/clobbered at this |
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1437 insn. */ |
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1438 reg_state[i].use_index = -1; |
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1439 reg_state[i].store_ruid = reload_combine_ruid; |
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1440 reg_state[i].real_store_ruid = reload_combine_ruid; |
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1441 } |
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1442 } |
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1443 else |
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1444 return; |
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1445 } |
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1446 |
| 0 | 1447 if (!REG_P (dst)) |
| 1448 return; | |
| 1449 regno += REGNO (dst); | |
| 1450 | |
| 1451 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be | |
| 1452 careful with registers / register parts that are not full words. | |
| 1453 Similarly for ZERO_EXTRACT. */ | |
|
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1454 if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT |
| 0 | 1455 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) |
| 1456 { | |
| 1457 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) | |
| 1458 { | |
| 1459 reg_state[i].use_index = -1; | |
| 1460 reg_state[i].store_ruid = reload_combine_ruid; | |
|
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1461 reg_state[i].real_store_ruid = reload_combine_ruid; |
| 0 | 1462 } |
| 1463 } | |
| 1464 else | |
| 1465 { | |
| 1466 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) | |
| 1467 { | |
| 1468 reg_state[i].store_ruid = reload_combine_ruid; | |
|
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1469 if (GET_CODE (set) == SET) |
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1470 reg_state[i].real_store_ruid = reload_combine_ruid; |
| 0 | 1471 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; |
| 1472 } | |
| 1473 } | |
| 1474 } | |
| 1475 | |
| 1476 /* XP points to a piece of rtl that has to be checked for any uses of | |
| 1477 registers. | |
| 1478 *XP is the pattern of INSN, or a part of it. | |
| 1479 Called from reload_combine, and recursively by itself. */ | |
| 1480 static void | |
|
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1481 reload_combine_note_use (rtx *xp, rtx insn, int ruid, rtx containing_mem) |
| 0 | 1482 { |
| 1483 rtx x = *xp; | |
| 1484 enum rtx_code code = x->code; | |
| 1485 const char *fmt; | |
| 1486 int i, j; | |
| 1487 rtx offset = const0_rtx; /* For the REG case below. */ | |
| 1488 | |
| 1489 switch (code) | |
| 1490 { | |
| 1491 case SET: | |
| 1492 if (REG_P (SET_DEST (x))) | |
| 1493 { | |
|
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1494 reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX); |
| 0 | 1495 return; |
| 1496 } | |
| 1497 break; | |
| 1498 | |
| 1499 case USE: | |
| 1500 /* If this is the USE of a return value, we can't change it. */ | |
| 1501 if (REG_P (XEXP (x, 0)) && REG_FUNCTION_VALUE_P (XEXP (x, 0))) | |
| 1502 { | |
| 1503 /* Mark the return register as used in an unknown fashion. */ | |
| 1504 rtx reg = XEXP (x, 0); | |
| 1505 int regno = REGNO (reg); | |
| 1506 int nregs = hard_regno_nregs[regno][GET_MODE (reg)]; | |
| 1507 | |
| 1508 while (--nregs >= 0) | |
| 1509 reg_state[regno + nregs].use_index = -1; | |
| 1510 return; | |
| 1511 } | |
| 1512 break; | |
| 1513 | |
| 1514 case CLOBBER: | |
| 1515 if (REG_P (SET_DEST (x))) | |
| 1516 { | |
| 1517 /* No spurious CLOBBERs of pseudo registers may remain. */ | |
| 1518 gcc_assert (REGNO (SET_DEST (x)) < FIRST_PSEUDO_REGISTER); | |
| 1519 return; | |
| 1520 } | |
| 1521 break; | |
| 1522 | |
| 1523 case PLUS: | |
| 1524 /* We are interested in (plus (reg) (const_int)) . */ | |
| 1525 if (!REG_P (XEXP (x, 0)) | |
|
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1526 || !CONST_INT_P (XEXP (x, 1))) |
| 0 | 1527 break; |
| 1528 offset = XEXP (x, 1); | |
| 1529 x = XEXP (x, 0); | |
| 1530 /* Fall through. */ | |
| 1531 case REG: | |
| 1532 { | |
| 1533 int regno = REGNO (x); | |
| 1534 int use_index; | |
| 1535 int nregs; | |
| 1536 | |
| 1537 /* No spurious USEs of pseudo registers may remain. */ | |
| 1538 gcc_assert (regno < FIRST_PSEUDO_REGISTER); | |
| 1539 | |
| 1540 nregs = hard_regno_nregs[regno][GET_MODE (x)]; | |
| 1541 | |
| 1542 /* We can't substitute into multi-hard-reg uses. */ | |
| 1543 if (nregs > 1) | |
| 1544 { | |
| 1545 while (--nregs >= 0) | |
| 1546 reg_state[regno + nregs].use_index = -1; | |
| 1547 return; | |
| 1548 } | |
| 1549 | |
|
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1550 /* We may be called to update uses in previously seen insns. |
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1551 Don't add uses beyond the last store we saw. */ |
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1552 if (ruid < reg_state[regno].store_ruid) |
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1553 return; |
|
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1554 |
| 0 | 1555 /* If this register is already used in some unknown fashion, we |
| 1556 can't do anything. | |
| 1557 If we decrement the index from zero to -1, we can't store more | |
| 1558 uses, so this register becomes used in an unknown fashion. */ | |
| 1559 use_index = --reg_state[regno].use_index; | |
| 1560 if (use_index < 0) | |
| 1561 return; | |
| 1562 | |
|
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1563 if (use_index == RELOAD_COMBINE_MAX_USES - 1) |
| 0 | 1564 { |
| 1565 /* This is the first use of this register we have seen since we | |
| 1566 marked it as dead. */ | |
| 1567 reg_state[regno].offset = offset; | |
|
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1568 reg_state[regno].all_offsets_match = true; |
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1569 reg_state[regno].use_ruid = ruid; |
| 0 | 1570 } |
|
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1571 else |
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1572 { |
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1573 if (reg_state[regno].use_ruid > ruid) |
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1574 reg_state[regno].use_ruid = ruid; |
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1575 |
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1576 if (! rtx_equal_p (offset, reg_state[regno].offset)) |
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1577 reg_state[regno].all_offsets_match = false; |
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1578 } |
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1579 |
| 0 | 1580 reg_state[regno].reg_use[use_index].insn = insn; |
|
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1581 reg_state[regno].reg_use[use_index].ruid = ruid; |
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1582 reg_state[regno].reg_use[use_index].containing_mem = containing_mem; |
| 0 | 1583 reg_state[regno].reg_use[use_index].usep = xp; |
| 1584 return; | |
| 1585 } | |
| 1586 | |
|
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|
1587 case MEM: |
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1588 containing_mem = x; |
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|
1589 break; |
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|
1590 |
| 0 | 1591 default: |
| 1592 break; | |
| 1593 } | |
| 1594 | |
| 1595 /* Recursively process the components of X. */ | |
| 1596 fmt = GET_RTX_FORMAT (code); | |
| 1597 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
| 1598 { | |
| 1599 if (fmt[i] == 'e') | |
|
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1600 reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem); |
| 0 | 1601 else if (fmt[i] == 'E') |
| 1602 { | |
| 1603 for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
|
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|
1604 reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid, |
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|
1605 containing_mem); |
| 0 | 1606 } |
| 1607 } | |
| 1608 } | |
| 1609 | |
| 1610 /* See if we can reduce the cost of a constant by replacing a move | |
| 1611 with an add. We track situations in which a register is set to a | |
| 1612 constant or to a register plus a constant. */ | |
| 1613 /* We cannot do our optimization across labels. Invalidating all the | |
| 1614 information about register contents we have would be costly, so we | |
| 1615 use move2add_last_label_luid to note where the label is and then | |
| 1616 later disable any optimization that would cross it. | |
|
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1617 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n] |
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1618 are only valid if reg_set_luid[n] is greater than |
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|
1619 move2add_last_label_luid. */ |
| 0 | 1620 static int reg_set_luid[FIRST_PSEUDO_REGISTER]; |
| 1621 | |
| 1622 /* If reg_base_reg[n] is negative, register n has been set to | |
|
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|
1623 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n]. |
| 0 | 1624 If reg_base_reg[n] is non-negative, register n has been set to the |
| 1625 sum of reg_offset[n] and the value of register reg_base_reg[n] | |
| 1626 before reg_set_luid[n], calculated in mode reg_mode[n] . */ | |
| 1627 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; | |
| 1628 static int reg_base_reg[FIRST_PSEUDO_REGISTER]; | |
|
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1629 static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER]; |
| 0 | 1630 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; |
| 1631 | |
| 1632 /* move2add_luid is linearly increased while scanning the instructions | |
| 1633 from first to last. It is used to set reg_set_luid in | |
| 1634 reload_cse_move2add and move2add_note_store. */ | |
| 1635 static int move2add_luid; | |
| 1636 | |
| 1637 /* move2add_last_label_luid is set whenever a label is found. Labels | |
| 1638 invalidate all previously collected reg_offset data. */ | |
| 1639 static int move2add_last_label_luid; | |
| 1640 | |
| 1641 /* ??? We don't know how zero / sign extension is handled, hence we | |
| 1642 can't go from a narrower to a wider mode. */ | |
| 1643 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \ | |
| 1644 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \ | |
| 1645 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \ | |
| 1646 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \ | |
| 1647 GET_MODE_BITSIZE (INMODE)))) | |
| 1648 | |
|
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1649 /* This function is called with INSN that sets REG to (SYM + OFF), |
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1650 while REG is known to already have value (SYM + offset). |
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1651 This function tries to change INSN into an add instruction |
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1652 (set (REG) (plus (REG) (OFF - offset))) using the known value. |
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1653 It also updates the information about REG's known value. |
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1654 Return true if we made a change. */ |
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1655 |
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|
1656 static bool |
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1657 move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn) |
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1658 { |
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1659 rtx pat = PATTERN (insn); |
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1660 rtx src = SET_SRC (pat); |
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|
1661 int regno = REGNO (reg); |
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|
1662 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno], |
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|
1663 GET_MODE (reg)); |
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1664 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
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|
1665 bool changed = false; |
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1666 |
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1667 /* (set (reg) (plus (reg) (const_int 0))) is not canonical; |
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1668 use (set (reg) (reg)) instead. |
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1669 We don't delete this insn, nor do we convert it into a |
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1670 note, to avoid losing register notes or the return |
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1671 value flag. jump2 already knows how to get rid of |
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1672 no-op moves. */ |
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1673 if (new_src == const0_rtx) |
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1674 { |
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1675 /* If the constants are different, this is a |
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1676 truncation, that, if turned into (set (reg) |
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1677 (reg)), would be discarded. Maybe we should |
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1678 try a truncMN pattern? */ |
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1679 if (INTVAL (off) == reg_offset [regno]) |
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1680 changed = validate_change (insn, &SET_SRC (pat), reg, 0); |
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1681 } |
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1682 else |
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1683 { |
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1684 struct full_rtx_costs oldcst, newcst; |
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1685 rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); |
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1686 |
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1687 get_full_rtx_cost (pat, SET, &oldcst); |
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1688 SET_SRC (pat) = tem; |
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|
1689 get_full_rtx_cost (pat, SET, &newcst); |
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1690 SET_SRC (pat) = src; |
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1691 |
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|
1692 if (costs_lt_p (&newcst, &oldcst, speed) |
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1693 && have_add2_insn (reg, new_src)) |
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1694 changed = validate_change (insn, &SET_SRC (pat), tem, 0); |
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1695 else if (sym == NULL_RTX && GET_MODE (reg) != BImode) |
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1696 { |
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1697 enum machine_mode narrow_mode; |
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1698 for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); |
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1699 narrow_mode != VOIDmode |
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1700 && narrow_mode != GET_MODE (reg); |
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1701 narrow_mode = GET_MODE_WIDER_MODE (narrow_mode)) |
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1702 { |
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1703 if (have_insn_for (STRICT_LOW_PART, narrow_mode) |
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1704 && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode)) |
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1705 == (INTVAL (off) & ~GET_MODE_MASK (narrow_mode)))) |
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1706 { |
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1707 rtx narrow_reg = gen_rtx_REG (narrow_mode, |
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1708 REGNO (reg)); |
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1709 rtx narrow_src = gen_int_mode (INTVAL (off), |
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1710 narrow_mode); |
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1711 rtx new_set |
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1712 = gen_rtx_SET (VOIDmode, |
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1713 gen_rtx_STRICT_LOW_PART (VOIDmode, |
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1714 narrow_reg), |
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1715 narrow_src); |
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1716 changed = validate_change (insn, &PATTERN (insn), |
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1717 new_set, 0); |
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1718 if (changed) |
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1719 break; |
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1720 } |
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1721 } |
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1722 } |
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1723 } |
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1724 reg_set_luid[regno] = move2add_luid; |
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1725 reg_base_reg[regno] = -1; |
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1726 reg_mode[regno] = GET_MODE (reg); |
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1727 reg_symbol_ref[regno] = sym; |
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1728 reg_offset[regno] = INTVAL (off); |
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1729 return changed; |
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1730 } |
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1731 |
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1732 |
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1733 /* This function is called with INSN that sets REG to (SYM + OFF), |
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1734 but REG doesn't have known value (SYM + offset). This function |
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1735 tries to find another register which is known to already have |
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1736 value (SYM + offset) and change INSN into an add instruction |
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1737 (set (REG) (plus (the found register) (OFF - offset))) if such |
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1738 a register is found. It also updates the information about |
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1739 REG's known value. |
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1740 Return true iff we made a change. */ |
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1741 |
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1742 static bool |
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1743 move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn) |
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1744 { |
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1745 rtx pat = PATTERN (insn); |
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1746 rtx src = SET_SRC (pat); |
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1747 int regno = REGNO (reg); |
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1748 int min_regno = 0; |
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1749 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); |
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1750 int i; |
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1751 bool changed = false; |
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1752 struct full_rtx_costs oldcst, newcst, mincst; |
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1753 rtx plus_expr; |
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1754 |
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1755 init_costs_to_max (&mincst); |
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1756 get_full_rtx_cost (pat, SET, &oldcst); |
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1757 |
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1758 plus_expr = gen_rtx_PLUS (GET_MODE (reg), reg, const0_rtx); |
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1759 SET_SRC (pat) = plus_expr; |
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1760 |
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1761 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
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1762 if (reg_set_luid[i] > move2add_last_label_luid |
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1763 && reg_mode[i] == GET_MODE (reg) |
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1764 && reg_base_reg[i] < 0 |
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1765 && reg_symbol_ref[i] != NULL_RTX |
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1766 && rtx_equal_p (sym, reg_symbol_ref[i])) |
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1767 { |
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1768 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[i], |
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1769 GET_MODE (reg)); |
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1770 /* (set (reg) (plus (reg) (const_int 0))) is not canonical; |
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1771 use (set (reg) (reg)) instead. |
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1772 We don't delete this insn, nor do we convert it into a |
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1773 note, to avoid losing register notes or the return |
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1774 value flag. jump2 already knows how to get rid of |
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1775 no-op moves. */ |
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1776 if (new_src == const0_rtx) |
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1777 { |
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1778 init_costs_to_zero (&mincst); |
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1779 min_regno = i; |
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1780 break; |
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1781 } |
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1782 else |
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1783 { |
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1784 XEXP (plus_expr, 1) = new_src; |
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1785 get_full_rtx_cost (pat, SET, &newcst); |
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1786 |
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1787 if (costs_lt_p (&newcst, &mincst, speed)) |
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1788 { |
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1789 mincst = newcst; |
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1790 min_regno = i; |
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1791 } |
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1792 } |
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1793 } |
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1794 SET_SRC (pat) = src; |
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1795 |
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1796 if (costs_lt_p (&mincst, &oldcst, speed)) |
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1797 { |
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1798 rtx tem; |
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1799 |
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1800 tem = gen_rtx_REG (GET_MODE (reg), min_regno); |
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1801 if (i != min_regno) |
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1802 { |
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1803 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[min_regno], |
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1804 GET_MODE (reg)); |
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1805 tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src); |
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1806 } |
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1807 if (validate_change (insn, &SET_SRC (pat), tem, 0)) |
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1808 changed = true; |
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1809 } |
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1810 reg_set_luid[regno] = move2add_luid; |
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1811 reg_base_reg[regno] = -1; |
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1812 reg_mode[regno] = GET_MODE (reg); |
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1813 reg_symbol_ref[regno] = sym; |
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1814 reg_offset[regno] = INTVAL (off); |
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1815 return changed; |
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1816 } |
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1817 |
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1818 /* Convert move insns with constant inputs to additions if they are cheaper. |
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1819 Return true if any changes were made. */ |
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1820 static bool |
| 0 | 1821 reload_cse_move2add (rtx first) |
| 1822 { | |
| 1823 int i; | |
| 1824 rtx insn; | |
|
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1825 bool changed = false; |
| 0 | 1826 |
| 1827 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
|
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1828 { |
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1829 reg_set_luid[i] = 0; |
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1830 reg_offset[i] = 0; |
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1831 reg_base_reg[i] = 0; |
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1832 reg_symbol_ref[i] = NULL_RTX; |
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1833 reg_mode[i] = VOIDmode; |
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1834 } |
| 0 | 1835 |
| 1836 move2add_last_label_luid = 0; | |
| 1837 move2add_luid = 2; | |
| 1838 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++) | |
| 1839 { | |
| 1840 rtx pat, note; | |
| 1841 | |
| 1842 if (LABEL_P (insn)) | |
| 1843 { | |
| 1844 move2add_last_label_luid = move2add_luid; | |
| 1845 /* We're going to increment move2add_luid twice after a | |
| 1846 label, so that we can use move2add_last_label_luid + 1 as | |
| 1847 the luid for constants. */ | |
| 1848 move2add_luid++; | |
| 1849 continue; | |
| 1850 } | |
| 1851 if (! INSN_P (insn)) | |
| 1852 continue; | |
| 1853 pat = PATTERN (insn); | |
| 1854 /* For simplicity, we only perform this optimization on | |
| 1855 straightforward SETs. */ | |
| 1856 if (GET_CODE (pat) == SET | |
| 1857 && REG_P (SET_DEST (pat))) | |
| 1858 { | |
| 1859 rtx reg = SET_DEST (pat); | |
| 1860 int regno = REGNO (reg); | |
| 1861 rtx src = SET_SRC (pat); | |
| 1862 | |
| 1863 /* Check if we have valid information on the contents of this | |
| 1864 register in the mode of REG. */ | |
| 1865 if (reg_set_luid[regno] > move2add_last_label_luid | |
| 1866 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]) | |
| 1867 && dbg_cnt (cse2_move2add)) | |
| 1868 { | |
| 1869 /* Try to transform (set (REGX) (CONST_INT A)) | |
| 1870 ... | |
| 1871 (set (REGX) (CONST_INT B)) | |
| 1872 to | |
| 1873 (set (REGX) (CONST_INT A)) | |
| 1874 ... | |
| 1875 (set (REGX) (plus (REGX) (CONST_INT B-A))) | |
| 1876 or | |
| 1877 (set (REGX) (CONST_INT A)) | |
| 1878 ... | |
| 1879 (set (STRICT_LOW_PART (REGX)) (CONST_INT B)) | |
| 1880 */ | |
| 1881 | |
|
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1882 if (CONST_INT_P (src) |
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1883 && reg_base_reg[regno] < 0 |
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1884 && reg_symbol_ref[regno] == NULL_RTX) |
| 0 | 1885 { |
|
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1886 changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn); |
| 0 | 1887 continue; |
| 1888 } | |
| 1889 | |
| 1890 /* Try to transform (set (REGX) (REGY)) | |
| 1891 (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
| 1892 ... | |
| 1893 (set (REGX) (REGY)) | |
| 1894 (set (REGX) (PLUS (REGX) (CONST_INT B))) | |
| 1895 to | |
| 1896 (set (REGX) (REGY)) | |
| 1897 (set (REGX) (PLUS (REGX) (CONST_INT A))) | |
| 1898 ... | |
| 1899 (set (REGX) (plus (REGX) (CONST_INT B-A))) */ | |
| 1900 else if (REG_P (src) | |
| 1901 && reg_set_luid[regno] == reg_set_luid[REGNO (src)] | |
| 1902 && reg_base_reg[regno] == reg_base_reg[REGNO (src)] | |
| 1903 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), | |
| 1904 reg_mode[REGNO (src)])) | |
| 1905 { | |
|
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1906 rtx next = next_nonnote_nondebug_insn (insn); |
| 0 | 1907 rtx set = NULL_RTX; |
| 1908 if (next) | |
| 1909 set = single_set (next); | |
| 1910 if (set | |
| 1911 && SET_DEST (set) == reg | |
| 1912 && GET_CODE (SET_SRC (set)) == PLUS | |
| 1913 && XEXP (SET_SRC (set), 0) == reg | |
|
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1914 && CONST_INT_P (XEXP (SET_SRC (set), 1))) |
| 0 | 1915 { |
| 1916 rtx src3 = XEXP (SET_SRC (set), 1); | |
| 1917 HOST_WIDE_INT added_offset = INTVAL (src3); | |
| 1918 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; | |
| 1919 HOST_WIDE_INT regno_offset = reg_offset[regno]; | |
| 1920 rtx new_src = | |
| 1921 gen_int_mode (added_offset | |
| 1922 + base_offset | |
| 1923 - regno_offset, | |
| 1924 GET_MODE (reg)); | |
| 1925 bool success = false; | |
| 1926 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | |
| 1927 | |
| 1928 if (new_src == const0_rtx) | |
| 1929 /* See above why we create (set (reg) (reg)) here. */ | |
| 1930 success | |
| 1931 = validate_change (next, &SET_SRC (set), reg, 0); | |
|
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1932 else |
| 0 | 1933 { |
|
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1934 rtx old_src = SET_SRC (set); |
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1935 struct full_rtx_costs oldcst, newcst; |
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1936 rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); |
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1937 |
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1938 get_full_rtx_cost (set, SET, &oldcst); |
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1939 SET_SRC (set) = tem; |
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1940 get_full_rtx_cost (tem, SET, &newcst); |
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1941 SET_SRC (set) = old_src; |
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1942 costs_add_n_insns (&oldcst, 1); |
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1943 |
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1944 if (costs_lt_p (&newcst, &oldcst, speed) |
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1945 && have_add2_insn (reg, new_src)) |
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1946 { |
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1947 rtx newpat = gen_rtx_SET (VOIDmode, reg, tem); |
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1948 success |
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1949 = validate_change (next, &PATTERN (next), |
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1950 newpat, 0); |
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1951 } |
| 0 | 1952 } |
| 1953 if (success) | |
| 1954 delete_insn (insn); | |
|
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1955 changed |= success; |
| 0 | 1956 insn = next; |
| 1957 reg_mode[regno] = GET_MODE (reg); | |
| 1958 reg_offset[regno] = | |
| 1959 trunc_int_for_mode (added_offset + base_offset, | |
| 1960 GET_MODE (reg)); | |
| 1961 continue; | |
| 1962 } | |
| 1963 } | |
| 1964 } | |
|
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1965 |
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1966 /* Try to transform |
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1967 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) |
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1968 ... |
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1969 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B)))) |
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1970 to |
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1971 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) |
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1972 ... |
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1973 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */ |
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1974 if ((GET_CODE (src) == SYMBOL_REF |
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1975 || (GET_CODE (src) == CONST |
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1976 && GET_CODE (XEXP (src, 0)) == PLUS |
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1977 && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF |
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1978 && CONST_INT_P (XEXP (XEXP (src, 0), 1)))) |
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1979 && dbg_cnt (cse2_move2add)) |
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1980 { |
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1981 rtx sym, off; |
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1982 |
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1983 if (GET_CODE (src) == SYMBOL_REF) |
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1984 { |
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1985 sym = src; |
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1986 off = const0_rtx; |
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1987 } |
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1988 else |
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1989 { |
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1990 sym = XEXP (XEXP (src, 0), 0); |
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1991 off = XEXP (XEXP (src, 0), 1); |
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1992 } |
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1993 |
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1994 /* If the reg already contains the value which is sum of |
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1995 sym and some constant value, we can use an add2 insn. */ |
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1996 if (reg_set_luid[regno] > move2add_last_label_luid |
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1997 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]) |
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1998 && reg_base_reg[regno] < 0 |
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1999 && reg_symbol_ref[regno] != NULL_RTX |
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2000 && rtx_equal_p (sym, reg_symbol_ref[regno])) |
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2001 changed |= move2add_use_add2_insn (reg, sym, off, insn); |
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2002 |
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2003 /* Otherwise, we have to find a register whose value is sum |
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2004 of sym and some constant value. */ |
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2005 else |
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2006 changed |= move2add_use_add3_insn (reg, sym, off, insn); |
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2007 |
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2008 continue; |
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2009 } |
| 0 | 2010 } |
| 2011 | |
| 2012 for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
| 2013 { | |
| 2014 if (REG_NOTE_KIND (note) == REG_INC | |
| 2015 && REG_P (XEXP (note, 0))) | |
| 2016 { | |
| 2017 /* Reset the information about this register. */ | |
| 2018 int regno = REGNO (XEXP (note, 0)); | |
| 2019 if (regno < FIRST_PSEUDO_REGISTER) | |
| 2020 reg_set_luid[regno] = 0; | |
| 2021 } | |
| 2022 } | |
|
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2023 note_stores (PATTERN (insn), move2add_note_store, insn); |
| 0 | 2024 |
| 2025 /* If INSN is a conditional branch, we try to extract an | |
| 2026 implicit set out of it. */ | |
| 2027 if (any_condjump_p (insn)) | |
| 2028 { | |
| 2029 rtx cnd = fis_get_condition (insn); | |
| 2030 | |
| 2031 if (cnd != NULL_RTX | |
| 2032 && GET_CODE (cnd) == NE | |
| 2033 && REG_P (XEXP (cnd, 0)) | |
| 2034 && !reg_set_p (XEXP (cnd, 0), insn) | |
| 2035 /* The following two checks, which are also in | |
| 2036 move2add_note_store, are intended to reduce the | |
| 2037 number of calls to gen_rtx_SET to avoid memory | |
| 2038 allocation if possible. */ | |
| 2039 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0))) | |
| 2040 && hard_regno_nregs[REGNO (XEXP (cnd, 0))][GET_MODE (XEXP (cnd, 0))] == 1 | |
|
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2041 && CONST_INT_P (XEXP (cnd, 1))) |
| 0 | 2042 { |
| 2043 rtx implicit_set = | |
| 2044 gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1)); | |
|
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2045 move2add_note_store (SET_DEST (implicit_set), implicit_set, insn); |
| 0 | 2046 } |
| 2047 } | |
| 2048 | |
| 2049 /* If this is a CALL_INSN, all call used registers are stored with | |
| 2050 unknown values. */ | |
| 2051 if (CALL_P (insn)) | |
| 2052 { | |
| 2053 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
| 2054 { | |
| 2055 if (call_used_regs[i]) | |
| 2056 /* Reset the information about this register. */ | |
| 2057 reg_set_luid[i] = 0; | |
| 2058 } | |
| 2059 } | |
| 2060 } | |
|
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2061 return changed; |
| 0 | 2062 } |
| 2063 | |
|
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2064 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which |
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2065 contains SET. |
| 0 | 2066 Update reg_set_luid, reg_offset and reg_base_reg accordingly. |
| 2067 Called from reload_cse_move2add via note_stores. */ | |
| 2068 | |
| 2069 static void | |
|
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2070 move2add_note_store (rtx dst, const_rtx set, void *data) |
| 0 | 2071 { |
|
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2072 rtx insn = (rtx) data; |
| 0 | 2073 unsigned int regno = 0; |
| 2074 unsigned int nregs = 0; | |
| 2075 unsigned int i; | |
| 2076 enum machine_mode mode = GET_MODE (dst); | |
| 2077 | |
| 2078 if (GET_CODE (dst) == SUBREG) | |
| 2079 { | |
| 2080 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), | |
| 2081 GET_MODE (SUBREG_REG (dst)), | |
| 2082 SUBREG_BYTE (dst), | |
| 2083 GET_MODE (dst)); | |
| 2084 nregs = subreg_nregs (dst); | |
| 2085 dst = SUBREG_REG (dst); | |
| 2086 } | |
| 2087 | |
| 2088 /* Some targets do argument pushes without adding REG_INC notes. */ | |
| 2089 | |
| 2090 if (MEM_P (dst)) | |
| 2091 { | |
| 2092 dst = XEXP (dst, 0); | |
| 2093 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC | |
| 2094 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC) | |
| 2095 reg_set_luid[REGNO (XEXP (dst, 0))] = 0; | |
| 2096 return; | |
| 2097 } | |
| 2098 if (!REG_P (dst)) | |
| 2099 return; | |
| 2100 | |
| 2101 regno += REGNO (dst); | |
| 2102 if (!nregs) | |
| 2103 nregs = hard_regno_nregs[regno][mode]; | |
| 2104 | |
| 2105 if (SCALAR_INT_MODE_P (GET_MODE (dst)) | |
|
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2106 && nregs == 1 && GET_CODE (set) == SET) |
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2107 { |
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2108 rtx note, sym = NULL_RTX; |
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2109 HOST_WIDE_INT off; |
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2110 |
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2111 note = find_reg_equal_equiv_note (insn); |
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2112 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF) |
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2113 { |
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2114 sym = XEXP (note, 0); |
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2115 off = 0; |
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2116 } |
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2117 else if (note && GET_CODE (XEXP (note, 0)) == CONST |
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2118 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS |
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2119 && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF |
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2120 && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1))) |
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2121 { |
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2122 sym = XEXP (XEXP (XEXP (note, 0), 0), 0); |
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2123 off = INTVAL (XEXP (XEXP (XEXP (note, 0), 0), 1)); |
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2124 } |
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2125 |
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2126 if (sym != NULL_RTX) |
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2127 { |
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2128 reg_base_reg[regno] = -1; |
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2129 reg_symbol_ref[regno] = sym; |
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2130 reg_offset[regno] = off; |
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2131 reg_mode[regno] = mode; |
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2132 reg_set_luid[regno] = move2add_luid; |
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2133 return; |
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2134 } |
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2135 } |
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2136 |
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2137 if (SCALAR_INT_MODE_P (GET_MODE (dst)) |
| 0 | 2138 && nregs == 1 && GET_CODE (set) == SET |
| 2139 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT | |
| 2140 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) | |
| 2141 { | |
| 2142 rtx src = SET_SRC (set); | |
| 2143 rtx base_reg; | |
| 2144 HOST_WIDE_INT offset; | |
| 2145 int base_regno; | |
| 2146 /* This may be different from mode, if SET_DEST (set) is a | |
| 2147 SUBREG. */ | |
| 2148 enum machine_mode dst_mode = GET_MODE (dst); | |
| 2149 | |
| 2150 switch (GET_CODE (src)) | |
| 2151 { | |
| 2152 case PLUS: | |
| 2153 if (REG_P (XEXP (src, 0))) | |
| 2154 { | |
| 2155 base_reg = XEXP (src, 0); | |
| 2156 | |
|
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2157 if (CONST_INT_P (XEXP (src, 1))) |
| 0 | 2158 offset = INTVAL (XEXP (src, 1)); |
| 2159 else if (REG_P (XEXP (src, 1)) | |
| 2160 && (reg_set_luid[REGNO (XEXP (src, 1))] | |
| 2161 > move2add_last_label_luid) | |
| 2162 && (MODES_OK_FOR_MOVE2ADD | |
| 2163 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))) | |
| 2164 { | |
|
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2165 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0 |
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2166 && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX) |
| 0 | 2167 offset = reg_offset[REGNO (XEXP (src, 1))]; |
| 2168 /* Maybe the first register is known to be a | |
| 2169 constant. */ | |
| 2170 else if (reg_set_luid[REGNO (base_reg)] | |
| 2171 > move2add_last_label_luid | |
| 2172 && (MODES_OK_FOR_MOVE2ADD | |
|
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2173 (dst_mode, reg_mode[REGNO (base_reg)])) |
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2174 && reg_base_reg[REGNO (base_reg)] < 0 |
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2175 && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX) |
| 0 | 2176 { |
| 2177 offset = reg_offset[REGNO (base_reg)]; | |
| 2178 base_reg = XEXP (src, 1); | |
| 2179 } | |
| 2180 else | |
| 2181 goto invalidate; | |
| 2182 } | |
| 2183 else | |
| 2184 goto invalidate; | |
| 2185 | |
| 2186 break; | |
| 2187 } | |
| 2188 | |
| 2189 goto invalidate; | |
| 2190 | |
| 2191 case REG: | |
| 2192 base_reg = src; | |
| 2193 offset = 0; | |
| 2194 break; | |
| 2195 | |
| 2196 case CONST_INT: | |
| 2197 /* Start tracking the register as a constant. */ | |
| 2198 reg_base_reg[regno] = -1; | |
|
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|
2199 reg_symbol_ref[regno] = NULL_RTX; |
| 0 | 2200 reg_offset[regno] = INTVAL (SET_SRC (set)); |
| 2201 /* We assign the same luid to all registers set to constants. */ | |
| 2202 reg_set_luid[regno] = move2add_last_label_luid + 1; | |
| 2203 reg_mode[regno] = mode; | |
| 2204 return; | |
| 2205 | |
| 2206 default: | |
| 2207 invalidate: | |
| 2208 /* Invalidate the contents of the register. */ | |
| 2209 reg_set_luid[regno] = 0; | |
| 2210 return; | |
| 2211 } | |
| 2212 | |
| 2213 base_regno = REGNO (base_reg); | |
| 2214 /* If information about the base register is not valid, set it | |
| 2215 up as a new base register, pretending its value is known | |
| 2216 starting from the current insn. */ | |
| 2217 if (reg_set_luid[base_regno] <= move2add_last_label_luid) | |
| 2218 { | |
| 2219 reg_base_reg[base_regno] = base_regno; | |
|
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2220 reg_symbol_ref[base_regno] = NULL_RTX; |
| 0 | 2221 reg_offset[base_regno] = 0; |
| 2222 reg_set_luid[base_regno] = move2add_luid; | |
| 2223 reg_mode[base_regno] = mode; | |
| 2224 } | |
| 2225 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode, | |
| 2226 reg_mode[base_regno])) | |
| 2227 goto invalidate; | |
| 2228 | |
| 2229 reg_mode[regno] = mode; | |
| 2230 | |
| 2231 /* Copy base information from our base register. */ | |
| 2232 reg_set_luid[regno] = reg_set_luid[base_regno]; | |
| 2233 reg_base_reg[regno] = reg_base_reg[base_regno]; | |
|
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2234 reg_symbol_ref[regno] = reg_symbol_ref[base_regno]; |
| 0 | 2235 |
| 2236 /* Compute the sum of the offsets or constants. */ | |
| 2237 reg_offset[regno] = trunc_int_for_mode (offset | |
| 2238 + reg_offset[base_regno], | |
| 2239 dst_mode); | |
| 2240 } | |
| 2241 else | |
| 2242 { | |
| 2243 unsigned int endregno = regno + nregs; | |
| 2244 | |
| 2245 for (i = regno; i < endregno; i++) | |
| 2246 /* Reset the information about this register. */ | |
| 2247 reg_set_luid[i] = 0; | |
| 2248 } | |
| 2249 } | |
| 2250 | |
| 2251 static bool | |
| 2252 gate_handle_postreload (void) | |
| 2253 { | |
| 2254 return (optimize > 0 && reload_completed); | |
| 2255 } | |
| 2256 | |
| 2257 | |
| 2258 static unsigned int | |
| 2259 rest_of_handle_postreload (void) | |
| 2260 { | |
| 2261 if (!dbg_cnt (postreload_cse)) | |
| 2262 return 0; | |
| 2263 | |
| 2264 /* Do a very simple CSE pass over just the hard registers. */ | |
| 2265 reload_cse_regs (get_insns ()); | |
| 2266 /* Reload_cse_regs can eliminate potentially-trapping MEMs. | |
| 2267 Remove any EH edges associated with them. */ | |
|
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2268 if (cfun->can_throw_non_call_exceptions) |
| 0 | 2269 purge_all_dead_edges (); |
| 2270 | |
| 2271 return 0; | |
| 2272 } | |
| 2273 | |
| 2274 struct rtl_opt_pass pass_postreload_cse = | |
| 2275 { | |
| 2276 { | |
| 2277 RTL_PASS, | |
| 2278 "postreload", /* name */ | |
| 2279 gate_handle_postreload, /* gate */ | |
| 2280 rest_of_handle_postreload, /* execute */ | |
| 2281 NULL, /* sub */ | |
| 2282 NULL, /* next */ | |
| 2283 0, /* static_pass_number */ | |
| 2284 TV_RELOAD_CSE_REGS, /* tv_id */ | |
| 2285 0, /* properties_required */ | |
| 2286 0, /* properties_provided */ | |
| 2287 0, /* properties_destroyed */ | |
| 2288 0, /* todo_flags_start */ | |
| 2289 TODO_df_finish | TODO_verify_rtl_sharing | | |
| 2290 TODO_dump_func /* todo_flags_finish */ | |
| 2291 } | |
| 2292 }; |