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1 ;; ARM Cortex-R4 scheduling description.
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2 ;; Copyright (C) 2007, 2008 Free Software Foundation, Inc.
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3 ;; Contributed by CodeSourcery.
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4
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_automaton "cortex_r4")
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22
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23 ;; We approximate the dual-issue constraints of this core using four
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24 ;; "issue units" and a reservation matrix as follows. The numbers indicate
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25 ;; the instruction groups' preferences in order. Multiple entries for
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26 ;; the same numbered preference indicate units that must be reserved
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27 ;; together.
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28 ;;
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29 ;; Issue unit: A B C ALU
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30 ;;
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31 ;; ALU w/o reg shift 1st 2nd 1st and 2nd
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32 ;; ALU w/ reg shift 1st 2nd 2nd 1st and 2nd
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33 ;; Moves 1st 2nd 2nd
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34 ;; Multiplication 1st 1st
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35 ;; Division 1st 1st
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36 ;; Load/store single 1st 1st
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37 ;; Other load/store 1st 1st
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38 ;; Branches 1st
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39
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40 (define_cpu_unit "cortex_r4_issue_a" "cortex_r4")
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41 (define_cpu_unit "cortex_r4_issue_b" "cortex_r4")
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42 (define_cpu_unit "cortex_r4_issue_c" "cortex_r4")
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43 (define_cpu_unit "cortex_r4_issue_alu" "cortex_r4")
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44
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45 (define_reservation "cortex_r4_alu"
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46 "(cortex_r4_issue_a+cortex_r4_issue_alu)|\
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47 (cortex_r4_issue_b+cortex_r4_issue_alu)")
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48 (define_reservation "cortex_r4_alu_shift_reg"
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49 "(cortex_r4_issue_a+cortex_r4_issue_alu)|\
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50 (cortex_r4_issue_b+cortex_r4_issue_c+\
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51 cortex_r4_issue_alu)")
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52 (define_reservation "cortex_r4_mov"
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53 "cortex_r4_issue_a|(cortex_r4_issue_b+\
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54 cortex_r4_issue_alu)")
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55 (define_reservation "cortex_r4_mul" "cortex_r4_issue_a+cortex_r4_issue_alu")
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56 (define_reservation "cortex_r4_mul_2"
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57 "(cortex_r4_issue_a+cortex_r4_issue_alu)*2")
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58 ;; Division instructions execute out-of-order with respect to the
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59 ;; rest of the pipeline and only require reservations on their first and
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60 ;; final cycles.
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61 (define_reservation "cortex_r4_div_9"
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62 "cortex_r4_issue_a+cortex_r4_issue_alu,\
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63 nothing*7,\
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64 cortex_r4_issue_a+cortex_r4_issue_alu")
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65 (define_reservation "cortex_r4_div_10"
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66 "cortex_r4_issue_a+cortex_r4_issue_alu,\
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67 nothing*8,\
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68 cortex_r4_issue_a+cortex_r4_issue_alu")
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69 (define_reservation "cortex_r4_load_store"
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70 "cortex_r4_issue_a+cortex_r4_issue_c")
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71 (define_reservation "cortex_r4_load_store_2"
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72 "(cortex_r4_issue_a+cortex_r4_issue_b)*2")
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73 (define_reservation "cortex_r4_branch" "cortex_r4_issue_b")
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74
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75 ;; We assume that all instructions are unconditional.
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76
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77 ;; Data processing instructions. Moves without shifts are kept separate
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78 ;; for the purposes of the dual-issue constraints above.
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79 (define_insn_reservation "cortex_r4_alu" 2
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80 (and (eq_attr "tune_cortexr4" "yes")
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81 (and (eq_attr "type" "alu")
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82 (not (eq_attr "insn" "mov"))))
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83 "cortex_r4_alu")
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84
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85 (define_insn_reservation "cortex_r4_mov" 2
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86 (and (eq_attr "tune_cortexr4" "yes")
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87 (and (eq_attr "type" "alu")
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88 (eq_attr "insn" "mov")))
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89 "cortex_r4_mov")
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90
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91 (define_insn_reservation "cortex_r4_alu_shift" 2
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92 (and (eq_attr "tune_cortexr4" "yes")
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93 (eq_attr "type" "alu_shift"))
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94 "cortex_r4_alu")
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95
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96 (define_insn_reservation "cortex_r4_alu_shift_reg" 2
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97 (and (eq_attr "tune_cortexr4" "yes")
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98 (eq_attr "type" "alu_shift_reg"))
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99 "cortex_r4_alu_shift_reg")
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100
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101 ;; An ALU instruction followed by an ALU instruction with no early dep.
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102 (define_bypass 1 "cortex_r4_alu,cortex_r4_alu_shift,cortex_r4_alu_shift_reg,\
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103 cortex_r4_mov"
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104 "cortex_r4_alu")
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105 (define_bypass 1 "cortex_r4_alu,cortex_r4_alu_shift,cortex_r4_alu_shift_reg,\
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106 cortex_r4_mov"
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107 "cortex_r4_alu_shift"
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108 "arm_no_early_alu_shift_dep")
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109 (define_bypass 1 "cortex_r4_alu,cortex_r4_alu_shift,cortex_r4_alu_shift_reg,\
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110 cortex_r4_mov"
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111 "cortex_r4_alu_shift_reg"
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112 "arm_no_early_alu_shift_value_dep")
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113
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114 ;; In terms of availabilities, a consumer mov could theoretically be
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115 ;; issued together with a producer ALU instruction, without stalls.
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116 ;; In practice this cannot happen because mov;add (in that order) is not
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117 ;; eligible for dual issue and furthermore dual issue is not permitted
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118 ;; when a dependency is involved. We therefore note it as latency one.
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119 ;; A mov followed by another of the same is also latency one.
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120 (define_bypass 1 "cortex_r4_alu,cortex_r4_alu_shift,cortex_r4_alu_shift_reg,\
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121 cortex_r4_mov"
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122 "cortex_r4_mov")
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123
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124 ;; qadd, qdadd, qsub and qdsub are not currently emitted, and neither are
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125 ;; media data processing instructions nor sad instructions.
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126
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127 ;; Multiplication instructions.
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128
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129 (define_insn_reservation "cortex_r4_mul_4" 4
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130 (and (eq_attr "tune_cortexr4" "yes")
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131 (eq_attr "insn" "mul,smmul"))
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132 "cortex_r4_mul_2")
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133
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134 (define_insn_reservation "cortex_r4_mul_3" 3
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135 (and (eq_attr "tune_cortexr4" "yes")
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136 (eq_attr "insn" "smulxy,smulwy,smuad,smusd"))
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137 "cortex_r4_mul")
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138
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139 (define_insn_reservation "cortex_r4_mla_4" 4
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140 (and (eq_attr "tune_cortexr4" "yes")
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141 (eq_attr "insn" "mla,smmla"))
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142 "cortex_r4_mul_2")
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143
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144 (define_insn_reservation "cortex_r4_mla_3" 3
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145 (and (eq_attr "tune_cortexr4" "yes")
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146 (eq_attr "insn" "smlaxy,smlawy,smlad,smlsd"))
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147 "cortex_r4_mul")
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148
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149 (define_insn_reservation "cortex_r4_smlald" 3
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150 (and (eq_attr "tune_cortexr4" "yes")
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151 (eq_attr "insn" "smlald,smlsld"))
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152 "cortex_r4_mul")
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153
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154 (define_insn_reservation "cortex_r4_mull" 4
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155 (and (eq_attr "tune_cortexr4" "yes")
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156 (eq_attr "insn" "smull,umull,umlal,umaal"))
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157 "cortex_r4_mul_2")
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158
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159 ;; A multiply or an MLA with a single-register result, followed by an
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160 ;; MLA with an accumulator dependency, has its result forwarded.
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161 (define_bypass 2 "cortex_r4_mul_3,cortex_r4_mla_3"
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162 "cortex_r4_mla_3,cortex_r4_mla_4"
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163 "arm_mac_accumulator_is_mul_result")
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164
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165 (define_bypass 3 "cortex_r4_mul_4,cortex_r4_mla_4"
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166 "cortex_r4_mla_3,cortex_r4_mla_4"
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167 "arm_mac_accumulator_is_mul_result")
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168
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169 ;; A multiply followed by an ALU instruction needing the multiply
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170 ;; result only at ALU has lower latency than one needing it at Shift.
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171 (define_bypass 2 "cortex_r4_mul_3,cortex_r4_mla_3,cortex_r4_smlald"
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172 "cortex_r4_alu")
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173 (define_bypass 2 "cortex_r4_mul_3,cortex_r4_mla_3,cortex_r4_smlald"
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174 "cortex_r4_alu_shift"
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175 "arm_no_early_alu_shift_dep")
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176 (define_bypass 2 "cortex_r4_mul_3,cortex_r4_mla_3,cortex_r4_smlald"
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177 "cortex_r4_alu_shift_reg"
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178 "arm_no_early_alu_shift_value_dep")
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179 (define_bypass 3 "cortex_r4_mul_4,cortex_r4_mla_4,cortex_r4_mull"
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180 "cortex_r4_alu")
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181 (define_bypass 3 "cortex_r4_mul_4,cortex_r4_mla_4,cortex_r4_mull"
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182 "cortex_r4_alu_shift"
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183 "arm_no_early_alu_shift_dep")
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184 (define_bypass 3 "cortex_r4_mul_4,cortex_r4_mla_4,cortex_r4_mull"
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185 "cortex_r4_alu_shift_reg"
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186 "arm_no_early_alu_shift_value_dep")
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187
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188 ;; A multiply followed by a mov has one cycle lower latency again.
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189 (define_bypass 1 "cortex_r4_mul_3,cortex_r4_mla_3,cortex_r4_smlald"
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190 "cortex_r4_mov")
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191 (define_bypass 2 "cortex_r4_mul_4,cortex_r4_mla_4,cortex_r4_mull"
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192 "cortex_r4_mov")
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193
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194 ;; We guess that division of A/B using sdiv or udiv, on average,
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195 ;; is performed with B having ten more leading zeros than A.
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196 ;; This gives a latency of nine for udiv and ten for sdiv.
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197 (define_insn_reservation "cortex_r4_udiv" 9
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198 (and (eq_attr "tune_cortexr4" "yes")
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199 (eq_attr "insn" "udiv"))
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200 "cortex_r4_div_9")
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201
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202 (define_insn_reservation "cortex_r4_sdiv" 10
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203 (and (eq_attr "tune_cortexr4" "yes")
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204 (eq_attr "insn" "sdiv"))
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205 "cortex_r4_div_10")
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206
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207 ;; Branches. We assume correct prediction.
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208
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209 (define_insn_reservation "cortex_r4_branch" 0
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210 (and (eq_attr "tune_cortexr4" "yes")
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211 (eq_attr "type" "branch"))
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212 "cortex_r4_branch")
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213
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214 ;; Call latencies are not predictable. A semi-arbitrary very large
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215 ;; number is used as "positive infinity" so that everything should be
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216 ;; finished by the time of return.
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217 (define_insn_reservation "cortex_r4_call" 32
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218 (and (eq_attr "tune_cortexr4" "yes")
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219 (eq_attr "type" "call"))
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220 "nothing")
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221
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222 ;; Status register access instructions are not currently emitted.
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223
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224 ;; Load instructions.
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225 ;; We do not model the "addr_md_3cycle" cases and assume that
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226 ;; accesses following are correctly aligned.
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227
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228 (define_insn_reservation "cortex_r4_load_1_2" 3
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229 (and (eq_attr "tune_cortexr4" "yes")
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230 (eq_attr "type" "load1,load2"))
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231 "cortex_r4_load_store")
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232
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233 (define_insn_reservation "cortex_r4_load_3_4" 4
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234 (and (eq_attr "tune_cortexr4" "yes")
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235 (eq_attr "type" "load3,load4"))
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236 "cortex_r4_load_store_2")
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237
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238 ;; If a producing load is followed by an instruction consuming only
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239 ;; as a Normal Reg, there is one fewer cycle of latency.
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240
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241 (define_bypass 2 "cortex_r4_load_1_2"
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242 "cortex_r4_alu")
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243 (define_bypass 2 "cortex_r4_load_1_2"
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244 "cortex_r4_alu_shift"
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245 "arm_no_early_alu_shift_dep")
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246 (define_bypass 2 "cortex_r4_load_1_2"
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247 "cortex_r4_alu_shift_reg"
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248 "arm_no_early_alu_shift_value_dep")
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249
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250 (define_bypass 3 "cortex_r4_load_3_4"
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251 "cortex_r4_alu")
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252 (define_bypass 3 "cortex_r4_load_3_4"
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253 "cortex_r4_alu_shift"
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254 "arm_no_early_alu_shift_dep")
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255 (define_bypass 3 "cortex_r4_load_3_4"
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256 "cortex_r4_alu_shift_reg"
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257 "arm_no_early_alu_shift_value_dep")
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258
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259 ;; If a producing load is followed by an instruction consuming only
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260 ;; as a Late Reg, there are two fewer cycles of latency. Such consumer
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261 ;; instructions are moves and stores.
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262
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263 (define_bypass 1 "cortex_r4_load_1_2"
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264 "cortex_r4_mov,cortex_r4_store_1_2,cortex_r4_store_3_4")
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265 (define_bypass 2 "cortex_r4_load_3_4"
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266 "cortex_r4_mov,cortex_r4_store_1_2,cortex_r4_store_3_4")
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267
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268 ;; If a producer's result is required as the base or offset of a load,
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269 ;; there is an extra cycle latency.
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270
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271 (define_bypass 3 "cortex_r4_alu,cortex_r4_mov,cortex_r4_alu_shift,\
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272 cortex_r4_alu_shift_reg"
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273 "cortex_r4_load_1_2,cortex_r4_load_3_4")
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274
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275 (define_bypass 4 "cortex_r4_mul_3,cortex_r4_mla_3,cortex_r4_smlald"
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276 "cortex_r4_load_1_2,cortex_r4_load_3_4")
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277
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278 (define_bypass 5 "cortex_r4_mul_4,cortex_r4_mla_4,cortex_r4_mull"
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279 "cortex_r4_load_1_2,cortex_r4_load_3_4")
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280
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281 ;; Store instructions.
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282
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283 (define_insn_reservation "cortex_r4_store_1_2" 0
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284 (and (eq_attr "tune_cortexr4" "yes")
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285 (eq_attr "type" "store1,store2"))
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286 "cortex_r4_load_store")
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287
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288 (define_insn_reservation "cortex_r4_store_3_4" 0
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289 (and (eq_attr "tune_cortexr4" "yes")
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290 (eq_attr "type" "store3,store4"))
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291 "cortex_r4_load_store_2")
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292
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