Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/frv/frv.h @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | 77e2b8dfacca |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 /* Target macros for the FRV port of GCC. |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
3 2010, 2011 |
| 0 | 4 Free Software Foundation, Inc. |
| 5 Contributed by Red Hat Inc. | |
| 6 | |
| 7 This file is part of GCC. | |
| 8 | |
| 9 GCC is free software; you can redistribute it and/or modify it | |
| 10 under the terms of the GNU General Public License as published | |
| 11 by the Free Software Foundation; either version 3, or (at your | |
| 12 option) any later version. | |
| 13 | |
| 14 GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 17 License for more details. | |
| 18 | |
| 19 You should have received a copy of the GNU General Public License | |
| 20 along with GCC; see the file COPYING3. If not see | |
| 21 <http://www.gnu.org/licenses/>. */ | |
| 22 | |
| 23 #ifndef __FRV_H__ | |
| 24 #define __FRV_H__ | |
| 25 | |
| 26 /* Frv general purpose macros. */ | |
| 27 /* Align an address. */ | |
| 28 #define ADDR_ALIGN(addr,align) (((addr) + (align) - 1) & ~((align) - 1)) | |
| 29 | |
| 30 /* Driver configuration. */ | |
| 31 | |
| 32 /* -fpic and -fPIC used to imply the -mlibrary-pic multilib, but with | |
| 33 FDPIC which multilib to use depends on whether FDPIC is in use or | |
| 34 not. The trick we use is to introduce -multilib-library-pic as a | |
| 35 pseudo-flag that selects the library-pic multilib, and map fpic | |
| 36 and fPIC to it only if fdpic is not selected. Also, if fdpic is | |
| 37 selected and no PIC/PIE options are present, we imply -fPIE. | |
| 38 Otherwise, if -fpic or -fPIC are enabled and we're optimizing for | |
| 39 speed, or if we have -On with n>=3, enable inlining of PLTs. As | |
| 40 for -mgprel-ro, we want to enable it by default, but not for -fpic or | |
| 41 -fpie. */ | |
| 42 | |
| 43 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS \ | |
| 44 "%{mno-pack:\ | |
| 45 %{!mhard-float:-msoft-float}\ | |
| 46 %{!mmedia:-mno-media}}\ | |
| 47 %{!mfdpic:%{fpic|fPIC: -multilib-library-pic}}\ | |
| 48 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\ | |
| 49 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fPIE}}}}}}}} \ | |
| 50 %{!mno-inline-plt:%{O*:%{!O0:%{!Os:%{fpic|fPIC:-minline-plt} \ | |
| 51 %{!fpic:%{!fPIC:%{!O:%{!O1:%{!O2:-minline-plt}}}}}}}}} \ | |
| 52 %{!mno-gprel-ro:%{!fpic:%{!fpie:-mgprel-ro}}}} \ | |
| 53 " | |
| 54 #ifndef SUBTARGET_DRIVER_SELF_SPECS | |
| 55 # define SUBTARGET_DRIVER_SELF_SPECS | |
| 56 #endif | |
| 57 | |
| 58 #undef ASM_SPEC | |
| 59 #define ASM_SPEC "\ | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
60 %{G*} \ |
| 0 | 61 %{mtomcat-stats} \ |
| 62 %{!mno-eflags: \ | |
| 63 %{mcpu=*} \ | |
| 64 %{mgpr-*} %{mfpr-*} \ | |
| 65 %{msoft-float} %{mhard-float} \ | |
| 66 %{mdword} %{mno-dword} \ | |
| 67 %{mdouble} %{mno-double} \ | |
| 68 %{mmedia} %{mno-media} \ | |
| 69 %{mmuladd} %{mno-muladd} \ | |
| 70 %{mpack} %{mno-pack} \ | |
| 71 %{mno-fdpic:-mnopic} %{mfdpic} \ | |
| 72 %{fpic|fpie: -mpic} %{fPIC|fPIE: -mPIC} %{mlibrary-pic}}" | |
| 73 | |
| 74 #undef STARTFILE_SPEC | |
| 75 #define STARTFILE_SPEC "crt0%O%s frvbegin%O%s" | |
| 76 | |
| 77 #undef ENDFILE_SPEC | |
| 78 #define ENDFILE_SPEC "frvend%O%s" | |
| 79 | |
| 80 | |
| 81 #define MASK_DEFAULT_FRV \ | |
| 82 (MASK_MEDIA \ | |
| 83 | MASK_DOUBLE \ | |
| 84 | MASK_MULADD \ | |
| 85 | MASK_DWORD \ | |
| 86 | MASK_PACK) | |
| 87 | |
| 88 #define MASK_DEFAULT_FR500 \ | |
| 89 (MASK_MEDIA | MASK_DWORD | MASK_PACK) | |
| 90 | |
| 91 #define MASK_DEFAULT_FR550 \ | |
| 92 (MASK_MEDIA | MASK_DWORD | MASK_PACK) | |
| 93 | |
| 94 #define MASK_DEFAULT_FR450 \ | |
| 95 (MASK_GPR_32 \ | |
| 96 | MASK_FPR_32 \ | |
| 97 | MASK_MEDIA \ | |
| 98 | MASK_SOFT_FLOAT \ | |
| 99 | MASK_DWORD \ | |
| 100 | MASK_PACK) | |
| 101 | |
| 102 #define MASK_DEFAULT_FR400 \ | |
| 103 (MASK_GPR_32 \ | |
| 104 | MASK_FPR_32 \ | |
| 105 | MASK_MEDIA \ | |
| 106 | MASK_ACC_4 \ | |
| 107 | MASK_SOFT_FLOAT \ | |
| 108 | MASK_DWORD \ | |
| 109 | MASK_PACK) | |
| 110 | |
| 111 #define MASK_DEFAULT_SIMPLE \ | |
| 112 (MASK_GPR_32 | MASK_SOFT_FLOAT) | |
| 113 | |
| 114 /* A C string constant that tells the GCC driver program options to pass to | |
| 115 `cc1'. It can also specify how to translate options you give to GCC into | |
| 116 options for GCC to pass to the `cc1'. | |
| 117 | |
| 118 Do not define this macro if it does not need to do anything. */ | |
| 119 /* For ABI compliance, we need to put bss data into the normal data section. */ | |
| 120 #define CC1_SPEC "%{G*}" | |
| 121 | |
| 122 #undef LINK_SPEC | |
| 123 #define LINK_SPEC "\ | |
| 124 %{h*} %{v:-V} \ | |
| 125 %{mfdpic:-melf32frvfd -z text} \ | |
| 126 %{static:-dn -Bstatic} \ | |
| 127 %{shared:-Bdynamic} \ | |
| 128 %{symbolic:-Bsymbolic} \ | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
129 %{G*}" |
| 0 | 130 |
| 131 #undef LIB_SPEC | |
| 132 #define LIB_SPEC "--start-group -lc -lsim --end-group" | |
| 133 | |
| 134 #ifndef CPU_TYPE | |
| 135 #define CPU_TYPE FRV_CPU_FR500 | |
| 136 #endif | |
| 137 | |
| 138 /* Run-time target specifications */ | |
| 139 | |
| 140 #define TARGET_CPU_CPP_BUILTINS() \ | |
| 141 do \ | |
| 142 { \ | |
| 143 int issue_rate; \ | |
| 144 \ | |
| 145 builtin_define ("__frv__"); \ | |
| 146 builtin_assert ("machine=frv"); \ | |
| 147 \ | |
| 148 issue_rate = frv_issue_rate (); \ | |
| 149 if (issue_rate > 1) \ | |
| 150 builtin_define_with_int_value ("__FRV_VLIW__", issue_rate); \ | |
| 151 builtin_define_with_int_value ("__FRV_GPR__", NUM_GPRS); \ | |
| 152 builtin_define_with_int_value ("__FRV_FPR__", NUM_FPRS); \ | |
| 153 builtin_define_with_int_value ("__FRV_ACC__", NUM_ACCS); \ | |
| 154 \ | |
| 155 switch (frv_cpu_type) \ | |
| 156 { \ | |
| 157 case FRV_CPU_GENERIC: \ | |
| 158 builtin_define ("__CPU_GENERIC__"); \ | |
| 159 break; \ | |
| 160 case FRV_CPU_FR550: \ | |
| 161 builtin_define ("__CPU_FR550__"); \ | |
| 162 break; \ | |
| 163 case FRV_CPU_FR500: \ | |
| 164 case FRV_CPU_TOMCAT: \ | |
| 165 builtin_define ("__CPU_FR500__"); \ | |
| 166 break; \ | |
| 167 case FRV_CPU_FR450: \ | |
| 168 builtin_define ("__CPU_FR450__"); \ | |
| 169 break; \ | |
| 170 case FRV_CPU_FR405: \ | |
| 171 builtin_define ("__CPU_FR405__"); \ | |
| 172 break; \ | |
| 173 case FRV_CPU_FR400: \ | |
| 174 builtin_define ("__CPU_FR400__"); \ | |
| 175 break; \ | |
| 176 case FRV_CPU_FR300: \ | |
| 177 case FRV_CPU_SIMPLE: \ | |
| 178 builtin_define ("__CPU_FR300__"); \ | |
| 179 break; \ | |
| 180 } \ | |
| 181 \ | |
| 182 if (TARGET_HARD_FLOAT) \ | |
| 183 builtin_define ("__FRV_HARD_FLOAT__"); \ | |
| 184 if (TARGET_DWORD) \ | |
| 185 builtin_define ("__FRV_DWORD__"); \ | |
| 186 if (TARGET_FDPIC) \ | |
| 187 builtin_define ("__FRV_FDPIC__"); \ | |
| 188 if (flag_leading_underscore > 0) \ | |
| 189 builtin_define ("__FRV_UNDERSCORE__"); \ | |
| 190 } \ | |
| 191 while (0) | |
| 192 | |
| 193 | |
| 194 #define TARGET_HAS_FPRS (TARGET_HARD_FLOAT || TARGET_MEDIA) | |
| 195 | |
| 196 #define NUM_GPRS (TARGET_GPR_32? 32 : 64) | |
| 197 #define NUM_FPRS (!TARGET_HAS_FPRS? 0 : TARGET_FPR_32? 32 : 64) | |
| 198 #define NUM_ACCS (!TARGET_MEDIA? 0 : TARGET_ACC_4? 4 : 8) | |
| 199 | |
| 200 /* X is a valid accumulator number if (X & ACC_MASK) == X. */ | |
| 201 #define ACC_MASK \ | |
| 202 (!TARGET_MEDIA ? 0 \ | |
| 203 : TARGET_ACC_4 ? 3 \ | |
| 204 : frv_cpu_type == FRV_CPU_FR450 ? 11 \ | |
| 205 : 7) | |
| 206 | |
| 207 /* Macros to identify the blend of media instructions available. Revision 1 | |
| 208 is the one found on the FR500. Revision 2 includes the changes made for | |
| 209 the FR400. | |
| 210 | |
| 211 Treat the generic processor as a revision 1 machine for now, for | |
| 212 compatibility with earlier releases. */ | |
| 213 | |
| 214 #define TARGET_MEDIA_REV1 \ | |
| 215 (TARGET_MEDIA \ | |
| 216 && (frv_cpu_type == FRV_CPU_GENERIC \ | |
| 217 || frv_cpu_type == FRV_CPU_FR500)) | |
| 218 | |
| 219 #define TARGET_MEDIA_REV2 \ | |
| 220 (TARGET_MEDIA \ | |
| 221 && (frv_cpu_type == FRV_CPU_FR400 \ | |
| 222 || frv_cpu_type == FRV_CPU_FR405 \ | |
| 223 || frv_cpu_type == FRV_CPU_FR450 \ | |
| 224 || frv_cpu_type == FRV_CPU_FR550)) | |
| 225 | |
| 226 #define TARGET_MEDIA_FR450 \ | |
| 227 (frv_cpu_type == FRV_CPU_FR450) | |
| 228 | |
| 229 #define TARGET_FR500_FR550_BUILTINS \ | |
| 230 (frv_cpu_type == FRV_CPU_FR500 \ | |
| 231 || frv_cpu_type == FRV_CPU_FR550) | |
| 232 | |
| 233 #define TARGET_FR405_BUILTINS \ | |
| 234 (frv_cpu_type == FRV_CPU_FR405 \ | |
| 235 || frv_cpu_type == FRV_CPU_FR450) | |
| 236 | |
| 237 #ifndef HAVE_AS_TLS | |
| 238 #define HAVE_AS_TLS 0 | |
| 239 #endif | |
| 240 | |
| 241 /* This macro is a C statement to print on `stderr' a string describing the | |
| 242 particular machine description choice. Every machine description should | |
| 243 define `TARGET_VERSION'. For example: | |
| 244 | |
| 245 #ifdef MOTOROLA | |
| 246 #define TARGET_VERSION \ | |
| 247 fprintf (stderr, " (68k, Motorola syntax)"); | |
| 248 #else | |
| 249 #define TARGET_VERSION \ | |
| 250 fprintf (stderr, " (68k, MIT syntax)"); | |
| 251 #endif */ | |
| 252 #define TARGET_VERSION fprintf (stderr, _(" (frv)")) | |
| 253 | |
| 254 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (TARGET_ALIGN_LABELS ? 3 : 0) | |
| 255 | |
| 256 /* Small Data Area Support. */ | |
| 257 /* Maximum size of variables that go in .sdata/.sbss. | |
| 258 The -msdata=foo switch also controls how small variables are handled. */ | |
| 259 #ifndef SDATA_DEFAULT_SIZE | |
| 260 #define SDATA_DEFAULT_SIZE 8 | |
| 261 #endif | |
| 262 | |
| 263 | |
| 264 /* Storage Layout */ | |
| 265 | |
| 266 /* Define this macro to have the value 1 if the most significant bit in a byte | |
| 267 has the lowest number; otherwise define it to have the value zero. This | |
| 268 means that bit-field instructions count from the most significant bit. If | |
| 269 the machine has no bit-field instructions, then this must still be defined, | |
| 270 but it doesn't matter which value it is defined to. This macro need not be | |
| 271 a constant. | |
| 272 | |
| 273 This macro does not affect the way structure fields are packed into bytes or | |
| 274 words; that is controlled by `BYTES_BIG_ENDIAN'. */ | |
| 275 #define BITS_BIG_ENDIAN 1 | |
| 276 | |
| 277 /* Define this macro to have the value 1 if the most significant byte in a word | |
| 278 has the lowest number. This macro need not be a constant. */ | |
| 279 #define BYTES_BIG_ENDIAN 1 | |
| 280 | |
| 281 /* Define this macro to have the value 1 if, in a multiword object, the most | |
| 282 significant word has the lowest number. This applies to both memory | |
| 283 locations and registers; GCC fundamentally assumes that the order of | |
| 284 words in memory is the same as the order in registers. This macro need not | |
| 285 be a constant. */ | |
| 286 #define WORDS_BIG_ENDIAN 1 | |
| 287 | |
| 288 /* Number of storage units in a word; normally 4. */ | |
| 289 #define UNITS_PER_WORD 4 | |
| 290 | |
| 291 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and | |
| 292 which has the specified mode and signedness is to be stored in a register. | |
| 293 This macro is only called when TYPE is a scalar type. | |
| 294 | |
| 295 On most RISC machines, which only have operations that operate on a full | |
| 296 register, define this macro to set M to `word_mode' if M is an integer mode | |
| 297 narrower than `BITS_PER_WORD'. In most cases, only integer modes should be | |
| 298 widened because wider-precision floating-point operations are usually more | |
| 299 expensive than their narrower counterparts. | |
| 300 | |
| 301 For most machines, the macro definition does not change UNSIGNEDP. However, | |
| 302 some machines, have instructions that preferentially handle either signed or | |
| 303 unsigned quantities of certain modes. For example, on the DEC Alpha, 32-bit | |
| 304 loads from memory and 32-bit add instructions sign-extend the result to 64 | |
| 305 bits. On such machines, set UNSIGNEDP according to which kind of extension | |
| 306 is more efficient. | |
| 307 | |
| 308 Do not define this macro if it would never modify MODE. */ | |
| 309 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
| 310 do \ | |
| 311 { \ | |
| 312 if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
| 313 && GET_MODE_SIZE (MODE) < 4) \ | |
| 314 (MODE) = SImode; \ | |
| 315 } \ | |
| 316 while (0) | |
| 317 | |
| 318 /* Normal alignment required for function parameters on the stack, in bits. | |
| 319 All stack parameters receive at least this much alignment regardless of data | |
| 320 type. On most machines, this is the same as the size of an integer. */ | |
| 321 #define PARM_BOUNDARY 32 | |
| 322 | |
| 323 /* Define this macro if you wish to preserve a certain alignment for the stack | |
| 324 pointer. The definition is a C expression for the desired alignment | |
| 325 (measured in bits). | |
| 326 | |
| 327 If `PUSH_ROUNDING' is not defined, the stack will always be aligned to the | |
| 328 specified boundary. If `PUSH_ROUNDING' is defined and specifies a less | |
| 329 strict alignment than `STACK_BOUNDARY', the stack may be momentarily | |
| 330 unaligned while pushing arguments. */ | |
| 331 #define STACK_BOUNDARY 64 | |
| 332 | |
| 333 /* Alignment required for a function entry point, in bits. */ | |
| 334 #define FUNCTION_BOUNDARY 128 | |
| 335 | |
| 336 /* Biggest alignment that any data type can require on this machine, | |
| 337 in bits. */ | |
| 338 #define BIGGEST_ALIGNMENT 64 | |
| 339 | |
| 340 /* @@@ A hack, needed because libobjc wants to use ADJUST_FIELD_ALIGN for | |
| 341 some reason. */ | |
| 342 #ifdef IN_TARGET_LIBS | |
| 343 #define BIGGEST_FIELD_ALIGNMENT 64 | |
| 344 #else | |
| 345 /* An expression for the alignment of a structure field FIELD if the | |
| 346 alignment computed in the usual way is COMPUTED. GCC uses this | |
| 347 value instead of the value in `BIGGEST_ALIGNMENT' or | |
| 348 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */ | |
| 349 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ | |
| 350 frv_adjust_field_align (FIELD, COMPUTED) | |
| 351 #endif | |
| 352 | |
| 353 /* If defined, a C expression to compute the alignment for a static variable. | |
| 354 TYPE is the data type, and ALIGN is the alignment that the object | |
| 355 would ordinarily have. The value of this macro is used instead of that | |
| 356 alignment to align the object. | |
| 357 | |
| 358 If this macro is not defined, then ALIGN is used. | |
| 359 | |
| 360 One use of this macro is to increase alignment of medium-size data to make | |
| 361 it all fit in fewer cache lines. Another is to cause character arrays to be | |
| 362 word-aligned so that `strcpy' calls that copy constants to character arrays | |
| 363 can be done inline. */ | |
| 364 #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
| 365 (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
| 366 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
| 367 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
| 368 | |
| 369 /* If defined, a C expression to compute the alignment given to a constant that | |
| 370 is being placed in memory. CONSTANT is the constant and ALIGN is the | |
| 371 alignment that the object would ordinarily have. The value of this macro is | |
| 372 used instead of that alignment to align the object. | |
| 373 | |
| 374 If this macro is not defined, then ALIGN is used. | |
| 375 | |
| 376 The typical use of this macro is to increase alignment for string constants | |
| 377 to be word aligned so that `strcpy' calls that copy constants can be done | |
| 378 inline. */ | |
| 379 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
| 380 (TREE_CODE (EXP) == STRING_CST \ | |
| 381 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
| 382 | |
| 383 /* Define this macro to be the value 1 if instructions will fail to work if | |
| 384 given data not on the nominal alignment. If instructions will merely go | |
| 385 slower in that case, define this macro as 0. */ | |
| 386 #define STRICT_ALIGNMENT 1 | |
| 387 | |
| 388 #define PCC_BITFIELD_TYPE_MATTERS 1 | |
| 389 | |
| 390 | |
| 391 /* Layout of Source Language Data Types. */ | |
| 392 | |
| 393 #define CHAR_TYPE_SIZE 8 | |
| 394 #define SHORT_TYPE_SIZE 16 | |
| 395 #define INT_TYPE_SIZE 32 | |
| 396 #define LONG_TYPE_SIZE 32 | |
| 397 #define LONG_LONG_TYPE_SIZE 64 | |
| 398 #define FLOAT_TYPE_SIZE 32 | |
| 399 #define DOUBLE_TYPE_SIZE 64 | |
| 400 #define LONG_DOUBLE_TYPE_SIZE 64 | |
| 401 | |
| 402 /* An expression whose value is 1 or 0, according to whether the type `char' | |
| 403 should be signed or unsigned by default. The user can always override this | |
| 404 default with the options `-fsigned-char' and `-funsigned-char'. */ | |
| 405 #define DEFAULT_SIGNED_CHAR 1 | |
| 406 | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
407 #undef SIZE_TYPE |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
408 #define SIZE_TYPE "unsigned int" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
409 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
410 #undef PTRDIFF_TYPE |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
411 #define PTRDIFF_TYPE "int" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
412 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
413 #undef WCHAR_TYPE |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
414 #define WCHAR_TYPE "long int" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
415 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
416 #undef WCHAR_TYPE_SIZE |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
417 #define WCHAR_TYPE_SIZE BITS_PER_WORD |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
418 |
| 0 | 419 |
| 420 /* General purpose registers. */ | |
| 421 #define GPR_FIRST 0 /* First gpr */ | |
| 422 #define GPR_LAST (GPR_FIRST + 63) /* Last gpr */ | |
| 423 #define GPR_R0 GPR_FIRST /* R0, constant 0 */ | |
| 424 #define GPR_FP (GPR_FIRST + 2) /* Frame pointer */ | |
| 425 #define GPR_SP (GPR_FIRST + 1) /* Stack pointer */ | |
| 426 /* small data register */ | |
| 427 #define SDA_BASE_REG ((unsigned)(TARGET_FDPIC ? -1 : flag_pic ? PIC_REGNO : (GPR_FIRST + 16))) | |
| 428 #define PIC_REGNO (GPR_FIRST + (TARGET_FDPIC?15:17)) /* PIC register. */ | |
| 429 #define FDPIC_FPTR_REGNO (GPR_FIRST + 14) /* uClinux PIC function pointer register. */ | |
| 430 #define FDPIC_REGNO (GPR_FIRST + 15) /* uClinux PIC register. */ | |
| 431 | |
| 432 #define HARD_REGNO_RENAME_OK(from,to) (TARGET_FDPIC ? ((to) != FDPIC_REG) : 1) | |
| 433 | |
| 434 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO) | |
| 435 | |
| 436 #define FPR_FIRST 64 /* First FP reg */ | |
| 437 #define FPR_LAST 127 /* Last FP reg */ | |
| 438 | |
| 439 #define GPR_TEMP_NUM frv_condexec_temps /* # gprs to reserve for temps */ | |
| 440 | |
| 441 /* We reserve the last CR and CCR in each category to be used as a reload | |
| 442 register to reload the CR/CCR registers. This is a kludge. */ | |
| 443 #define CC_FIRST 128 /* First ICC/FCC reg */ | |
| 444 #define CC_LAST 135 /* Last ICC/FCC reg */ | |
| 445 #define ICC_FIRST (CC_FIRST + 4) /* First ICC reg */ | |
| 446 #define ICC_LAST (CC_FIRST + 7) /* Last ICC reg */ | |
| 447 #define ICC_TEMP (CC_FIRST + 7) /* Temporary ICC reg */ | |
| 448 #define FCC_FIRST (CC_FIRST) /* First FCC reg */ | |
| 449 #define FCC_LAST (CC_FIRST + 3) /* Last FCC reg */ | |
| 450 | |
| 451 /* Amount to shift a value to locate a ICC or FCC register in the CCR | |
| 452 register and shift it to the bottom 4 bits. */ | |
| 453 #define CC_SHIFT_RIGHT(REGNO) (((REGNO) - CC_FIRST) << 2) | |
| 454 | |
| 455 /* Mask to isolate a single ICC/FCC value. */ | |
| 456 #define CC_MASK 0xf | |
| 457 | |
| 458 /* Masks to isolate the various bits in an ICC field. */ | |
| 459 #define ICC_MASK_N 0x8 /* negative */ | |
| 460 #define ICC_MASK_Z 0x4 /* zero */ | |
| 461 #define ICC_MASK_V 0x2 /* overflow */ | |
| 462 #define ICC_MASK_C 0x1 /* carry */ | |
| 463 | |
| 464 /* Mask to isolate the N/Z flags in an ICC. */ | |
| 465 #define ICC_MASK_NZ (ICC_MASK_N | ICC_MASK_Z) | |
| 466 | |
| 467 /* Mask to isolate the Z/C flags in an ICC. */ | |
| 468 #define ICC_MASK_ZC (ICC_MASK_Z | ICC_MASK_C) | |
| 469 | |
| 470 /* Masks to isolate the various bits in a FCC field. */ | |
| 471 #define FCC_MASK_E 0x8 /* equal */ | |
| 472 #define FCC_MASK_L 0x4 /* less than */ | |
| 473 #define FCC_MASK_G 0x2 /* greater than */ | |
| 474 #define FCC_MASK_U 0x1 /* unordered */ | |
| 475 | |
| 476 /* For CCR registers, the machine wants CR4..CR7 to be used for integer | |
| 477 code and CR0..CR3 to be used for floating point. */ | |
| 478 #define CR_FIRST 136 /* First CCR */ | |
| 479 #define CR_LAST 143 /* Last CCR */ | |
| 480 #define CR_NUM (CR_LAST-CR_FIRST+1) /* # of CCRs (8) */ | |
| 481 #define ICR_FIRST (CR_FIRST + 4) /* First integer CCR */ | |
| 482 #define ICR_LAST (CR_FIRST + 7) /* Last integer CCR */ | |
| 483 #define ICR_TEMP ICR_LAST /* Temp integer CCR */ | |
| 484 #define FCR_FIRST (CR_FIRST + 0) /* First float CCR */ | |
| 485 #define FCR_LAST (CR_FIRST + 3) /* Last float CCR */ | |
| 486 | |
| 487 /* Amount to shift a value to locate a CR register in the CCCR special purpose | |
| 488 register and shift it to the bottom 2 bits. */ | |
| 489 #define CR_SHIFT_RIGHT(REGNO) (((REGNO) - CR_FIRST) << 1) | |
| 490 | |
| 491 /* Mask to isolate a single CR value. */ | |
| 492 #define CR_MASK 0x3 | |
| 493 | |
| 494 #define ACC_FIRST 144 /* First acc register */ | |
| 495 #define ACC_LAST 155 /* Last acc register */ | |
| 496 | |
| 497 #define ACCG_FIRST 156 /* First accg register */ | |
| 498 #define ACCG_LAST 167 /* Last accg register */ | |
| 499 | |
| 500 #define AP_FIRST 168 /* fake argument pointer */ | |
| 501 | |
| 502 #define SPR_FIRST 169 | |
| 503 #define SPR_LAST 172 | |
| 504 #define LR_REGNO (SPR_FIRST) | |
| 505 #define LCR_REGNO (SPR_FIRST + 1) | |
| 506 #define IACC_FIRST (SPR_FIRST + 2) | |
| 507 #define IACC_LAST (SPR_FIRST + 3) | |
| 508 | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
509 #define GPR_P(R) IN_RANGE (R, GPR_FIRST, GPR_LAST) |
| 0 | 510 #define GPR_OR_AP_P(R) (GPR_P (R) || (R) == ARG_POINTER_REGNUM) |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
511 #define FPR_P(R) IN_RANGE (R, FPR_FIRST, FPR_LAST) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
512 #define CC_P(R) IN_RANGE (R, CC_FIRST, CC_LAST) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
513 #define ICC_P(R) IN_RANGE (R, ICC_FIRST, ICC_LAST) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
514 #define FCC_P(R) IN_RANGE (R, FCC_FIRST, FCC_LAST) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
515 #define CR_P(R) IN_RANGE (R, CR_FIRST, CR_LAST) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
516 #define ICR_P(R) IN_RANGE (R, ICR_FIRST, ICR_LAST) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
517 #define FCR_P(R) IN_RANGE (R, FCR_FIRST, FCR_LAST) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
518 #define ACC_P(R) IN_RANGE (R, ACC_FIRST, ACC_LAST) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
519 #define ACCG_P(R) IN_RANGE (R, ACCG_FIRST, ACCG_LAST) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
520 #define SPR_P(R) IN_RANGE (R, SPR_FIRST, SPR_LAST) |
| 0 | 521 |
| 522 #define GPR_OR_PSEUDO_P(R) (GPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
| 523 #define FPR_OR_PSEUDO_P(R) (FPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
| 524 #define GPR_AP_OR_PSEUDO_P(R) (GPR_OR_AP_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
| 525 #define CC_OR_PSEUDO_P(R) (CC_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
| 526 #define ICC_OR_PSEUDO_P(R) (ICC_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
| 527 #define FCC_OR_PSEUDO_P(R) (FCC_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
| 528 #define CR_OR_PSEUDO_P(R) (CR_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
| 529 #define ICR_OR_PSEUDO_P(R) (ICR_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
| 530 #define FCR_OR_PSEUDO_P(R) (FCR_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
| 531 #define ACC_OR_PSEUDO_P(R) (ACC_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
| 532 #define ACCG_OR_PSEUDO_P(R) (ACCG_P (R) || (R) >= FIRST_PSEUDO_REGISTER) | |
| 533 | |
| 534 #define MAX_STACK_IMMEDIATE_OFFSET 2047 | |
| 535 | |
| 536 | |
| 537 /* Register Basics. */ | |
| 538 | |
| 539 /* Number of hardware registers known to the compiler. They receive numbers 0 | |
| 540 through `FIRST_PSEUDO_REGISTER-1'; thus, the first pseudo register's number | |
| 541 really is assigned the number `FIRST_PSEUDO_REGISTER'. */ | |
| 542 #define FIRST_PSEUDO_REGISTER (SPR_LAST + 1) | |
| 543 | |
| 544 /* The first/last register that can contain the arguments to a function. */ | |
| 545 #define FIRST_ARG_REGNUM (GPR_FIRST + 8) | |
| 546 #define LAST_ARG_REGNUM (FIRST_ARG_REGNUM + FRV_NUM_ARG_REGS - 1) | |
| 547 | |
| 548 /* Registers used by the exception handling functions. These should be | |
| 549 registers that are not otherwise used by the calling sequence. */ | |
| 550 #define FIRST_EH_REGNUM 14 | |
| 551 #define LAST_EH_REGNUM 15 | |
| 552 | |
| 553 /* Scratch registers used in the prologue, epilogue and thunks. | |
| 554 OFFSET_REGNO is for loading constant addends that are too big for a | |
| 555 single instruction. TEMP_REGNO is used for transferring SPRs to and from | |
| 556 the stack, and various other activities. */ | |
| 557 #define OFFSET_REGNO 4 | |
| 558 #define TEMP_REGNO 5 | |
| 559 | |
| 560 /* Registers used in the prologue. OLD_SP_REGNO is the old stack pointer, | |
| 561 which is sometimes used to set up the frame pointer. */ | |
| 562 #define OLD_SP_REGNO 6 | |
| 563 | |
| 564 /* Registers used in the epilogue. STACKADJ_REGNO stores the exception | |
| 565 handler's stack adjustment. */ | |
| 566 #define STACKADJ_REGNO 6 | |
| 567 | |
| 568 /* Registers used in thunks. JMP_REGNO is used for loading the target | |
| 569 address. */ | |
| 570 #define JUMP_REGNO 6 | |
| 571 | |
| 572 #define EH_RETURN_DATA_REGNO(N) ((N) <= (LAST_EH_REGNUM - FIRST_EH_REGNUM)? \ | |
| 573 (N) + FIRST_EH_REGNUM : INVALID_REGNUM) | |
| 574 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, STACKADJ_REGNO) | |
| 575 #define EH_RETURN_HANDLER_RTX RETURN_ADDR_RTX (0, frame_pointer_rtx) | |
| 576 | |
| 577 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNO) | |
| 578 | |
| 579 /* An initializer that says which registers are used for fixed purposes all | |
| 580 throughout the compiled code and are therefore not available for general | |
| 581 allocation. These would include the stack pointer, the frame pointer | |
| 582 (except on machines where that can be used as a general register when no | |
| 583 frame pointer is needed), the program counter on machines where that is | |
| 584 considered one of the addressable registers, and any other numbered register | |
| 585 with a standard use. | |
| 586 | |
| 587 This information is expressed as a sequence of numbers, separated by commas | |
| 588 and surrounded by braces. The Nth number is 1 if register N is fixed, 0 | |
| 589 otherwise. | |
| 590 | |
| 591 The table initialized from this macro, and the table initialized by the | |
| 592 following one, may be overridden at run time either automatically, by the | |
| 593 actions of the macro `CONDITIONAL_REGISTER_USAGE', or by the user with the | |
| 594 command options `-ffixed-REG', `-fcall-used-REG' and `-fcall-saved-REG'. */ | |
| 595 | |
| 596 /* gr0 -- Hard Zero | |
| 597 gr1 -- Stack Pointer | |
| 598 gr2 -- Frame Pointer | |
| 599 gr3 -- Hidden Parameter | |
| 600 gr16 -- Small Data reserved | |
| 601 gr17 -- Pic reserved | |
| 602 gr28 -- OS reserved | |
| 603 gr29 -- OS reserved | |
| 604 gr30 -- OS reserved | |
| 605 gr31 -- OS reserved | |
| 606 cr3 -- reserved to reload FCC registers. | |
| 607 cr7 -- reserved to reload ICC registers. */ | |
| 608 #define FIXED_REGISTERS \ | |
| 609 { /* Integer Registers */ \ | |
| 610 1, 1, 1, 1, 0, 0, 0, 0, /* 000-007, gr0 - gr7 */ \ | |
| 611 0, 0, 0, 0, 0, 0, 0, 0, /* 008-015, gr8 - gr15 */ \ | |
| 612 1, 1, 0, 0, 0, 0, 0, 0, /* 016-023, gr16 - gr23 */ \ | |
| 613 0, 0, 0, 0, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \ | |
| 614 0, 0, 0, 0, 0, 0, 0, 0, /* 032-039, gr32 - gr39 */ \ | |
| 615 0, 0, 0, 0, 0, 0, 0, 0, /* 040-040, gr48 - gr47 */ \ | |
| 616 0, 0, 0, 0, 0, 0, 0, 0, /* 048-055, gr48 - gr55 */ \ | |
| 617 0, 0, 0, 0, 0, 0, 0, 0, /* 056-063, gr56 - gr63 */ \ | |
| 618 /* Float Registers */ \ | |
| 619 0, 0, 0, 0, 0, 0, 0, 0, /* 064-071, fr0 - fr7 */ \ | |
| 620 0, 0, 0, 0, 0, 0, 0, 0, /* 072-079, fr8 - fr15 */ \ | |
| 621 0, 0, 0, 0, 0, 0, 0, 0, /* 080-087, fr16 - fr23 */ \ | |
| 622 0, 0, 0, 0, 0, 0, 0, 0, /* 088-095, fr24 - fr31 */ \ | |
| 623 0, 0, 0, 0, 0, 0, 0, 0, /* 096-103, fr32 - fr39 */ \ | |
| 624 0, 0, 0, 0, 0, 0, 0, 0, /* 104-111, fr48 - fr47 */ \ | |
| 625 0, 0, 0, 0, 0, 0, 0, 0, /* 112-119, fr48 - fr55 */ \ | |
| 626 0, 0, 0, 0, 0, 0, 0, 0, /* 120-127, fr56 - fr63 */ \ | |
| 627 /* Condition Code Registers */ \ | |
| 628 0, 0, 0, 0, /* 128-131, fcc0 - fcc3 */ \ | |
| 629 0, 0, 0, 1, /* 132-135, icc0 - icc3 */ \ | |
| 630 /* Conditional execution Registers (CCR) */ \ | |
| 631 0, 0, 0, 0, 0, 0, 0, 1, /* 136-143, cr0 - cr7 */ \ | |
| 632 /* Accumulators */ \ | |
| 633 1, 1, 1, 1, 1, 1, 1, 1, /* 144-151, acc0 - acc7 */ \ | |
| 634 1, 1, 1, 1, /* 152-155, acc8 - acc11 */ \ | |
| 635 1, 1, 1, 1, 1, 1, 1, 1, /* 156-163, accg0 - accg7 */ \ | |
| 636 1, 1, 1, 1, /* 164-167, accg8 - accg11 */ \ | |
| 637 /* Other registers */ \ | |
| 638 1, /* 168, AP - fake arg ptr */ \ | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
639 1, /* 169, LR - Link register*/ \ |
| 0 | 640 0, /* 170, LCR - Loop count reg*/ \ |
| 641 1, 1 /* 171-172, iacc0 */ \ | |
| 642 } | |
| 643 | |
| 644 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in | |
| 645 general) by function calls as well as for fixed registers. This macro | |
| 646 therefore identifies the registers that are not available for general | |
| 647 allocation of values that must live across function calls. | |
| 648 | |
| 649 If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically | |
| 650 saves it on function entry and restores it on function exit, if the register | |
| 651 is used within the function. */ | |
| 652 #define CALL_USED_REGISTERS \ | |
| 653 { /* Integer Registers */ \ | |
| 654 1, 1, 1, 1, 1, 1, 1, 1, /* 000-007, gr0 - gr7 */ \ | |
| 655 1, 1, 1, 1, 1, 1, 1, 1, /* 008-015, gr8 - gr15 */ \ | |
| 656 1, 1, 0, 0, 0, 0, 0, 0, /* 016-023, gr16 - gr23 */ \ | |
| 657 0, 0, 0, 0, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \ | |
| 658 1, 1, 1, 1, 1, 1, 1, 1, /* 032-039, gr32 - gr39 */ \ | |
| 659 1, 1, 1, 1, 1, 1, 1, 1, /* 040-040, gr48 - gr47 */ \ | |
| 660 0, 0, 0, 0, 0, 0, 0, 0, /* 048-055, gr48 - gr55 */ \ | |
| 661 0, 0, 0, 0, 0, 0, 0, 0, /* 056-063, gr56 - gr63 */ \ | |
| 662 /* Float Registers */ \ | |
| 663 1, 1, 1, 1, 1, 1, 1, 1, /* 064-071, fr0 - fr7 */ \ | |
| 664 1, 1, 1, 1, 1, 1, 1, 1, /* 072-079, fr8 - fr15 */ \ | |
| 665 0, 0, 0, 0, 0, 0, 0, 0, /* 080-087, fr16 - fr23 */ \ | |
| 666 0, 0, 0, 0, 0, 0, 0, 0, /* 088-095, fr24 - fr31 */ \ | |
| 667 1, 1, 1, 1, 1, 1, 1, 1, /* 096-103, fr32 - fr39 */ \ | |
| 668 1, 1, 1, 1, 1, 1, 1, 1, /* 104-111, fr48 - fr47 */ \ | |
| 669 0, 0, 0, 0, 0, 0, 0, 0, /* 112-119, fr48 - fr55 */ \ | |
| 670 0, 0, 0, 0, 0, 0, 0, 0, /* 120-127, fr56 - fr63 */ \ | |
| 671 /* Condition Code Registers */ \ | |
| 672 1, 1, 1, 1, /* 128-131, fcc0 - fcc3 */ \ | |
| 673 1, 1, 1, 1, /* 132-135, icc0 - icc3 */ \ | |
| 674 /* Conditional execution Registers (CCR) */ \ | |
| 675 1, 1, 1, 1, 1, 1, 1, 1, /* 136-143, cr0 - cr7 */ \ | |
| 676 /* Accumulators */ \ | |
| 677 1, 1, 1, 1, 1, 1, 1, 1, /* 144-151, acc0 - acc7 */ \ | |
| 678 1, 1, 1, 1, /* 152-155, acc8 - acc11 */ \ | |
| 679 1, 1, 1, 1, 1, 1, 1, 1, /* 156-163, accg0 - accg7 */ \ | |
| 680 1, 1, 1, 1, /* 164-167, accg8 - accg11 */ \ | |
| 681 /* Other registers */ \ | |
| 682 1, /* 168, AP - fake arg ptr */ \ | |
| 683 1, /* 169, LR - Link register*/ \ | |
| 684 1, /* 170, LCR - Loop count reg */ \ | |
| 685 1, 1 /* 171-172, iacc0 */ \ | |
| 686 } | |
| 687 | |
| 688 | |
| 689 /* Order of allocation of registers. */ | |
| 690 | |
| 691 /* If defined, an initializer for a vector of integers, containing the numbers | |
| 692 of hard registers in the order in which GCC should prefer to use them | |
| 693 (from most preferred to least). | |
| 694 | |
| 695 If this macro is not defined, registers are used lowest numbered first (all | |
| 696 else being equal). | |
| 697 | |
| 698 One use of this macro is on machines where the highest numbered registers | |
| 699 must always be saved and the save-multiple-registers instruction supports | |
| 700 only sequences of consecutive registers. On such machines, define | |
| 701 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered | |
| 702 allocatable register first. */ | |
| 703 | |
| 704 /* On the FRV, allocate GR16 and GR17 after other saved registers so that we | |
| 705 have a better chance of allocating 2 registers at a time and can use the | |
| 706 double word load/store instructions in the prologue. */ | |
| 707 #define REG_ALLOC_ORDER \ | |
| 708 { \ | |
| 709 /* volatile registers */ \ | |
| 710 GPR_FIRST + 4, GPR_FIRST + 5, GPR_FIRST + 6, GPR_FIRST + 7, \ | |
| 711 GPR_FIRST + 8, GPR_FIRST + 9, GPR_FIRST + 10, GPR_FIRST + 11, \ | |
| 712 GPR_FIRST + 12, GPR_FIRST + 13, GPR_FIRST + 14, GPR_FIRST + 15, \ | |
| 713 GPR_FIRST + 32, GPR_FIRST + 33, GPR_FIRST + 34, GPR_FIRST + 35, \ | |
| 714 GPR_FIRST + 36, GPR_FIRST + 37, GPR_FIRST + 38, GPR_FIRST + 39, \ | |
| 715 GPR_FIRST + 40, GPR_FIRST + 41, GPR_FIRST + 42, GPR_FIRST + 43, \ | |
| 716 GPR_FIRST + 44, GPR_FIRST + 45, GPR_FIRST + 46, GPR_FIRST + 47, \ | |
| 717 \ | |
| 718 FPR_FIRST + 0, FPR_FIRST + 1, FPR_FIRST + 2, FPR_FIRST + 3, \ | |
| 719 FPR_FIRST + 4, FPR_FIRST + 5, FPR_FIRST + 6, FPR_FIRST + 7, \ | |
| 720 FPR_FIRST + 8, FPR_FIRST + 9, FPR_FIRST + 10, FPR_FIRST + 11, \ | |
| 721 FPR_FIRST + 12, FPR_FIRST + 13, FPR_FIRST + 14, FPR_FIRST + 15, \ | |
| 722 FPR_FIRST + 32, FPR_FIRST + 33, FPR_FIRST + 34, FPR_FIRST + 35, \ | |
| 723 FPR_FIRST + 36, FPR_FIRST + 37, FPR_FIRST + 38, FPR_FIRST + 39, \ | |
| 724 FPR_FIRST + 40, FPR_FIRST + 41, FPR_FIRST + 42, FPR_FIRST + 43, \ | |
| 725 FPR_FIRST + 44, FPR_FIRST + 45, FPR_FIRST + 46, FPR_FIRST + 47, \ | |
| 726 \ | |
| 727 ICC_FIRST + 0, ICC_FIRST + 1, ICC_FIRST + 2, ICC_FIRST + 3, \ | |
| 728 FCC_FIRST + 0, FCC_FIRST + 1, FCC_FIRST + 2, FCC_FIRST + 3, \ | |
| 729 CR_FIRST + 0, CR_FIRST + 1, CR_FIRST + 2, CR_FIRST + 3, \ | |
| 730 CR_FIRST + 4, CR_FIRST + 5, CR_FIRST + 6, CR_FIRST + 7, \ | |
| 731 \ | |
| 732 /* saved registers */ \ | |
| 733 GPR_FIRST + 18, GPR_FIRST + 19, \ | |
| 734 GPR_FIRST + 20, GPR_FIRST + 21, GPR_FIRST + 22, GPR_FIRST + 23, \ | |
| 735 GPR_FIRST + 24, GPR_FIRST + 25, GPR_FIRST + 26, GPR_FIRST + 27, \ | |
| 736 GPR_FIRST + 48, GPR_FIRST + 49, GPR_FIRST + 50, GPR_FIRST + 51, \ | |
| 737 GPR_FIRST + 52, GPR_FIRST + 53, GPR_FIRST + 54, GPR_FIRST + 55, \ | |
| 738 GPR_FIRST + 56, GPR_FIRST + 57, GPR_FIRST + 58, GPR_FIRST + 59, \ | |
| 739 GPR_FIRST + 60, GPR_FIRST + 61, GPR_FIRST + 62, GPR_FIRST + 63, \ | |
| 740 GPR_FIRST + 16, GPR_FIRST + 17, \ | |
| 741 \ | |
| 742 FPR_FIRST + 16, FPR_FIRST + 17, FPR_FIRST + 18, FPR_FIRST + 19, \ | |
| 743 FPR_FIRST + 20, FPR_FIRST + 21, FPR_FIRST + 22, FPR_FIRST + 23, \ | |
| 744 FPR_FIRST + 24, FPR_FIRST + 25, FPR_FIRST + 26, FPR_FIRST + 27, \ | |
| 745 FPR_FIRST + 28, FPR_FIRST + 29, FPR_FIRST + 30, FPR_FIRST + 31, \ | |
| 746 FPR_FIRST + 48, FPR_FIRST + 49, FPR_FIRST + 50, FPR_FIRST + 51, \ | |
| 747 FPR_FIRST + 52, FPR_FIRST + 53, FPR_FIRST + 54, FPR_FIRST + 55, \ | |
| 748 FPR_FIRST + 56, FPR_FIRST + 57, FPR_FIRST + 58, FPR_FIRST + 59, \ | |
| 749 FPR_FIRST + 60, FPR_FIRST + 61, FPR_FIRST + 62, FPR_FIRST + 63, \ | |
| 750 \ | |
| 751 /* special or fixed registers */ \ | |
| 752 GPR_FIRST + 0, GPR_FIRST + 1, GPR_FIRST + 2, GPR_FIRST + 3, \ | |
| 753 GPR_FIRST + 28, GPR_FIRST + 29, GPR_FIRST + 30, GPR_FIRST + 31, \ | |
| 754 ACC_FIRST + 0, ACC_FIRST + 1, ACC_FIRST + 2, ACC_FIRST + 3, \ | |
| 755 ACC_FIRST + 4, ACC_FIRST + 5, ACC_FIRST + 6, ACC_FIRST + 7, \ | |
| 756 ACC_FIRST + 8, ACC_FIRST + 9, ACC_FIRST + 10, ACC_FIRST + 11, \ | |
| 757 ACCG_FIRST + 0, ACCG_FIRST + 1, ACCG_FIRST + 2, ACCG_FIRST + 3, \ | |
| 758 ACCG_FIRST + 4, ACCG_FIRST + 5, ACCG_FIRST + 6, ACCG_FIRST + 7, \ | |
| 759 ACCG_FIRST + 8, ACCG_FIRST + 9, ACCG_FIRST + 10, ACCG_FIRST + 11, \ | |
| 760 AP_FIRST, LR_REGNO, LCR_REGNO, \ | |
| 761 IACC_FIRST + 0, IACC_FIRST + 1 \ | |
| 762 } | |
| 763 | |
| 764 | |
| 765 /* How Values Fit in Registers. */ | |
| 766 | |
| 767 /* A C expression for the number of consecutive hard registers, starting at | |
| 768 register number REGNO, required to hold a value of mode MODE. | |
| 769 | |
| 770 On a machine where all registers are exactly one word, a suitable definition | |
| 771 of this macro is | |
| 772 | |
| 773 #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
| 774 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \ | |
| 775 / UNITS_PER_WORD)) */ | |
| 776 | |
| 777 /* On the FRV, make the CC modes take 3 words in the integer registers, so that | |
| 778 we can build the appropriate instructions to properly reload the values. */ | |
| 779 #define HARD_REGNO_NREGS(REGNO, MODE) frv_hard_regno_nregs (REGNO, MODE) | |
| 780 | |
| 781 /* A C expression that is nonzero if it is permissible to store a value of mode | |
| 782 MODE in hard register number REGNO (or in several registers starting with | |
| 783 that one). For a machine where all registers are equivalent, a suitable | |
| 784 definition is | |
| 785 | |
| 786 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1 | |
| 787 | |
| 788 It is not necessary for this macro to check for the numbers of fixed | |
| 789 registers, because the allocation mechanism considers them to be always | |
| 790 occupied. | |
| 791 | |
| 792 On some machines, double-precision values must be kept in even/odd register | |
| 793 pairs. The way to implement that is to define this macro to reject odd | |
| 794 register numbers for such modes. | |
| 795 | |
| 796 The minimum requirement for a mode to be OK in a register is that the | |
| 797 `movMODE' instruction pattern support moves between the register and any | |
| 798 other hard register for which the mode is OK; and that moving a value into | |
| 799 the register and back out not alter it. | |
| 800 | |
| 801 Since the same instruction used to move `SImode' will work for all narrower | |
| 802 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK' | |
| 803 to distinguish between these modes, provided you define patterns `movhi', | |
| 804 etc., to take advantage of this. This is useful because of the interaction | |
| 805 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for | |
| 806 all integer modes to be tieable. | |
| 807 | |
| 808 Many machines have special registers for floating point arithmetic. Often | |
| 809 people assume that floating point machine modes are allowed only in floating | |
| 810 point registers. This is not true. Any registers that can hold integers | |
| 811 can safely *hold* a floating point machine mode, whether or not floating | |
| 812 arithmetic can be done on it in those registers. Integer move instructions | |
| 813 can be used to move the values. | |
| 814 | |
| 815 On some machines, though, the converse is true: fixed-point machine modes | |
| 816 may not go in floating registers. This is true if the floating registers | |
| 817 normalize any value stored in them, because storing a non-floating value | |
| 818 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject | |
| 819 fixed-point machine modes in floating registers. But if the floating | |
| 820 registers do not automatically normalize, if you can store any bit pattern | |
| 821 in one and retrieve it unchanged without a trap, then any machine mode may | |
| 822 go in a floating register, so you can define this macro to say so. | |
| 823 | |
| 824 The primary significance of special floating registers is rather that they | |
| 825 are the registers acceptable in floating point arithmetic instructions. | |
| 826 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by | |
| 827 writing the proper constraints for those instructions. | |
| 828 | |
| 829 On some machines, the floating registers are especially slow to access, so | |
| 830 that it is better to store a value in a stack frame than in such a register | |
| 831 if floating point arithmetic is not being done. As long as the floating | |
| 832 registers are not in class `GENERAL_REGS', they will not be used unless some | |
| 833 pattern's constraint asks for one. */ | |
| 834 #define HARD_REGNO_MODE_OK(REGNO, MODE) frv_hard_regno_mode_ok (REGNO, MODE) | |
| 835 | |
| 836 /* A C expression that is nonzero if it is desirable to choose register | |
| 837 allocation so as to avoid move instructions between a value of mode MODE1 | |
| 838 and a value of mode MODE2. | |
| 839 | |
| 840 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are | |
| 841 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be | |
| 842 zero. */ | |
| 843 #define MODES_TIEABLE_P(MODE1, MODE2) (MODE1 == MODE2) | |
| 844 | |
| 845 /* Define this macro if the compiler should avoid copies to/from CCmode | |
| 846 registers. You should only define this macro if support fo copying to/from | |
| 847 CCmode is incomplete. */ | |
| 848 #define AVOID_CCMODE_COPIES | |
| 849 | |
| 850 | |
| 851 /* Register Classes. */ | |
| 852 | |
| 853 /* An enumeral type that must be defined with all the register class names as | |
| 854 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last | |
| 855 register class, followed by one more enumeral value, `LIM_REG_CLASSES', | |
| 856 which is not a register class but rather tells how many classes there are. | |
| 857 | |
| 858 Each register class has a number, which is the value of casting the class | |
| 859 name to type `int'. The number serves as an index in many of the tables | |
| 860 described below. */ | |
| 861 enum reg_class | |
| 862 { | |
| 863 NO_REGS, | |
| 864 ICC_REGS, | |
| 865 FCC_REGS, | |
| 866 CC_REGS, | |
| 867 ICR_REGS, | |
| 868 FCR_REGS, | |
| 869 CR_REGS, | |
| 870 LCR_REG, | |
| 871 LR_REG, | |
| 872 GR8_REGS, | |
| 873 GR9_REGS, | |
| 874 GR89_REGS, | |
| 875 FDPIC_REGS, | |
| 876 FDPIC_FPTR_REGS, | |
| 877 FDPIC_CALL_REGS, | |
| 878 SPR_REGS, | |
| 879 QUAD_ACC_REGS, | |
| 880 EVEN_ACC_REGS, | |
| 881 ACC_REGS, | |
| 882 ACCG_REGS, | |
| 883 QUAD_FPR_REGS, | |
| 884 FEVEN_REGS, | |
| 885 FPR_REGS, | |
| 886 QUAD_REGS, | |
| 887 EVEN_REGS, | |
| 888 GPR_REGS, | |
| 889 ALL_REGS, | |
| 890 LIM_REG_CLASSES | |
| 891 }; | |
| 892 | |
| 893 #define GENERAL_REGS GPR_REGS | |
| 894 | |
| 895 /* The number of distinct register classes, defined as follows: | |
| 896 | |
| 897 #define N_REG_CLASSES (int) LIM_REG_CLASSES */ | |
| 898 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) | |
| 899 | |
| 900 /* An initializer containing the names of the register classes as C string | |
| 901 constants. These names are used in writing some of the debugging dumps. */ | |
| 902 #define REG_CLASS_NAMES { \ | |
| 903 "NO_REGS", \ | |
| 904 "ICC_REGS", \ | |
| 905 "FCC_REGS", \ | |
| 906 "CC_REGS", \ | |
| 907 "ICR_REGS", \ | |
| 908 "FCR_REGS", \ | |
| 909 "CR_REGS", \ | |
| 910 "LCR_REG", \ | |
| 911 "LR_REG", \ | |
| 912 "GR8_REGS", \ | |
| 913 "GR9_REGS", \ | |
| 914 "GR89_REGS", \ | |
| 915 "FDPIC_REGS", \ | |
| 916 "FDPIC_FPTR_REGS", \ | |
| 917 "FDPIC_CALL_REGS", \ | |
| 918 "SPR_REGS", \ | |
| 919 "QUAD_ACC_REGS", \ | |
| 920 "EVEN_ACC_REGS", \ | |
| 921 "ACC_REGS", \ | |
| 922 "ACCG_REGS", \ | |
| 923 "QUAD_FPR_REGS", \ | |
| 924 "FEVEN_REGS", \ | |
| 925 "FPR_REGS", \ | |
| 926 "QUAD_REGS", \ | |
| 927 "EVEN_REGS", \ | |
| 928 "GPR_REGS", \ | |
| 929 "ALL_REGS" \ | |
| 930 } | |
| 931 | |
| 932 /* An initializer containing the contents of the register classes, as integers | |
| 933 which are bit masks. The Nth integer specifies the contents of class N. | |
| 934 The way the integer MASK is interpreted is that register R is in the class | |
| 935 if `MASK & (1 << R)' is 1. | |
| 936 | |
| 937 When the machine has more than 32 registers, an integer does not suffice. | |
| 938 Then the integers are replaced by sub-initializers, braced groupings | |
| 939 containing several integers. Each sub-initializer must be suitable as an | |
| 940 initializer for the type `HARD_REG_SET' which is defined in | |
| 941 `hard-reg-set.h'. */ | |
| 942 #define REG_CLASS_CONTENTS \ | |
| 943 { /* gr0-gr31 gr32-gr63 fr0-fr31 fr32-fr-63 cc/ccr/acc ap/spr */ \ | |
| 944 { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* NO_REGS */\ | |
| 945 { 0x00000000,0x00000000,0x00000000,0x00000000,0x000000f0,0x0}, /* ICC_REGS */\ | |
| 946 { 0x00000000,0x00000000,0x00000000,0x00000000,0x0000000f,0x0}, /* FCC_REGS */\ | |
| 947 { 0x00000000,0x00000000,0x00000000,0x00000000,0x000000ff,0x0}, /* CC_REGS */\ | |
| 948 { 0x00000000,0x00000000,0x00000000,0x00000000,0x0000f000,0x0}, /* ICR_REGS */\ | |
| 949 { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000f00,0x0}, /* FCR_REGS */\ | |
| 950 { 0x00000000,0x00000000,0x00000000,0x00000000,0x0000ff00,0x0}, /* CR_REGS */\ | |
| 951 { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x400}, /* LCR_REGS */\ | |
| 952 { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x200}, /* LR_REGS */\ | |
| 953 { 0x00000100,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* GR8_REGS */\ | |
| 954 { 0x00000200,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* GR9_REGS */\ | |
| 955 { 0x00000300,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* GR89_REGS */\ | |
| 956 { 0x00008000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_REGS */\ | |
| 957 { 0x00004000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_FPTR_REGS */\ | |
| 958 { 0x0000c000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_CALL_REGS */\ | |
| 959 { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x1e00}, /* SPR_REGS */\ | |
| 960 { 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* QUAD_ACC */\ | |
| 961 { 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* EVEN_ACC */\ | |
| 962 { 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* ACC_REGS */\ | |
| 963 { 0x00000000,0x00000000,0x00000000,0x00000000,0xf0000000,0xff}, /* ACCG_REGS*/\ | |
| 964 { 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* QUAD_FPR */\ | |
| 965 { 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* FEVEN_REG*/\ | |
| 966 { 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* FPR_REGS */\ | |
| 967 { 0x0ffffffc,0xffffffff,0x00000000,0x00000000,0x00000000,0x0}, /* QUAD_REGS*/\ | |
| 968 { 0xfffffffc,0xffffffff,0x00000000,0x00000000,0x00000000,0x0}, /* EVEN_REGS*/\ | |
| 969 { 0xffffffff,0xffffffff,0x00000000,0x00000000,0x00000000,0x100}, /* GPR_REGS */\ | |
| 970 { 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0x1fff}, /* ALL_REGS */\ | |
| 971 } | |
| 972 | |
| 973 /* The following macro defines cover classes for Integrated Register | |
| 974 Allocator. Cover classes is a set of non-intersected register | |
| 975 classes covering all hard registers used for register allocation | |
| 976 purpose. Any move between two registers of a cover class should be | |
| 977 cheaper than load or store of the registers. The macro value is | |
| 978 array of register classes with LIM_REG_CLASSES used as the end | |
| 979 marker. */ | |
| 980 | |
| 981 #define IRA_COVER_CLASSES \ | |
| 982 { \ | |
| 983 GPR_REGS, FPR_REGS, ACC_REGS, ICR_REGS, FCR_REGS, ICC_REGS, FCC_REGS, \ | |
| 984 ACCG_REGS, SPR_REGS, \ | |
| 985 LIM_REG_CLASSES \ | |
| 986 } | |
| 987 | |
| 988 /* A C expression whose value is a register class containing hard register | |
| 989 REGNO. In general there is more than one such class; choose a class which | |
| 990 is "minimal", meaning that no smaller class also contains the register. */ | |
| 991 | |
| 992 extern enum reg_class regno_reg_class[]; | |
| 993 #define REGNO_REG_CLASS(REGNO) regno_reg_class [REGNO] | |
| 994 | |
| 995 /* A macro whose definition is the name of the class to which a valid base | |
| 996 register must belong. A base register is one used in an address which is | |
| 997 the register value plus a displacement. */ | |
| 998 #define BASE_REG_CLASS GPR_REGS | |
| 999 | |
| 1000 /* A macro whose definition is the name of the class to which a valid index | |
| 1001 register must belong. An index register is one used in an address where its | |
| 1002 value is either multiplied by a scale factor or added to another register | |
| 1003 (as well as added to a displacement). */ | |
| 1004 #define INDEX_REG_CLASS GPR_REGS | |
| 1005 | |
| 1006 /* A C expression which is nonzero if register number NUM is suitable for use | |
| 1007 as a base register in operand addresses. It may be either a suitable hard | |
| 1008 register or a pseudo register that has been allocated such a hard register. */ | |
| 1009 #define REGNO_OK_FOR_BASE_P(NUM) \ | |
| 1010 ((NUM) < FIRST_PSEUDO_REGISTER \ | |
| 1011 ? GPR_P (NUM) \ | |
| 1012 : (reg_renumber [NUM] >= 0 && GPR_P (reg_renumber [NUM]))) | |
| 1013 | |
| 1014 /* A C expression which is nonzero if register number NUM is suitable for use | |
| 1015 as an index register in operand addresses. It may be either a suitable hard | |
| 1016 register or a pseudo register that has been allocated such a hard register. | |
| 1017 | |
| 1018 The difference between an index register and a base register is that the | |
| 1019 index register may be scaled. If an address involves the sum of two | |
| 1020 registers, neither one of them scaled, then either one may be labeled the | |
| 1021 "base" and the other the "index"; but whichever labeling is used must fit | |
| 1022 the machine's constraints of which registers may serve in each capacity. | |
| 1023 The compiler will try both labelings, looking for one that is valid, and | |
| 1024 will reload one or both registers only if neither labeling works. */ | |
| 1025 #define REGNO_OK_FOR_INDEX_P(NUM) \ | |
| 1026 ((NUM) < FIRST_PSEUDO_REGISTER \ | |
| 1027 ? GPR_P (NUM) \ | |
| 1028 : (reg_renumber [NUM] >= 0 && GPR_P (reg_renumber [NUM]))) | |
| 1029 | |
| 1030 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
| 1031 frv_secondary_reload_class (CLASS, MODE, X) | |
| 1032 | |
| 1033 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
| 1034 frv_secondary_reload_class (CLASS, MODE, X) | |
| 1035 | |
| 1036 /* A C expression for the maximum number of consecutive registers of | |
| 1037 class CLASS needed to hold a value of mode MODE. | |
| 1038 | |
| 1039 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value | |
| 1040 of the macro `CLASS_MAX_NREGS (CLASS, MODE)' should be the maximum value of | |
| 1041 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class CLASS. | |
| 1042 | |
| 1043 This macro helps control the handling of multiple-word values in | |
| 1044 the reload pass. | |
| 1045 | |
| 1046 This declaration is required. */ | |
| 1047 #define CLASS_MAX_NREGS(CLASS, MODE) frv_class_max_nregs (CLASS, MODE) | |
| 1048 | |
| 1049 #define ZERO_P(x) (x == CONST0_RTX (GET_MODE (x))) | |
| 1050 | |
| 1051 | |
| 1052 /* Basic Stack Layout. */ | |
| 1053 | |
| 1054 /* Structure to describe information about a saved range of registers */ | |
| 1055 | |
| 1056 typedef struct frv_stack_regs { | |
| 1057 const char * name; /* name of the register ranges */ | |
| 1058 int first; /* first register in the range */ | |
| 1059 int last; /* last register in the range */ | |
| 1060 int size_1word; /* # of bytes to be stored via 1 word stores */ | |
| 1061 int size_2words; /* # of bytes to be stored via 2 word stores */ | |
| 1062 unsigned char field_p; /* true if the registers are a single SPR */ | |
| 1063 unsigned char dword_p; /* true if we can do dword stores */ | |
| 1064 unsigned char special_p; /* true if the regs have a fixed save loc. */ | |
| 1065 } frv_stack_regs_t; | |
| 1066 | |
| 1067 /* Register ranges to look into saving. */ | |
| 1068 #define STACK_REGS_GPR 0 /* Gprs (normally gr16..gr31, gr48..gr63) */ | |
| 1069 #define STACK_REGS_FPR 1 /* Fprs (normally fr16..fr31, fr48..fr63) */ | |
| 1070 #define STACK_REGS_LR 2 /* LR register */ | |
| 1071 #define STACK_REGS_CC 3 /* CCrs (normally not saved) */ | |
| 1072 #define STACK_REGS_LCR 5 /* lcr register */ | |
| 1073 #define STACK_REGS_STDARG 6 /* stdarg registers */ | |
| 1074 #define STACK_REGS_STRUCT 7 /* structure return (gr3) */ | |
| 1075 #define STACK_REGS_FP 8 /* FP register */ | |
| 1076 #define STACK_REGS_MAX 9 /* # of register ranges */ | |
| 1077 | |
| 1078 /* Values for save_p field. */ | |
| 1079 #define REG_SAVE_NO_SAVE 0 /* register not saved */ | |
| 1080 #define REG_SAVE_1WORD 1 /* save the register */ | |
| 1081 #define REG_SAVE_2WORDS 2 /* save register and register+1 */ | |
| 1082 | |
| 1083 /* Structure used to define the frv stack. */ | |
| 1084 | |
| 1085 typedef struct frv_stack { | |
| 1086 int total_size; /* total bytes allocated for stack */ | |
| 1087 int vars_size; /* variable save area size */ | |
| 1088 int parameter_size; /* outgoing parameter size */ | |
| 1089 int stdarg_size; /* size of regs needed to be saved for stdarg */ | |
| 1090 int regs_size; /* size of the saved registers */ | |
| 1091 int regs_size_1word; /* # of bytes to be stored via 1 word stores */ | |
| 1092 int regs_size_2words; /* # of bytes to be stored via 2 word stores */ | |
| 1093 int header_size; /* size of the old FP, struct ret., LR save */ | |
| 1094 int pretend_size; /* size of pretend args */ | |
| 1095 int vars_offset; /* offset to save local variables from new SP*/ | |
| 1096 int regs_offset; /* offset to save registers from new SP */ | |
| 1097 /* register range information */ | |
| 1098 frv_stack_regs_t regs[STACK_REGS_MAX]; | |
| 1099 /* offset to store each register */ | |
| 1100 int reg_offset[FIRST_PSEUDO_REGISTER]; | |
| 1101 /* whether to save register (& reg+1) */ | |
| 1102 unsigned char save_p[FIRST_PSEUDO_REGISTER]; | |
| 1103 } frv_stack_t; | |
| 1104 | |
| 1105 /* Define this macro if pushing a word onto the stack moves the stack pointer | |
| 1106 to a smaller address. */ | |
| 1107 #define STACK_GROWS_DOWNWARD 1 | |
| 1108 | |
| 1109 /* Define this macro to nonzero if the addresses of local variable slots | |
| 1110 are at negative offsets from the frame pointer. */ | |
| 1111 #define FRAME_GROWS_DOWNWARD 1 | |
| 1112 | |
| 1113 /* Offset from the frame pointer to the first local variable slot to be | |
| 1114 allocated. | |
| 1115 | |
| 1116 If `FRAME_GROWS_DOWNWARD', find the next slot's offset by subtracting the | |
| 1117 first slot's length from `STARTING_FRAME_OFFSET'. Otherwise, it is found by | |
| 1118 adding the length of the first slot to the value `STARTING_FRAME_OFFSET'. */ | |
| 1119 #define STARTING_FRAME_OFFSET 0 | |
| 1120 | |
| 1121 /* Offset from the stack pointer register to the first location at which | |
| 1122 outgoing arguments are placed. If not specified, the default value of zero | |
| 1123 is used. This is the proper value for most machines. | |
| 1124 | |
| 1125 If `ARGS_GROW_DOWNWARD', this is the offset to the location above the first | |
| 1126 location at which outgoing arguments are placed. */ | |
| 1127 #define STACK_POINTER_OFFSET 0 | |
| 1128 | |
| 1129 /* Offset from the argument pointer register to the first argument's address. | |
| 1130 On some machines it may depend on the data type of the function. | |
| 1131 | |
| 1132 If `ARGS_GROW_DOWNWARD', this is the offset to the location above the first | |
| 1133 argument's address. */ | |
| 1134 #define FIRST_PARM_OFFSET(FUNDECL) 0 | |
| 1135 | |
| 1136 /* A C expression whose value is RTL representing the address in a stack frame | |
| 1137 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is | |
| 1138 an RTL expression for the address of the stack frame itself. | |
| 1139 | |
| 1140 If you don't define this macro, the default is to return the value of | |
| 1141 FRAMEADDR--that is, the stack frame address is also the address of the stack | |
| 1142 word that points to the previous frame. */ | |
| 1143 #define DYNAMIC_CHAIN_ADDRESS(FRAMEADDR) frv_dynamic_chain_address (FRAMEADDR) | |
| 1144 | |
| 1145 /* A C expression whose value is RTL representing the value of the return | |
| 1146 address for the frame COUNT steps up from the current frame, after the | |
| 1147 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame | |
| 1148 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is | |
| 1149 defined. | |
| 1150 | |
| 1151 The value of the expression must always be the correct address when COUNT is | |
| 1152 zero, but may be `NULL_RTX' if there is not way to determine the return | |
| 1153 address of other frames. */ | |
| 1154 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) frv_return_addr_rtx (COUNT, FRAMEADDR) | |
| 1155 | |
| 1156 #define RETURN_POINTER_REGNUM LR_REGNO | |
| 1157 | |
| 1158 /* A C expression whose value is RTL representing the location of the incoming | |
| 1159 return address at the beginning of any function, before the prologue. This | |
| 1160 RTL is either a `REG', indicating that the return value is saved in `REG', | |
| 1161 or a `MEM' representing a location in the stack. | |
| 1162 | |
| 1163 You only need to define this macro if you want to support call frame | |
| 1164 debugging information like that provided by DWARF 2. */ | |
| 1165 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (SImode, RETURN_POINTER_REGNUM) | |
| 1166 | |
| 1167 | |
| 1168 /* Register That Address the Stack Frame. */ | |
| 1169 | |
| 1170 /* The register number of the stack pointer register, which must also be a | |
| 1171 fixed register according to `FIXED_REGISTERS'. On most machines, the | |
| 1172 hardware determines which register this is. */ | |
| 1173 #define STACK_POINTER_REGNUM (GPR_FIRST + 1) | |
| 1174 | |
| 1175 /* The register number of the frame pointer register, which is used to access | |
| 1176 automatic variables in the stack frame. On some machines, the hardware | |
| 1177 determines which register this is. On other machines, you can choose any | |
| 1178 register you wish for this purpose. */ | |
| 1179 #define FRAME_POINTER_REGNUM (GPR_FIRST + 2) | |
| 1180 | |
| 1181 /* The register number of the arg pointer register, which is used to access the | |
| 1182 function's argument list. On some machines, this is the same as the frame | |
| 1183 pointer register. On some machines, the hardware determines which register | |
| 1184 this is. On other machines, you can choose any register you wish for this | |
| 1185 purpose. If this is not the same register as the frame pointer register, | |
| 1186 then you must mark it as a fixed register according to `FIXED_REGISTERS', or | |
| 1187 arrange to be able to eliminate it. */ | |
| 1188 | |
| 1189 /* On frv this is a fake register that is eliminated in | |
| 1190 terms of either the frame pointer or stack pointer. */ | |
| 1191 #define ARG_POINTER_REGNUM AP_FIRST | |
| 1192 | |
| 1193 /* Register numbers used for passing a function's static chain pointer. If | |
| 1194 register windows are used, the register number as seen by the called | |
| 1195 function is `STATIC_CHAIN_INCOMING_REGNUM', while the register number as | |
| 1196 seen by the calling function is `STATIC_CHAIN_REGNUM'. If these registers | |
| 1197 are the same, `STATIC_CHAIN_INCOMING_REGNUM' need not be defined. | |
| 1198 | |
| 1199 The static chain register need not be a fixed register. | |
| 1200 | |
| 1201 If the static chain is passed in memory, these macros should not be defined; | |
| 1202 instead, the next two macros should be defined. */ | |
| 1203 #define STATIC_CHAIN_REGNUM (GPR_FIRST + 7) | |
| 1204 #define STATIC_CHAIN_INCOMING_REGNUM (GPR_FIRST + 7) | |
| 1205 | |
| 1206 | |
| 1207 /* Eliminating the Frame Pointer and the Arg Pointer. */ | |
| 1208 | |
| 1209 /* If defined, this macro specifies a table of register pairs used to eliminate | |
| 1210 unneeded registers that point into the stack frame. If it is not defined, | |
| 1211 the only elimination attempted by the compiler is to replace references to | |
| 1212 the frame pointer with references to the stack pointer. | |
| 1213 | |
| 1214 The definition of this macro is a list of structure initializations, each of | |
| 1215 which specifies an original and replacement register. | |
| 1216 | |
| 1217 On some machines, the position of the argument pointer is not known until | |
| 1218 the compilation is completed. In such a case, a separate hard register must | |
| 1219 be used for the argument pointer. This register can be eliminated by | |
| 1220 replacing it with either the frame pointer or the argument pointer, | |
| 1221 depending on whether or not the frame pointer has been eliminated. | |
| 1222 | |
| 1223 In this case, you might specify: | |
| 1224 #define ELIMINABLE_REGS \ | |
| 1225 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1226 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ | |
| 1227 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} | |
| 1228 | |
| 1229 Note that the elimination of the argument pointer with the stack pointer is | |
| 1230 specified first since that is the preferred elimination. */ | |
| 1231 | |
| 1232 #define ELIMINABLE_REGS \ | |
| 1233 { \ | |
| 1234 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1235 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ | |
| 1236 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM} \ | |
| 1237 } | |
| 1238 | |
| 1239 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the | |
| 1240 initial difference between the specified pair of registers. This macro must | |
| 1241 be defined if `ELIMINABLE_REGS' is defined. */ | |
| 1242 | |
| 1243 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
| 1244 (OFFSET) = frv_initial_elimination_offset (FROM, TO) | |
| 1245 | |
| 1246 | |
| 1247 /* Passing Function Arguments on the Stack. */ | |
| 1248 | |
| 1249 /* If defined, the maximum amount of space required for outgoing arguments will | |
| 1250 be computed and placed into the variable | |
| 1251 `crtl->outgoing_args_size'. No space will be pushed onto the | |
| 1252 stack for each call; instead, the function prologue should increase the | |
| 1253 stack frame size by this amount. | |
| 1254 | |
| 1255 Defining both `PUSH_ROUNDING' and `ACCUMULATE_OUTGOING_ARGS' is not | |
| 1256 proper. */ | |
| 1257 #define ACCUMULATE_OUTGOING_ARGS 1 | |
| 1258 | |
| 1259 | |
| 1260 /* The number of register assigned to holding function arguments. */ | |
| 1261 | |
| 1262 #define FRV_NUM_ARG_REGS 6 | |
| 1263 | |
| 1264 /* A C type for declaring a variable that is used as the first argument of | |
| 1265 `FUNCTION_ARG' and other related values. For some target machines, the type | |
| 1266 `int' suffices and can hold the number of bytes of argument so far. | |
| 1267 | |
| 1268 There is no need to record in `CUMULATIVE_ARGS' anything about the arguments | |
| 1269 that have been passed on the stack. The compiler has other variables to | |
| 1270 keep track of that. For target machines on which all arguments are passed | |
| 1271 on the stack, there is no need to store anything in `CUMULATIVE_ARGS'; | |
| 1272 however, the data structure must exist and should not be empty, so use | |
| 1273 `int'. */ | |
| 1274 #define CUMULATIVE_ARGS int | |
| 1275 | |
| 1276 /* A C statement (sans semicolon) for initializing the variable CUM for the | |
| 1277 state at the beginning of the argument list. The variable has type | |
| 1278 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type | |
| 1279 of the function which will receive the args, or 0 if the args are to a | |
| 1280 compiler support library function. The value of INDIRECT is nonzero when | |
| 1281 processing an indirect call, for example a call through a function pointer. | |
| 1282 The value of INDIRECT is zero for a call to an explicitly named function, a | |
| 1283 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find | |
| 1284 arguments for the function being compiled. | |
| 1285 | |
| 1286 When processing a call to a compiler support library function, LIBNAME | |
| 1287 identifies which one. It is a `symbol_ref' rtx which contains the name of | |
| 1288 the function, as a string. LIBNAME is 0 when an ordinary C function call is | |
| 1289 being processed. Thus, each time this macro is called, either LIBNAME or | |
| 1290 FNTYPE is nonzero, but never both of them at once. */ | |
| 1291 | |
| 1292 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ | |
| 1293 frv_init_cumulative_args (&CUM, FNTYPE, LIBNAME, FNDECL, FALSE) | |
| 1294 | |
| 1295 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the | |
| 1296 arguments for the function being compiled. If this macro is undefined, | |
| 1297 `INIT_CUMULATIVE_ARGS' is used instead. | |
| 1298 | |
| 1299 The value passed for LIBNAME is always 0, since library routines with | |
| 1300 special calling conventions are never compiled with GCC. The argument | |
| 1301 LIBNAME exists for symmetry with `INIT_CUMULATIVE_ARGS'. */ | |
| 1302 | |
| 1303 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ | |
| 1304 frv_init_cumulative_args (&CUM, FNTYPE, LIBNAME, NULL, TRUE) | |
| 1305 | |
| 1306 /* A C expression that is nonzero if REGNO is the number of a hard register in | |
| 1307 which function arguments are sometimes passed. This does *not* include | |
| 1308 implicit arguments such as the static chain and the structure-value address. | |
| 1309 On many machines, no registers can be used for this purpose since all | |
| 1310 function arguments are pushed on the stack. */ | |
| 1311 #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
| 1312 ((REGNO) >= FIRST_ARG_REGNUM && ((REGNO) <= LAST_ARG_REGNUM)) | |
| 1313 | |
| 1314 | |
| 1315 /* How Scalar Function Values are Returned. */ | |
| 1316 | |
| 1317 /* The number of the hard register that is used to return a scalar value from a | |
| 1318 function call. */ | |
| 1319 #define RETURN_VALUE_REGNUM (GPR_FIRST + 8) | |
| 1320 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1321 #define FUNCTION_VALUE_REGNO_P(REGNO) frv_function_value_regno_p (REGNO) |
| 0 | 1322 |
| 1323 | |
| 1324 /* How Large Values are Returned. */ | |
| 1325 | |
| 1326 /* The number of the register that is used to pass the structure | |
| 1327 value address. */ | |
| 1328 #define FRV_STRUCT_VALUE_REGNUM (GPR_FIRST + 3) | |
| 1329 | |
| 1330 | |
| 1331 /* Function Entry and Exit. */ | |
| 1332 | |
| 1333 /* Define this macro as a C expression that is nonzero if the return | |
| 1334 instruction or the function epilogue ignores the value of the stack pointer; | |
| 1335 in other words, if it is safe to delete an instruction to adjust the stack | |
| 1336 pointer before a return from the function. | |
| 1337 | |
| 1338 Note that this macro's value is relevant only for functions for which frame | |
| 1339 pointers are maintained. It is never safe to delete a final stack | |
| 1340 adjustment in a function that has no frame pointer, and the compiler knows | |
| 1341 this regardless of `EXIT_IGNORE_STACK'. */ | |
| 1342 #define EXIT_IGNORE_STACK 1 | |
| 1343 | |
| 1344 /* Generating Code for Profiling. */ | |
| 1345 | |
| 1346 /* A C statement or compound statement to output to FILE some assembler code to | |
| 1347 call the profiling subroutine `mcount'. Before calling, the assembler code | |
| 1348 must load the address of a counter variable into a register where `mcount' | |
| 1349 expects to find the address. The name of this variable is `LP' followed by | |
| 1350 the number LABELNO, so you would generate the name using `LP%d' in a | |
| 1351 `fprintf'. | |
| 1352 | |
| 1353 The details of how the address should be passed to `mcount' are determined | |
| 1354 by your operating system environment, not by GCC. To figure them out, | |
| 1355 compile a small program for profiling using the system's installed C | |
| 1356 compiler and look at the assembler code that results. | |
| 1357 | |
| 1358 This declaration must be present, but it can be an abort if profiling is | |
| 1359 not implemented. */ | |
| 1360 | |
| 1361 #define FUNCTION_PROFILER(FILE, LABELNO) | |
| 1362 | |
| 1363 /* Trampolines for Nested Functions. */ | |
| 1364 | |
| 1365 /* A C expression for the size in bytes of the trampoline, as an integer. */ | |
| 1366 #define TRAMPOLINE_SIZE frv_trampoline_size () | |
| 1367 | |
| 1368 /* Alignment required for trampolines, in bits. | |
| 1369 | |
| 1370 If you don't define this macro, the value of `BIGGEST_ALIGNMENT' is used for | |
| 1371 aligning trampolines. */ | |
| 1372 #define TRAMPOLINE_ALIGNMENT (TARGET_FDPIC ? 64 : 32) | |
| 1373 | |
| 1374 /* Define this macro if trampolines need a special subroutine to do their work. | |
| 1375 The macro should expand to a series of `asm' statements which will be | |
| 1376 compiled with GCC. They go in a library function named | |
| 1377 `__transfer_from_trampoline'. | |
| 1378 | |
| 1379 If you need to avoid executing the ordinary prologue code of a compiled C | |
| 1380 function when you jump to the subroutine, you can do so by placing a special | |
| 1381 label of your own in the assembler code. Use one `asm' statement to | |
| 1382 generate an assembler label, and another to make the label global. Then | |
| 1383 trampolines can use that label to jump directly to your special assembler | |
| 1384 code. */ | |
| 1385 | |
| 1386 #ifdef __FRV_UNDERSCORE__ | |
| 1387 #define TRAMPOLINE_TEMPLATE_NAME "___trampoline_template" | |
| 1388 #else | |
| 1389 #define TRAMPOLINE_TEMPLATE_NAME "__trampoline_template" | |
| 1390 #endif | |
| 1391 | |
| 1392 #define Twrite _write | |
| 1393 | |
| 1394 #if ! __FRV_FDPIC__ | |
| 1395 #define TRANSFER_FROM_TRAMPOLINE \ | |
| 1396 extern int Twrite (int, const void *, unsigned); \ | |
| 1397 \ | |
| 1398 void \ | |
| 1399 __trampoline_setup (short * addr, int size, int fnaddr, int sc) \ | |
| 1400 { \ | |
| 1401 extern short __trampoline_template[]; \ | |
| 1402 short * to = addr; \ | |
| 1403 short * from = &__trampoline_template[0]; \ | |
| 1404 int i; \ | |
| 1405 \ | |
| 1406 if (size < 20) \ | |
| 1407 { \ | |
| 1408 Twrite (2, "__trampoline_setup bad size\n", \ | |
| 1409 sizeof ("__trampoline_setup bad size\n") - 1); \ | |
| 1410 exit (-1); \ | |
| 1411 } \ | |
| 1412 \ | |
| 1413 to[0] = from[0]; \ | |
| 1414 to[1] = (short)(fnaddr); \ | |
| 1415 to[2] = from[2]; \ | |
| 1416 to[3] = (short)(sc); \ | |
| 1417 to[4] = from[4]; \ | |
| 1418 to[5] = (short)(fnaddr >> 16); \ | |
| 1419 to[6] = from[6]; \ | |
| 1420 to[7] = (short)(sc >> 16); \ | |
| 1421 to[8] = from[8]; \ | |
| 1422 to[9] = from[9]; \ | |
| 1423 \ | |
| 1424 for (i = 0; i < 20; i++) \ | |
| 1425 __asm__ volatile ("dcf @(%0,%1)\n\tici @(%0,%1)" :: "r" (to), "r" (i)); \ | |
| 1426 } \ | |
| 1427 \ | |
| 1428 __asm__("\n" \ | |
| 1429 "\t.globl " TRAMPOLINE_TEMPLATE_NAME "\n" \ | |
| 1430 "\t.text\n" \ | |
| 1431 TRAMPOLINE_TEMPLATE_NAME ":\n" \ | |
| 1432 "\tsetlos #0, gr6\n" /* jump register */ \ | |
| 1433 "\tsetlos #0, gr7\n" /* static chain */ \ | |
| 1434 "\tsethi #0, gr6\n" \ | |
| 1435 "\tsethi #0, gr7\n" \ | |
| 1436 "\tjmpl @(gr0,gr6)\n"); | |
| 1437 #else | |
| 1438 #define TRANSFER_FROM_TRAMPOLINE \ | |
| 1439 extern int Twrite (int, const void *, unsigned); \ | |
| 1440 \ | |
| 1441 void \ | |
| 1442 __trampoline_setup (addr, size, fnaddr, sc) \ | |
| 1443 short * addr; \ | |
| 1444 int size; \ | |
| 1445 int fnaddr; \ | |
| 1446 int sc; \ | |
| 1447 { \ | |
| 1448 extern short __trampoline_template[]; \ | |
| 1449 short * from = &__trampoline_template[0]; \ | |
| 1450 int i; \ | |
| 1451 short **desc = (short **)addr; \ | |
| 1452 short * to = addr + 4; \ | |
| 1453 \ | |
| 1454 if (size != 32) \ | |
| 1455 { \ | |
| 1456 Twrite (2, "__trampoline_setup bad size\n", \ | |
| 1457 sizeof ("__trampoline_setup bad size\n") - 1); \ | |
| 1458 exit (-1); \ | |
| 1459 } \ | |
| 1460 \ | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1461 /* Create a function descriptor with the address of the code below \ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1462 and NULL as the FDPIC value. We don't need the real GOT value \ |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1463 here, since we don't use it, so we use NULL, that is just as \ |
| 0 | 1464 good. */ \ |
| 1465 desc[0] = to; \ | |
| 1466 desc[1] = NULL; \ | |
| 1467 size -= 8; \ | |
| 1468 \ | |
| 1469 to[0] = from[0]; \ | |
| 1470 to[1] = (short)(fnaddr); \ | |
| 1471 to[2] = from[2]; \ | |
| 1472 to[3] = (short)(sc); \ | |
| 1473 to[4] = from[4]; \ | |
| 1474 to[5] = (short)(fnaddr >> 16); \ | |
| 1475 to[6] = from[6]; \ | |
| 1476 to[7] = (short)(sc >> 16); \ | |
| 1477 to[8] = from[8]; \ | |
| 1478 to[9] = from[9]; \ | |
| 1479 to[10] = from[10]; \ | |
| 1480 to[11] = from[11]; \ | |
| 1481 \ | |
| 1482 for (i = 0; i < size; i++) \ | |
| 1483 __asm__ volatile ("dcf @(%0,%1)\n\tici @(%0,%1)" :: "r" (to), "r" (i)); \ | |
| 1484 } \ | |
| 1485 \ | |
| 1486 __asm__("\n" \ | |
| 1487 "\t.globl " TRAMPOLINE_TEMPLATE_NAME "\n" \ | |
| 1488 "\t.text\n" \ | |
| 1489 TRAMPOLINE_TEMPLATE_NAME ":\n" \ | |
| 1490 "\tsetlos #0, gr6\n" /* Jump register. */ \ | |
| 1491 "\tsetlos #0, gr7\n" /* Static chain. */ \ | |
| 1492 "\tsethi #0, gr6\n" \ | |
| 1493 "\tsethi #0, gr7\n" \ | |
| 1494 "\tldd @(gr6,gr0),gr14\n" \ | |
| 1495 "\tjmpl @(gr14,gr0)\n" \ | |
| 1496 ); | |
| 1497 #endif | |
| 1498 | |
| 1499 | |
| 1500 /* Addressing Modes. */ | |
| 1501 | |
| 1502 /* A number, the maximum number of registers that can appear in a valid memory | |
| 1503 address. Note that it is up to you to specify a value equal to the maximum | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1504 number that `TARGET_LEGITIMATE_ADDRESS_P' would ever accept. */ |
| 0 | 1505 #define MAX_REGS_PER_ADDRESS 2 |
| 1506 | |
| 1507 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for | |
| 1508 use as a base register. For hard registers, it should always accept those | |
| 1509 which the hardware permits and reject the others. Whether the macro accepts | |
| 1510 or rejects pseudo registers must be controlled by `REG_OK_STRICT' as | |
| 1511 described above. This usually requires two variant definitions, of which | |
| 1512 `REG_OK_STRICT' controls the one actually used. */ | |
| 1513 #ifdef REG_OK_STRICT | |
| 1514 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X)) | |
| 1515 #else | |
| 1516 #define REG_OK_FOR_BASE_P(X) GPR_AP_OR_PSEUDO_P (REGNO (X)) | |
| 1517 #endif | |
| 1518 | |
| 1519 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for | |
| 1520 use as an index register. | |
| 1521 | |
| 1522 The difference between an index register and a base register is that the | |
| 1523 index register may be scaled. If an address involves the sum of two | |
| 1524 registers, neither one of them scaled, then either one may be labeled the | |
| 1525 "base" and the other the "index"; but whichever labeling is used must fit | |
| 1526 the machine's constraints of which registers may serve in each capacity. | |
| 1527 The compiler will try both labelings, looking for one that is valid, and | |
| 1528 will reload one or both registers only if neither labeling works. */ | |
| 1529 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) | |
| 1530 | |
| 1531 #define FIND_BASE_TERM frv_find_base_term | |
| 1532 | |
| 1533 /* A C expression that is nonzero if X is a legitimate constant for an | |
| 1534 immediate operand on the target machine. You can assume that X satisfies | |
| 1535 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable | |
| 1536 definition for this macro on machines where anything `CONSTANT_P' is valid. */ | |
| 1537 #define LEGITIMATE_CONSTANT_P(X) frv_legitimate_constant_p (X) | |
| 1538 | |
| 1539 /* The load-and-update commands allow pre-modification in addresses. | |
| 1540 The index has to be in a register. */ | |
| 1541 #define HAVE_PRE_MODIFY_REG 1 | |
| 1542 | |
| 1543 | |
| 1544 /* We define extra CC modes in frv-modes.def so we need a selector. */ | |
| 1545 | |
| 1546 #define SELECT_CC_MODE frv_select_cc_mode | |
| 1547 | |
| 1548 /* A C expression whose value is one if it is always safe to reverse a | |
| 1549 comparison whose mode is MODE. If `SELECT_CC_MODE' can ever return MODE for | |
| 1550 a floating-point inequality comparison, then `REVERSIBLE_CC_MODE (MODE)' | |
| 1551 must be zero. | |
| 1552 | |
| 1553 You need not define this macro if it would always returns zero or if the | |
| 1554 floating-point format is anything other than `IEEE_FLOAT_FORMAT'. For | |
| 1555 example, here is the definition used on the SPARC, where floating-point | |
| 1556 inequality comparisons are always given `CCFPEmode': | |
| 1557 | |
| 1558 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) */ | |
| 1559 | |
| 1560 /* On frv, don't consider floating point comparisons to be reversible. In | |
| 1561 theory, fp equality comparisons can be reversible. */ | |
| 1562 #define REVERSIBLE_CC_MODE(MODE) \ | |
| 1563 ((MODE) == CCmode || (MODE) == CC_UNSmode || (MODE) == CC_NZmode) | |
| 1564 | |
| 1565 /* Frv CCR_MODE's are not reversible. */ | |
| 1566 #define REVERSE_CONDEXEC_PREDICATES_P(x,y) 0 | |
| 1567 | |
| 1568 | |
| 1569 /* Describing Relative Costs of Operations. */ | |
| 1570 | |
| 1571 /* A C expression for the cost of a branch instruction. A value of 1 is the | |
| 1572 default; other values are interpreted relative to that. */ | |
| 1573 #define BRANCH_COST(speed_p, predictable_p) frv_branch_cost_int | |
| 1574 | |
| 1575 /* Define this macro as a C expression which is nonzero if accessing less than | |
| 1576 a word of memory (i.e. a `char' or a `short') is no faster than accessing a | |
| 1577 word of memory, i.e., if such access require more than one instruction or if | |
| 1578 there is no difference in cost between byte and (aligned) word loads. | |
| 1579 | |
| 1580 When this macro is not defined, the compiler will access a field by finding | |
| 1581 the smallest containing object; when it is defined, a fullword load will be | |
| 1582 used if alignment permits. Unless bytes accesses are faster than word | |
| 1583 accesses, using word accesses is preferable since it may eliminate | |
| 1584 subsequent memory access if subsequent accesses occur to other fields in the | |
| 1585 same word of the structure, but to different bytes. */ | |
| 1586 #define SLOW_BYTE_ACCESS 1 | |
| 1587 | |
| 1588 /* Define this macro if it is as good or better to call a constant function | |
| 1589 address than to call an address kept in a register. */ | |
| 1590 #define NO_FUNCTION_CSE | |
| 1591 | |
| 1592 | |
| 1593 /* Dividing the output into sections. */ | |
| 1594 | |
| 1595 /* A C expression whose value is a string containing the assembler operation | |
| 1596 that should precede instructions and read-only data. Normally `".text"' is | |
| 1597 right. */ | |
| 1598 #define TEXT_SECTION_ASM_OP "\t.text" | |
| 1599 | |
| 1600 /* A C expression whose value is a string containing the assembler operation to | |
| 1601 identify the following data as writable initialized data. Normally | |
| 1602 `".data"' is right. */ | |
| 1603 #define DATA_SECTION_ASM_OP "\t.data" | |
| 1604 | |
| 1605 /* If defined, a C expression whose value is a string containing the | |
| 1606 assembler operation to identify the following data as | |
| 1607 uninitialized global data. If not defined, and neither | |
| 1608 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined, | |
| 1609 uninitialized global data will be output in the data section if | |
| 1610 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be | |
| 1611 used. */ | |
| 1612 #define BSS_SECTION_ASM_OP "\t.section .bss,\"aw\"" | |
| 1613 | |
| 1614 /* Short Data Support */ | |
| 1615 #define SDATA_SECTION_ASM_OP "\t.section .sdata,\"aw\"" | |
| 1616 | |
| 1617 #undef INIT_SECTION_ASM_OP | |
| 1618 #undef FINI_SECTION_ASM_OP | |
| 1619 #define INIT_SECTION_ASM_OP "\t.section .init,\"ax\"" | |
| 1620 #define FINI_SECTION_ASM_OP "\t.section .fini,\"ax\"" | |
| 1621 | |
| 1622 #undef CTORS_SECTION_ASM_OP | |
| 1623 #undef DTORS_SECTION_ASM_OP | |
| 1624 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\"" | |
| 1625 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\"" | |
| 1626 | |
| 1627 /* A C expression whose value is a string containing the assembler operation to | |
| 1628 switch to the fixup section that records all initialized pointers in a -fpic | |
| 1629 program so they can be changed program startup time if the program is loaded | |
| 1630 at a different address than linked for. */ | |
| 1631 #define FIXUP_SECTION_ASM_OP "\t.section .rofixup,\"a\"" | |
| 1632 | |
| 1633 /* Position Independent Code. */ | |
| 1634 | |
| 1635 /* A C expression that is nonzero if X is a legitimate immediate operand on the | |
| 1636 target machine when generating position independent code. You can assume | |
| 1637 that X satisfies `CONSTANT_P', so you need not check this. You can also | |
| 1638 assume FLAG_PIC is true, so you need not check it either. You need not | |
| 1639 define this macro if all constants (including `SYMBOL_REF') can be immediate | |
| 1640 operands when generating position independent code. */ | |
| 1641 #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
| 1642 ( GET_CODE (X) == CONST_INT \ | |
| 1643 || GET_CODE (X) == CONST_DOUBLE \ | |
| 1644 || (GET_CODE (X) == HIGH && GET_CODE (XEXP (X, 0)) == CONST_INT) \ | |
| 1645 || got12_operand (X, VOIDmode)) \ | |
| 1646 | |
| 1647 | |
| 1648 /* The Overall Framework of an Assembler File. */ | |
| 1649 | |
| 1650 /* A C string constant describing how to begin a comment in the target | |
| 1651 assembler language. The compiler assumes that the comment will end at the | |
| 1652 end of the line. */ | |
| 1653 #define ASM_COMMENT_START ";" | |
| 1654 | |
| 1655 /* A C string constant for text to be output before each `asm' statement or | |
| 1656 group of consecutive ones. Normally this is `"#APP"', which is a comment | |
| 1657 that has no effect on most assemblers but tells the GNU assembler that it | |
| 1658 must check the lines that follow for all valid assembler constructs. */ | |
| 1659 #define ASM_APP_ON "#APP\n" | |
| 1660 | |
| 1661 /* A C string constant for text to be output after each `asm' statement or | |
| 1662 group of consecutive ones. Normally this is `"#NO_APP"', which tells the | |
| 1663 GNU assembler to resume making the time-saving assumptions that are valid | |
| 1664 for ordinary compiler output. */ | |
| 1665 #define ASM_APP_OFF "#NO_APP\n" | |
| 1666 | |
| 1667 | |
| 1668 /* Output of Data. */ | |
| 1669 | |
| 1670 /* This is how to output a label to dwarf/dwarf2. */ | |
| 1671 #define ASM_OUTPUT_DWARF_ADDR(STREAM, LABEL) \ | |
| 1672 do { \ | |
| 1673 fprintf (STREAM, "\t.picptr\t"); \ | |
| 1674 assemble_name (STREAM, LABEL); \ | |
| 1675 } while (0) | |
| 1676 | |
| 1677 /* Whether to emit the gas specific dwarf2 line number support. */ | |
| 1678 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DEBUG_LOC) | |
| 1679 | |
| 1680 /* Output of Uninitialized Variables. */ | |
| 1681 | |
| 1682 /* A C statement (sans semicolon) to output to the stdio stream STREAM the | |
| 1683 assembler definition of a local-common-label named NAME whose size is SIZE | |
| 1684 bytes. The variable ROUNDED is the size rounded up to whatever alignment | |
| 1685 the caller wants. | |
| 1686 | |
| 1687 Use the expression `assemble_name (STREAM, NAME)' to output the name itself; | |
| 1688 before and after that, output the additional assembler syntax for defining | |
| 1689 the name, and a newline. | |
| 1690 | |
| 1691 This macro controls how the assembler definitions of uninitialized static | |
| 1692 variables are output. */ | |
| 1693 #undef ASM_OUTPUT_LOCAL | |
| 1694 | |
| 1695 #undef ASM_OUTPUT_ALIGNED_LOCAL | |
| 1696 | |
| 1697 /* This is for final.c, because it is used by ASM_DECLARE_OBJECT_NAME. */ | |
| 1698 extern int size_directive_output; | |
| 1699 | |
| 1700 /* Like `ASM_OUTPUT_ALIGNED_LOCAL' except that it takes an additional | |
| 1701 parameter - the DECL of variable to be output, if there is one. | |
| 1702 This macro can be called with DECL == NULL_TREE. If you define | |
| 1703 this macro, it is used in place of `ASM_OUTPUT_LOCAL' and | |
| 1704 `ASM_OUTPUT_ALIGNED_LOCAL', and gives you more flexibility in | |
| 1705 handling the destination of the variable. */ | |
| 1706 #undef ASM_OUTPUT_ALIGNED_DECL_LOCAL | |
| 1707 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGN) \ | |
| 1708 do { \ | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1709 if ((SIZE) > 0 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \ |
| 0 | 1710 switch_to_section (get_named_section (NULL, ".sbss", 0)); \ |
| 1711 else \ | |
| 1712 switch_to_section (bss_section); \ | |
| 1713 ASM_OUTPUT_ALIGN (STREAM, floor_log2 ((ALIGN) / BITS_PER_UNIT)); \ | |
| 1714 ASM_DECLARE_OBJECT_NAME (STREAM, NAME, DECL); \ | |
| 1715 ASM_OUTPUT_SKIP (STREAM, (SIZE) ? (SIZE) : 1); \ | |
| 1716 } while (0) | |
| 1717 | |
| 1718 | |
| 1719 /* Output and Generation of Labels. */ | |
| 1720 | |
| 1721 /* A C statement (sans semicolon) to output to the stdio stream STREAM the | |
| 1722 assembler definition of a label named NAME. Use the expression | |
| 1723 `assemble_name (STREAM, NAME)' to output the name itself; before and after | |
| 1724 that, output the additional assembler syntax for defining the name, and a | |
| 1725 newline. */ | |
| 1726 #define ASM_OUTPUT_LABEL(STREAM, NAME) \ | |
| 1727 do { \ | |
| 1728 assemble_name (STREAM, NAME); \ | |
| 1729 fputs (":\n", STREAM); \ | |
| 1730 } while (0) | |
| 1731 | |
| 1732 /* Globalizing directive for a label. */ | |
| 1733 #define GLOBAL_ASM_OP "\t.globl " | |
| 1734 | |
| 1735 #undef ASM_GENERATE_INTERNAL_LABEL | |
| 1736 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ | |
| 1737 do { \ | |
| 1738 sprintf (LABEL, "*.%s%ld", PREFIX, (long)NUM); \ | |
| 1739 } while (0) | |
| 1740 | |
| 1741 | |
| 1742 /* Macros Controlling Initialization Routines. */ | |
| 1743 | |
| 1744 #undef INIT_SECTION_ASM_OP | |
| 1745 | |
| 1746 /* If defined, `main' will call `__main' despite the presence of | |
| 1747 `INIT_SECTION_ASM_OP'. This macro should be defined for systems where the | |
| 1748 init section is not actually run automatically, but is still useful for | |
| 1749 collecting the lists of constructors and destructors. */ | |
| 1750 #define INVOKE__main | |
| 1751 | |
| 1752 /* Output of Assembler Instructions. */ | |
| 1753 | |
| 1754 /* A C initializer containing the assembler's names for the machine registers, | |
| 1755 each one as a C string constant. This is what translates register numbers | |
| 1756 in the compiler into assembler language. */ | |
| 1757 #define REGISTER_NAMES \ | |
| 1758 { \ | |
| 1759 "gr0", "sp", "fp", "gr3", "gr4", "gr5", "gr6", "gr7", \ | |
| 1760 "gr8", "gr9", "gr10", "gr11", "gr12", "gr13", "gr14", "gr15", \ | |
| 1761 "gr16", "gr17", "gr18", "gr19", "gr20", "gr21", "gr22", "gr23", \ | |
| 1762 "gr24", "gr25", "gr26", "gr27", "gr28", "gr29", "gr30", "gr31", \ | |
| 1763 "gr32", "gr33", "gr34", "gr35", "gr36", "gr37", "gr38", "gr39", \ | |
| 1764 "gr40", "gr41", "gr42", "gr43", "gr44", "gr45", "gr46", "gr47", \ | |
| 1765 "gr48", "gr49", "gr50", "gr51", "gr52", "gr53", "gr54", "gr55", \ | |
| 1766 "gr56", "gr57", "gr58", "gr59", "gr60", "gr61", "gr62", "gr63", \ | |
| 1767 \ | |
| 1768 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \ | |
| 1769 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \ | |
| 1770 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \ | |
| 1771 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \ | |
| 1772 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \ | |
| 1773 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \ | |
| 1774 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \ | |
| 1775 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \ | |
| 1776 \ | |
| 1777 "fcc0", "fcc1", "fcc2", "fcc3", "icc0", "icc1", "icc2", "icc3", \ | |
| 1778 "cc0", "cc1", "cc2", "cc3", "cc4", "cc5", "cc6", "cc7", \ | |
| 1779 "acc0", "acc1", "acc2", "acc3", "acc4", "acc5", "acc6", "acc7", \ | |
| 1780 "acc8", "acc9", "acc10", "acc11", \ | |
| 1781 "accg0","accg1","accg2","accg3","accg4","accg5","accg6","accg7", \ | |
| 1782 "accg8", "accg9", "accg10", "accg11", \ | |
| 1783 "ap", "lr", "lcr", "iacc0h", "iacc0l" \ | |
| 1784 } | |
| 1785 | |
| 1786 /* Define this macro if you are using an unusual assembler that | |
| 1787 requires different names for the machine instructions. | |
| 1788 | |
| 1789 The definition is a C statement or statements which output an | |
| 1790 assembler instruction opcode to the stdio stream STREAM. The | |
| 1791 macro-operand PTR is a variable of type `char *' which points to | |
| 1792 the opcode name in its "internal" form--the form that is written | |
| 1793 in the machine description. The definition should output the | |
| 1794 opcode name to STREAM, performing any translation you desire, and | |
| 1795 increment the variable PTR to point at the end of the opcode so | |
| 1796 that it will not be output twice. | |
| 1797 | |
| 1798 In fact, your macro definition may process less than the entire | |
| 1799 opcode name, or more than the opcode name; but if you want to | |
| 1800 process text that includes `%'-sequences to substitute operands, | |
| 1801 you must take care of the substitution yourself. Just be sure to | |
| 1802 increment PTR over whatever text should not be output normally. | |
| 1803 | |
| 1804 If you need to look at the operand values, they can be found as the | |
| 1805 elements of `recog_operand'. | |
| 1806 | |
| 1807 If the macro definition does nothing, the instruction is output in | |
| 1808 the usual way. */ | |
| 1809 | |
| 1810 #define ASM_OUTPUT_OPCODE(STREAM, PTR)\ | |
| 1811 (PTR) = frv_asm_output_opcode (STREAM, PTR) | |
| 1812 | |
| 1813 /* If defined, a C statement to be executed just prior to the output | |
| 1814 of assembler code for INSN, to modify the extracted operands so | |
| 1815 they will be output differently. | |
| 1816 | |
| 1817 Here the argument OPVEC is the vector containing the operands | |
| 1818 extracted from INSN, and NOPERANDS is the number of elements of | |
| 1819 the vector which contain meaningful data for this insn. The | |
| 1820 contents of this vector are what will be used to convert the insn | |
| 1821 template into assembler code, so you can change the assembler | |
| 1822 output by changing the contents of the vector. | |
| 1823 | |
| 1824 This macro is useful when various assembler syntaxes share a single | |
| 1825 file of instruction patterns; by defining this macro differently, | |
| 1826 you can cause a large class of instructions to be output | |
| 1827 differently (such as with rearranged operands). Naturally, | |
| 1828 variations in assembler syntax affecting individual insn patterns | |
| 1829 ought to be handled by writing conditional output routines in | |
| 1830 those patterns. | |
| 1831 | |
| 1832 If this macro is not defined, it is equivalent to a null statement. */ | |
| 1833 | |
| 1834 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)\ | |
| 1835 frv_final_prescan_insn (INSN, OPVEC, NOPERANDS) | |
| 1836 | |
| 1837 #undef USER_LABEL_PREFIX | |
| 1838 #define USER_LABEL_PREFIX "" | |
| 1839 #define REGISTER_PREFIX "" | |
| 1840 #define LOCAL_LABEL_PREFIX "." | |
| 1841 #define IMMEDIATE_PREFIX "#" | |
| 1842 | |
| 1843 | |
| 1844 /* Output of dispatch tables. */ | |
| 1845 | |
| 1846 /* This macro should be provided on machines where the addresses in a dispatch | |
| 1847 table are relative to the table's own address. | |
| 1848 | |
| 1849 The definition should be a C statement to output to the stdio stream STREAM | |
| 1850 an assembler pseudo-instruction to generate a difference between two labels. | |
| 1851 VALUE and REL are the numbers of two internal labels. The definitions of | |
| 1852 these labels are output using `(*targetm.asm_out.internal_label)', and they must be | |
| 1853 printed in the same way here. For example, | |
| 1854 | |
| 1855 fprintf (STREAM, "\t.word L%d-L%d\n", VALUE, REL) */ | |
| 1856 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ | |
| 1857 fprintf (STREAM, "\t.word .L%d-.L%d\n", VALUE, REL) | |
| 1858 | |
| 1859 /* This macro should be provided on machines where the addresses in a dispatch | |
| 1860 table are absolute. | |
| 1861 | |
| 1862 The definition should be a C statement to output to the stdio stream STREAM | |
| 1863 an assembler pseudo-instruction to generate a reference to a label. VALUE | |
| 1864 is the number of an internal label whose definition is output using | |
| 1865 `(*targetm.asm_out.internal_label)'. For example, | |
| 1866 | |
| 1867 fprintf (STREAM, "\t.word L%d\n", VALUE) */ | |
| 1868 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ | |
| 1869 fprintf (STREAM, "\t.word .L%d\n", VALUE) | |
| 1870 | |
| 1871 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) | |
| 1872 | |
| 1873 /* Assembler Commands for Exception Regions. */ | |
| 1874 | |
| 1875 /* Define this macro to 0 if your target supports DWARF 2 frame unwind | |
| 1876 information, but it does not yet work with exception handling. Otherwise, | |
| 1877 if your target supports this information (if it defines | |
| 1878 `INCOMING_RETURN_ADDR_RTX' and either `UNALIGNED_INT_ASM_OP' or | |
| 1879 `OBJECT_FORMAT_ELF'), GCC will provide a default definition of 1. | |
| 1880 | |
| 1881 If this macro is defined to 1, the DWARF 2 unwinder will be the default | |
| 1882 exception handling mechanism; otherwise, setjmp/longjmp will be used by | |
| 1883 default. | |
| 1884 | |
| 1885 If this macro is defined to anything, the DWARF 2 unwinder will be used | |
| 1886 instead of inline unwinders and __unwind_function in the non-setjmp case. */ | |
| 1887 #define DWARF2_UNWIND_INFO 1 | |
| 1888 | |
| 1889 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) | |
| 1890 | |
| 1891 /* Assembler Commands for Alignment. */ | |
| 1892 | |
| 1893 #undef ASM_OUTPUT_SKIP | |
| 1894 #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \ | |
| 1895 fprintf (STREAM, "\t.zero\t%u\n", (int)(NBYTES)) | |
| 1896 | |
| 1897 /* A C statement to output to the stdio stream STREAM an assembler command to | |
| 1898 advance the location counter to a multiple of 2 to the POWER bytes. POWER | |
| 1899 will be a C expression of type `int'. */ | |
| 1900 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ | |
| 1901 fprintf ((STREAM), "\t.p2align %d\n", (POWER)) | |
| 1902 | |
| 1903 /* Inside the text section, align with unpacked nops rather than zeros. */ | |
| 1904 #define ASM_OUTPUT_ALIGN_WITH_NOP(STREAM, POWER) \ | |
| 1905 fprintf ((STREAM), "\t.p2alignl %d,0x80880000\n", (POWER)) | |
| 1906 | |
| 1907 /* Macros Affecting all Debug Formats. */ | |
| 1908 | |
| 1909 /* A C expression that returns the DBX register number for the compiler | |
| 1910 register number REGNO. In simple cases, the value of this expression may be | |
| 1911 REGNO itself. But sometimes there are some registers that the compiler | |
| 1912 knows about and DBX does not, or vice versa. In such cases, some register | |
| 1913 may need to have one number in the compiler and another for DBX. | |
| 1914 | |
| 1915 If two registers have consecutive numbers inside GCC, and they can be | |
| 1916 used as a pair to hold a multiword value, then they *must* have consecutive | |
| 1917 numbers after renumbering with `DBX_REGISTER_NUMBER'. Otherwise, debuggers | |
| 1918 will be unable to access such a pair, because they expect register pairs to | |
| 1919 be consecutive in their own numbering scheme. | |
| 1920 | |
| 1921 If you find yourself defining `DBX_REGISTER_NUMBER' in way that does not | |
| 1922 preserve register pairs, then what you must do instead is redefine the | |
| 1923 actual register numbering scheme. | |
| 1924 | |
| 1925 This declaration is required. */ | |
| 1926 #define DBX_REGISTER_NUMBER(REGNO) (REGNO) | |
| 1927 | |
| 1928 #undef PREFERRED_DEBUGGING_TYPE | |
| 1929 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG | |
| 1930 | |
| 1931 /* Miscellaneous Parameters. */ | |
| 1932 | |
| 1933 /* An alias for a machine mode name. This is the machine mode that elements of | |
| 1934 a jump-table should have. */ | |
| 1935 #define CASE_VECTOR_MODE SImode | |
| 1936 | |
| 1937 /* Define this macro if operations between registers with integral mode smaller | |
| 1938 than a word are always performed on the entire register. Most RISC machines | |
| 1939 have this property and most CISC machines do not. */ | |
| 1940 #define WORD_REGISTER_OPERATIONS | |
| 1941 | |
| 1942 /* Define this macro to be a C expression indicating when insns that read | |
| 1943 memory in MODE, an integral mode narrower than a word, set the bits outside | |
| 1944 of MODE to be either the sign-extension or the zero-extension of the data | |
| 1945 read. Return `SIGN_EXTEND' for values of MODE for which the insn | |
| 1946 sign-extends, `ZERO_EXTEND' for which it zero-extends, and `UNKNOWN' for other | |
| 1947 modes. | |
| 1948 | |
| 1949 This macro is not called with MODE non-integral or with a width greater than | |
| 1950 or equal to `BITS_PER_WORD', so you may return any value in this case. Do | |
| 1951 not define this macro if it would always return `UNKNOWN'. On machines where | |
| 1952 this macro is defined, you will normally define it as the constant | |
| 1953 `SIGN_EXTEND' or `ZERO_EXTEND'. */ | |
| 1954 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND | |
| 1955 | |
| 1956 /* Define if loading short immediate values into registers sign extends. */ | |
| 1957 #define SHORT_IMMEDIATES_SIGN_EXTEND | |
| 1958 | |
| 1959 /* The maximum number of bytes that a single instruction can move quickly from | |
| 1960 memory to memory. */ | |
| 1961 #define MOVE_MAX 8 | |
| 1962 | |
| 1963 /* A C expression which is nonzero if on this machine it is safe to "convert" | |
| 1964 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller | |
| 1965 than INPREC) by merely operating on it as if it had only OUTPREC bits. | |
| 1966 | |
| 1967 On many machines, this expression can be 1. | |
| 1968 | |
| 1969 When `TRULY_NOOP_TRUNCATION' returns 1 for a pair of sizes for modes for | |
| 1970 which `MODES_TIEABLE_P' is 0, suboptimal code can result. If this is the | |
| 1971 case, making `TRULY_NOOP_TRUNCATION' return 0 in such cases may improve | |
| 1972 things. */ | |
| 1973 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
| 1974 | |
| 1975 /* An alias for the machine mode for pointers. On most machines, define this | |
| 1976 to be the integer mode corresponding to the width of a hardware pointer; | |
| 1977 `SImode' on 32-bit machine or `DImode' on 64-bit machines. On some machines | |
| 1978 you must define this to be one of the partial integer modes, such as | |
| 1979 `PSImode'. | |
| 1980 | |
| 1981 The width of `Pmode' must be at least as large as the value of | |
| 1982 `POINTER_SIZE'. If it is not equal, you must define the macro | |
| 1983 `POINTERS_EXTEND_UNSIGNED' to specify how pointers are extended to `Pmode'. */ | |
| 1984 #define Pmode SImode | |
| 1985 | |
| 1986 /* An alias for the machine mode used for memory references to functions being | |
| 1987 called, in `call' RTL expressions. On most machines this should be | |
| 1988 `QImode'. */ | |
| 1989 #define FUNCTION_MODE QImode | |
| 1990 | |
| 1991 /* A C expression for the maximum number of instructions to execute via | |
| 1992 conditional execution instructions instead of a branch. A value of | |
| 1993 BRANCH_COST+1 is the default if the machine does not use | |
| 1994 cc0, and 1 if it does use cc0. */ | |
| 1995 #define MAX_CONDITIONAL_EXECUTE frv_condexec_insns | |
| 1996 | |
| 1997 /* A C expression to modify the code described by the conditional if | |
| 1998 information CE_INFO, possibly updating the tests in TRUE_EXPR, and | |
| 1999 FALSE_EXPR for converting if-then and if-then-else code to conditional | |
| 2000 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the | |
| 2001 tests cannot be converted. */ | |
| 2002 #define IFCVT_MODIFY_TESTS(CE_INFO, TRUE_EXPR, FALSE_EXPR) \ | |
| 2003 frv_ifcvt_modify_tests (CE_INFO, &TRUE_EXPR, &FALSE_EXPR) | |
| 2004 | |
| 2005 /* A C expression to modify the code described by the conditional if | |
| 2006 information CE_INFO, for the basic block BB, possibly updating the tests in | |
| 2007 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or | |
| 2008 if-then-else code to conditional instructions. OLD_TRUE and OLD_FALSE are | |
| 2009 the previous tests. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if | |
| 2010 the tests cannot be converted. */ | |
| 2011 #define IFCVT_MODIFY_MULTIPLE_TESTS(CE_INFO, BB, TRUE_EXPR, FALSE_EXPR) \ | |
| 2012 frv_ifcvt_modify_multiple_tests (CE_INFO, BB, &TRUE_EXPR, &FALSE_EXPR) | |
| 2013 | |
| 2014 /* A C expression to modify the code described by the conditional if | |
| 2015 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null | |
| 2016 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that | |
| 2017 insn cannot be converted to be executed conditionally. */ | |
| 2018 #define IFCVT_MODIFY_INSN(CE_INFO, PATTERN, INSN) \ | |
| 2019 (PATTERN) = frv_ifcvt_modify_insn (CE_INFO, PATTERN, INSN) | |
| 2020 | |
| 2021 /* A C expression to perform any final machine dependent modifications in | |
| 2022 converting code to conditional execution in the code described by the | |
| 2023 conditional if information CE_INFO. */ | |
| 2024 #define IFCVT_MODIFY_FINAL(CE_INFO) frv_ifcvt_modify_final (CE_INFO) | |
| 2025 | |
| 2026 /* A C expression to cancel any machine dependent modifications in converting | |
| 2027 code to conditional execution in the code described by the conditional if | |
| 2028 information CE_INFO. */ | |
| 2029 #define IFCVT_MODIFY_CANCEL(CE_INFO) frv_ifcvt_modify_cancel (CE_INFO) | |
| 2030 | |
| 2031 /* Initialize the extra fields provided by IFCVT_EXTRA_FIELDS. */ | |
| 2032 #define IFCVT_INIT_EXTRA_FIELDS(CE_INFO) frv_ifcvt_init_extra_fields (CE_INFO) | |
| 2033 | |
| 2034 /* The definition of the following macro results in that the 2nd jump | |
| 2035 optimization (after the 2nd insn scheduling) is minimal. It is | |
| 2036 necessary to define when start cycle marks of insns (TImode is used | |
| 2037 for this) is used for VLIW insn packing. Some jump optimizations | |
| 2038 make such marks invalid. These marks are corrected for some | |
| 2039 (minimal) optimizations. ??? Probably the macro is temporary. | |
| 2040 Final solution could making the 2nd jump optimizations before the | |
| 2041 2nd instruction scheduling or corrections of the marks for all jump | |
| 2042 optimizations. Although some jump optimizations are actually | |
| 2043 deoptimizations for VLIW (super-scalar) processors. */ | |
| 2044 | |
| 2045 #define MINIMAL_SECOND_JUMP_OPTIMIZATION | |
| 2046 | |
| 2047 | |
| 2048 /* If the following macro is defined and nonzero and deterministic | |
| 2049 finite state automata are used for pipeline hazard recognition, we | |
| 2050 will try to exchange insns in queue ready to improve the schedule. | |
| 2051 The more macro value, the more tries will be made. */ | |
| 2052 #define FIRST_CYCLE_MULTIPASS_SCHEDULING 1 | |
| 2053 | |
| 2054 /* The following macro is used only when value of | |
| 2055 FIRST_CYCLE_MULTIPASS_SCHEDULING is nonzero. The more macro value, | |
| 2056 the more tries will be made to choose better schedule. If the | |
| 2057 macro value is zero or negative there will be no multi-pass | |
| 2058 scheduling. */ | |
| 2059 #define FIRST_CYCLE_MULTIPASS_SCHEDULING_LOOKAHEAD frv_sched_lookahead | |
| 2060 | |
| 2061 enum frv_builtins | |
| 2062 { | |
| 2063 FRV_BUILTIN_MAND, | |
| 2064 FRV_BUILTIN_MOR, | |
| 2065 FRV_BUILTIN_MXOR, | |
| 2066 FRV_BUILTIN_MNOT, | |
| 2067 FRV_BUILTIN_MAVEH, | |
| 2068 FRV_BUILTIN_MSATHS, | |
| 2069 FRV_BUILTIN_MSATHU, | |
| 2070 FRV_BUILTIN_MADDHSS, | |
| 2071 FRV_BUILTIN_MADDHUS, | |
| 2072 FRV_BUILTIN_MSUBHSS, | |
| 2073 FRV_BUILTIN_MSUBHUS, | |
| 2074 FRV_BUILTIN_MPACKH, | |
| 2075 FRV_BUILTIN_MQADDHSS, | |
| 2076 FRV_BUILTIN_MQADDHUS, | |
| 2077 FRV_BUILTIN_MQSUBHSS, | |
| 2078 FRV_BUILTIN_MQSUBHUS, | |
| 2079 FRV_BUILTIN_MUNPACKH, | |
| 2080 FRV_BUILTIN_MDPACKH, | |
| 2081 FRV_BUILTIN_MBTOH, | |
| 2082 FRV_BUILTIN_MHTOB, | |
| 2083 FRV_BUILTIN_MCOP1, | |
| 2084 FRV_BUILTIN_MCOP2, | |
| 2085 FRV_BUILTIN_MROTLI, | |
| 2086 FRV_BUILTIN_MROTRI, | |
| 2087 FRV_BUILTIN_MWCUT, | |
| 2088 FRV_BUILTIN_MSLLHI, | |
| 2089 FRV_BUILTIN_MSRLHI, | |
| 2090 FRV_BUILTIN_MSRAHI, | |
| 2091 FRV_BUILTIN_MEXPDHW, | |
| 2092 FRV_BUILTIN_MEXPDHD, | |
| 2093 FRV_BUILTIN_MMULHS, | |
| 2094 FRV_BUILTIN_MMULHU, | |
| 2095 FRV_BUILTIN_MMULXHS, | |
| 2096 FRV_BUILTIN_MMULXHU, | |
| 2097 FRV_BUILTIN_MMACHS, | |
| 2098 FRV_BUILTIN_MMACHU, | |
| 2099 FRV_BUILTIN_MMRDHS, | |
| 2100 FRV_BUILTIN_MMRDHU, | |
| 2101 FRV_BUILTIN_MQMULHS, | |
| 2102 FRV_BUILTIN_MQMULHU, | |
| 2103 FRV_BUILTIN_MQMULXHU, | |
| 2104 FRV_BUILTIN_MQMULXHS, | |
| 2105 FRV_BUILTIN_MQMACHS, | |
| 2106 FRV_BUILTIN_MQMACHU, | |
| 2107 FRV_BUILTIN_MCPXRS, | |
| 2108 FRV_BUILTIN_MCPXRU, | |
| 2109 FRV_BUILTIN_MCPXIS, | |
| 2110 FRV_BUILTIN_MCPXIU, | |
| 2111 FRV_BUILTIN_MQCPXRS, | |
| 2112 FRV_BUILTIN_MQCPXRU, | |
| 2113 FRV_BUILTIN_MQCPXIS, | |
| 2114 FRV_BUILTIN_MQCPXIU, | |
| 2115 FRV_BUILTIN_MCUT, | |
| 2116 FRV_BUILTIN_MCUTSS, | |
| 2117 FRV_BUILTIN_MWTACC, | |
| 2118 FRV_BUILTIN_MWTACCG, | |
| 2119 FRV_BUILTIN_MRDACC, | |
| 2120 FRV_BUILTIN_MRDACCG, | |
| 2121 FRV_BUILTIN_MTRAP, | |
| 2122 FRV_BUILTIN_MCLRACC, | |
| 2123 FRV_BUILTIN_MCLRACCA, | |
| 2124 FRV_BUILTIN_MDUNPACKH, | |
| 2125 FRV_BUILTIN_MBTOHE, | |
| 2126 FRV_BUILTIN_MQXMACHS, | |
| 2127 FRV_BUILTIN_MQXMACXHS, | |
| 2128 FRV_BUILTIN_MQMACXHS, | |
| 2129 FRV_BUILTIN_MADDACCS, | |
| 2130 FRV_BUILTIN_MSUBACCS, | |
| 2131 FRV_BUILTIN_MASACCS, | |
| 2132 FRV_BUILTIN_MDADDACCS, | |
| 2133 FRV_BUILTIN_MDSUBACCS, | |
| 2134 FRV_BUILTIN_MDASACCS, | |
| 2135 FRV_BUILTIN_MABSHS, | |
| 2136 FRV_BUILTIN_MDROTLI, | |
| 2137 FRV_BUILTIN_MCPLHI, | |
| 2138 FRV_BUILTIN_MCPLI, | |
| 2139 FRV_BUILTIN_MDCUTSSI, | |
| 2140 FRV_BUILTIN_MQSATHS, | |
| 2141 FRV_BUILTIN_MQLCLRHS, | |
| 2142 FRV_BUILTIN_MQLMTHS, | |
| 2143 FRV_BUILTIN_MQSLLHI, | |
| 2144 FRV_BUILTIN_MQSRAHI, | |
| 2145 FRV_BUILTIN_MHSETLOS, | |
| 2146 FRV_BUILTIN_MHSETLOH, | |
| 2147 FRV_BUILTIN_MHSETHIS, | |
| 2148 FRV_BUILTIN_MHSETHIH, | |
| 2149 FRV_BUILTIN_MHDSETS, | |
| 2150 FRV_BUILTIN_MHDSETH, | |
| 2151 FRV_BUILTIN_SMUL, | |
| 2152 FRV_BUILTIN_UMUL, | |
| 2153 FRV_BUILTIN_PREFETCH0, | |
| 2154 FRV_BUILTIN_PREFETCH, | |
| 2155 FRV_BUILTIN_SMASS, | |
| 2156 FRV_BUILTIN_SMSSS, | |
| 2157 FRV_BUILTIN_SMU, | |
| 2158 FRV_BUILTIN_SCUTSS, | |
| 2159 FRV_BUILTIN_ADDSS, | |
| 2160 FRV_BUILTIN_SUBSS, | |
| 2161 FRV_BUILTIN_SLASS, | |
| 2162 FRV_BUILTIN_IACCreadll, | |
| 2163 FRV_BUILTIN_IACCreadl, | |
| 2164 FRV_BUILTIN_IACCsetll, | |
| 2165 FRV_BUILTIN_IACCsetl, | |
| 2166 FRV_BUILTIN_SCAN, | |
| 2167 FRV_BUILTIN_READ8, | |
| 2168 FRV_BUILTIN_READ16, | |
| 2169 FRV_BUILTIN_READ32, | |
| 2170 FRV_BUILTIN_READ64, | |
| 2171 FRV_BUILTIN_WRITE8, | |
| 2172 FRV_BUILTIN_WRITE16, | |
| 2173 FRV_BUILTIN_WRITE32, | |
| 2174 FRV_BUILTIN_WRITE64 | |
| 2175 }; | |
| 2176 #define FRV_BUILTIN_FIRST_NONMEDIA FRV_BUILTIN_SMUL | |
| 2177 | |
| 2178 /* Enable prototypes on the call rtl functions. */ | |
| 2179 #define MD_CALL_PROTOTYPES 1 | |
| 2180 | |
| 2181 #define CPU_UNITS_QUERY 1 | |
| 2182 | |
| 2183 #ifdef __FRV_FDPIC__ | |
| 2184 #define CRT_GET_RFIB_DATA(dbase) \ | |
| 2185 ({ extern void *_GLOBAL_OFFSET_TABLE_; (dbase) = &_GLOBAL_OFFSET_TABLE_; }) | |
| 2186 #endif | |
| 2187 | |
| 2188 #endif /* __FRV_H__ */ |