Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/i386/driver-i386.c @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | b7f97abdc517 |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 /* Subroutines for the gcc driver. |
|
67
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|
2 Copyright (C) 2006, 2007, 2008, 2010 Free Software Foundation, Inc. |
| 0 | 3 |
| 4 This file is part of GCC. | |
| 5 | |
| 6 GCC is free software; you can redistribute it and/or modify | |
| 7 it under the terms of the GNU General Public License as published by | |
| 8 the Free Software Foundation; either version 3, or (at your option) | |
| 9 any later version. | |
| 10 | |
| 11 GCC is distributed in the hope that it will be useful, | |
| 12 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 GNU General Public License for more details. | |
| 15 | |
| 16 You should have received a copy of the GNU General Public License | |
| 17 along with GCC; see the file COPYING3. If not see | |
| 18 <http://www.gnu.org/licenses/>. */ | |
| 19 | |
| 20 #include "config.h" | |
| 21 #include "system.h" | |
| 22 #include "coretypes.h" | |
| 23 #include "tm.h" | |
| 24 | |
| 25 const char *host_detect_local_cpu (int argc, const char **argv); | |
| 26 | |
| 27 #ifdef __GNUC__ | |
| 28 #include "cpuid.h" | |
| 29 | |
| 30 struct cache_desc | |
| 31 { | |
| 32 unsigned sizekb; | |
| 33 unsigned assoc; | |
| 34 unsigned line; | |
| 35 }; | |
| 36 | |
| 37 /* Returns command line parameters that describe size and | |
| 38 cache line size of the processor caches. */ | |
| 39 | |
| 40 static char * | |
| 41 describe_cache (struct cache_desc level1, struct cache_desc level2) | |
| 42 { | |
| 43 char size[100], line[100], size2[100]; | |
| 44 | |
| 45 /* At the moment, gcc does not use the information | |
| 46 about the associativity of the cache. */ | |
| 47 | |
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48 snprintf (size, sizeof (size), |
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49 "--param l1-cache-size=%u ", level1.sizekb); |
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50 snprintf (line, sizeof (line), |
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51 "--param l1-cache-line-size=%u ", level1.line); |
| 0 | 52 |
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53 snprintf (size2, sizeof (size2), |
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54 "--param l2-cache-size=%u ", level2.sizekb); |
| 0 | 55 |
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56 return concat (size, line, size2, NULL); |
| 0 | 57 } |
| 58 | |
| 59 /* Detect L2 cache parameters using CPUID extended function 0x80000006. */ | |
| 60 | |
| 61 static void | |
| 62 detect_l2_cache (struct cache_desc *level2) | |
| 63 { | |
| 64 unsigned eax, ebx, ecx, edx; | |
| 65 unsigned assoc; | |
| 66 | |
| 67 __cpuid (0x80000006, eax, ebx, ecx, edx); | |
| 68 | |
| 69 level2->sizekb = (ecx >> 16) & 0xffff; | |
| 70 level2->line = ecx & 0xff; | |
| 71 | |
| 72 assoc = (ecx >> 12) & 0xf; | |
| 73 if (assoc == 6) | |
| 74 assoc = 8; | |
| 75 else if (assoc == 8) | |
| 76 assoc = 16; | |
| 77 else if (assoc >= 0xa && assoc <= 0xc) | |
| 78 assoc = 32 + (assoc - 0xa) * 16; | |
| 79 else if (assoc >= 0xd && assoc <= 0xe) | |
| 80 assoc = 96 + (assoc - 0xd) * 32; | |
| 81 | |
| 82 level2->assoc = assoc; | |
| 83 } | |
| 84 | |
| 85 /* Returns the description of caches for an AMD processor. */ | |
| 86 | |
| 87 static const char * | |
| 88 detect_caches_amd (unsigned max_ext_level) | |
| 89 { | |
| 90 unsigned eax, ebx, ecx, edx; | |
| 91 | |
| 92 struct cache_desc level1, level2 = {0, 0, 0}; | |
| 93 | |
| 94 if (max_ext_level < 0x80000005) | |
| 95 return ""; | |
| 96 | |
| 97 __cpuid (0x80000005, eax, ebx, ecx, edx); | |
| 98 | |
| 99 level1.sizekb = (ecx >> 24) & 0xff; | |
| 100 level1.assoc = (ecx >> 16) & 0xff; | |
| 101 level1.line = ecx & 0xff; | |
| 102 | |
| 103 if (max_ext_level >= 0x80000006) | |
| 104 detect_l2_cache (&level2); | |
| 105 | |
| 106 return describe_cache (level1, level2); | |
| 107 } | |
| 108 | |
| 109 /* Decodes the size, the associativity and the cache line size of | |
| 110 L1/L2 caches of an Intel processor. Values are based on | |
| 111 "Intel Processor Identification and the CPUID Instruction" | |
| 112 [Application Note 485], revision -032, December 2007. */ | |
| 113 | |
| 114 static void | |
| 115 decode_caches_intel (unsigned reg, bool xeon_mp, | |
| 116 struct cache_desc *level1, struct cache_desc *level2) | |
| 117 { | |
| 118 int i; | |
| 119 | |
| 120 for (i = 24; i >= 0; i -= 8) | |
| 121 switch ((reg >> i) & 0xff) | |
| 122 { | |
| 123 case 0x0a: | |
| 124 level1->sizekb = 8; level1->assoc = 2; level1->line = 32; | |
| 125 break; | |
| 126 case 0x0c: | |
| 127 level1->sizekb = 16; level1->assoc = 4; level1->line = 32; | |
| 128 break; | |
| 129 case 0x2c: | |
| 130 level1->sizekb = 32; level1->assoc = 8; level1->line = 64; | |
| 131 break; | |
| 132 case 0x39: | |
| 133 level2->sizekb = 128; level2->assoc = 4; level2->line = 64; | |
| 134 break; | |
| 135 case 0x3a: | |
| 136 level2->sizekb = 192; level2->assoc = 6; level2->line = 64; | |
| 137 break; | |
| 138 case 0x3b: | |
| 139 level2->sizekb = 128; level2->assoc = 2; level2->line = 64; | |
| 140 break; | |
| 141 case 0x3c: | |
| 142 level2->sizekb = 256; level2->assoc = 4; level2->line = 64; | |
| 143 break; | |
| 144 case 0x3d: | |
| 145 level2->sizekb = 384; level2->assoc = 6; level2->line = 64; | |
| 146 break; | |
| 147 case 0x3e: | |
| 148 level2->sizekb = 512; level2->assoc = 4; level2->line = 64; | |
| 149 break; | |
| 150 case 0x41: | |
| 151 level2->sizekb = 128; level2->assoc = 4; level2->line = 32; | |
| 152 break; | |
| 153 case 0x42: | |
| 154 level2->sizekb = 256; level2->assoc = 4; level2->line = 32; | |
| 155 break; | |
| 156 case 0x43: | |
| 157 level2->sizekb = 512; level2->assoc = 4; level2->line = 32; | |
| 158 break; | |
| 159 case 0x44: | |
| 160 level2->sizekb = 1024; level2->assoc = 4; level2->line = 32; | |
| 161 break; | |
| 162 case 0x45: | |
| 163 level2->sizekb = 2048; level2->assoc = 4; level2->line = 32; | |
| 164 break; | |
| 165 case 0x49: | |
| 166 if (xeon_mp) | |
| 167 break; | |
| 168 level2->sizekb = 4096; level2->assoc = 16; level2->line = 64; | |
| 169 break; | |
| 170 case 0x4e: | |
| 171 level2->sizekb = 6144; level2->assoc = 24; level2->line = 64; | |
| 172 break; | |
| 173 case 0x60: | |
| 174 level1->sizekb = 16; level1->assoc = 8; level1->line = 64; | |
| 175 break; | |
| 176 case 0x66: | |
| 177 level1->sizekb = 8; level1->assoc = 4; level1->line = 64; | |
| 178 break; | |
| 179 case 0x67: | |
| 180 level1->sizekb = 16; level1->assoc = 4; level1->line = 64; | |
| 181 break; | |
| 182 case 0x68: | |
| 183 level1->sizekb = 32; level1->assoc = 4; level1->line = 64; | |
| 184 break; | |
| 185 case 0x78: | |
| 186 level2->sizekb = 1024; level2->assoc = 4; level2->line = 64; | |
| 187 break; | |
| 188 case 0x79: | |
| 189 level2->sizekb = 128; level2->assoc = 8; level2->line = 64; | |
| 190 break; | |
| 191 case 0x7a: | |
| 192 level2->sizekb = 256; level2->assoc = 8; level2->line = 64; | |
| 193 break; | |
| 194 case 0x7b: | |
| 195 level2->sizekb = 512; level2->assoc = 8; level2->line = 64; | |
| 196 break; | |
| 197 case 0x7c: | |
| 198 level2->sizekb = 1024; level2->assoc = 8; level2->line = 64; | |
| 199 break; | |
| 200 case 0x7d: | |
| 201 level2->sizekb = 2048; level2->assoc = 8; level2->line = 64; | |
| 202 break; | |
| 203 case 0x7f: | |
| 204 level2->sizekb = 512; level2->assoc = 2; level2->line = 64; | |
| 205 break; | |
| 206 case 0x82: | |
| 207 level2->sizekb = 256; level2->assoc = 8; level2->line = 32; | |
| 208 break; | |
| 209 case 0x83: | |
| 210 level2->sizekb = 512; level2->assoc = 8; level2->line = 32; | |
| 211 break; | |
| 212 case 0x84: | |
| 213 level2->sizekb = 1024; level2->assoc = 8; level2->line = 32; | |
| 214 break; | |
| 215 case 0x85: | |
| 216 level2->sizekb = 2048; level2->assoc = 8; level2->line = 32; | |
| 217 break; | |
| 218 case 0x86: | |
| 219 level2->sizekb = 512; level2->assoc = 4; level2->line = 64; | |
| 220 break; | |
| 221 case 0x87: | |
| 222 level2->sizekb = 1024; level2->assoc = 8; level2->line = 64; | |
| 223 | |
| 224 default: | |
| 225 break; | |
| 226 } | |
| 227 } | |
| 228 | |
| 229 /* Detect cache parameters using CPUID function 2. */ | |
| 230 | |
| 231 static void | |
| 232 detect_caches_cpuid2 (bool xeon_mp, | |
| 233 struct cache_desc *level1, struct cache_desc *level2) | |
| 234 { | |
| 235 unsigned regs[4]; | |
| 236 int nreps, i; | |
| 237 | |
| 238 __cpuid (2, regs[0], regs[1], regs[2], regs[3]); | |
| 239 | |
| 240 nreps = regs[0] & 0x0f; | |
| 241 regs[0] &= ~0x0f; | |
| 242 | |
| 243 while (--nreps >= 0) | |
| 244 { | |
| 245 for (i = 0; i < 4; i++) | |
| 246 if (regs[i] && !((regs[i] >> 31) & 1)) | |
| 247 decode_caches_intel (regs[i], xeon_mp, level1, level2); | |
| 248 | |
| 249 if (nreps) | |
| 250 __cpuid (2, regs[0], regs[1], regs[2], regs[3]); | |
| 251 } | |
| 252 } | |
| 253 | |
| 254 /* Detect cache parameters using CPUID function 4. This | |
| 255 method doesn't require hardcoded tables. */ | |
| 256 | |
| 257 enum cache_type | |
| 258 { | |
| 259 CACHE_END = 0, | |
| 260 CACHE_DATA = 1, | |
| 261 CACHE_INST = 2, | |
| 262 CACHE_UNIFIED = 3 | |
| 263 }; | |
| 264 | |
| 265 static void | |
|
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266 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2, |
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267 struct cache_desc *level3) |
| 0 | 268 { |
| 269 struct cache_desc *cache; | |
| 270 | |
| 271 unsigned eax, ebx, ecx, edx; | |
| 272 int count; | |
| 273 | |
| 274 for (count = 0;; count++) | |
| 275 { | |
| 276 __cpuid_count(4, count, eax, ebx, ecx, edx); | |
| 277 switch (eax & 0x1f) | |
| 278 { | |
| 279 case CACHE_END: | |
| 280 return; | |
| 281 case CACHE_DATA: | |
| 282 case CACHE_UNIFIED: | |
| 283 { | |
| 284 switch ((eax >> 5) & 0x07) | |
| 285 { | |
| 286 case 1: | |
| 287 cache = level1; | |
| 288 break; | |
| 289 case 2: | |
| 290 cache = level2; | |
| 291 break; | |
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292 case 3: |
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293 cache = level3; |
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294 break; |
| 0 | 295 default: |
| 296 cache = NULL; | |
| 297 } | |
| 298 | |
| 299 if (cache) | |
| 300 { | |
| 301 unsigned sets = ecx + 1; | |
| 302 unsigned part = ((ebx >> 12) & 0x03ff) + 1; | |
| 303 | |
| 304 cache->assoc = ((ebx >> 22) & 0x03ff) + 1; | |
| 305 cache->line = (ebx & 0x0fff) + 1; | |
| 306 | |
| 307 cache->sizekb = (cache->assoc * part | |
| 308 * cache->line * sets) / 1024; | |
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309 } |
| 0 | 310 } |
| 311 default: | |
| 312 break; | |
| 313 } | |
| 314 } | |
| 315 } | |
| 316 | |
| 317 /* Returns the description of caches for an Intel processor. */ | |
| 318 | |
| 319 static const char * | |
|
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320 detect_caches_intel (bool xeon_mp, unsigned max_level, |
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321 unsigned max_ext_level, unsigned *l2sizekb) |
| 0 | 322 { |
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323 struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0}; |
| 0 | 324 |
| 325 if (max_level >= 4) | |
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326 detect_caches_cpuid4 (&level1, &level2, &level3); |
| 0 | 327 else if (max_level >= 2) |
| 328 detect_caches_cpuid2 (xeon_mp, &level1, &level2); | |
| 329 else | |
| 330 return ""; | |
| 331 | |
| 332 if (level1.sizekb == 0) | |
| 333 return ""; | |
| 334 | |
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335 /* Let the L3 replace the L2. This assumes inclusive caches |
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336 and single threaded program for now. */ |
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337 if (level3.sizekb) |
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338 level2 = level3; |
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339 |
| 0 | 340 /* Intel CPUs are equipped with AMD style L2 cache info. Try this |
| 341 method if other methods fail to provide L2 cache parameters. */ | |
| 342 if (level2.sizekb == 0 && max_ext_level >= 0x80000006) | |
| 343 detect_l2_cache (&level2); | |
| 344 | |
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345 *l2sizekb = level2.sizekb; |
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346 |
| 0 | 347 return describe_cache (level1, level2); |
| 348 } | |
| 349 | |
| 350 enum vendor_signatures | |
| 351 { | |
| 352 SIG_INTEL = 0x756e6547 /* Genu */, | |
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353 SIG_AMD = 0x68747541 /* Auth */ |
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354 }; |
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355 |
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356 enum processor_signatures |
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357 { |
| 0 | 358 SIG_GEODE = 0x646f6547 /* Geod */ |
| 359 }; | |
| 360 | |
| 361 /* This will be called by the spec parser in gcc.c when it sees | |
| 362 a %:local_cpu_detect(args) construct. Currently it will be called | |
| 363 with either "arch" or "tune" as argument depending on if -march=native | |
| 364 or -mtune=native is to be substituted. | |
| 365 | |
| 366 It returns a string containing new command line parameters to be | |
| 367 put at the place of the above two options, depending on what CPU | |
| 368 this is executed. E.g. "-march=k8" on an AMD64 machine | |
| 369 for -march=native. | |
| 370 | |
| 371 ARGC and ARGV are set depending on the actual arguments given | |
| 372 in the spec. */ | |
| 373 | |
| 374 const char *host_detect_local_cpu (int argc, const char **argv) | |
| 375 { | |
| 376 enum processor_type processor = PROCESSOR_I386; | |
| 377 const char *cpu = "i386"; | |
| 378 | |
| 379 const char *cache = ""; | |
| 380 const char *options = ""; | |
| 381 | |
| 382 unsigned int eax, ebx, ecx, edx; | |
| 383 | |
| 384 unsigned int max_level, ext_level; | |
| 385 | |
| 386 unsigned int vendor; | |
| 387 unsigned int model, family; | |
| 388 | |
| 389 unsigned int has_sse3, has_ssse3, has_cmpxchg16b; | |
| 390 unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2; | |
| 391 | |
| 392 /* Extended features */ | |
| 393 unsigned int has_lahf_lm = 0, has_sse4a = 0; | |
| 394 unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0; | |
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395 unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0; |
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396 unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0; |
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397 unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0; |
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398 unsigned int has_fma4 = 0, has_xop = 0; |
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399 unsigned int has_bmi = 0, has_tbm = 0; |
| 0 | 400 |
| 401 bool arch; | |
| 402 | |
|
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|
403 unsigned int l2sizekb = 0; |
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|
404 |
| 0 | 405 if (argc < 1) |
| 406 return NULL; | |
| 407 | |
| 408 arch = !strcmp (argv[0], "arch"); | |
| 409 | |
| 410 if (!arch && strcmp (argv[0], "tune")) | |
| 411 return NULL; | |
| 412 | |
| 413 max_level = __get_cpuid_max (0, &vendor); | |
| 414 if (max_level < 1) | |
| 415 goto done; | |
| 416 | |
| 417 __cpuid (1, eax, ebx, ecx, edx); | |
| 418 | |
| 419 model = (eax >> 4) & 0x0f; | |
| 420 family = (eax >> 8) & 0x0f; | |
|
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diff
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|
421 if (vendor == SIG_INTEL) |
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|
422 { |
|
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diff
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|
423 unsigned int extended_model, extended_family; |
|
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|
424 |
|
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|
425 extended_model = (eax >> 12) & 0xf0; |
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|
426 extended_family = (eax >> 20) & 0xff; |
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diff
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|
427 if (family == 0x0f) |
|
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|
428 { |
|
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diff
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|
429 family += extended_family; |
|
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|
430 model += extended_model; |
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|
431 } |
|
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diff
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|
432 else if (family == 0x06) |
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|
433 model += extended_model; |
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|
434 } |
| 0 | 435 |
| 436 has_sse3 = ecx & bit_SSE3; | |
| 437 has_ssse3 = ecx & bit_SSSE3; | |
|
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|
438 has_sse4_1 = ecx & bit_SSE4_1; |
|
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|
439 has_sse4_2 = ecx & bit_SSE4_2; |
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440 has_avx = ecx & bit_AVX; |
| 0 | 441 has_cmpxchg16b = ecx & bit_CMPXCHG16B; |
|
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|
442 has_movbe = ecx & bit_MOVBE; |
|
19
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|
443 has_popcnt = ecx & bit_POPCNT; |
|
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|
444 has_aes = ecx & bit_AES; |
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445 has_pclmul = ecx & bit_PCLMUL; |
| 0 | 446 |
| 447 has_cmpxchg8b = edx & bit_CMPXCHG8B; | |
| 448 has_cmov = edx & bit_CMOV; | |
| 449 has_mmx = edx & bit_MMX; | |
| 450 has_sse = edx & bit_SSE; | |
| 451 has_sse2 = edx & bit_SSE2; | |
| 452 | |
| 453 /* Check cpuid level of extended features. */ | |
| 454 __cpuid (0x80000000, ext_level, ebx, ecx, edx); | |
| 455 | |
| 456 if (ext_level > 0x80000000) | |
| 457 { | |
| 458 __cpuid (0x80000001, eax, ebx, ecx, edx); | |
| 459 | |
| 460 has_lahf_lm = ecx & bit_LAHF_LM; | |
| 461 has_sse4a = ecx & bit_SSE4a; | |
|
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|
462 has_abm = ecx & bit_ABM; |
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463 has_lwp = ecx & bit_LWP; |
|
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464 has_fma4 = ecx & bit_FMA4; |
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465 has_xop = ecx & bit_XOP; |
|
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|
466 has_tbm = ecx & bit_TBM; |
| 0 | 467 |
| 468 has_longmode = edx & bit_LM; | |
| 469 has_3dnowp = edx & bit_3DNOWP; | |
| 470 has_3dnow = edx & bit_3DNOW; | |
|
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|
471 |
|
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|
472 __cpuid (0x7, eax, ebx, ecx, edx); |
|
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|
473 |
|
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|
474 has_bmi = ebx & bit_BMI; |
| 0 | 475 } |
| 476 | |
| 477 if (!arch) | |
| 478 { | |
| 479 if (vendor == SIG_AMD) | |
| 480 cache = detect_caches_amd (ext_level); | |
| 481 else if (vendor == SIG_INTEL) | |
| 482 { | |
| 483 bool xeon_mp = (family == 15 && model == 6); | |
|
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484 cache = detect_caches_intel (xeon_mp, max_level, |
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|
485 ext_level, &l2sizekb); |
| 0 | 486 } |
| 487 } | |
| 488 | |
| 489 if (vendor == SIG_AMD) | |
| 490 { | |
|
19
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|
491 unsigned int name; |
|
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|
492 |
|
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|
493 /* Detect geode processor by its processor signature. */ |
|
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|
494 if (ext_level > 0x80000001) |
|
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|
495 __cpuid (0x80000002, name, ebx, ecx, edx); |
|
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|
496 else |
|
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|
497 name = 0; |
| 0 | 498 |
|
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|
499 if (name == SIG_GEODE) |
|
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|
500 processor = PROCESSOR_GEODE; |
|
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|
501 else if (has_xop) |
|
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|
502 processor = PROCESSOR_BDVER1; |
|
67
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|
503 else if (has_sse4a && has_ssse3) |
|
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|
504 processor = PROCESSOR_BTVER1; |
|
19
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changeset
|
505 else if (has_sse4a) |
|
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changeset
|
506 processor = PROCESSOR_AMDFAM10; |
|
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changeset
|
507 else if (has_sse2 || has_longmode) |
|
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changeset
|
508 processor = PROCESSOR_K8; |
|
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|
509 else if (has_3dnowp) |
| 0 | 510 processor = PROCESSOR_ATHLON; |
|
19
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changeset
|
511 else if (has_mmx) |
|
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changeset
|
512 processor = PROCESSOR_K6; |
|
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changeset
|
513 else |
|
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changeset
|
514 processor = PROCESSOR_PENTIUM; |
| 0 | 515 } |
| 516 else | |
| 517 { | |
| 518 switch (family) | |
| 519 { | |
| 520 case 4: | |
| 521 processor = PROCESSOR_I486; | |
| 522 break; | |
| 523 case 5: | |
| 524 processor = PROCESSOR_PENTIUM; | |
| 525 break; | |
| 526 case 6: | |
| 527 processor = PROCESSOR_PENTIUMPRO; | |
| 528 break; | |
| 529 case 15: | |
| 530 processor = PROCESSOR_PENTIUM4; | |
| 531 break; | |
| 532 default: | |
| 533 /* We have no idea. */ | |
| 534 processor = PROCESSOR_GENERIC32; | |
| 535 } | |
| 536 } | |
| 537 | |
| 538 switch (processor) | |
| 539 { | |
| 540 case PROCESSOR_I386: | |
| 541 /* Default. */ | |
| 542 break; | |
| 543 case PROCESSOR_I486: | |
| 544 cpu = "i486"; | |
| 545 break; | |
| 546 case PROCESSOR_PENTIUM: | |
| 547 if (arch && has_mmx) | |
| 548 cpu = "pentium-mmx"; | |
| 549 else | |
| 550 cpu = "pentium"; | |
| 551 break; | |
| 552 case PROCESSOR_PENTIUMPRO: | |
|
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diff
changeset
|
553 switch (model) |
| 0 | 554 { |
|
63
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diff
changeset
|
555 case 0x1c: |
|
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diff
changeset
|
556 case 0x26: |
|
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update gcc from gcc-4.5.0 to gcc-4.6
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parents:
55
diff
changeset
|
557 /* Atom. */ |
|
b7f97abdc517
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parents:
55
diff
changeset
|
558 cpu = "atom"; |
|
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diff
changeset
|
559 break; |
|
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diff
changeset
|
560 case 0x1a: |
|
b7f97abdc517
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parents:
55
diff
changeset
|
561 case 0x1e: |
|
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55
diff
changeset
|
562 case 0x1f: |
|
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diff
changeset
|
563 case 0x2e: |
|
67
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diff
changeset
|
564 /* Nehalem. */ |
|
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|
565 cpu = "corei7"; |
|
63
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diff
changeset
|
566 break; |
|
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parents:
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diff
changeset
|
567 case 0x25: |
|
67
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diff
changeset
|
568 case 0x2c: |
|
63
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update gcc from gcc-4.5.0 to gcc-4.6
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parents:
55
diff
changeset
|
569 case 0x2f: |
|
67
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changeset
|
570 /* Westmere. */ |
|
f6334be47118
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parents:
63
diff
changeset
|
571 cpu = "corei7"; |
|
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|
572 break; |
|
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changeset
|
573 case 0x2a: |
|
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|
574 /* Sandy Bridge. */ |
|
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diff
changeset
|
575 cpu = "corei7-avx"; |
|
63
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diff
changeset
|
576 break; |
|
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diff
changeset
|
577 case 0x17: |
|
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changeset
|
578 case 0x1d: |
|
67
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changeset
|
579 /* Penryn. */ |
|
63
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diff
changeset
|
580 cpu = "core2"; |
|
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parents:
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diff
changeset
|
581 break; |
|
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582 case 0x0f: |
|
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583 /* Merom. */ |
|
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584 cpu = "core2"; |
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585 break; |
|
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586 default: |
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587 if (arch) |
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588 { |
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589 if (has_ssse3) |
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590 /* If it is an unknown CPU with SSSE3, assume Core 2. */ |
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591 cpu = "core2"; |
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592 else if (has_sse3) |
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593 /* It is Core Duo. */ |
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594 cpu = "pentium-m"; |
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595 else if (has_sse2) |
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596 /* It is Pentium M. */ |
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597 cpu = "pentium-m"; |
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598 else if (has_sse) |
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599 /* It is Pentium III. */ |
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600 cpu = "pentium3"; |
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601 else if (has_mmx) |
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602 /* It is Pentium II. */ |
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603 cpu = "pentium2"; |
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604 else |
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605 /* Default to Pentium Pro. */ |
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606 cpu = "pentiumpro"; |
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607 } |
| 0 | 608 else |
|
63
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609 /* For -mtune, we default to -mtune=generic. */ |
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610 cpu = "generic"; |
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|
611 break; |
| 0 | 612 } |
| 613 break; | |
| 614 case PROCESSOR_PENTIUM4: | |
| 615 if (has_sse3) | |
| 616 { | |
| 617 if (has_longmode) | |
| 618 cpu = "nocona"; | |
| 619 else | |
| 620 cpu = "prescott"; | |
| 621 } | |
| 622 else | |
| 623 cpu = "pentium4"; | |
| 624 break; | |
| 625 case PROCESSOR_GEODE: | |
| 626 cpu = "geode"; | |
| 627 break; | |
| 628 case PROCESSOR_K6: | |
| 629 if (arch && has_3dnow) | |
| 630 cpu = "k6-3"; | |
| 631 else | |
| 632 cpu = "k6"; | |
| 633 break; | |
| 634 case PROCESSOR_ATHLON: | |
| 635 if (arch && has_sse) | |
| 636 cpu = "athlon-4"; | |
| 637 else | |
| 638 cpu = "athlon"; | |
| 639 break; | |
| 640 case PROCESSOR_K8: | |
| 641 if (arch && has_sse3) | |
| 642 cpu = "k8-sse3"; | |
| 643 else | |
| 644 cpu = "k8"; | |
| 645 break; | |
| 646 case PROCESSOR_AMDFAM10: | |
| 647 cpu = "amdfam10"; | |
| 648 break; | |
|
63
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649 case PROCESSOR_BDVER1: |
|
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650 cpu = "bdver1"; |
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651 break; |
|
67
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652 case PROCESSOR_BTVER1: |
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653 cpu = "btver1"; |
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654 break; |
| 0 | 655 |
| 656 default: | |
| 657 /* Use something reasonable. */ | |
| 658 if (arch) | |
| 659 { | |
| 660 if (has_ssse3) | |
| 661 cpu = "core2"; | |
| 662 else if (has_sse3) | |
| 663 { | |
| 664 if (has_longmode) | |
| 665 cpu = "nocona"; | |
| 666 else | |
| 667 cpu = "prescott"; | |
| 668 } | |
| 669 else if (has_sse2) | |
| 670 cpu = "pentium4"; | |
| 671 else if (has_cmov) | |
| 672 cpu = "pentiumpro"; | |
| 673 else if (has_mmx) | |
| 674 cpu = "pentium-mmx"; | |
| 675 else if (has_cmpxchg8b) | |
| 676 cpu = "pentium"; | |
| 677 } | |
| 678 else | |
| 679 cpu = "generic"; | |
| 680 } | |
| 681 | |
| 682 if (arch) | |
| 683 { | |
| 684 if (has_cmpxchg16b) | |
|
55
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|
685 options = concat (options, " -mcx16", NULL); |
| 0 | 686 if (has_lahf_lm) |
|
55
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687 options = concat (options, " -msahf", NULL); |
|
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|
688 if (has_movbe) |
|
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|
689 options = concat (options, " -mmovbe", NULL); |
|
19
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changeset
|
690 if (has_aes) |
|
55
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691 options = concat (options, " -maes", NULL); |
|
19
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changeset
|
692 if (has_pclmul) |
|
55
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|
693 options = concat (options, " -mpclmul", NULL); |
|
19
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changeset
|
694 if (has_popcnt) |
|
55
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|
695 options = concat (options, " -mpopcnt", NULL); |
|
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|
696 if (has_abm) |
|
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697 options = concat (options, " -mabm", NULL); |
|
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|
698 if (has_lwp) |
|
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|
699 options = concat (options, " -mlwp", NULL); |
|
63
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|
700 if (has_fma4) |
|
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701 options = concat (options, " -mfma4", NULL); |
|
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|
702 if (has_xop) |
|
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|
703 options = concat (options, " -mxop", NULL); |
|
67
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|
704 if (has_bmi) |
|
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|
705 options = concat (options, " -mbmi", NULL); |
|
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|
706 if (has_tbm) |
|
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|
707 options = concat (options, " -mtbm", NULL); |
|
55
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diff
changeset
|
708 |
|
19
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parents:
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diff
changeset
|
709 if (has_avx) |
|
55
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diff
changeset
|
710 options = concat (options, " -mavx", NULL); |
|
19
58ad6c70ea60
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diff
changeset
|
711 else if (has_sse4_2) |
|
55
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diff
changeset
|
712 options = concat (options, " -msse4.2", NULL); |
|
19
58ad6c70ea60
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diff
changeset
|
713 else if (has_sse4_1) |
|
55
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diff
changeset
|
714 options = concat (options, " -msse4.1", NULL); |
| 0 | 715 } |
| 716 | |
| 717 done: | |
|
55
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diff
changeset
|
718 return concat (cache, "-m", argv[0], "=", cpu, options, NULL); |
| 0 | 719 } |
| 720 #else | |
| 721 | |
|
55
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diff
changeset
|
722 /* If we aren't compiling with GCC then the driver will just ignore |
|
77e2b8dfacca
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diff
changeset
|
723 -march and -mtune "native" target and will leave to the newly |
|
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diff
changeset
|
724 built compiler to generate code for its default target. */ |
| 0 | 725 |
|
55
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changeset
|
726 const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED, |
|
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changeset
|
727 const char **argv ATTRIBUTE_UNUSED) |
|
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changeset
|
728 { |
|
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|
729 return NULL; |
| 0 | 730 } |
| 731 #endif /* __GNUC__ */ |