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annotate gcc/config/ia64/div.md @ 67:f6334be47118

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update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
date Tue, 22 Mar 2011 17:18:12 +0900
parents 77e2b8dfacca
children 04ced10e8804
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
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1 ;; Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
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2 ;;
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3 ;; This file is part of GCC.
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4 ;;
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5 ;; GCC is free software; you can redistribute it and/or modify
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6 ;; it under the terms of the GNU General Public License as published by
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7 ;; the Free Software Foundation; either version 3, or (at your option)
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8 ;; any later version.
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9 ;;
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10 ;; GCC is distributed in the hope that it will be useful,
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11 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 ;; GNU General Public License for more details.
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14 ;;
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15 ;; You should have received a copy of the GNU General Public License
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16 ;; along with GCC; see the file COPYING3. If not see
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17 ;; <http://www.gnu.org/licenses/>.
0
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18
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19 ;; For the internal conditional math routines:
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20
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21 ;; operand 0 is always the result
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22 ;; operand 1 is always the predicate
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23 ;; operand 2, 3, and sometimes 4 are the input values.
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24 ;; operand 4 or 5 is the floating point status register to use.
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25 ;; operand 5 or 6 is the rounding to do. (0 = single, 1 = double, 2 = none)
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26 ;;
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27 ;; addrf3_cond - F0 = F2 + F3
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28 ;; subrf3_cond - F0 = F2 - F3
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29 ;; mulrf3_cond - F0 = F2 * F3
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30 ;; nmulrf3_cond - F0 = - (F2 * F3)
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31 ;; m1addrf4_cond - F0 = (F2 * F3) + F4
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32 ;; m1subrf4_cond - F0 = (F2 * F3) - F4
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33 ;; m2addrf4_cond - F0 = F2 + (F3 * F4)
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34 ;; m2subrf4_cond - F0 = F2 - (F3 * F4)
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35
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36 ;; Basic plus/minus/mult operations
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37
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38 (define_insn "addrf3_cond"
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39 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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40 (if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
0
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41 (const_int 0))
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42 (plus:RF
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43 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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44 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
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45 (match_operand:RF 4 "fr_reg_or_0_operand" "0,H")))
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46 (use (match_operand:SI 5 "const_int_operand" ""))
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47 (use (match_operand:SI 6 "const_int_operand" ""))]
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48 ""
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49 "(%1) fadd%R6.s%5 %0 = %F2, %F3"
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50 [(set_attr "itanium_class" "fmac")
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51 (set_attr "predicable" "no")])
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52
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53 (define_insn "subrf3_cond"
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54 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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55 (if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
0
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56 (const_int 0))
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57 (minus:RF
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58 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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59 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
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60 (match_operand:RF 4 "fr_reg_or_0_operand" "0,H")))
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61 (use (match_operand:SI 5 "const_int_operand" ""))
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62 (use (match_operand:SI 6 "const_int_operand" ""))]
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63 ""
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64 "(%1) fsub%R6.s%5 %0 = %F2, %F3"
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65 [(set_attr "itanium_class" "fmac")
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66 (set_attr "predicable" "no")])
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67
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68 (define_insn "mulrf3_cond"
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69 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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70 (if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
0
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71 (const_int 0))
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72 (mult:RF
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73 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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74 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
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75 (match_operand:RF 4 "fr_reg_or_0_operand" "0,H")))
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76 (use (match_operand:SI 5 "const_int_operand" ""))
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77 (use (match_operand:SI 6 "const_int_operand" ""))]
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78 ""
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79 "(%1) fmpy%R6.s%5 %0 = %F2, %F3"
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80 [(set_attr "itanium_class" "fmac")
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81 (set_attr "predicable" "no")])
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82
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83 ;; neg-mult operation
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84
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85 (define_insn "nmulrf3_cond"
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86 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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87 (if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
0
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88 (const_int 0))
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89 (neg:RF (mult:RF
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90 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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91 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG")))
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92 (match_operand:RF 4 "fr_reg_or_0_operand" "0,H")))
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93 (use (match_operand:SI 5 "const_int_operand" ""))
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94 (use (match_operand:SI 6 "const_int_operand" ""))]
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95 ""
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96 "(%1) fnmpy%R6.s%5 %0 = %F2, %F3"
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97 [(set_attr "itanium_class" "fmac")
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98 (set_attr "predicable" "no")])
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99
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100 ;; add-mult/sub-mult operations (mult as op1)
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101
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102 (define_insn "m1addrf4_cond"
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103 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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104 (if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
0
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105 (const_int 0))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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106 (plus:RF
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107 (mult:RF
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108 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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109 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
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110 (match_operand:RF 4 "fr_reg_or_fp01_operand" "fG,fG"))
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111 (match_operand:RF 5 "fr_reg_or_0_operand" "0,H")))
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112 (use (match_operand:SI 6 "const_int_operand" ""))
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113 (use (match_operand:SI 7 "const_int_operand" ""))]
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114 ""
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115 "(%1) fma%R7.s%6 %0 = %F2, %F3, %F4"
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116 [(set_attr "itanium_class" "fmac")
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117 (set_attr "predicable" "no")])
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118
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119 (define_insn "m1subrf4_cond"
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120 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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121 (if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
0
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122 (const_int 0))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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123 (minus:RF
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124 (mult:RF
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125 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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126 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG"))
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127 (match_operand:RF 4 "fr_reg_or_fp01_operand" "fG,fG"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
128 (match_operand:RF 5 "fr_reg_or_0_operand" "0,H")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
129 (use (match_operand:SI 6 "const_int_operand" ""))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
130 (use (match_operand:SI 7 "const_int_operand" ""))]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
131 ""
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
132 "(%1) fms%R7.s%6 %0 = %F2, %F3, %F4"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
133 [(set_attr "itanium_class" "fmac")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
134 (set_attr "predicable" "no")])
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
135
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
136 ;; add-mult/sub-mult operations (mult as op2)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
137
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
138 (define_insn "m2addrf4_cond"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
139 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
140 (if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
141 (const_int 0))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
142 (plus:RF
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
143 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
144 (mult:RF
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
145 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
146 (match_operand:RF 4 "fr_reg_or_fp01_operand" "fG,fG")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
147 (match_operand:RF 5 "fr_reg_or_0_operand" "0,H")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
148 (use (match_operand:SI 6 "const_int_operand" ""))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
149 (use (match_operand:SI 7 "const_int_operand" ""))]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
150 ""
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
151 "(%1) fma%R7.s%6 %0 = %F3, %F4, %F2"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
152 [(set_attr "itanium_class" "fmac")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
153 (set_attr "predicable" "no")])
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
154
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
155 (define_insn "m2subrf4_cond"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
156 [(set (match_operand:RF 0 "fr_register_operand" "=f,f")
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
157 (if_then_else:RF (ne:RF (match_operand:CCI 1 "register_operand" "c,c")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
158 (const_int 0))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
159 (minus:RF
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
160 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG,fG")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
161 (mult:RF
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
162 (match_operand:RF 3 "fr_reg_or_fp01_operand" "fG,fG")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
163 (match_operand:RF 4 "fr_reg_or_fp01_operand" "fG,fG")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
164 (match_operand:RF 5 "fr_reg_or_0_operand" "0,H")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
165 (use (match_operand:SI 6 "const_int_operand" ""))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
166 (use (match_operand:SI 7 "const_int_operand" ""))]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
167 ""
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
168 "(%1) fnma%R7.s%6 %0 = %F3, %F4, %F2"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
169 [(set_attr "itanium_class" "fmac")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
170 (set_attr "predicable" "no")])
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
171
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
172 ;; Conversions to/from RF and SF/DF/XF
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
173 ;; These conversions should not generate any code but make it possible
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
174 ;; for all the instructions used to implement floating point division
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
175 ;; to be written for RFmode only and to not have to handle multiple
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
176 ;; modes or to have to handle a register in more than one mode.
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
177
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
178 (define_mode_iterator SDX_F [SF DF XF])
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
179
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
180 (define_insn "extend<mode>rf2"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
181 [(set (match_operand:RF 0 "fr_register_operand" "=f")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
182 (float_extend:RF (match_operand:SDX_F 1 "fr_reg_or_fp01_operand" "fG")))]
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
183 ""
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
184 "#"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
185 [(set_attr "itanium_class" "fmisc")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
186 (set_attr "predicable" "yes")])
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
187
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
188 (define_split
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
189 [(set (match_operand:RF 0 "fr_register_operand" "")
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
190 (float_extend:RF (match_operand:SDX_F 1 "fr_reg_or_fp01_operand" "")))]
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
191 "reload_completed"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
192 [(set (match_dup 0) (match_dup 2))]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
193 {
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
194 if (operands[1] == CONST0_RTX (<MODE>mode))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
195 operands[2] = gen_rtx_REG (RFmode, FR_REG (0));
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
196 else if (operands[1] == CONST1_RTX (<MODE>mode))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
197 operands[2] = gen_rtx_REG (RFmode, FR_REG (1));
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
198 else
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
199 operands[2] = gen_rtx_REG (RFmode, REGNO (operands[1]));
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
200 })
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
201
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
202
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
203 (define_insn "truncrf<mode>2"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
204 [(set (match_operand:SDX_F 0 "fr_register_operand" "=f")
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
205 (float_truncate:SDX_F (match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")))]
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
206 ""
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
207 "#"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
208 [(set_attr "itanium_class" "fmisc")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
209 (set_attr "predicable" "yes")])
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
210
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
211 (define_split
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
212 [(set (match_operand:SDX_F 0 "fr_register_operand" "")
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
213 (float_truncate:SDX_F (match_operand:RF 1 "fr_reg_or_fp01_operand" "")))]
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
214 "reload_completed"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
215 [(set (match_dup 0) (match_dup 2))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
216 {
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
217 if (operands[1] == CONST0_RTX (RFmode))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
218 operands[2] = gen_rtx_REG (<MODE>mode, FR_REG (0));
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
219 else if (operands[1] == CONST1_RTX (RFmode))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
220 operands[2] = gen_rtx_REG (<MODE>mode, FR_REG (1));
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
221 else
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
222 operands[2] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
223 })
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
224
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
225 ;; Float to integer truncations using an alternative status register.
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
226
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
227 (define_insn "fix_truncrfdi2_alts"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
228 [(set (match_operand:DI 0 "fr_register_operand" "=f")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
229 (fix:DI (match_operand:RF 1 "fr_register_operand" "f")))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
230 (use (match_operand:SI 2 "const_int_operand" ""))]
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
231 ""
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
232 "fcvt.fx.trunc.s%2 %0 = %1"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
233 [(set_attr "itanium_class" "fcvtfx")])
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
234
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
235 (define_insn "fixuns_truncrfdi2_alts"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
236 [(set (match_operand:DI 0 "fr_register_operand" "=f")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
237 (unsigned_fix:DI (match_operand:RF 1 "fr_register_operand" "f")))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
238 (use (match_operand:SI 2 "const_int_operand" ""))]
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
239 ""
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
240 "fcvt.fxu.trunc.s%2 %0 = %1"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
241 [(set_attr "itanium_class" "fcvtfx")])
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
242
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
243 (define_insn "setf_exp_rf"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
244 [(set (match_operand:RF 0 "fr_register_operand" "=f")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
245 (unspec:RF [(match_operand:DI 1 "register_operand" "r")]
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
246 UNSPEC_SETF_EXP))]
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
247 ""
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
248 "setf.exp %0 = %1"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
249 [(set_attr "itanium_class" "frfr")])
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
250
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
251 ;; Reciprocal approximation
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
252
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
253 (define_insn "recip_approx_rf"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
254 [(set (match_operand:RF 0 "fr_register_operand" "=f")
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
255 (unspec:RF [(match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
256 (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG")]
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
257 UNSPEC_FR_RECIP_APPROX_RES))
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
258 (set (match_operand:CCI 3 "register_operand" "=c")
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
259 (unspec:CCI [(match_dup 1) (match_dup 2)] UNSPEC_FR_RECIP_APPROX))
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
260 (use (match_operand:SI 4 "const_int_operand" ""))]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
261 ""
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
262 "frcpa.s%4 %0, %3 = %F1, %F2"
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
263 [(set_attr "itanium_class" "fmisc")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
264 (set_attr "predicable" "no")])
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
265
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
266 ;; Single precision floating point division
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
267
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
268 (define_expand "divsf3"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
269 [(set (match_operand:SF 0 "fr_register_operand" "")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
270 (div:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
271 (match_operand:SF 2 "fr_reg_or_fp01_operand" "")))]
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
272 "TARGET_INLINE_FLOAT_DIV"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
273 {
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
274 rtx insn;
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
275 if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT)
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
276 insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
277 else
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
278 insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
279 emit_insn (insn);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
280 DONE;
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
281 })
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
282
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
283 ;; Single precision floating point division (maximum throughput algorithm).
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
284
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
285 (define_expand "divsf3_internal_thr"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
286 [(set (match_operand:SF 0 "fr_register_operand" "")
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
287 (div:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
288 (match_operand:SF 2 "fr_reg_or_fp01_operand" "")))]
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
289 "TARGET_INLINE_FLOAT_DIV"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
290 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
291 rtx y = gen_reg_rtx (RFmode);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
292 rtx a = gen_reg_rtx (RFmode);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
293 rtx b = gen_reg_rtx (RFmode);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
294 rtx e = gen_reg_rtx (RFmode);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
295 rtx y1 = gen_reg_rtx (RFmode);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
296 rtx y2 = gen_reg_rtx (RFmode);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
297 rtx q = gen_reg_rtx (RFmode);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
298 rtx r = gen_reg_rtx (RFmode);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
299 rtx q_res = gen_reg_rtx (RFmode);
67
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
300 rtx cond = gen_reg_rtx (CCImode);
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
301 rtx zero = CONST0_RTX (RFmode);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
302 rtx one = CONST1_RTX (RFmode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
303 rtx status0 = CONST0_RTX (SImode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
304 rtx status1 = CONST1_RTX (SImode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
305 rtx trunc_sgl = CONST0_RTX (SImode);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
306 rtx trunc_off = CONST2_RTX (SImode);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
307
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
308 /* Empty conversions to put inputs into RFmode. */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
309 emit_insn (gen_extendsfrf2 (a, operands[1]));
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
310 emit_insn (gen_extendsfrf2 (b, operands[2]));
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
311 /* y = 1 / b */
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
312 emit_insn (gen_recip_approx_rf (y, a, b, cond, status0));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
313 /* e = 1 - (b * y) */
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
314 emit_insn (gen_m2subrf4_cond (e, cond, one, b, y, zero, status1, trunc_off));
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
315 /* y1 = y + (y * e) */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
316 emit_insn (gen_m2addrf4_cond (y1, cond, y, y, e, zero, status1, trunc_off));
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
317 /* y2 = y + (y1 * e) */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
318 emit_insn (gen_m2addrf4_cond (y2, cond, y, y1, e, zero, status1, trunc_off));
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
319 /* q = single(a * y2) */
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
320 emit_insn (gen_mulrf3_cond (q, cond, a, y2, zero, status1, trunc_sgl));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
321 /* r = a - (q * b) */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
322 emit_insn (gen_m2subrf4_cond (r, cond, a, q, b, zero, status1, trunc_off));
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
323 /* Q = single (q + (r * y2)) */
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
324 emit_insn (gen_m2addrf4_cond (q_res, cond, q, r, y2, y, status0, trunc_sgl));
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
325 /* Conversion back into SFmode. */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
326 emit_insn (gen_truncrfsf2 (operands[0], q_res));
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
327 DONE;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
328 })
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
329
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
330 ;; Single precision floating point division (minimum latency algorithm).
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
331
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
332 (define_expand "divsf3_internal_lat"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
333 [(set (match_operand:SF 0 "fr_register_operand" "")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
334 (div:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
335 (match_operand:SF 2 "fr_reg_or_fp01_operand" "")))]
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
336 "TARGET_INLINE_FLOAT_DIV"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
337 {
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
338 rtx y = gen_reg_rtx (RFmode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
339 rtx a = gen_reg_rtx (RFmode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
340 rtx b = gen_reg_rtx (RFmode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
341 rtx e = gen_reg_rtx (RFmode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
342 rtx q = gen_reg_rtx (RFmode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
343 rtx e1 = gen_reg_rtx (RFmode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
344 rtx y1 = gen_reg_rtx (RFmode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
345 rtx q1 = gen_reg_rtx (RFmode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
346 rtx r = gen_reg_rtx (RFmode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
347 rtx q_res = gen_reg_rtx (RFmode);
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
348 rtx cond = gen_reg_rtx (CCImode);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
349 rtx zero = CONST0_RTX (RFmode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
350 rtx one = CONST1_RTX (RFmode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
351 rtx status0 = CONST0_RTX (SImode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
352 rtx status1 = CONST1_RTX (SImode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
353 rtx trunc_sgl = CONST0_RTX (SImode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
354 rtx trunc_off = CONST2_RTX (SImode);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
355
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
356 /* Empty conversions to put inputs into RFmode. */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
357 emit_insn (gen_extendsfrf2 (a, operands[1]));
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
358 emit_insn (gen_extendsfrf2 (b, operands[2]));
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
359 /* y = 1 / b */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
360 emit_insn (gen_recip_approx_rf (y, a, b, cond, status0));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
361 /* q = a * y */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
362 emit_insn (gen_mulrf3_cond (q, cond, a, y, zero, status1, trunc_off));
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
363 /* e = 1 - (b * y) */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
364 emit_insn (gen_m2subrf4_cond (e, cond, one, b, y, zero, status1, trunc_off));
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
365 /* e1 = e + (e * e) */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
366 emit_insn (gen_m2addrf4_cond (e1, cond, e, e, e, zero, status1, trunc_off));
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
367 /* q1 = single(q + (q * e1)) */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
368 emit_insn (gen_m2addrf4_cond (q1, cond, q, q, e1, zero, status1, trunc_sgl));
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
369 /* y1 = y + (y * e1) */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
370 emit_insn (gen_m2addrf4_cond (y1, cond, y, y, e1, zero, status1, trunc_off));
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
371 /* r = a - (q1 * b) */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
372 emit_insn (gen_m2subrf4_cond (r, cond, a, q1, b, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
373 /* Q = single (q1 + (r * y1)) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
374 emit_insn (gen_m2addrf4_cond (q_res, cond, q1, r, y1, y, status0, trunc_sgl));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
375 /* Conversion back into SFmode. */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
376 emit_insn (gen_truncrfsf2 (operands[0], q_res));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
377 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
378 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
379
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
380 ;; Double precision floating point division
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
381
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
382 (define_expand "divdf3"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
383 [(set (match_operand:DF 0 "fr_register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
384 (div:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
385 (match_operand:DF 2 "fr_reg_or_fp01_operand" "")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
386 "TARGET_INLINE_FLOAT_DIV"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
387 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
388 rtx insn;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
389 if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
390 insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
391 else
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
392 insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
393 emit_insn (insn);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
394 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
395 })
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
396
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
397 ;; Double precision floating point division (maximum throughput algorithm).
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
398
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
399 (define_expand "divdf3_internal_thr"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
400 [(set (match_operand:DF 0 "fr_register_operand" "")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
401 (div:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
402 (match_operand:DF 2 "fr_reg_or_fp01_operand" "")))]
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
403 "TARGET_INLINE_FLOAT_DIV"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
404 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
405 rtx q_res = gen_reg_rtx (RFmode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
406 rtx a = gen_reg_rtx (RFmode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
407 rtx b = gen_reg_rtx (RFmode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
408 rtx y = gen_reg_rtx (RFmode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
409 rtx e = gen_reg_rtx (RFmode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
410 rtx y1 = gen_reg_rtx (RFmode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
411 rtx e1 = gen_reg_rtx (RFmode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
412 rtx y2 = gen_reg_rtx (RFmode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
413 rtx e2 = gen_reg_rtx (RFmode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
414 rtx y3 = gen_reg_rtx (RFmode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
415 rtx q = gen_reg_rtx (RFmode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
416 rtx r = gen_reg_rtx (RFmode);
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
417 rtx cond = gen_reg_rtx (CCImode);
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
418 rtx zero = CONST0_RTX (RFmode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
419 rtx one = CONST1_RTX (RFmode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
420 rtx status0 = CONST0_RTX (SImode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
421 rtx status1 = CONST1_RTX (SImode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
422 rtx trunc_dbl = CONST1_RTX (SImode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
423 rtx trunc_off = CONST2_RTX (SImode);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
424 /* Empty conversions to put inputs into RFmode */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
425 emit_insn (gen_extenddfrf2 (a, operands[1]));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
426 emit_insn (gen_extenddfrf2 (b, operands[2]));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
427 /* y = 1 / b */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
428 emit_insn (gen_recip_approx_rf (y, a, b, cond, status0));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
429 /* e = 1 - (b * y) */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
430 emit_insn (gen_m2subrf4_cond (e, cond, one, b, y, zero, status1, trunc_off));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
431 /* y1 = y + (y * e) */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
432 emit_insn (gen_m2addrf4_cond (y1, cond, y, y, e, zero, status1, trunc_off));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
433 /* e1 = e * e */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
434 emit_insn (gen_mulrf3_cond (e1, cond, e, e, zero, status1, trunc_off));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
435 /* y2 = y1 + (y1 * e1) */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
436 emit_insn (gen_m2addrf4_cond (y2, cond, y1, y1, e1, zero, status1, trunc_off));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
437 /* e2 = e1 * e1 */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
438 emit_insn (gen_mulrf3_cond (e2, cond, e1, e1, zero, status1, trunc_off));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
439 /* y3 = y2 + (y2 * e2) */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
440 emit_insn (gen_m2addrf4_cond (y3, cond, y2, y2, e2, zero, status1, trunc_off));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
441 /* q = double (a * y3) */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
442 emit_insn (gen_mulrf3_cond (q, cond, a, y3, zero, status1, trunc_dbl));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
443 /* r = a - (b * q) */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
444 emit_insn (gen_m2subrf4_cond (r, cond, a, b, q, zero, status1, trunc_off));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
445 /* Q = double (q + (r * y3)) */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
446 emit_insn (gen_m2addrf4_cond (q_res, cond, q, r, y3, y, status0, trunc_dbl));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
447 /* Conversion back into DFmode */
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
448 emit_insn (gen_truncrfdf2 (operands[0], q_res));
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
449 DONE;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
450 })
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
451
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
452 ;; Double precision floating point division (minimum latency algorithm).
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
453
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
454 (define_expand "divdf3_internal_lat"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
455 [(set (match_operand:DF 0 "fr_register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
456 (div:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
457 (match_operand:DF 2 "fr_reg_or_fp01_operand" "")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
458 "TARGET_INLINE_FLOAT_DIV"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
459 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
460 rtx q_res = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
461 rtx a = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
462 rtx b = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
463 rtx y = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
464 rtx e = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
465 rtx y1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
466 rtx e1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
467 rtx q1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
468 rtx y2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
469 rtx e2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
470 rtx q2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
471 rtx e3 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
472 rtx q = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
473 rtx r1 = gen_reg_rtx (RFmode);
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
474 rtx cond = gen_reg_rtx (CCImode);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
475 rtx zero = CONST0_RTX (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
476 rtx one = CONST1_RTX (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
477 rtx status0 = CONST0_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
478 rtx status1 = CONST1_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
479 rtx trunc_dbl = CONST1_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
480 rtx trunc_off = CONST2_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
481
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
482 /* Empty conversions to put inputs into RFmode */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
483 emit_insn (gen_extenddfrf2 (a, operands[1]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
484 emit_insn (gen_extenddfrf2 (b, operands[2]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
485 /* y = 1 / b */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
486 emit_insn (gen_recip_approx_rf (y, a, b, cond, status0));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
487 /* e = 1 - (b * y) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
488 emit_insn (gen_m2subrf4_cond (e, cond, one, b, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
489 /* q = a * y */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
490 emit_insn (gen_mulrf3_cond (q, cond, a, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
491 /* e2 = e + (e * e) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
492 emit_insn (gen_m2addrf4_cond (e2, cond, e, e, e, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
493 /* e1 = e * e */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
494 emit_insn (gen_mulrf3_cond (e1, cond, e, e, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
495 /* e3 = e + (e1 * e1) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
496 emit_insn (gen_m2addrf4_cond (e3, cond, e, e1, e1, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
497 /* q1 = q + (q * e2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
498 emit_insn (gen_m2addrf4_cond (q1, cond, q, q, e2, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
499 /* y1 = y + (y * e2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
500 emit_insn (gen_m2addrf4_cond (y1, cond, y, y, e2, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
501 /* q2 = double(q + (q1 * e3)) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
502 emit_insn (gen_m2addrf4_cond (q2, cond, q, q1, e3, zero, status1, trunc_dbl));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
503 /* y2 = y + (y1 * e3) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
504 emit_insn (gen_m2addrf4_cond (y2, cond, y, y1, e3, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
505 /* r1 = a - (b * q2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
506 emit_insn (gen_m2subrf4_cond (r1, cond, a, b, q2, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
507 /* Q = double (q2 + (r1 * y2)) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
508 emit_insn (gen_m2addrf4_cond (q_res, cond, q2, r1, y2, y, status0, trunc_dbl));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
509 /* Conversion back into DFmode */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
510 emit_insn (gen_truncrfdf2 (operands[0], q_res));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
511 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
512 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
513
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
514 ;; Extended precision floating point division.
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
515
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
516 (define_expand "divxf3"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
517 [(set (match_operand:XF 0 "fr_register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
518 (div:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
519 (match_operand:XF 2 "fr_reg_or_fp01_operand" "")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
520 "TARGET_INLINE_FLOAT_DIV"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
521 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
522 rtx q_res = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
523 rtx a = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
524 rtx b = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
525 rtx y = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
526 rtx e = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
527 rtx y1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
528 rtx e1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
529 rtx q1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
530 rtx y2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
531 rtx e2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
532 rtx y3 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
533 rtx e3 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
534 rtx e4 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
535 rtx q = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
536 rtx r = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
537 rtx r1 = gen_reg_rtx (RFmode);
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
538 rtx cond = gen_reg_rtx (CCImode);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
539 rtx zero = CONST0_RTX (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
540 rtx one = CONST1_RTX (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
541 rtx status0 = CONST0_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
542 rtx status1 = CONST1_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
543 rtx trunc_off = CONST2_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
544
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
545 /* Empty conversions to put inputs into RFmode */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
546 emit_insn (gen_extendxfrf2 (a, operands[1]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
547 emit_insn (gen_extendxfrf2 (b, operands[2]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
548 /* y = 1 / b */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
549 emit_insn (gen_recip_approx_rf (y, a, b, cond, status0));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
550 /* e = 1 - (b * y) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
551 emit_insn (gen_m2subrf4_cond (e, cond, one, b, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
552 /* q = a * y */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
553 emit_insn (gen_mulrf3_cond (q, cond, a, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
554 /* e2 = e + (e * e) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
555 emit_insn (gen_m2addrf4_cond (e2, cond, e, e, e, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
556 /* e1 = e * e */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
557 emit_insn (gen_mulrf3_cond (e1, cond, e, e, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
558 /* y1 = y + (y * e2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
559 emit_insn (gen_m2addrf4_cond (y1, cond, y, y, e2, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
560 /* e3 = e + (e1 * e1) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
561 emit_insn (gen_m2addrf4_cond (e3, cond, e, e1, e1, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
562 /* y2 = y + (y1 * e3) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
563 emit_insn (gen_m2addrf4_cond (y2, cond, y, y1, e3, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
564 /* r = a - (b * q) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
565 emit_insn (gen_m2subrf4_cond (r, cond, a, b, q, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
566 /* e4 = 1 - (b * y2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
567 emit_insn (gen_m2subrf4_cond (e4, cond, one, b, y2, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
568 /* q1 = q + (r * y2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
569 emit_insn (gen_m2addrf4_cond (q1, cond, q, r, y2, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
570 /* y3 = y2 + (y2 * e4) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
571 emit_insn (gen_m2addrf4_cond (y3, cond, y2, y2, e4, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
572 /* r1 = a - (b * q1) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
573 emit_insn (gen_m2subrf4_cond (r1, cond, a, b, q1, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
574 /* Q = q1 + (r1 * y3) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
575 emit_insn (gen_m2addrf4_cond (q_res, cond, q1, r1, y3, y, status0, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
576 /* Conversion back into XFmode */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
577 emit_insn (gen_truncrfxf2 (operands[0], q_res));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
578 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
579 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
580
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
581
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
582 ;; Integer division operations
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
583
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
584 (define_expand "divsi3"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
585 [(set (match_operand:SI 0 "register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
586 (div:SI (match_operand:SI 1 "general_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
587 (match_operand:SI 2 "general_operand" "")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
588 "TARGET_INLINE_INT_DIV"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
589 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
590 rtx op1_rf, op2_rf, op0_rf, op0_di;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
591
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
592 op0_rf = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
593 op0_di = gen_reg_rtx (DImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
594
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
595 if (! register_operand (operands[1], SImode))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
596 operands[1] = force_reg (SImode, operands[1]);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
597 op1_rf = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
598 expand_float (op1_rf, operands[1], 0);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
599
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
600 if (! register_operand (operands[2], SImode))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
601 operands[2] = force_reg (SImode, operands[2]);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
602 op2_rf = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
603 expand_float (op2_rf, operands[2], 0);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
604
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
605 emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode),
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
606 CONST1_RTX (SImode)));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
607
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
608 emit_insn (gen_divsi3_internal (op0_rf, op1_rf, op2_rf));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
609
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
610 emit_insn (gen_fix_truncrfdi2_alts (op0_di, op0_rf, const1_rtx));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
611 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
612 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
613 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
614
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
615 (define_expand "modsi3"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
616 [(set (match_operand:SI 0 "register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
617 (mod:SI (match_operand:SI 1 "general_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
618 (match_operand:SI 2 "general_operand" "")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
619 "TARGET_INLINE_INT_DIV"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
620 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
621 rtx op2_neg, op1_di, div;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
622
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
623 div = gen_reg_rtx (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
624 emit_insn (gen_divsi3 (div, operands[1], operands[2]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
625
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
626 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
627
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
628 /* This is a trick to get us to reuse the value that we're sure to
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
629 have already copied to the FP regs. */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
630 op1_di = gen_reg_rtx (DImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
631 convert_move (op1_di, operands[1], 0);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
632
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
633 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
634 gen_lowpart (SImode, op1_di)));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
635 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
636 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
637
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
638 (define_expand "udivsi3"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
639 [(set (match_operand:SI 0 "register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
640 (udiv:SI (match_operand:SI 1 "general_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
641 (match_operand:SI 2 "general_operand" "")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
642 "TARGET_INLINE_INT_DIV"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
643 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
644 rtx op1_rf, op2_rf, op0_rf, op0_di;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
645
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
646 op0_rf = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
647 op0_di = gen_reg_rtx (DImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
648
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
649 if (! register_operand (operands[1], SImode))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
650 operands[1] = force_reg (SImode, operands[1]);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
651 op1_rf = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
652 expand_float (op1_rf, operands[1], 1);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
653
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
654 if (! register_operand (operands[2], SImode))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
655 operands[2] = force_reg (SImode, operands[2]);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
656 op2_rf = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
657 expand_float (op2_rf, operands[2], 1);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
658
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
659 emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode),
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
660 CONST1_RTX (SImode)));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
661
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
662 emit_insn (gen_divsi3_internal (op0_rf, op1_rf, op2_rf));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
663
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
664 emit_insn (gen_fixuns_truncrfdi2_alts (op0_di, op0_rf, const1_rtx));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
665 emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
666 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
667 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
668
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
669 (define_expand "umodsi3"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
670 [(set (match_operand:SI 0 "register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
671 (umod:SI (match_operand:SI 1 "general_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
672 (match_operand:SI 2 "general_operand" "")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
673 "TARGET_INLINE_INT_DIV"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
674 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
675 rtx op2_neg, op1_di, div;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
676
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
677 div = gen_reg_rtx (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
678 emit_insn (gen_udivsi3 (div, operands[1], operands[2]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
679
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
680 op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
681
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
682 /* This is a trick to get us to reuse the value that we're sure to
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
683 have already copied to the FP regs. */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
684 op1_di = gen_reg_rtx (DImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
685 convert_move (op1_di, operands[1], 1);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
686
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
687 emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
688 gen_lowpart (SImode, op1_di)));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
689 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
690 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
691
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
692 (define_expand "divsi3_internal"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
693 [(set (match_operand:RF 0 "fr_register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
694 (float:RF (div:SI (match_operand:RF 1 "fr_register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
695 (match_operand:RF 2 "fr_register_operand" ""))))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
696 "TARGET_INLINE_INT_DIV"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
697 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
698 rtx a = operands[1];
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
699 rtx b = operands[2];
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
700 rtx y = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
701 rtx e = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
702 rtx e1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
703 rtx q = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
704 rtx q1 = gen_reg_rtx (RFmode);
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
705 rtx cond = gen_reg_rtx (CCImode);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
706 rtx zero = CONST0_RTX (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
707 rtx one = CONST1_RTX (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
708 rtx status1 = CONST1_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
709 rtx trunc_off = CONST2_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
710 rtx twon34_exp = gen_reg_rtx (DImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
711 rtx twon34 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
712
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
713 /* Load cosntant 2**(-34) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
714 emit_move_insn (twon34_exp, GEN_INT (65501));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
715 emit_insn (gen_setf_exp_rf (twon34, twon34_exp));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
716
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
717 /* y = 1 / b */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
718 emit_insn (gen_recip_approx_rf (y, a, b, cond, status1));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
719 /* e = 1 - (b * y) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
720 emit_insn (gen_m2subrf4_cond (e, cond, one, b, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
721 /* q = a * y */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
722 emit_insn (gen_mulrf3_cond (q, cond, a, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
723 /* q1 = q + (q * e) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
724 emit_insn (gen_m2addrf4_cond (q1, cond, q, q, e, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
725 /* e1 = (2**-34) + (e * e) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
726 emit_insn (gen_m2addrf4_cond (e1, cond, twon34, e, e, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
727 /* q2 = q1 + (e1 * q1) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
728 emit_insn (gen_m2addrf4_cond (operands[0], cond, q1, e1, q1, y, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
729 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
730 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
731
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
732 (define_expand "divdi3"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
733 [(set (match_operand:DI 0 "register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
734 (div:DI (match_operand:DI 1 "general_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
735 (match_operand:DI 2 "general_operand" "")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
736 "TARGET_INLINE_INT_DIV"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
737 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
738 rtx op1_rf, op2_rf, op0_rf;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
739
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
740 op0_rf = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
741
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
742 if (! register_operand (operands[1], DImode))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
743 operands[1] = force_reg (DImode, operands[1]);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
744 op1_rf = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
745 expand_float (op1_rf, operands[1], 0);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
746
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
747 if (! register_operand (operands[2], DImode))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
748 operands[2] = force_reg (DImode, operands[2]);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
749 op2_rf = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
750 expand_float (op2_rf, operands[2], 0);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
751
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
752 emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode),
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
753 CONST1_RTX (DImode)));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
754
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
755 if (TARGET_INLINE_INT_DIV == INL_MIN_LAT)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
756 emit_insn (gen_divdi3_internal_lat (op0_rf, op1_rf, op2_rf));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
757 else
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
758 emit_insn (gen_divdi3_internal_thr (op0_rf, op1_rf, op2_rf));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
759
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
760 emit_insn (gen_fix_truncrfdi2_alts (operands[0], op0_rf, const1_rtx));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
761 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
762 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
763
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
764 (define_expand "moddi3"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
765 [(set (match_operand:DI 0 "register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
766 (mod:SI (match_operand:DI 1 "general_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
767 (match_operand:DI 2 "general_operand" "")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
768 "TARGET_INLINE_INT_DIV"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
769 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
770 rtx op2_neg, div;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
771
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
772 div = gen_reg_rtx (DImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
773 emit_insn (gen_divdi3 (div, operands[1], operands[2]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
774
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
775 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
776
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
777 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
778 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
779 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
780
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
781 (define_expand "udivdi3"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
782 [(set (match_operand:DI 0 "register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
783 (udiv:DI (match_operand:DI 1 "general_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
784 (match_operand:DI 2 "general_operand" "")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
785 "TARGET_INLINE_INT_DIV"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
786 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
787 rtx op1_rf, op2_rf, op0_rf;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
788
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
789 op0_rf = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
790
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
791 if (! register_operand (operands[1], DImode))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
792 operands[1] = force_reg (DImode, operands[1]);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
793 op1_rf = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
794 expand_float (op1_rf, operands[1], 1);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
795
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
796 if (! register_operand (operands[2], DImode))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
797 operands[2] = force_reg (DImode, operands[2]);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
798 op2_rf = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
799 expand_float (op2_rf, operands[2], 1);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
800
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
801 emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode),
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
802 CONST1_RTX (DImode)));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
803
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
804 if (TARGET_INLINE_INT_DIV == INL_MIN_LAT)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
805 emit_insn (gen_divdi3_internal_lat (op0_rf, op1_rf, op2_rf));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
806 else
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
807 emit_insn (gen_divdi3_internal_thr (op0_rf, op1_rf, op2_rf));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
808
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
809 emit_insn (gen_fixuns_truncrfdi2_alts (operands[0], op0_rf, const1_rtx));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
810 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
811 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
812
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
813 (define_expand "umoddi3"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
814 [(set (match_operand:DI 0 "register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
815 (umod:DI (match_operand:DI 1 "general_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
816 (match_operand:DI 2 "general_operand" "")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
817 "TARGET_INLINE_INT_DIV"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
818 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
819 rtx op2_neg, div;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
820
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
821 div = gen_reg_rtx (DImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
822 emit_insn (gen_udivdi3 (div, operands[1], operands[2]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
823
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
824 op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
825
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
826 emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
827 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
828 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
829
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
830 (define_expand "divdi3_internal_lat"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
831 [(set (match_operand:RF 0 "fr_register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
832 (float:RF (div:DI (match_operand:RF 1 "fr_register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
833 (match_operand:RF 2 "fr_register_operand" ""))))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
834 "TARGET_INLINE_INT_DIV"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
835 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
836 rtx a = operands[1];
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
837 rtx b = operands[2];
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
838 rtx y = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
839 rtx y1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
840 rtx y2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
841 rtx e = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
842 rtx e1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
843 rtx q = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
844 rtx q1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
845 rtx q2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
846 rtx r = gen_reg_rtx (RFmode);
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
847 rtx cond = gen_reg_rtx (CCImode);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
848 rtx zero = CONST0_RTX (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
849 rtx one = CONST1_RTX (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
850 rtx status1 = CONST1_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
851 rtx trunc_off = CONST2_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
852
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
853 /* y = 1 / b */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
854 emit_insn (gen_recip_approx_rf (y, a, b, cond, status1));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
855 /* e = 1 - (b * y) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
856 emit_insn (gen_m2subrf4_cond (e, cond, one, b, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
857 /* q = a * y */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
858 emit_insn (gen_mulrf3_cond (q, cond, a, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
859 /* q1 = q + (q * e) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
860 emit_insn (gen_m2addrf4_cond (q1, cond, q, q, e, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
861 /* e1 = e * e */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
862 emit_insn (gen_mulrf3_cond (e1, cond, e, e, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
863 /* q2 = q1 + (e1 * q1) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
864 emit_insn (gen_m2addrf4_cond (q2, cond, q1, e1, q1, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
865 /* y1 = y + (y * e) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
866 emit_insn (gen_m2addrf4_cond (y1, cond, y, y, e, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
867 /* r = a - (b * q2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
868 emit_insn (gen_m2subrf4_cond (r, cond, a, b, q2, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
869 /* y2 = y1 + (y1 * e1) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
870 emit_insn (gen_m2addrf4_cond (y2, cond, y1, y1, e1, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
871 /* q3 = q2 + (r * y2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
872 emit_insn (gen_m2addrf4_cond (operands[0], cond, q2, r, y2, y, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
873 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
874 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
875
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
876 (define_expand "divdi3_internal_thr"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
877 [(set (match_operand:RF 0 "fr_register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
878 (float:RF (div:DI (match_operand:RF 1 "fr_register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
879 (match_operand:RF 2 "fr_register_operand" ""))))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
880 "TARGET_INLINE_INT_DIV"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
881 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
882 rtx a = operands[1];
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
883 rtx b = operands[2];
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
884 rtx y = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
885 rtx y1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
886 rtx y2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
887 rtx e = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
888 rtx e1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
889 rtx q2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
890 rtx r = gen_reg_rtx (RFmode);
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
891 rtx cond = gen_reg_rtx (CCImode);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
892 rtx zero = CONST0_RTX (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
893 rtx one = CONST1_RTX (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
894 rtx status1 = CONST1_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
895 rtx trunc_off = CONST2_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
896
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
897 /* y = 1 / b */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
898 emit_insn (gen_recip_approx_rf (y, a, b, cond, status1));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
899 /* e = 1 - (b * y) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
900 emit_insn (gen_m2subrf4_cond (e, cond, one, b, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
901 /* y1 = y + (y * e) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
902 emit_insn (gen_m2addrf4_cond (y1, cond, y, y, e, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
903 /* e1 = e * e */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
904 emit_insn (gen_mulrf3_cond (e1, cond, e, e, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
905 /* y2 = y1 + (y1 * e1) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
906 emit_insn (gen_m2addrf4_cond (y2, cond, y1, y1, e1, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
907 /* q2 = y2 * a */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
908 emit_insn (gen_mulrf3_cond (q2, cond, y2, a, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
909 /* r = a - (b * q2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
910 emit_insn (gen_m2subrf4_cond (r, cond, a, b, q2, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
911 /* q3 = q2 + (r * y2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
912 emit_insn (gen_m2addrf4_cond (operands[0], cond, q2, r, y2, y, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
913 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
914 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
915
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
916 ;; SQRT operations
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
917
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
918
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
919 (define_insn "sqrt_approx_rf"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
920 [(set (match_operand:RF 0 "fr_register_operand" "=f")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
921 (unspec:RF [(match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
922 UNSPEC_FR_SQRT_RECIP_APPROX_RES))
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
923 (set (match_operand:CCI 2 "register_operand" "=c")
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
924 (unspec:CCI [(match_dup 1)] UNSPEC_FR_SQRT_RECIP_APPROX))
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
925 (use (match_operand:SI 3 "const_int_operand" ""))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
926 ""
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
927 "frsqrta.s%3 %0, %2 = %F1"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
928 [(set_attr "itanium_class" "fmisc")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
929 (set_attr "predicable" "no")])
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
930
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
931 (define_expand "sqrtsf2"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
932 [(set (match_operand:SF 0 "fr_register_operand" "=&f")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
933 (sqrt:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
934 "TARGET_INLINE_SQRT"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
935 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
936 rtx insn;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
937 if (TARGET_INLINE_SQRT == INL_MIN_LAT)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
938 insn = gen_sqrtsf2_internal_lat (operands[0], operands[1]);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
939 else
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
940 insn = gen_sqrtsf2_internal_thr (operands[0], operands[1]);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
941 emit_insn (insn);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
942 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
943 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
944
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
945 (define_expand "sqrtsf2_internal_thr"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
946 [(set (match_operand:SF 0 "fr_register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
947 (sqrt:SF (match_operand:SF 1 "fr_register_operand" "")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
948 "TARGET_INLINE_SQRT"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
949 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
950 rtx y = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
951 rtx b = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
952 rtx g = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
953 rtx e = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
954 rtx s = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
955 rtx f = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
956 rtx y1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
957 rtx g1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
958 rtx h = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
959 rtx d = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
960 rtx g2 = gen_reg_rtx (RFmode);
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
961 rtx cond = gen_reg_rtx (CCImode);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
962 rtx zero = CONST0_RTX (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
963 rtx one = CONST1_RTX (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
964 rtx c1 = ia64_dconst_0_5();
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
965 rtx c2 = ia64_dconst_0_375();
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
966 rtx reg_df_c1 = gen_reg_rtx (DFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
967 rtx reg_df_c2 = gen_reg_rtx (DFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
968 rtx reg_rf_c1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
969 rtx reg_rf_c2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
970 rtx status0 = CONST0_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
971 rtx status1 = CONST1_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
972 rtx trunc_sgl = CONST0_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
973 rtx trunc_off = CONST2_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
974
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
975 /* Put needed constants into registers. */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
976 emit_insn (gen_movdf (reg_df_c1, c1));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
977 emit_insn (gen_movdf (reg_df_c2, c2));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
978 emit_insn (gen_extenddfrf2 (reg_rf_c1, reg_df_c1));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
979 emit_insn (gen_extenddfrf2 (reg_rf_c2, reg_df_c2));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
980 /* Empty conversion to put input into RFmode. */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
981 emit_insn (gen_extendsfrf2 (b, operands[1]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
982 /* y = sqrt (1 / b) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
983 emit_insn (gen_sqrt_approx_rf (y, b, cond, status0));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
984 /* g = b * y */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
985 emit_insn (gen_mulrf3_cond (g, cond, b, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
986 /* e = 1 - (g * y) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
987 emit_insn (gen_m2subrf4_cond (e, cond, one, g, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
988 /* s = 0.5 + (0.375 * e) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
989 emit_insn (gen_m2addrf4_cond (s, cond, reg_rf_c1, reg_rf_c2, e, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
990 /* f = y * e */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
991 emit_insn (gen_mulrf3_cond (f, cond, y, e, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
992 /* y1 = y + (f * s) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
993 emit_insn (gen_m2addrf4_cond (y1, cond, y, f, s, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
994 /* g1 = single (b * y1) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
995 emit_insn (gen_mulrf3_cond (g1, cond, b, y1, zero, status1, trunc_sgl));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
996 /* h = 0.5 * y1 */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
997 emit_insn (gen_mulrf3_cond (h, cond, reg_rf_c1, y1, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
998 /* d = b - g1 * g1 */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
999 emit_insn (gen_m2subrf4_cond (d, cond, b, g1, g1, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1000 /* g2 = single(g1 + (d * h)) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1001 emit_insn (gen_m2addrf4_cond (g2, cond, g1, d, h, y, status0, trunc_sgl));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1002 /* Conversion back into SFmode. */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1003 emit_insn (gen_truncrfsf2 (operands[0], g2));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1004 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1005 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1006
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1007 (define_expand "sqrtsf2_internal_lat"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1008 [(set (match_operand:SF 0 "fr_register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1009 (sqrt:SF (match_operand:SF 1 "fr_register_operand" "")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1010 "TARGET_INLINE_SQRT"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1011 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1012 rtx y = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1013 rtx b = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1014 rtx g = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1015 rtx g1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1016 rtx g2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1017 rtx e = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1018 rtx s = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1019 rtx f = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1020 rtx f1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1021 rtx h = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1022 rtx h1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1023 rtx d = gen_reg_rtx (RFmode);
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
1024 rtx cond = gen_reg_rtx (CCImode);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1025 rtx zero = CONST0_RTX (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1026 rtx one = CONST1_RTX (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1027 rtx c1 = ia64_dconst_0_5();
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1028 rtx c2 = ia64_dconst_0_375();
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1029 rtx reg_df_c1 = gen_reg_rtx (DFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1030 rtx reg_df_c2 = gen_reg_rtx (DFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1031 rtx reg_rf_c1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1032 rtx reg_rf_c2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1033 rtx status0 = CONST0_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1034 rtx status1 = CONST1_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1035 rtx trunc_sgl = CONST0_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1036 rtx trunc_off = CONST2_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1037
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1038 /* Put needed constants into registers. */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1039 emit_insn (gen_movdf (reg_df_c1, c1));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1040 emit_insn (gen_movdf (reg_df_c2, c2));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1041 emit_insn (gen_extenddfrf2 (reg_rf_c1, reg_df_c1));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1042 emit_insn (gen_extenddfrf2 (reg_rf_c2, reg_df_c2));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1043 /* Empty conversion to put input into RFmode. */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1044 emit_insn (gen_extendsfrf2 (b, operands[1]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1045 /* y = sqrt (1 / b) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1046 emit_insn (gen_sqrt_approx_rf (y, b, cond, status0));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1047 /* g = b * y */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1048 emit_insn (gen_mulrf3_cond (g, cond, b, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1049 /* e = 1 - (g * y) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1050 emit_insn (gen_m2subrf4_cond (e, cond, one, g, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1051 /* h = 0.5 * y */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1052 emit_insn (gen_mulrf3_cond (h, cond, reg_rf_c1, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1053 /* s = 0.5 + (0.375 * e) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1054 emit_insn (gen_m2addrf4_cond (s, cond, reg_rf_c1, reg_rf_c2, e, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1055 /* f = e * g */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1056 emit_insn (gen_mulrf3_cond (f, cond, e, g, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1057 /* g1 = single (g + (f * s)) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1058 emit_insn (gen_m2addrf4_cond (g1, cond, g, f, s, zero, status1, trunc_sgl));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1059 /* f1 = e * h */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1060 emit_insn (gen_mulrf3_cond (f1, cond, e, h, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1061 /* d = b - g1 * g1 */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1062 emit_insn (gen_m2subrf4_cond (d, cond, b, g1, g1, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1063 /* h1 = h + (f1 * s) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1064 emit_insn (gen_m2addrf4_cond (h1, cond, h, f1, s, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1065 /* g2 = single(g1 + (d * h1)) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1066 emit_insn (gen_m2addrf4_cond (g2, cond, g1, d, h1, y, status0, trunc_sgl));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1067 /* Conversion back into SFmode. */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1068 emit_insn (gen_truncrfsf2 (operands[0], g2));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1069 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1070 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1071
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1072 (define_expand "sqrtdf2"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1073 [(set (match_operand:DF 0 "fr_register_operand" "=&f")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1074 (sqrt:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1075 "TARGET_INLINE_SQRT"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1076 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1077 rtx insn;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1078 #if 0
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1079 if (TARGET_INLINE_SQRT == INL_MIN_LAT)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1080 insn = gen_sqrtdf2_internal_lat (operands[0], operands[1]);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1081 else
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1082 #endif
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1083 insn = gen_sqrtdf2_internal_thr (operands[0], operands[1]);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1084 emit_insn (insn);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1085 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1086 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1087
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1088 (define_expand "sqrtdf2_internal_thr"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1089 [(set (match_operand:DF 0 "fr_register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1090 (sqrt:DF (match_operand:DF 1 "fr_register_operand" "")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1091 "TARGET_INLINE_SQRT"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1092 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1093 rtx y = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1094 rtx b = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1095 rtx g = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1096 rtx g1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1097 rtx g2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1098 rtx g3 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1099 rtx g4 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1100 rtx r = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1101 rtx r1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1102 rtx h = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1103 rtx h1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1104 rtx h2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1105 rtx d = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1106 rtx d1 = gen_reg_rtx (RFmode);
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
1107 rtx cond = gen_reg_rtx (CCImode);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1108 rtx zero = CONST0_RTX (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1109 rtx c1 = ia64_dconst_0_5();
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1110 rtx reg_df_c1 = gen_reg_rtx (DFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1111 rtx reg_rf_c1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1112 rtx status0 = CONST0_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1113 rtx status1 = CONST1_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1114 rtx trunc_dbl = CONST1_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1115 rtx trunc_off = CONST2_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1116
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1117 /* Put needed constants into registers. */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1118 emit_insn (gen_movdf (reg_df_c1, c1));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1119 emit_insn (gen_extenddfrf2 (reg_rf_c1, reg_df_c1));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1120 /* Empty conversion to put input into RFmode. */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1121 emit_insn (gen_extenddfrf2 (b, operands[1]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1122 /* y = sqrt (1 / b) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1123 emit_insn (gen_sqrt_approx_rf (y, b, cond, status0));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1124 /* g = b * y */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1125 emit_insn (gen_mulrf3_cond (g, cond, b, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1126 /* h = 0.5 * y */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1127 emit_insn (gen_mulrf3_cond (h, cond, reg_rf_c1, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1128 /* r = 0.5 - (g * h) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1129 emit_insn (gen_m2subrf4_cond (r, cond, reg_rf_c1, g, h, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1130 /* g1 = g + (g * r) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1131 emit_insn (gen_m2addrf4_cond (g1, cond, g, g, r, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1132 /* h1 = h + (h * r) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1133 emit_insn (gen_m2addrf4_cond (h1, cond, h, h, r, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1134 /* r1 = 0.5 - (g1 * h1) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1135 emit_insn (gen_m2subrf4_cond (r1, cond, reg_rf_c1, g1, h1, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1136 /* g2 = g1 + (g1 * r1) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1137 emit_insn (gen_m2addrf4_cond (g2, cond, g1, g1, r1, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1138 /* h2 = h1 + (h1 * r1) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1139 emit_insn (gen_m2addrf4_cond (h2, cond, h1, h1, r1, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1140 /* d = b - (g2 * g2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1141 emit_insn (gen_m2subrf4_cond (d, cond, b, g2, g2, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1142 /* g3 = g2 + (d * h2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1143 emit_insn (gen_m2addrf4_cond (g3, cond, g2, d, h2, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1144 /* d1 = b - (g3 * g3) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1145 emit_insn (gen_m2subrf4_cond (d1, cond, b, g3, g3, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1146 /* g4 = g3 + (d1 * h2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1147 emit_insn (gen_m2addrf4_cond (g4, cond, g3, d1, h2, y, status1, trunc_dbl));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1148 /* Conversion back into SFmode. */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1149 emit_insn (gen_truncrfdf2 (operands[0], g4));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1150 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1151 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1152
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1153 (define_expand "sqrtxf2"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1154 [(set (match_operand:XF 0 "fr_register_operand" "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1155 (sqrt:XF (match_operand:XF 1 "fr_register_operand" "")))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1156 "TARGET_INLINE_SQRT"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1157 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1158 rtx y = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1159 rtx b = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1160 rtx g = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1161 rtx g1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1162 rtx g2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1163 rtx g3 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1164 rtx g4 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1165 rtx e = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1166 rtx e1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1167 rtx e2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1168 rtx h = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1169 rtx h1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1170 rtx h2 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1171 rtx h3 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1172 rtx d = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1173 rtx d1 = gen_reg_rtx (RFmode);
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
1174 rtx cond = gen_reg_rtx (CCImode);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1175 rtx zero = CONST0_RTX (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1176 rtx c1 = ia64_dconst_0_5();
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1177 rtx reg_df_c1 = gen_reg_rtx (DFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1178 rtx reg_rf_c1 = gen_reg_rtx (RFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1179 rtx status0 = CONST0_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1180 rtx status1 = CONST1_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1181 rtx trunc_off = CONST2_RTX (SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1182
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1183 /* Put needed constants into registers. */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1184 emit_insn (gen_movdf (reg_df_c1, c1));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1185 emit_insn (gen_extenddfrf2 (reg_rf_c1, reg_df_c1));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1186 /* Empty conversion to put input into RFmode. */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1187 emit_insn (gen_extendxfrf2 (b, operands[1]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1188 /* y = sqrt (1 / b) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1189 emit_insn (gen_sqrt_approx_rf (y, b, cond, status0));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1190 /* g = b * y */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1191 emit_insn (gen_mulrf3_cond (g, cond, b, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1192 /* h = 0.5 * y */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1193 emit_insn (gen_mulrf3_cond (h, cond, reg_rf_c1, y, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1194 /* e = 0.5 - (g * h) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1195 emit_insn (gen_m2subrf4_cond (e, cond, reg_rf_c1, g, h, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1196 /* g1 = g + (g * e) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1197 emit_insn (gen_m2addrf4_cond (g1, cond, g, g, e, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1198 /* h1 = h + (h * e) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1199 emit_insn (gen_m2addrf4_cond (h1, cond, h, h, e, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1200 /* e1 = 0.5 - (g1 * h1) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1201 emit_insn (gen_m2subrf4_cond (e1, cond, reg_rf_c1, g1, h1, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1202 /* g2 = g1 + (g1 * e1) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1203 emit_insn (gen_m2addrf4_cond (g2, cond, g1, g1, e1, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1204 /* h2 = h1 + (h1 * e1) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1205 emit_insn (gen_m2addrf4_cond (h2, cond, h1, h1, e1, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1206 /* d = b - (g2 * g2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1207 emit_insn (gen_m2subrf4_cond (d, cond, b, g2, g2, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1208 /* e2 = 0.5 - (g2 * h2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1209 emit_insn (gen_m2subrf4_cond (e2, cond, reg_rf_c1, g2, h2, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1210 /* g3 = g2 + (d * h2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1211 emit_insn (gen_m2addrf4_cond (g3, cond, g2, d, h2, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1212 /* h3 = h2 + (e2 * h2) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1213 emit_insn (gen_m2addrf4_cond (h3, cond, h2, e2, h2, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1214 /* d1 = b - (g3 * g3) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1215 emit_insn (gen_m2subrf4_cond (d1, cond, b, g3, g3, zero, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1216 /* g4 = g3 + (d1 * h3) */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1217 emit_insn (gen_m2addrf4_cond (g4, cond, g3, d1, h3, y, status1, trunc_off));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1218 /* Conversion back into SFmode. */
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1219 emit_insn (gen_truncrfxf2 (operands[0], g4));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1220 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
1221 })