Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/m32c/m32c-lib1.S @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | a06113de4d67 |
| children |
| rev | line source |
|---|---|
| 0 | 1 /* libgcc routines for R8C/M16C/M32C |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2 Copyright (C) 2005, 2009, 2010 |
| 0 | 3 Free Software Foundation, Inc. |
| 4 Contributed by Red Hat. | |
| 5 | |
| 6 This file is part of GCC. | |
| 7 | |
| 8 GCC is free software; you can redistribute it and/or modify it | |
| 9 under the terms of the GNU General Public License as published | |
| 10 by the Free Software Foundation; either version 3, or (at your | |
| 11 option) any later version. | |
| 12 | |
| 13 GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 16 License for more details. | |
| 17 | |
| 18 Under Section 7 of GPL version 3, you are granted additional | |
| 19 permissions described in the GCC Runtime Library Exception, version | |
| 20 3.1, as published by the Free Software Foundation. | |
| 21 | |
| 22 You should have received a copy of the GNU General Public License and | |
| 23 a copy of the GCC Runtime Library Exception along with this program; | |
| 24 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
| 25 <http://www.gnu.org/licenses/>. */ | |
| 26 | |
| 27 #if defined(__r8c_cpu__) || defined(__m16c_cpu__) | |
| 28 #define A16 | |
| 29 #define A(n,w) n | |
| 30 #define W w | |
| 31 #else | |
| 32 #define A24 | |
| 33 #define A(n,w) w | |
| 34 #define W l | |
| 35 #endif | |
| 36 | |
| 37 | |
| 38 #ifdef L__m32c_memregs | |
| 39 | |
| 40 /* Warning: these memory locations are used as a register bank. They | |
| 41 *must* end up consecutive in any final executable, so you may *not* | |
| 42 use the otherwise obvious ".comm" directive to allocate space for | |
| 43 them. */ | |
| 44 | |
| 45 .bss | |
| 46 .global mem0 | |
| 47 mem0: .space 1 | |
| 48 .global mem1 | |
| 49 mem1: .space 1 | |
| 50 .global mem2 | |
| 51 mem2: .space 1 | |
| 52 .global mem3 | |
| 53 mem3: .space 1 | |
| 54 .global mem4 | |
| 55 mem4: .space 1 | |
| 56 .global mem5 | |
| 57 mem5: .space 1 | |
| 58 .global mem6 | |
| 59 mem6: .space 1 | |
| 60 .global mem7 | |
| 61 mem7: .space 1 | |
| 62 .global mem8 | |
| 63 mem8: .space 1 | |
| 64 .global mem9 | |
| 65 mem9: .space 1 | |
| 66 .global mem10 | |
| 67 mem10: .space 1 | |
| 68 .global mem11 | |
| 69 mem11: .space 1 | |
| 70 .global mem12 | |
| 71 mem12: .space 1 | |
| 72 .global mem13 | |
| 73 mem13: .space 1 | |
| 74 .global mem14 | |
| 75 mem14: .space 1 | |
| 76 .global mem15 | |
| 77 mem15: .space 1 | |
| 78 | |
| 79 #endif | |
| 80 | |
| 81 #ifdef L__m32c_eh_return | |
| 82 .text | |
| 83 .global __m32c_eh_return | |
| 84 __m32c_eh_return: | |
| 85 | |
| 86 /* At this point, r0 has the stack adjustment, r1r3 has the | |
| 87 address to return to. The stack looks like this: | |
| 88 | |
| 89 old_ra | |
| 90 old_fp | |
| 91 <- unwound sp | |
| 92 ... | |
| 93 fb | |
| 94 through | |
| 95 r0 | |
| 96 <- sp | |
| 97 | |
| 98 What we need to do is restore all the registers, update the | |
| 99 stack, and return to the right place. | |
| 100 */ | |
| 101 | |
| 102 stc sp,a0 | |
| 103 | |
| 104 add.W A(#16,#24),a0 | |
| 105 /* a0 points to the current stack, just above the register | |
| 106 save areas */ | |
| 107 | |
| 108 mov.w a0,a1 | |
| 109 exts.w r0 | |
| 110 sub.W A(r0,r2r0),a1 | |
| 111 sub.W A(#3,#4),a1 | |
| 112 /* a1 points to the new stack. */ | |
| 113 | |
| 114 /* This is for the "rts" below. */ | |
| 115 mov.w r1,[a1] | |
| 116 #ifdef A16 | |
| 117 mov.w r2,r1 | |
| 118 mov.b r1l,2[a1] | |
| 119 #else | |
| 120 mov.w r2,2[a1] | |
| 121 #endif | |
| 122 | |
| 123 /* This is for the "popc sp" below. */ | |
| 124 mov.W a1,[a0] | |
| 125 | |
| 126 popm r0,r1,r2,r3,a0,a1,sb,fb | |
| 127 popc sp | |
| 128 rts | |
| 129 #endif | |
| 130 | |
| 131 /* SImode arguments for SI foo(SI,SI) functions. */ | |
| 132 #ifdef A16 | |
| 133 #define SAL 5[fb] | |
| 134 #define SAH 7[fb] | |
| 135 #define SBL 9[fb] | |
| 136 #define SBH 11[fb] | |
| 137 #else | |
| 138 #define SAL 8[fb] | |
| 139 #define SAH 10[fb] | |
| 140 #define SBL 12[fb] | |
| 141 #define SBH 14[fb] | |
| 142 #endif | |
| 143 | |
| 144 #ifdef L__m32c_mulsi3 | |
| 145 .text | |
| 146 .global ___mulsi3 | |
| 147 ___mulsi3: | |
| 148 enter #0 | |
| 149 push.w r2 | |
| 150 mov.w SAL,r0 | |
| 151 mulu.w SBL,r0 /* writes to r2r0 */ | |
| 152 mov.w r0,mem0 | |
| 153 mov.w r2,mem2 | |
| 154 mov.w SAL,r0 | |
| 155 mulu.w SBH,r0 /* writes to r2r0 */ | |
| 156 add.w r0,mem2 | |
| 157 mov.w SAH,r0 | |
| 158 mulu.w SBL,r0 /* writes to r2r0 */ | |
| 159 add.w r0,mem2 | |
| 160 pop.w r2 | |
| 161 exitd | |
| 162 #endif | |
| 163 | |
| 164 #ifdef L__m32c_cmpsi2 | |
| 165 .text | |
| 166 .global ___cmpsi2 | |
| 167 ___cmpsi2: | |
| 168 enter #0 | |
| 169 cmp.w SBH,SAH | |
| 170 jgt cmpsi_gt | |
| 171 jlt cmpsi_lt | |
| 172 cmp.w SBL,SAL | |
| 173 jgt cmpsi_gt | |
| 174 jlt cmpsi_lt | |
| 175 mov.w #1,r0 | |
| 176 exitd | |
| 177 cmpsi_gt: | |
| 178 mov.w #2,r0 | |
| 179 exitd | |
| 180 cmpsi_lt: | |
| 181 mov.w #0,r0 | |
| 182 exitd | |
| 183 #endif | |
| 184 | |
| 185 #ifdef L__m32c_ucmpsi2 | |
| 186 .text | |
| 187 .global ___ucmpsi2 | |
| 188 ___ucmpsi2: | |
| 189 enter #0 | |
| 190 cmp.w SBH,SAH | |
| 191 jgtu cmpsi_gt | |
| 192 jltu cmpsi_lt | |
| 193 cmp.w SBL,SAL | |
| 194 jgtu cmpsi_gt | |
| 195 jltu cmpsi_lt | |
| 196 mov.w #1,r0 | |
| 197 exitd | |
| 198 cmpsi_gt: | |
| 199 mov.w #2,r0 | |
| 200 exitd | |
| 201 cmpsi_lt: | |
| 202 mov.w #0,r0 | |
| 203 exitd | |
| 204 #endif | |
| 205 | |
| 206 #ifdef L__m32c_jsri16 | |
| 207 .text | |
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67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
208 #ifdef A16 |
| 0 | 209 .global m32c_jsri16 |
| 210 m32c_jsri16: | |
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67
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
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211 add.w #-1, sp |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
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212 |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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213 /* Read the address (16 bits) and return address (24 bits) off |
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f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
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214 the stack. */ |
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f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
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changeset
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215 mov.w 4[sp], r0 |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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216 mov.w 1[sp], r3 |
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f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
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217 mov.b 3[sp], a0 /* This zero-extends, so the high byte has |
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f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
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218 zero in it. */ |
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f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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219 |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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220 /* Write the return address, then new address, to the stack. */ |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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221 mov.w a0, 1[sp] /* Just to get the zero in 2[sp]. */ |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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222 mov.w r0, 0[sp] |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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223 mov.w r3, 3[sp] |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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224 mov.b a0, 5[sp] |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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225 |
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parents:
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226 /* This "returns" to the target address, leaving the pending |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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227 return address on the stack. */ |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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228 rts |
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parents:
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229 #endif |
| 0 | 230 |
| 231 #endif |