Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/pa/pa64-regs.h @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
---|---|
date | Tue, 22 Mar 2011 17:18:12 +0900 |
parents | a06113de4d67 |
children | 04ced10e8804 |
rev | line source |
---|---|
0 | 1 /* Configuration for GCC-compiler for PA-RISC. |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2 Copyright (C) 1999, 2000, 2003, 2004, 2007, 2008, 2010 |
0 | 3 Free Software Foundation, Inc. |
4 | |
5 This file is part of GCC. | |
6 | |
7 GCC is free software; you can redistribute it and/or modify | |
8 it under the terms of the GNU General Public License as published by | |
9 the Free Software Foundation; either version 3, or (at your option) | |
10 any later version. | |
11 | |
12 GCC is distributed in the hope that it will be useful, | |
13 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 GNU General Public License for more details. | |
16 | |
17 You should have received a copy of the GNU General Public License | |
18 along with GCC; see the file COPYING3. If not see | |
19 <http://www.gnu.org/licenses/>. */ | |
20 | |
21 /* Standard register usage. | |
22 | |
23 It is safe to refer to actual register numbers in this file. */ | |
24 | |
25 /* Number of actual hardware registers. | |
26 The hardware registers are assigned numbers for the compiler | |
27 from 0 to just below FIRST_PSEUDO_REGISTER. | |
28 All registers that the compiler knows about must be given numbers, | |
29 even those that are not normally considered general registers. | |
30 | |
31 HP-PA 2.0w has 32 fullword registers and 32 floating point | |
32 registers. However, the floating point registers behave | |
33 differently: the left and right halves of registers are addressable | |
34 as 32-bit registers. | |
35 | |
36 Due to limitations within GCC itself, we do not expose the left/right | |
37 half addressability when in wide mode. This is not a major performance | |
38 issue as using the halves independently triggers false dependency stalls | |
39 anyway. */ | |
40 | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
41 #define FIRST_PSEUDO_REGISTER 62 /* 32 general regs + 28 fp regs + |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
42 + 1 shift reg + frame pointer */ |
0 | 43 |
44 /* 1 for registers that have pervasive standard uses | |
45 and are not available for the register allocator. | |
46 | |
47 On the HP-PA, these are: | |
48 Reg 0 = 0 (hardware). However, 0 is used for condition code, | |
49 so is not fixed. | |
50 Reg 1 = ADDIL target/Temporary (hardware). | |
51 Reg 2 = Return Pointer | |
52 Reg 3 = Frame Pointer | |
53 Reg 4 = Frame Pointer (>8k varying frame with HP compilers only) | |
54 Reg 4-18 = Preserved Registers | |
55 Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme. | |
56 Reg 20-22 = Temporary Registers | |
57 Reg 23-26 = Temporary/Parameter Registers | |
58 Reg 27 = Global Data Pointer (hp) | |
59 Reg 28 = Temporary/Return Value register | |
60 Reg 29 = Temporary/Static Chain/Return Value register #2 | |
61 Reg 30 = stack pointer | |
62 Reg 31 = Temporary/Millicode Return Pointer (hp) | |
63 | |
64 Freg 0-3 = Status Registers -- Not known to the compiler. | |
65 Freg 4-7 = Arguments/Return Value | |
66 Freg 8-11 = Temporary Registers | |
67 Freg 12-21 = Preserved Registers | |
68 Freg 22-31 = Temporary Registers | |
69 | |
70 */ | |
71 | |
72 #define FIXED_REGISTERS \ | |
73 {0, 0, 0, 0, 0, 0, 0, 0, \ | |
74 0, 0, 0, 0, 0, 0, 0, 0, \ | |
75 0, 0, 0, 0, 0, 0, 0, 0, \ | |
76 0, 0, 0, 1, 0, 0, 1, 0, \ | |
77 /* fp registers */ \ | |
78 0, 0, 0, 0, 0, 0, 0, 0, \ | |
79 0, 0, 0, 0, 0, 0, 0, 0, \ | |
80 0, 0, 0, 0, 0, 0, 0, 0, \ | |
81 0, 0, 0, 0, \ | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
82 /* shift register and soft frame pointer */ \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
83 0, 1} |
0 | 84 |
85 /* 1 for registers not available across function calls. | |
86 These must include the FIXED_REGISTERS and also any | |
87 registers that can be used without being saved. | |
88 The latter must include the registers where values are returned | |
89 and the register where structure-value addresses are passed. | |
90 Aside from that, you can include as many other registers as you like. */ | |
91 #define CALL_USED_REGISTERS \ | |
92 {1, 1, 1, 0, 0, 0, 0, 0, \ | |
93 0, 0, 0, 0, 0, 0, 0, 0, \ | |
94 0, 0, 0, 1, 1, 1, 1, 1, \ | |
95 1, 1, 1, 1, 1, 1, 1, 1, \ | |
96 /* fp registers */ \ | |
97 1, 1, 1, 1, 1, 1, 1, 1, \ | |
98 0, 0, 0, 0, 0, 0, 0, 0, \ | |
99 0, 0, 1, 1, 1, 1, 1, 1, \ | |
100 1, 1, 1, 1, \ | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
101 /* shift register and soft frame pointer */ \ |
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
102 1, 1} |
0 | 103 |
104 /* Allocate the call used registers first. This should minimize | |
105 the number of registers that need to be saved (as call used | |
106 registers will generally not be allocated across a call). | |
107 | |
108 Experimentation has shown slightly better results by allocating | |
109 FP registers first. We allocate the caller-saved registers more | |
110 or less in reverse order to their allocation as arguments. */ | |
111 | |
112 #define REG_ALLOC_ORDER \ | |
113 { \ | |
114 /* caller-saved fp regs. */ \ | |
115 50, 51, 52, 53, 54, 55, 56, 57, \ | |
116 58, 59, 39, 38, 37, 36, 35, 34, \ | |
117 33, 32, \ | |
118 /* caller-saved general regs. */ \ | |
119 28, 31, 19, 20, 21, 22, 23, 24, \ | |
120 25, 26, 29, 2, \ | |
121 /* callee-saved fp regs. */ \ | |
122 40, 41, 42, 43, 44, 45, 46, 47, \ | |
123 48, 49, \ | |
124 /* callee-saved general regs. */ \ | |
125 3, 4, 5, 6, 7, 8, 9, 10, \ | |
126 11, 12, 13, 14, 15, 16, 17, 18, \ | |
127 /* special registers. */ \ | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
128 1, 27, 30, 0, 60, 61} |
0 | 129 |
130 | |
131 /* Return number of consecutive hard regs needed starting at reg REGNO | |
132 to hold something of mode MODE. | |
133 This is ordinarily the length in words of a value of mode MODE | |
134 but can be less for certain modes in special long registers. | |
135 | |
136 For PA64, GPRs and FPRs hold 64 bits worth. We ignore the 32-bit | |
137 addressability of the FPRs and pretend each register holds precisely | |
138 WORD_SIZE bits. Note that SCmode values are placed in a single FPR. | |
139 Thus, any patterns defined to operate on these values would have to | |
140 use the 32-bit addressability of the FPR registers. */ | |
141 #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
142 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
143 | |
144 /* These are the valid FP modes. */ | |
145 #define VALID_FP_MODE_P(MODE) \ | |
146 ((MODE) == SFmode || (MODE) == DFmode \ | |
147 || (MODE) == SCmode || (MODE) == DCmode \ | |
148 || (MODE) == SImode || (MODE) == DImode) | |
149 | |
150 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
151 On the HP-PA, the cpu registers can hold any mode. We | |
152 force this to be an even register is it cannot hold the full mode. */ | |
153 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
154 ((REGNO) == 0 \ | |
155 ? (MODE) == CCmode || (MODE) == CCFPmode \ | |
156 /* Make wide modes be in aligned registers. */ \ | |
157 : FP_REGNO_P (REGNO) \ | |
158 ? (VALID_FP_MODE_P (MODE) \ | |
159 && (GET_MODE_SIZE (MODE) <= 8 \ | |
160 || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 1) == 0) \ | |
161 || (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 3) == 0))) \ | |
162 : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \ | |
163 || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD \ | |
164 && ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28)) \ | |
165 || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD \ | |
166 && ((REGNO) & 3) == 3 && (REGNO) <= 23))) | |
167 | |
168 /* How to renumber registers for dbx and gdb. | |
169 | |
170 Registers 0 - 31 remain unchanged. | |
171 | |
172 Registers 32 - 59 are mapped to 72, 74, 76 ... | |
173 | |
174 Register 60 is mapped to 32. */ | |
175 #define DBX_REGISTER_NUMBER(REGNO) \ | |
176 ((REGNO) <= 31 ? (REGNO) : ((REGNO) < 60 ? (REGNO - 32) * 2 + 72 : 32)) | |
177 | |
178 /* We must not use the DBX register numbers for the DWARF 2 CFA column | |
179 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. | |
180 Instead use the identity mapping. */ | |
181 #define DWARF_FRAME_REGNUM(REG) REG | |
182 | |
183 /* Define the classes of registers for register constraints in the | |
184 machine description. Also define ranges of constants. | |
185 | |
186 One of the classes must always be named ALL_REGS and include all hard regs. | |
187 If there is more than one class, another class must be named NO_REGS | |
188 and contain no registers. | |
189 | |
190 The name GENERAL_REGS must be the name of a class (or an alias for | |
191 another name such as ALL_REGS). This is the class of registers | |
192 that is allowed by "g" or "r" in a register constraint. | |
193 Also, registers outside this class are allocated only when | |
194 instructions express preferences for them. | |
195 | |
196 The classes must be numbered in nondecreasing order; that is, | |
197 a larger-numbered class must never be contained completely | |
198 in a smaller-numbered class. | |
199 | |
200 For any two classes, it is very desirable that there be another | |
201 class that represents their union. */ | |
202 | |
203 /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs, | |
204 1.1 fp regs, and the high 1.1 fp regs, to which the operands of | |
205 fmpyadd and fmpysub are restricted. */ | |
206 | |
207 enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, | |
208 GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES}; | |
209 | |
210 #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
211 | |
212 /* Give names of register classes as strings for dump file. */ | |
213 | |
214 #define REG_CLASS_NAMES \ | |
215 {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \ | |
216 "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"} | |
217 | |
218 /* Define which registers fit in which classes. | |
219 This is an initializer for a vector of HARD_REG_SET | |
220 of length N_REG_CLASSES. Register 0, the "condition code" register, | |
221 is in no class. */ | |
222 | |
223 #define REG_CLASS_CONTENTS \ | |
224 {{0x00000000, 0x00000000}, /* NO_REGS */ \ | |
225 {0x00000002, 0x00000000}, /* R1_REGS */ \ | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
226 {0xfffffffe, 0x20000000}, /* GENERAL_REGS */ \ |
0 | 227 {0x00000000, 0x00000000}, /* FPUPPER_REGS */ \ |
228 {0x00000000, 0x0fffffff}, /* FP_REGS */ \ | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
229 {0xfffffffe, 0x2fffffff}, /* GENERAL_OR_FP_REGS */ \ |
0 | 230 {0x00000000, 0x10000000}, /* SHIFT_REGS */ \ |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
231 {0xfffffffe, 0x3fffffff}} /* ALL_REGS */ |
0 | 232 |
233 /* The following macro defines cover classes for Integrated Register | |
234 Allocator. Cover classes is a set of non-intersected register | |
235 classes covering all hard registers used for register allocation | |
236 purpose. Any move between two registers of a cover class should be | |
237 cheaper than load or store of the registers. The macro value is | |
238 array of register classes with LIM_REG_CLASSES used as the end | |
239 marker. */ | |
240 | |
241 #define IRA_COVER_CLASSES \ | |
242 { \ | |
243 GENERAL_REGS, FP_REGS, SHIFT_REGS, LIM_REG_CLASSES \ | |
244 } | |
245 | |
246 /* Defines invalid mode changes. */ | |
247 | |
248 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
249 pa_cannot_change_mode_class (FROM, TO, CLASS) | |
250 | |
251 /* Return the class number of the smallest class containing | |
252 reg number REGNO. This could be a conditional expression | |
253 or could index an array. */ | |
254 | |
255 #define REGNO_REG_CLASS(REGNO) \ | |
256 ((REGNO) == 0 ? NO_REGS \ | |
257 : (REGNO) == 1 ? R1_REGS \ | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
258 : (REGNO) < 32 || (REGNO) == 61 ? GENERAL_REGS \ |
0 | 259 : (REGNO) < 60 ? FP_REGS \ |
260 : SHIFT_REGS) | |
261 | |
262 /* Return the maximum number of consecutive registers | |
263 needed to represent mode MODE in a register of class CLASS. */ | |
264 #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
265 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
266 | |
267 /* 1 if N is a possible register number for function argument passing. */ | |
268 | |
269 #define FUNCTION_ARG_REGNO_P(N) \ | |
270 ((((N) >= 19) && (N) <= 26) \ | |
271 || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39)) | |
272 | |
273 /* How to refer to registers in assembler output. | |
274 This sequence is indexed by compiler's hard-register-number (see above). */ | |
275 | |
276 #define REGISTER_NAMES \ | |
277 {"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ | |
278 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ | |
279 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \ | |
280 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \ | |
281 "%fr4", "%fr5", "%fr6", "%fr7", "%fr8", "%fr9", "%fr10", "%fr11", \ | |
282 "%fr12", "%fr13", "%fr14", "%fr15", "%fr16", "%fr17", "%fr18", "%fr19", \ | |
283 "%fr20", "%fr21", "%fr22", "%fr23", "%fr24", "%fr25", "%fr26", "%fr27", \ | |
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
284 "%fr28", "%fr29", "%fr30", "%fr31", "SAR", "sfp"} |
0 | 285 |
286 #define ADDITIONAL_REGISTER_NAMES \ | |
287 {{"%cr11",60}} | |
288 | |
289 #define FP_SAVED_REG_LAST 49 | |
290 #define FP_SAVED_REG_FIRST 40 | |
291 #define FP_REG_STEP 1 | |
292 #define FP_REG_FIRST 32 | |
293 #define FP_REG_LAST 59 |