Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/rs6000/power4.md @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | 77e2b8dfacca |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 ;; Scheduling description for IBM Power4 and PowerPC 970 processors. |
|
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2 ;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. |
| 0 | 3 ;; |
| 4 ;; This file is part of GCC. | |
| 5 ;; | |
| 6 ;; GCC is free software; you can redistribute it and/or modify it | |
| 7 ;; under the terms of the GNU General Public License as published | |
| 8 ;; by the Free Software Foundation; either version 3, or (at your | |
| 9 ;; option) any later version. | |
| 10 ;; | |
| 11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 14 ;; License for more details. | |
| 15 ;; | |
| 16 ;; You should have received a copy of the GNU General Public License | |
| 17 ;; along with GCC; see the file COPYING3. If not see | |
| 18 ;; <http://www.gnu.org/licenses/>. | |
| 19 | |
| 20 ;; Sources: IBM Red Book and White Paper on POWER4 | |
| 21 | |
| 22 ;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip). | |
| 23 ;; Instructions that update more than one register get broken into two | |
| 24 ;; (split) or more internal ops. The chip can issue up to 5 | |
| 25 ;; internal ops per cycle. | |
| 26 | |
| 27 (define_automaton "power4iu,power4fpu,power4vec,power4misc") | |
| 28 | |
| 29 (define_cpu_unit "iu1_power4,iu2_power4" "power4iu") | |
| 30 (define_cpu_unit "lsu1_power4,lsu2_power4" "power4misc") | |
| 31 (define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu") | |
| 32 (define_cpu_unit "bpu_power4,cru_power4" "power4misc") | |
| 33 (define_cpu_unit "vec_power4,vecperm_power4" "power4vec") | |
| 34 (define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4" | |
| 35 "power4misc") | |
| 36 | |
| 37 (define_reservation "lsq_power4" | |
| 38 "(du1_power4,lsu1_power4)\ | |
| 39 |(du2_power4,lsu2_power4)\ | |
| 40 |(du3_power4,lsu2_power4)\ | |
| 41 |(du4_power4,lsu1_power4)") | |
| 42 | |
| 43 (define_reservation "lsuq_power4" | |
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44 "((du1_power4+du2_power4,lsu1_power4)\ |
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45 |(du2_power4+du3_power4,lsu2_power4)\ |
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46 |(du3_power4+du4_power4,lsu2_power4))\ |
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47 +(nothing,iu2_power4|nothing,iu1_power4)") |
| 0 | 48 |
| 49 (define_reservation "iq_power4" | |
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50 "(du1_power4|du2_power4|du3_power4|du4_power4),\ |
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51 (iu1_power4|iu2_power4)") |
| 0 | 52 |
| 53 (define_reservation "fpq_power4" | |
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54 "(du1_power4|du2_power4|du3_power4|du4_power4),\ |
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55 (fpu1_power4|fpu2_power4)") |
| 0 | 56 |
| 57 (define_reservation "vq_power4" | |
| 58 "(du1_power4,vec_power4)\ | |
| 59 |(du2_power4,vec_power4)\ | |
| 60 |(du3_power4,vec_power4)\ | |
| 61 |(du4_power4,vec_power4)") | |
| 62 | |
| 63 (define_reservation "vpq_power4" | |
| 64 "(du1_power4,vecperm_power4)\ | |
| 65 |(du2_power4,vecperm_power4)\ | |
| 66 |(du3_power4,vecperm_power4)\ | |
| 67 |(du4_power4,vecperm_power4)") | |
| 68 | |
| 69 | |
| 70 ; Dispatch slots are allocated in order conforming to program order. | |
| 71 (absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4") | |
| 72 (absence_set "du2_power4" "du3_power4,du4_power4,du5_power4") | |
| 73 (absence_set "du3_power4" "du4_power4,du5_power4") | |
| 74 (absence_set "du4_power4" "du5_power4") | |
| 75 | |
| 76 | |
| 77 ; Load/store | |
| 78 (define_insn_reservation "power4-load" 4 ; 3 | |
| 79 (and (eq_attr "type" "load") | |
| 80 (eq_attr "cpu" "power4")) | |
| 81 "lsq_power4") | |
| 82 | |
| 83 (define_insn_reservation "power4-load-ext" 5 | |
| 84 (and (eq_attr "type" "load_ext") | |
| 85 (eq_attr "cpu" "power4")) | |
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86 "(du1_power4+du2_power4,lsu1_power4\ |
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87 |du2_power4+du3_power4,lsu2_power4\ |
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88 |du3_power4+du4_power4,lsu2_power4),\ |
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89 nothing,nothing,\ |
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90 (iu2_power4|iu1_power4)") |
| 0 | 91 |
| 92 (define_insn_reservation "power4-load-ext-update" 5 | |
| 93 (and (eq_attr "type" "load_ext_u") | |
| 94 (eq_attr "cpu" "power4")) | |
| 95 "du1_power4+du2_power4+du3_power4+du4_power4,\ | |
| 96 lsu1_power4+iu2_power4,nothing,nothing,iu2_power4") | |
| 97 | |
| 98 (define_insn_reservation "power4-load-ext-update-indexed" 5 | |
| 99 (and (eq_attr "type" "load_ext_ux") | |
| 100 (eq_attr "cpu" "power4")) | |
| 101 "du1_power4+du2_power4+du3_power4+du4_power4,\ | |
| 102 iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4") | |
| 103 | |
| 104 (define_insn_reservation "power4-load-update-indexed" 3 | |
| 105 (and (eq_attr "type" "load_ux") | |
| 106 (eq_attr "cpu" "power4")) | |
| 107 "du1_power4+du2_power4+du3_power4+du4_power4,\ | |
| 108 iu1_power4,lsu2_power4+iu2_power4") | |
| 109 | |
| 110 (define_insn_reservation "power4-load-update" 4 ; 3 | |
| 111 (and (eq_attr "type" "load_u") | |
| 112 (eq_attr "cpu" "power4")) | |
| 113 "lsuq_power4") | |
| 114 | |
| 115 (define_insn_reservation "power4-fpload" 6 ; 5 | |
| 116 (and (eq_attr "type" "fpload") | |
| 117 (eq_attr "cpu" "power4")) | |
| 118 "lsq_power4") | |
| 119 | |
| 120 (define_insn_reservation "power4-fpload-update" 6 ; 5 | |
| 121 (and (eq_attr "type" "fpload_u,fpload_ux") | |
| 122 (eq_attr "cpu" "power4")) | |
| 123 "lsuq_power4") | |
| 124 | |
| 125 (define_insn_reservation "power4-vecload" 6 ; 5 | |
| 126 (and (eq_attr "type" "vecload") | |
| 127 (eq_attr "cpu" "power4")) | |
| 128 "lsq_power4") | |
| 129 | |
| 130 (define_insn_reservation "power4-store" 12 | |
| 131 (and (eq_attr "type" "store") | |
| 132 (eq_attr "cpu" "power4")) | |
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133 "((du1_power4,lsu1_power4)\ |
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134 |(du2_power4,lsu2_power4)\ |
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135 |(du3_power4,lsu2_power4)\ |
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136 |(du4_power4,lsu1_power4)),\ |
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137 (iu1_power4|iu2_power4)") |
| 0 | 138 |
| 139 (define_insn_reservation "power4-store-update" 12 | |
| 140 (and (eq_attr "type" "store_u") | |
| 141 (eq_attr "cpu" "power4")) | |
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142 "((du1_power4+du2_power4,lsu1_power4)\ |
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143 |(du2_power4+du3_power4,lsu2_power4)\ |
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144 |(du3_power4+du4_power4,lsu2_power4)\ |
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145 |(du3_power4+du4_power4,lsu2_power4))+\ |
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146 ((nothing,iu2_power4,iu1_power4)\ |
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147 |(nothing,iu2_power4,iu2_power4)\ |
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148 |(nothing,iu1_power4,iu2_power4)\ |
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149 |(nothing,iu1_power4,iu2_power4))") |
| 0 | 150 |
| 151 (define_insn_reservation "power4-store-update-indexed" 12 | |
| 152 (and (eq_attr "type" "store_ux") | |
| 153 (eq_attr "cpu" "power4")) | |
| 154 "du1_power4+du2_power4+du3_power4+du4_power4,\ | |
| 155 iu1_power4,lsu2_power4+iu2_power4,iu2_power4") | |
| 156 | |
| 157 (define_insn_reservation "power4-fpstore" 12 | |
| 158 (and (eq_attr "type" "fpstore") | |
| 159 (eq_attr "cpu" "power4")) | |
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160 "((du1_power4,lsu1_power4)\ |
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161 |(du2_power4,lsu2_power4)\ |
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162 |(du3_power4,lsu2_power4)\ |
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163 |(du4_power4,lsu1_power4)),\ |
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164 (fpu1_power4|fpu2_power4)") |
| 0 | 165 |
| 166 (define_insn_reservation "power4-fpstore-update" 12 | |
| 167 (and (eq_attr "type" "fpstore_u,fpstore_ux") | |
| 168 (eq_attr "cpu" "power4")) | |
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169 "((du1_power4+du2_power4,lsu1_power4)\ |
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170 |(du2_power4+du3_power4,lsu2_power4)\ |
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171 |(du3_power4+du4_power4,lsu2_power4))\ |
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172 +(nothing,(iu1_power4|iu2_power4),(fpu1_power4|fpu2_power4))") |
| 0 | 173 |
| 174 (define_insn_reservation "power4-vecstore" 12 | |
| 175 (and (eq_attr "type" "vecstore") | |
| 176 (eq_attr "cpu" "power4")) | |
| 177 "(du1_power4,lsu1_power4,vec_power4)\ | |
| 178 |(du2_power4,lsu2_power4,vec_power4)\ | |
| 179 |(du3_power4,lsu2_power4,vec_power4)\ | |
| 180 |(du4_power4,lsu1_power4,vec_power4)") | |
| 181 | |
| 182 (define_insn_reservation "power4-llsc" 11 | |
| 183 (and (eq_attr "type" "load_l,store_c,sync") | |
| 184 (eq_attr "cpu" "power4")) | |
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185 "du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4") |
| 0 | 186 |
| 187 | |
| 188 ; Integer latency is 2 cycles | |
| 189 (define_insn_reservation "power4-integer" 2 | |
| 190 (and (eq_attr "type" "integer,insert_dword,shift,trap,\ | |
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191 var_shift_rotate,cntlz,exts,isel") |
| 0 | 192 (eq_attr "cpu" "power4")) |
| 193 "iq_power4") | |
| 194 | |
| 195 (define_insn_reservation "power4-two" 2 | |
| 196 (and (eq_attr "type" "two") | |
| 197 (eq_attr "cpu" "power4")) | |
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198 "((du1_power4+du2_power4)\ |
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199 |(du2_power4+du3_power4)\ |
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200 |(du3_power4+du4_power4)\ |
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201 |(du4_power4+du1_power4)),\ |
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202 ((iu1_power4,nothing,iu2_power4)\ |
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203 |(iu2_power4,nothing,iu2_power4)\ |
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204 |(iu2_power4,nothing,iu1_power4)\ |
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205 |(iu1_power4,nothing,iu1_power4))") |
| 0 | 206 |
| 207 (define_insn_reservation "power4-three" 2 | |
| 208 (and (eq_attr "type" "three") | |
| 209 (eq_attr "cpu" "power4")) | |
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210 "(du1_power4+du2_power4+du3_power4|du2_power4+du3_power4+du4_power4\ |
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211 |du3_power4+du4_power4+du1_power4|du4_power4+du1_power4+du2_power4),\ |
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212 ((iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\ |
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213 |(iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\ |
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214 |(iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\ |
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215 |(iu1_power4,nothing,iu2_power4,nothing,iu2_power4))") |
| 0 | 216 |
| 217 (define_insn_reservation "power4-insert" 4 | |
| 218 (and (eq_attr "type" "insert_word") | |
| 219 (eq_attr "cpu" "power4")) | |
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220 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ |
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221 ((iu1_power4,nothing,iu2_power4)\ |
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222 |(iu2_power4,nothing,iu2_power4)\ |
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223 |(iu2_power4,nothing,iu1_power4))") |
| 0 | 224 |
| 225 (define_insn_reservation "power4-cmp" 3 | |
| 226 (and (eq_attr "type" "cmp,fast_compare") | |
| 227 (eq_attr "cpu" "power4")) | |
| 228 "iq_power4") | |
| 229 | |
| 230 (define_insn_reservation "power4-compare" 2 | |
| 231 (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare") | |
| 232 (eq_attr "cpu" "power4")) | |
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233 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ |
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234 ((iu1_power4,iu2_power4)\ |
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235 |(iu2_power4,iu2_power4)\ |
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236 |(iu2_power4,iu1_power4))") |
| 0 | 237 |
| 238 (define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") | |
| 239 | |
| 240 (define_insn_reservation "power4-lmul-cmp" 7 | |
| 241 (and (eq_attr "type" "lmul_compare") | |
| 242 (eq_attr "cpu" "power4")) | |
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243 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ |
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244 ((iu1_power4*6,iu2_power4)\ |
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245 |(iu2_power4*6,iu2_power4)\ |
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246 |(iu2_power4*6,iu1_power4))") |
| 0 | 247 |
| 248 (define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") | |
| 249 | |
| 250 (define_insn_reservation "power4-imul-cmp" 5 | |
| 251 (and (eq_attr "type" "imul_compare") | |
| 252 (eq_attr "cpu" "power4")) | |
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253 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ |
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254 ((iu1_power4*4,iu2_power4)\ |
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255 |(iu2_power4*4,iu2_power4)\ |
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256 |(iu2_power4*4,iu1_power4))") |
| 0 | 257 |
| 258 (define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") | |
| 259 | |
| 260 (define_insn_reservation "power4-lmul" 7 | |
| 261 (and (eq_attr "type" "lmul") | |
| 262 (eq_attr "cpu" "power4")) | |
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263 "(du1_power4|du2_power4|du3_power4|du4_power4),\ |
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264 (iu1_power4*6|iu2_power4*6)") |
| 0 | 265 |
| 266 (define_insn_reservation "power4-imul" 5 | |
| 267 (and (eq_attr "type" "imul") | |
| 268 (eq_attr "cpu" "power4")) | |
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269 "(du1_power4|du2_power4|du3_power4|du4_power4),\ |
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270 (iu1_power4*4|iu2_power4*4)") |
| 0 | 271 |
| 272 (define_insn_reservation "power4-imul3" 4 | |
| 273 (and (eq_attr "type" "imul2,imul3") | |
| 274 (eq_attr "cpu" "power4")) | |
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275 "(du1_power4|du2_power4|du3_power4|du4_power4),\ |
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276 (iu1_power4*3|iu2_power4*3)") |
| 0 | 277 |
| 278 | |
| 279 ; SPR move only executes in first IU. | |
| 280 ; Integer division only executes in second IU. | |
| 281 (define_insn_reservation "power4-idiv" 36 | |
| 282 (and (eq_attr "type" "idiv") | |
| 283 (eq_attr "cpu" "power4")) | |
| 284 "du1_power4+du2_power4,iu2_power4*35") | |
| 285 | |
| 286 (define_insn_reservation "power4-ldiv" 68 | |
| 287 (and (eq_attr "type" "ldiv") | |
| 288 (eq_attr "cpu" "power4")) | |
| 289 "du1_power4+du2_power4,iu2_power4*67") | |
| 290 | |
| 291 | |
| 292 (define_insn_reservation "power4-mtjmpr" 3 | |
| 293 (and (eq_attr "type" "mtjmpr,mfjmpr") | |
| 294 (eq_attr "cpu" "power4")) | |
| 295 "du1_power4,bpu_power4") | |
| 296 | |
| 297 | |
| 298 ; Branches take dispatch Slot 4. The presence_sets prevent other insn from | |
| 299 ; grabbing previous dispatch slots once this is assigned. | |
| 300 (define_insn_reservation "power4-branch" 2 | |
| 301 (and (eq_attr "type" "jmpreg,branch") | |
| 302 (eq_attr "cpu" "power4")) | |
| 303 "(du5_power4\ | |
| 304 |du4_power4+du5_power4\ | |
| 305 |du3_power4+du4_power4+du5_power4\ | |
| 306 |du2_power4+du3_power4+du4_power4+du5_power4\ | |
| 307 |du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4") | |
| 308 | |
| 309 | |
| 310 ; Condition Register logical ops are split if non-destructive (RT != RB) | |
| 311 (define_insn_reservation "power4-crlogical" 2 | |
| 312 (and (eq_attr "type" "cr_logical") | |
| 313 (eq_attr "cpu" "power4")) | |
| 314 "du1_power4,cru_power4") | |
| 315 | |
| 316 (define_insn_reservation "power4-delayedcr" 4 | |
| 317 (and (eq_attr "type" "delayed_cr") | |
| 318 (eq_attr "cpu" "power4")) | |
| 319 "du1_power4+du2_power4,cru_power4,cru_power4") | |
| 320 | |
| 321 ; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu | |
| 322 (define_insn_reservation "power4-mfcr" 6 | |
| 323 (and (eq_attr "type" "mfcr") | |
| 324 (eq_attr "cpu" "power4")) | |
| 325 "du1_power4+du2_power4+du3_power4+du4_power4,\ | |
| 326 du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\ | |
| 327 cru_power4,cru_power4,cru_power4") | |
| 328 | |
| 329 ; mfcrf (1 field) | |
| 330 (define_insn_reservation "power4-mfcrf" 3 | |
| 331 (and (eq_attr "type" "mfcrf") | |
| 332 (eq_attr "cpu" "power4")) | |
| 333 "du1_power4,cru_power4") | |
| 334 | |
| 335 ; mtcrf (1 field) | |
| 336 (define_insn_reservation "power4-mtcr" 4 | |
| 337 (and (eq_attr "type" "mtcr") | |
| 338 (eq_attr "cpu" "power4")) | |
| 339 "du1_power4,iu1_power4") | |
| 340 | |
| 341 ; Basic FP latency is 6 cycles | |
| 342 (define_insn_reservation "power4-fp" 6 | |
| 343 (and (eq_attr "type" "fp,dmul") | |
| 344 (eq_attr "cpu" "power4")) | |
| 345 "fpq_power4") | |
| 346 | |
| 347 (define_insn_reservation "power4-fpcompare" 5 | |
| 348 (and (eq_attr "type" "fpcompare") | |
| 349 (eq_attr "cpu" "power4")) | |
| 350 "fpq_power4") | |
| 351 | |
| 352 (define_insn_reservation "power4-sdiv" 33 | |
| 353 (and (eq_attr "type" "sdiv,ddiv") | |
| 354 (eq_attr "cpu" "power4")) | |
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355 "(du1_power4|du2_power4|du3_power4|du4_power4),\ |
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356 (fpu1_power4*28|fpu2_power4*28)") |
| 0 | 357 |
| 358 (define_insn_reservation "power4-sqrt" 40 | |
| 359 (and (eq_attr "type" "ssqrt,dsqrt") | |
| 360 (eq_attr "cpu" "power4")) | |
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361 "(du1_power4|du2_power4|du3_power4|du4_power4),\ |
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362 (fpu1_power4*35|fpu2_power4*35)") |
| 0 | 363 |
| 364 (define_insn_reservation "power4-isync" 2 | |
| 365 (and (eq_attr "type" "isync") | |
| 366 (eq_attr "cpu" "power4")) | |
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367 "du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4") |
| 0 | 368 |
| 369 | |
| 370 ; VMX | |
| 371 (define_insn_reservation "power4-vecsimple" 2 | |
| 372 (and (eq_attr "type" "vecsimple") | |
| 373 (eq_attr "cpu" "power4")) | |
| 374 "vq_power4") | |
| 375 | |
| 376 (define_insn_reservation "power4-veccomplex" 5 | |
| 377 (and (eq_attr "type" "veccomplex") | |
| 378 (eq_attr "cpu" "power4")) | |
| 379 "vq_power4") | |
| 380 | |
| 381 ; vecfp compare | |
| 382 (define_insn_reservation "power4-veccmp" 8 | |
| 383 (and (eq_attr "type" "veccmp") | |
| 384 (eq_attr "cpu" "power4")) | |
| 385 "vq_power4") | |
| 386 | |
| 387 (define_insn_reservation "power4-vecfloat" 8 | |
| 388 (and (eq_attr "type" "vecfloat") | |
| 389 (eq_attr "cpu" "power4")) | |
| 390 "vq_power4") | |
| 391 | |
| 392 (define_insn_reservation "power4-vecperm" 2 | |
| 393 (and (eq_attr "type" "vecperm") | |
| 394 (eq_attr "cpu" "power4")) | |
| 395 "vpq_power4") | |
| 396 | |
| 397 (define_bypass 4 "power4-vecload" "power4-vecperm") | |
| 398 | |
| 399 (define_bypass 3 "power4-vecsimple" "power4-vecperm") | |
| 400 (define_bypass 6 "power4-veccomplex" "power4-vecperm") | |
| 401 (define_bypass 3 "power4-vecperm" | |
| 402 "power4-vecsimple,power4-veccomplex,power4-vecfloat") | |
| 403 (define_bypass 9 "power4-vecfloat" "power4-vecperm") | |
| 404 | |
| 405 (define_bypass 5 "power4-vecsimple,power4-veccomplex" | |
| 406 "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") | |
| 407 | |
| 408 (define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore") | |
| 409 (define_bypass 7 "power4-veccomplex" "power4-vecstore") | |
| 410 (define_bypass 10 "power4-vecfloat" "power4-vecstore") |