Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/rs6000/predicates.md @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | 77e2b8dfacca |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 ;; Predicate definitions for POWER and PowerPC. |
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2 ;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010 |
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3 ;; Free Software Foundation, Inc. |
| 0 | 4 ;; |
| 5 ;; This file is part of GCC. | |
| 6 ;; | |
| 7 ;; GCC is free software; you can redistribute it and/or modify | |
| 8 ;; it under the terms of the GNU General Public License as published by | |
| 9 ;; the Free Software Foundation; either version 3, or (at your option) | |
| 10 ;; any later version. | |
| 11 ;; | |
| 12 ;; GCC is distributed in the hope that it will be useful, | |
| 13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 ;; GNU General Public License for more details. | |
| 16 ;; | |
| 17 ;; You should have received a copy of the GNU General Public License | |
| 18 ;; along with GCC; see the file COPYING3. If not see | |
| 19 ;; <http://www.gnu.org/licenses/>. | |
| 20 | |
| 21 ;; Return 1 for anything except PARALLEL. | |
| 22 (define_predicate "any_operand" | |
| 23 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")) | |
| 24 | |
| 25 ;; Return 1 for any PARALLEL. | |
| 26 (define_predicate "any_parallel_operand" | |
| 27 (match_code "parallel")) | |
| 28 | |
| 29 ;; Return 1 if op is COUNT register. | |
| 30 (define_predicate "count_register_operand" | |
| 31 (and (match_code "reg") | |
| 32 (match_test "REGNO (op) == CTR_REGNO | |
| 33 || REGNO (op) > LAST_VIRTUAL_REGISTER"))) | |
| 34 | |
| 35 ;; Return 1 if op is an Altivec register. | |
| 36 (define_predicate "altivec_register_operand" | |
| 37 (and (match_operand 0 "register_operand") | |
| 38 (match_test "GET_CODE (op) != REG | |
| 39 || ALTIVEC_REGNO_P (REGNO (op)) | |
| 40 || REGNO (op) > LAST_VIRTUAL_REGISTER"))) | |
| 41 | |
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42 ;; Return 1 if op is a VSX register. |
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43 (define_predicate "vsx_register_operand" |
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44 (and (match_operand 0 "register_operand") |
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45 (match_test "GET_CODE (op) != REG |
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46 || VSX_REGNO_P (REGNO (op)) |
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47 || REGNO (op) > LAST_VIRTUAL_REGISTER"))) |
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48 |
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49 ;; Return 1 if op is a vector register that operates on floating point vectors |
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50 ;; (either altivec or VSX). |
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51 (define_predicate "vfloat_operand" |
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52 (and (match_operand 0 "register_operand") |
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53 (match_test "GET_CODE (op) != REG |
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54 || VFLOAT_REGNO_P (REGNO (op)) |
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55 || REGNO (op) > LAST_VIRTUAL_REGISTER"))) |
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56 |
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57 ;; Return 1 if op is a vector register that operates on integer vectors |
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58 ;; (only altivec, VSX doesn't support integer vectors) |
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59 (define_predicate "vint_operand" |
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60 (and (match_operand 0 "register_operand") |
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61 (match_test "GET_CODE (op) != REG |
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62 || VINT_REGNO_P (REGNO (op)) |
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63 || REGNO (op) > LAST_VIRTUAL_REGISTER"))) |
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64 |
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65 ;; Return 1 if op is a vector register to do logical operations on (and, or, |
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66 ;; xor, etc.) |
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67 (define_predicate "vlogical_operand" |
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68 (and (match_operand 0 "register_operand") |
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69 (match_test "GET_CODE (op) != REG |
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70 || VLOGICAL_REGNO_P (REGNO (op)) |
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71 || REGNO (op) > LAST_VIRTUAL_REGISTER"))) |
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72 |
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73 ;; Return 1 if op is the carry register. |
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74 (define_predicate "ca_operand" |
| 0 | 75 (and (match_code "reg") |
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76 (match_test "CA_REGNO_P (REGNO (op))"))) |
| 0 | 77 |
| 78 ;; Return 1 if op is a signed 5-bit constant integer. | |
| 79 (define_predicate "s5bit_cint_operand" | |
| 80 (and (match_code "const_int") | |
| 81 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15"))) | |
| 82 | |
| 83 ;; Return 1 if op is a unsigned 5-bit constant integer. | |
| 84 (define_predicate "u5bit_cint_operand" | |
| 85 (and (match_code "const_int") | |
| 86 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31"))) | |
| 87 | |
| 88 ;; Return 1 if op is a signed 8-bit constant integer. | |
| 89 ;; Integer multiplication complete more quickly | |
| 90 (define_predicate "s8bit_cint_operand" | |
| 91 (and (match_code "const_int") | |
| 92 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127"))) | |
| 93 | |
| 94 ;; Return 1 if op is a constant integer that can fit in a D field. | |
| 95 (define_predicate "short_cint_operand" | |
| 96 (and (match_code "const_int") | |
| 97 (match_test "satisfies_constraint_I (op)"))) | |
| 98 | |
| 99 ;; Return 1 if op is a constant integer that can fit in an unsigned D field. | |
| 100 (define_predicate "u_short_cint_operand" | |
| 101 (and (match_code "const_int") | |
| 102 (match_test "satisfies_constraint_K (op)"))) | |
| 103 | |
| 104 ;; Return 1 if op is a constant integer that cannot fit in a signed D field. | |
| 105 (define_predicate "non_short_cint_operand" | |
| 106 (and (match_code "const_int") | |
| 107 (match_test "(unsigned HOST_WIDE_INT) | |
| 108 (INTVAL (op) + 0x8000) >= 0x10000"))) | |
| 109 | |
| 110 ;; Return 1 if op is a positive constant integer that is an exact power of 2. | |
| 111 (define_predicate "exact_log2_cint_operand" | |
| 112 (and (match_code "const_int") | |
| 113 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0"))) | |
| 114 | |
| 115 ;; Return 1 if op is a register that is not special. | |
| 116 (define_predicate "gpc_reg_operand" | |
| 117 (and (match_operand 0 "register_operand") | |
| 118 (match_test "(GET_CODE (op) != REG | |
| 119 || (REGNO (op) >= ARG_POINTER_REGNUM | |
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120 && !CA_REGNO_P (REGNO (op))) |
| 0 | 121 || REGNO (op) < MQ_REGNO) |
| 122 && !((TARGET_E500_DOUBLE || TARGET_SPE) | |
| 123 && invalid_e500_subreg (op, mode))"))) | |
| 124 | |
| 125 ;; Return 1 if op is a register that is a condition register field. | |
| 126 (define_predicate "cc_reg_operand" | |
| 127 (and (match_operand 0 "register_operand") | |
| 128 (match_test "GET_CODE (op) != REG | |
| 129 || REGNO (op) > LAST_VIRTUAL_REGISTER | |
| 130 || CR_REGNO_P (REGNO (op))"))) | |
| 131 | |
| 132 ;; Return 1 if op is a register that is a condition register field not cr0. | |
| 133 (define_predicate "cc_reg_not_cr0_operand" | |
| 134 (and (match_operand 0 "register_operand") | |
| 135 (match_test "GET_CODE (op) != REG | |
| 136 || REGNO (op) > LAST_VIRTUAL_REGISTER | |
| 137 || CR_REGNO_NOT_CR0_P (REGNO (op))"))) | |
| 138 | |
| 139 ;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0. | |
| 140 (define_predicate "cc_reg_not_micro_cr0_operand" | |
| 141 (and (match_operand 0 "register_operand") | |
| 142 (match_test "GET_CODE (op) != REG | |
| 143 || REGNO (op) > LAST_VIRTUAL_REGISTER | |
| 144 || (rs6000_gen_cell_microcode && CR_REGNO_NOT_CR0_P (REGNO (op))) | |
| 145 || (!rs6000_gen_cell_microcode && CR_REGNO_P (REGNO (op)))"))) | |
| 146 | |
| 147 ;; Return 1 if op is a constant integer valid for D field | |
| 148 ;; or non-special register register. | |
| 149 (define_predicate "reg_or_short_operand" | |
| 150 (if_then_else (match_code "const_int") | |
| 151 (match_operand 0 "short_cint_operand") | |
| 152 (match_operand 0 "gpc_reg_operand"))) | |
| 153 | |
| 154 ;; Return 1 if op is a constant integer valid whose negation is valid for | |
| 155 ;; D field or non-special register register. | |
| 156 ;; Do not allow a constant zero because all patterns that call this | |
| 157 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than | |
| 158 ;; or equal to const, which does not work for zero. | |
| 159 (define_predicate "reg_or_neg_short_operand" | |
| 160 (if_then_else (match_code "const_int") | |
| 161 (match_test "satisfies_constraint_P (op) | |
| 162 && INTVAL (op) != 0") | |
| 163 (match_operand 0 "gpc_reg_operand"))) | |
| 164 | |
| 165 ;; Return 1 if op is a constant integer valid for DS field | |
| 166 ;; or non-special register. | |
| 167 (define_predicate "reg_or_aligned_short_operand" | |
| 168 (if_then_else (match_code "const_int") | |
| 169 (and (match_operand 0 "short_cint_operand") | |
| 170 (match_test "!(INTVAL (op) & 3)")) | |
| 171 (match_operand 0 "gpc_reg_operand"))) | |
| 172 | |
| 173 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero | |
| 174 ;; or non-special register. | |
| 175 (define_predicate "reg_or_u_short_operand" | |
| 176 (if_then_else (match_code "const_int") | |
| 177 (match_operand 0 "u_short_cint_operand") | |
| 178 (match_operand 0 "gpc_reg_operand"))) | |
| 179 | |
| 180 ;; Return 1 if op is any constant integer | |
| 181 ;; or non-special register. | |
| 182 (define_predicate "reg_or_cint_operand" | |
| 183 (ior (match_code "const_int") | |
| 184 (match_operand 0 "gpc_reg_operand"))) | |
| 185 | |
| 186 ;; Return 1 if op is a constant integer valid for addition | |
| 187 ;; or non-special register. | |
| 188 (define_predicate "reg_or_add_cint_operand" | |
| 189 (if_then_else (match_code "const_int") | |
| 190 (match_test "(HOST_BITS_PER_WIDE_INT == 32 | |
| 191 && (mode == SImode || INTVAL (op) < 0x7fff8000)) | |
| 192 || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) | |
| 193 < (unsigned HOST_WIDE_INT) 0x100000000ll)") | |
| 194 (match_operand 0 "gpc_reg_operand"))) | |
| 195 | |
| 196 ;; Return 1 if op is a constant integer valid for subtraction | |
| 197 ;; or non-special register. | |
| 198 (define_predicate "reg_or_sub_cint_operand" | |
| 199 (if_then_else (match_code "const_int") | |
| 200 (match_test "(HOST_BITS_PER_WIDE_INT == 32 | |
| 201 && (mode == SImode || - INTVAL (op) < 0x7fff8000)) | |
| 202 || ((unsigned HOST_WIDE_INT) (- INTVAL (op) | |
| 203 + (mode == SImode | |
| 204 ? 0x80000000 : 0x80008000)) | |
| 205 < (unsigned HOST_WIDE_INT) 0x100000000ll)") | |
| 206 (match_operand 0 "gpc_reg_operand"))) | |
| 207 | |
| 208 ;; Return 1 if op is any 32-bit unsigned constant integer | |
| 209 ;; or non-special register. | |
| 210 (define_predicate "reg_or_logical_cint_operand" | |
| 211 (if_then_else (match_code "const_int") | |
| 212 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT | |
| 213 && INTVAL (op) >= 0) | |
| 214 || ((INTVAL (op) & GET_MODE_MASK (mode) | |
| 215 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)") | |
| 216 (if_then_else (match_code "const_double") | |
| 217 (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT | |
| 218 && mode == DImode | |
| 219 && CONST_DOUBLE_HIGH (op) == 0") | |
| 220 (match_operand 0 "gpc_reg_operand")))) | |
| 221 | |
| 222 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register | |
| 223 ;; with no more than one instruction per word. | |
| 224 (define_predicate "easy_fp_constant" | |
| 225 (match_code "const_double") | |
| 226 { | |
| 227 long k[4]; | |
| 228 REAL_VALUE_TYPE rv; | |
| 229 | |
| 230 if (GET_MODE (op) != mode | |
| 231 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode)) | |
| 232 return 0; | |
| 233 | |
| 234 /* Consider all constants with -msoft-float to be easy. */ | |
| 235 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE | |
| 236 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT))) | |
| 237 && mode != DImode) | |
| 238 return 1; | |
| 239 | |
| 240 if (DECIMAL_FLOAT_MODE_P (mode)) | |
| 241 return 0; | |
| 242 | |
| 243 /* If we are using V.4 style PIC, consider all constants to be hard. */ | |
| 244 if (flag_pic && DEFAULT_ABI == ABI_V4) | |
| 245 return 0; | |
| 246 | |
| 247 #ifdef TARGET_RELOCATABLE | |
| 248 /* Similarly if we are using -mrelocatable, consider all constants | |
| 249 to be hard. */ | |
| 250 if (TARGET_RELOCATABLE) | |
| 251 return 0; | |
| 252 #endif | |
| 253 | |
| 254 switch (mode) | |
| 255 { | |
| 256 case TFmode: | |
| 257 if (TARGET_E500_DOUBLE) | |
| 258 return 0; | |
| 259 | |
| 260 REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
| 261 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); | |
| 262 | |
| 263 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 | |
| 264 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1 | |
| 265 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1 | |
| 266 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1); | |
| 267 | |
| 268 case DFmode: | |
|
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269 /* The constant 0.f is easy under VSX. */ |
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270 if (op == CONST0_RTX (DFmode) && VECTOR_UNIT_VSX_P (DFmode)) |
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271 return 1; |
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272 |
| 0 | 273 /* Force constants to memory before reload to utilize |
| 274 compress_float_constant. | |
| 275 Avoid this when flag_unsafe_math_optimizations is enabled | |
| 276 because RDIV division to reciprocal optimization is not able | |
| 277 to regenerate the division. */ | |
| 278 if (TARGET_E500_DOUBLE | |
| 279 || (!reload_in_progress && !reload_completed | |
| 280 && !flag_unsafe_math_optimizations)) | |
| 281 return 0; | |
| 282 | |
| 283 REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
| 284 REAL_VALUE_TO_TARGET_DOUBLE (rv, k); | |
| 285 | |
| 286 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 | |
| 287 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1); | |
| 288 | |
| 289 case SFmode: | |
| 290 /* The constant 0.f is easy. */ | |
| 291 if (op == CONST0_RTX (SFmode)) | |
| 292 return 1; | |
| 293 | |
| 294 /* Force constants to memory before reload to utilize | |
| 295 compress_float_constant. | |
| 296 Avoid this when flag_unsafe_math_optimizations is enabled | |
| 297 because RDIV division to reciprocal optimization is not able | |
| 298 to regenerate the division. */ | |
| 299 if (!reload_in_progress && !reload_completed | |
| 300 && !flag_unsafe_math_optimizations) | |
| 301 return 0; | |
| 302 | |
| 303 REAL_VALUE_FROM_CONST_DOUBLE (rv, op); | |
| 304 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]); | |
| 305 | |
| 306 return num_insns_constant_wide (k[0]) == 1; | |
| 307 | |
| 308 case DImode: | |
| 309 return ((TARGET_POWERPC64 | |
| 310 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) | |
| 311 || (num_insns_constant (op, DImode) <= 2)); | |
| 312 | |
| 313 case SImode: | |
| 314 return 1; | |
| 315 | |
| 316 default: | |
| 317 gcc_unreachable (); | |
| 318 } | |
| 319 }) | |
| 320 | |
| 321 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a | |
| 322 ;; vector register without using memory. | |
| 323 (define_predicate "easy_vector_constant" | |
| 324 (match_code "const_vector") | |
| 325 { | |
| 326 /* As the paired vectors are actually FPRs it seems that there is | |
| 327 no easy way to load a CONST_VECTOR without using memory. */ | |
| 328 if (TARGET_PAIRED_FLOAT) | |
| 329 return false; | |
| 330 | |
|
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331 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)) |
| 0 | 332 { |
| 333 if (zero_constant (op, mode)) | |
|
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334 return true; |
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335 |
| 0 | 336 return easy_altivec_constant (op, mode); |
| 337 } | |
| 338 | |
| 339 if (SPE_VECTOR_MODE (mode)) | |
| 340 { | |
| 341 int cst, cst2; | |
| 342 if (zero_constant (op, mode)) | |
| 343 return true; | |
| 344 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) | |
| 345 return false; | |
| 346 | |
| 347 /* Limit SPE vectors to 15 bits signed. These we can generate with: | |
| 348 li r0, CONSTANT1 | |
| 349 evmergelo r0, r0, r0 | |
| 350 li r0, CONSTANT2 | |
| 351 | |
| 352 I don't know how efficient it would be to allow bigger constants, | |
| 353 considering we'll have an extra 'ori' for every 'li'. I doubt 5 | |
| 354 instructions is better than a 64-bit memory load, but I don't | |
| 355 have the e500 timing specs. */ | |
| 356 if (mode == V2SImode) | |
| 357 { | |
| 358 cst = INTVAL (CONST_VECTOR_ELT (op, 0)); | |
| 359 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1)); | |
| 360 return cst >= -0x7fff && cst <= 0x7fff | |
| 361 && cst2 >= -0x7fff && cst2 <= 0x7fff; | |
| 362 } | |
| 363 } | |
| 364 | |
| 365 return false; | |
| 366 }) | |
| 367 | |
| 368 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. | |
| 369 (define_predicate "easy_vector_constant_add_self" | |
| 370 (and (match_code "const_vector") | |
| 371 (and (match_test "TARGET_ALTIVEC") | |
| 372 (match_test "easy_altivec_constant (op, mode)"))) | |
| 373 { | |
|
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374 HOST_WIDE_INT val; |
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375 if (mode == V2DImode || mode == V2DFmode) |
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376 return 0; |
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377 val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1); |
| 0 | 378 val = ((val & 0xff) ^ 0x80) - 0x80; |
| 379 return EASY_VECTOR_15_ADD_SELF (val); | |
| 380 }) | |
| 381 | |
|
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382 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB. |
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383 (define_predicate "easy_vector_constant_msb" |
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384 (and (match_code "const_vector") |
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385 (and (match_test "TARGET_ALTIVEC") |
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386 (match_test "easy_altivec_constant (op, mode)"))) |
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387 { |
|
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388 HOST_WIDE_INT val; |
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389 if (mode == V2DImode || mode == V2DFmode) |
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390 return 0; |
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391 val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1); |
|
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392 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode)); |
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393 }) |
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394 |
| 0 | 395 ;; Return 1 if operand is constant zero (scalars and vectors). |
| 396 (define_predicate "zero_constant" | |
| 397 (and (match_code "const_int,const_double,const_vector") | |
| 398 (match_test "op == CONST0_RTX (mode)"))) | |
| 399 | |
| 400 ;; Return 1 if operand is 0.0. | |
| 401 ;; or non-special register register field no cr0 | |
| 402 (define_predicate "zero_fp_constant" | |
| 403 (and (match_code "const_double") | |
| 404 (match_test "SCALAR_FLOAT_MODE_P (mode) | |
| 405 && op == CONST0_RTX (mode)"))) | |
| 406 | |
| 407 ;; Return 1 if the operand is in volatile memory. Note that during the | |
| 408 ;; RTL generation phase, memory_operand does not return TRUE for volatile | |
| 409 ;; memory references. So this function allows us to recognize volatile | |
| 410 ;; references where it's safe. | |
| 411 (define_predicate "volatile_mem_operand" | |
| 412 (and (and (match_code "mem") | |
| 413 (match_test "MEM_VOLATILE_P (op)")) | |
| 414 (if_then_else (match_test "reload_completed") | |
| 415 (match_operand 0 "memory_operand") | |
| 416 (if_then_else (match_test "reload_in_progress") | |
| 417 (match_test "strict_memory_address_p (mode, XEXP (op, 0))") | |
| 418 (match_test "memory_address_p (mode, XEXP (op, 0))"))))) | |
| 419 | |
| 420 ;; Return 1 if the operand is an offsettable memory operand. | |
| 421 (define_predicate "offsettable_mem_operand" | |
| 422 (and (match_operand 0 "memory_operand") | |
|
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423 (match_test "offsettable_nonstrict_memref_p (op)"))) |
| 0 | 424 |
| 425 ;; Return 1 if the operand is a memory operand with an address divisible by 4 | |
| 426 (define_predicate "word_offset_memref_operand" | |
| 427 (match_operand 0 "memory_operand") | |
| 428 { | |
| 429 /* Address inside MEM. */ | |
| 430 op = XEXP (op, 0); | |
| 431 | |
| 432 /* Extract address from auto-inc/dec. */ | |
| 433 if (GET_CODE (op) == PRE_INC | |
| 434 || GET_CODE (op) == PRE_DEC) | |
| 435 op = XEXP (op, 0); | |
| 436 else if (GET_CODE (op) == PRE_MODIFY) | |
| 437 op = XEXP (op, 1); | |
| 438 | |
| 439 return (GET_CODE (op) != PLUS | |
| 440 || ! REG_P (XEXP (op, 0)) | |
| 441 || GET_CODE (XEXP (op, 1)) != CONST_INT | |
| 442 || INTVAL (XEXP (op, 1)) % 4 == 0); | |
| 443 }) | |
| 444 | |
| 445 ;; Return 1 if the operand is an indexed or indirect memory operand. | |
| 446 (define_predicate "indexed_or_indirect_operand" | |
| 447 (match_code "mem") | |
| 448 { | |
| 449 op = XEXP (op, 0); | |
|
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450 if (VECTOR_MEM_ALTIVEC_P (mode) |
| 0 | 451 && GET_CODE (op) == AND |
| 452 && GET_CODE (XEXP (op, 1)) == CONST_INT | |
| 453 && INTVAL (XEXP (op, 1)) == -16) | |
| 454 op = XEXP (op, 0); | |
| 455 | |
| 456 return indexed_or_indirect_address (op, mode); | |
| 457 }) | |
| 458 | |
|
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459 ;; Return 1 if the operand is an indexed or indirect memory operand with an |
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460 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads |
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461 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits, |
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462 ;; while VSX uses the full address and traps) |
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463 (define_predicate "altivec_indexed_or_indirect_operand" |
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464 (match_code "mem") |
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465 { |
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466 op = XEXP (op, 0); |
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467 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) |
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468 && GET_CODE (op) == AND |
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469 && GET_CODE (XEXP (op, 1)) == CONST_INT |
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470 && INTVAL (XEXP (op, 1)) == -16) |
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471 return indexed_or_indirect_address (XEXP (op, 0), mode); |
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472 |
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473 return 0; |
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474 }) |
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475 |
| 0 | 476 ;; Return 1 if the operand is an indexed or indirect address. |
| 477 (define_special_predicate "indexed_or_indirect_address" | |
| 478 (and (match_test "REG_P (op) | |
| 479 || (GET_CODE (op) == PLUS | |
| 480 /* Omit testing REG_P (XEXP (op, 0)). */ | |
| 481 && REG_P (XEXP (op, 1)))") | |
| 482 (match_operand 0 "address_operand"))) | |
| 483 | |
| 484 ;; Used for the destination of the fix_truncdfsi2 expander. | |
| 485 ;; If stfiwx will be used, the result goes to memory; otherwise, | |
| 486 ;; we're going to emit a store and a load of a subreg, so the dest is a | |
| 487 ;; register. | |
| 488 (define_predicate "fix_trunc_dest_operand" | |
| 489 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT") | |
| 490 (match_operand 0 "memory_operand") | |
| 491 (match_operand 0 "gpc_reg_operand"))) | |
| 492 | |
| 493 ;; Return 1 if the operand is either a non-special register or can be used | |
| 494 ;; as the operand of a `mode' add insn. | |
| 495 (define_predicate "add_operand" | |
| 496 (if_then_else (match_code "const_int") | |
| 497 (match_test "satisfies_constraint_I (op) | |
| 498 || satisfies_constraint_L (op)") | |
| 499 (match_operand 0 "gpc_reg_operand"))) | |
| 500 | |
| 501 ;; Return 1 if OP is a constant but not a valid add_operand. | |
| 502 (define_predicate "non_add_cint_operand" | |
| 503 (and (match_code "const_int") | |
| 504 (match_test "!satisfies_constraint_I (op) | |
| 505 && !satisfies_constraint_L (op)"))) | |
| 506 | |
| 507 ;; Return 1 if the operand is a constant that can be used as the operand | |
| 508 ;; of an OR or XOR. | |
| 509 (define_predicate "logical_const_operand" | |
| 510 (match_code "const_int,const_double") | |
| 511 { | |
| 512 HOST_WIDE_INT opl, oph; | |
| 513 | |
| 514 if (GET_CODE (op) == CONST_INT) | |
| 515 { | |
| 516 opl = INTVAL (op) & GET_MODE_MASK (mode); | |
| 517 | |
| 518 if (HOST_BITS_PER_WIDE_INT <= 32 | |
| 519 && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) | |
| 520 return 0; | |
| 521 } | |
| 522 else if (GET_CODE (op) == CONST_DOUBLE) | |
| 523 { | |
| 524 gcc_assert (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT); | |
| 525 | |
| 526 opl = CONST_DOUBLE_LOW (op); | |
| 527 oph = CONST_DOUBLE_HIGH (op); | |
| 528 if (oph != 0) | |
| 529 return 0; | |
| 530 } | |
| 531 else | |
| 532 return 0; | |
| 533 | |
| 534 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 | |
| 535 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); | |
| 536 }) | |
| 537 | |
| 538 ;; Return 1 if the operand is a non-special register or a constant that | |
| 539 ;; can be used as the operand of an OR or XOR. | |
| 540 (define_predicate "logical_operand" | |
| 541 (ior (match_operand 0 "gpc_reg_operand") | |
| 542 (match_operand 0 "logical_const_operand"))) | |
| 543 | |
| 544 ;; Return 1 if op is a constant that is not a logical operand, but could | |
| 545 ;; be split into one. | |
| 546 (define_predicate "non_logical_cint_operand" | |
| 547 (and (match_code "const_int,const_double") | |
| 548 (and (not (match_operand 0 "logical_operand")) | |
| 549 (match_operand 0 "reg_or_logical_cint_operand")))) | |
| 550 | |
| 551 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask, | |
| 552 ;; suitable for use with rlwinm (no more than two 1->0 or 0->1 | |
| 553 ;; transitions). Reject all ones and all zeros, since these should have | |
| 554 ;; been optimized away and confuse the making of MB and ME. | |
| 555 (define_predicate "mask_operand" | |
| 556 (match_code "const_int") | |
| 557 { | |
| 558 HOST_WIDE_INT c, lsb; | |
| 559 | |
| 560 c = INTVAL (op); | |
| 561 | |
| 562 if (TARGET_POWERPC64) | |
| 563 { | |
| 564 /* Fail if the mask is not 32-bit. */ | |
| 565 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0) | |
| 566 return 0; | |
| 567 | |
| 568 /* Fail if the mask wraps around because the upper 32-bits of the | |
| 569 mask will all be 1s, contrary to GCC's internal view. */ | |
| 570 if ((c & 0x80000001) == 0x80000001) | |
| 571 return 0; | |
| 572 } | |
| 573 | |
| 574 /* We don't change the number of transitions by inverting, | |
| 575 so make sure we start with the LS bit zero. */ | |
| 576 if (c & 1) | |
| 577 c = ~c; | |
| 578 | |
| 579 /* Reject all zeros or all ones. */ | |
| 580 if (c == 0) | |
| 581 return 0; | |
| 582 | |
| 583 /* Find the first transition. */ | |
| 584 lsb = c & -c; | |
| 585 | |
| 586 /* Invert to look for a second transition. */ | |
| 587 c = ~c; | |
| 588 | |
| 589 /* Erase first transition. */ | |
| 590 c &= -lsb; | |
| 591 | |
| 592 /* Find the second transition (if any). */ | |
| 593 lsb = c & -c; | |
| 594 | |
| 595 /* Match if all the bits above are 1's (or c is zero). */ | |
| 596 return c == -lsb; | |
| 597 }) | |
| 598 | |
| 599 ;; Return 1 for the PowerPC64 rlwinm corner case. | |
| 600 (define_predicate "mask_operand_wrap" | |
| 601 (match_code "const_int") | |
| 602 { | |
| 603 HOST_WIDE_INT c, lsb; | |
| 604 | |
| 605 c = INTVAL (op); | |
| 606 | |
| 607 if ((c & 0x80000001) != 0x80000001) | |
| 608 return 0; | |
| 609 | |
| 610 c = ~c; | |
| 611 if (c == 0) | |
| 612 return 0; | |
| 613 | |
| 614 lsb = c & -c; | |
| 615 c = ~c; | |
| 616 c &= -lsb; | |
| 617 lsb = c & -c; | |
| 618 return c == -lsb; | |
| 619 }) | |
| 620 | |
| 621 ;; Return 1 if the operand is a constant that is a PowerPC64 mask | |
| 622 ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1 | |
| 623 ;; transition). Reject all zeros, since zero should have been | |
| 624 ;; optimized away and confuses the making of MB and ME. | |
| 625 (define_predicate "mask64_operand" | |
| 626 (match_code "const_int") | |
| 627 { | |
| 628 HOST_WIDE_INT c, lsb; | |
| 629 | |
| 630 c = INTVAL (op); | |
| 631 | |
| 632 /* Reject all zeros. */ | |
| 633 if (c == 0) | |
| 634 return 0; | |
| 635 | |
| 636 /* We don't change the number of transitions by inverting, | |
| 637 so make sure we start with the LS bit zero. */ | |
| 638 if (c & 1) | |
| 639 c = ~c; | |
| 640 | |
| 641 /* Find the first transition. */ | |
| 642 lsb = c & -c; | |
| 643 | |
| 644 /* Match if all the bits above are 1's (or c is zero). */ | |
| 645 return c == -lsb; | |
| 646 }) | |
| 647 | |
| 648 ;; Like mask64_operand, but allow up to three transitions. This | |
| 649 ;; predicate is used by insn patterns that generate two rldicl or | |
| 650 ;; rldicr machine insns. | |
| 651 (define_predicate "mask64_2_operand" | |
| 652 (match_code "const_int") | |
| 653 { | |
| 654 HOST_WIDE_INT c, lsb; | |
| 655 | |
| 656 c = INTVAL (op); | |
| 657 | |
| 658 /* Disallow all zeros. */ | |
| 659 if (c == 0) | |
| 660 return 0; | |
| 661 | |
| 662 /* We don't change the number of transitions by inverting, | |
| 663 so make sure we start with the LS bit zero. */ | |
| 664 if (c & 1) | |
| 665 c = ~c; | |
| 666 | |
| 667 /* Find the first transition. */ | |
| 668 lsb = c & -c; | |
| 669 | |
| 670 /* Invert to look for a second transition. */ | |
| 671 c = ~c; | |
| 672 | |
| 673 /* Erase first transition. */ | |
| 674 c &= -lsb; | |
| 675 | |
| 676 /* Find the second transition. */ | |
| 677 lsb = c & -c; | |
| 678 | |
| 679 /* Invert to look for a third transition. */ | |
| 680 c = ~c; | |
| 681 | |
| 682 /* Erase second transition. */ | |
| 683 c &= -lsb; | |
| 684 | |
| 685 /* Find the third transition (if any). */ | |
| 686 lsb = c & -c; | |
| 687 | |
| 688 /* Match if all the bits above are 1's (or c is zero). */ | |
| 689 return c == -lsb; | |
| 690 }) | |
| 691 | |
| 692 ;; Like and_operand, but also match constants that can be implemented | |
| 693 ;; with two rldicl or rldicr insns. | |
| 694 (define_predicate "and64_2_operand" | |
| 695 (ior (match_operand 0 "mask64_2_operand") | |
| 696 (if_then_else (match_test "fixed_regs[CR0_REGNO]") | |
| 697 (match_operand 0 "gpc_reg_operand") | |
| 698 (match_operand 0 "logical_operand")))) | |
| 699 | |
| 700 ;; Return 1 if the operand is either a non-special register or a | |
| 701 ;; constant that can be used as the operand of a logical AND. | |
| 702 (define_predicate "and_operand" | |
| 703 (ior (match_operand 0 "mask_operand") | |
| 704 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode") | |
| 705 (match_operand 0 "mask64_operand")) | |
| 706 (if_then_else (match_test "fixed_regs[CR0_REGNO]") | |
| 707 (match_operand 0 "gpc_reg_operand") | |
| 708 (match_operand 0 "logical_operand"))))) | |
| 709 | |
| 710 ;; Return 1 if the operand is either a logical operand or a short cint operand. | |
| 711 (define_predicate "scc_eq_operand" | |
| 712 (ior (match_operand 0 "logical_operand") | |
| 713 (match_operand 0 "short_cint_operand"))) | |
| 714 | |
| 715 ;; Return 1 if the operand is a general non-special register or memory operand. | |
| 716 (define_predicate "reg_or_mem_operand" | |
| 717 (ior (match_operand 0 "memory_operand") | |
| 718 (ior (and (match_code "mem") | |
| 719 (match_test "macho_lo_sum_memory_operand (op, mode)")) | |
| 720 (ior (match_operand 0 "volatile_mem_operand") | |
| 721 (match_operand 0 "gpc_reg_operand"))))) | |
| 722 | |
| 723 ;; Return 1 if the operand is either an easy FP constant or memory or reg. | |
| 724 (define_predicate "reg_or_none500mem_operand" | |
| 725 (if_then_else (match_code "mem") | |
| 726 (and (match_test "!TARGET_E500_DOUBLE") | |
| 727 (ior (match_operand 0 "memory_operand") | |
| 728 (ior (match_test "macho_lo_sum_memory_operand (op, mode)") | |
| 729 (match_operand 0 "volatile_mem_operand")))) | |
| 730 (match_operand 0 "gpc_reg_operand"))) | |
| 731 | |
| 732 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand. | |
| 733 (define_predicate "zero_reg_mem_operand" | |
| 734 (ior (match_operand 0 "zero_fp_constant") | |
| 735 (match_operand 0 "reg_or_mem_operand"))) | |
| 736 | |
| 737 ;; Return 1 if the operand is a general register or memory operand without | |
| 738 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC | |
| 739 ;; lwa instruction. | |
| 740 (define_predicate "lwa_operand" | |
| 741 (match_code "reg,subreg,mem") | |
| 742 { | |
|
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743 rtx inner, addr, offset; |
| 0 | 744 |
|
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745 inner = op; |
| 0 | 746 if (reload_completed && GET_CODE (inner) == SUBREG) |
| 747 inner = SUBREG_REG (inner); | |
| 748 | |
|
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749 if (gpc_reg_operand (inner, mode)) |
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750 return true; |
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751 if (!memory_operand (inner, mode)) |
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752 return false; |
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753 addr = XEXP (inner, 0); |
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754 if (GET_CODE (addr) == PRE_INC |
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755 || GET_CODE (addr) == PRE_DEC |
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756 || (GET_CODE (addr) == PRE_MODIFY |
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757 && !legitimate_indexed_address_p (XEXP (addr, 1), 0))) |
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758 return false; |
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759 if (GET_CODE (addr) == LO_SUM |
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760 && GET_CODE (XEXP (addr, 0)) == REG |
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761 && GET_CODE (XEXP (addr, 1)) == CONST) |
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762 addr = XEXP (XEXP (addr, 1), 0); |
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763 if (GET_CODE (addr) != PLUS) |
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764 return true; |
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765 offset = XEXP (addr, 1); |
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766 if (GET_CODE (offset) != CONST_INT) |
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767 return true; |
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768 return INTVAL (offset) % 4 == 0; |
| 0 | 769 }) |
| 770 | |
| 771 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. | |
| 772 (define_predicate "symbol_ref_operand" | |
| 773 (and (match_code "symbol_ref") | |
| 774 (match_test "(mode == VOIDmode || GET_MODE (op) == mode) | |
| 775 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))"))) | |
| 776 | |
| 777 ;; Return 1 if op is an operand that can be loaded via the GOT. | |
| 778 ;; or non-special register register field no cr0 | |
| 779 (define_predicate "got_operand" | |
| 780 (match_code "symbol_ref,const,label_ref")) | |
| 781 | |
| 782 ;; Return 1 if op is a simple reference that can be loaded via the GOT, | |
| 783 ;; excluding labels involving addition. | |
| 784 (define_predicate "got_no_const_operand" | |
| 785 (match_code "symbol_ref,label_ref")) | |
| 786 | |
| 787 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol. | |
| 788 (define_predicate "rs6000_tls_symbol_ref" | |
| 789 (and (match_code "symbol_ref") | |
| 790 (match_test "RS6000_SYMBOL_REF_TLS_P (op)"))) | |
| 791 | |
| 792 ;; Return 1 if the operand, used inside a MEM, is a valid first argument | |
| 793 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. | |
| 794 (define_predicate "call_operand" | |
| 795 (if_then_else (match_code "reg") | |
| 796 (match_test "REGNO (op) == LR_REGNO | |
| 797 || REGNO (op) == CTR_REGNO | |
| 798 || REGNO (op) >= FIRST_PSEUDO_REGISTER") | |
| 799 (match_code "symbol_ref"))) | |
| 800 | |
| 801 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in | |
| 802 ;; this file. | |
| 803 (define_predicate "current_file_function_operand" | |
| 804 (and (match_code "symbol_ref") | |
| 805 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) | |
| 806 && ((SYMBOL_REF_LOCAL_P (op) | |
| 807 && (DEFAULT_ABI != ABI_AIX | |
| 808 || !SYMBOL_REF_EXTERNAL_P (op))) | |
| 809 || (op == XEXP (DECL_RTL (current_function_decl), | |
| 810 0)))"))) | |
| 811 | |
| 812 ;; Return 1 if this operand is a valid input for a move insn. | |
| 813 (define_predicate "input_operand" | |
| 814 (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem, | |
| 815 const_double,const_vector,const_int,plus") | |
| 816 { | |
| 817 /* Memory is always valid. */ | |
| 818 if (memory_operand (op, mode)) | |
| 819 return 1; | |
| 820 | |
| 821 /* For floating-point, easy constants are valid. */ | |
| 822 if (SCALAR_FLOAT_MODE_P (mode) | |
| 823 && CONSTANT_P (op) | |
| 824 && easy_fp_constant (op, mode)) | |
| 825 return 1; | |
| 826 | |
| 827 /* Allow any integer constant. */ | |
| 828 if (GET_MODE_CLASS (mode) == MODE_INT | |
| 829 && (GET_CODE (op) == CONST_INT | |
| 830 || GET_CODE (op) == CONST_DOUBLE)) | |
| 831 return 1; | |
| 832 | |
| 833 /* Allow easy vector constants. */ | |
| 834 if (GET_CODE (op) == CONST_VECTOR | |
| 835 && easy_vector_constant (op, mode)) | |
| 836 return 1; | |
| 837 | |
| 838 /* Do not allow invalid E500 subregs. */ | |
| 839 if ((TARGET_E500_DOUBLE || TARGET_SPE) | |
| 840 && GET_CODE (op) == SUBREG | |
| 841 && invalid_e500_subreg (op, mode)) | |
| 842 return 0; | |
| 843 | |
| 844 /* For floating-point or multi-word mode, the only remaining valid type | |
| 845 is a register. */ | |
| 846 if (SCALAR_FLOAT_MODE_P (mode) | |
| 847 || GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
| 848 return register_operand (op, mode); | |
| 849 | |
| 850 /* The only cases left are integral modes one word or smaller (we | |
| 851 do not get called for MODE_CC values). These can be in any | |
| 852 register. */ | |
| 853 if (register_operand (op, mode)) | |
| 854 return 1; | |
| 855 | |
| 856 /* A SYMBOL_REF referring to the TOC is valid. */ | |
|
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857 if (legitimate_constant_pool_address_p (op, mode, false)) |
| 0 | 858 return 1; |
| 859 | |
| 860 /* A constant pool expression (relative to the TOC) is valid */ | |
| 861 if (toc_relative_expr_p (op)) | |
| 862 return 1; | |
| 863 | |
| 864 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region | |
| 865 to be valid. */ | |
| 866 if (DEFAULT_ABI == ABI_V4 | |
| 867 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST) | |
| 868 && small_data_operand (op, Pmode)) | |
| 869 return 1; | |
| 870 | |
| 871 return 0; | |
| 872 }) | |
| 873 | |
| 874 ;; Return true if OP is an invalid SUBREG operation on the e500. | |
| 875 (define_predicate "rs6000_nonimmediate_operand" | |
| 876 (match_code "reg,subreg,mem") | |
| 877 { | |
| 878 if ((TARGET_E500_DOUBLE || TARGET_SPE) | |
| 879 && GET_CODE (op) == SUBREG | |
| 880 && invalid_e500_subreg (op, mode)) | |
| 881 return 0; | |
| 882 | |
| 883 return nonimmediate_operand (op, mode); | |
| 884 }) | |
| 885 | |
| 886 ;; Return true if operand is boolean operator. | |
| 887 (define_predicate "boolean_operator" | |
| 888 (match_code "and,ior,xor")) | |
| 889 | |
| 890 ;; Return true if operand is OR-form of boolean operator. | |
| 891 (define_predicate "boolean_or_operator" | |
| 892 (match_code "ior,xor")) | |
| 893 | |
| 894 ;; Return true if operand is an equality operator. | |
| 895 (define_special_predicate "equality_operator" | |
| 896 (match_code "eq,ne")) | |
| 897 | |
| 898 ;; Return true if operand is MIN or MAX operator. | |
| 899 (define_predicate "min_max_operator" | |
| 900 (match_code "smin,smax,umin,umax")) | |
| 901 | |
| 902 ;; Return 1 if OP is a comparison operation that is valid for a branch | |
| 903 ;; instruction. We check the opcode against the mode of the CC value. | |
| 904 ;; validate_condition_mode is an assertion. | |
| 905 (define_predicate "branch_comparison_operator" | |
| 906 (and (match_operand 0 "comparison_operator") | |
| 907 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC") | |
| 908 (match_test "validate_condition_mode (GET_CODE (op), | |
| 909 GET_MODE (XEXP (op, 0))), | |
| 910 1")))) | |
| 911 | |
|
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912 (define_predicate "rs6000_cbranch_operator" |
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913 (if_then_else (match_test "TARGET_HARD_FLOAT && !TARGET_FPRS") |
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914 (match_operand 0 "ordered_comparison_operator") |
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915 (match_operand 0 "comparison_operator"))) |
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916 |
| 0 | 917 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn -- |
| 918 ;; it must be a positive comparison. | |
| 919 (define_predicate "scc_comparison_operator" | |
| 920 (and (match_operand 0 "branch_comparison_operator") | |
| 921 (match_code "eq,lt,gt,ltu,gtu,unordered"))) | |
| 922 | |
|
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923 ;; Return 1 if OP is a comparison operation whose inverse would be valid for |
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924 ;; an SCC insn. |
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925 (define_predicate "scc_rev_comparison_operator" |
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926 (and (match_operand 0 "branch_comparison_operator") |
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927 (match_code "ne,le,ge,leu,geu,ordered"))) |
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928 |
| 0 | 929 ;; Return 1 if OP is a comparison operation that is valid for a branch |
| 930 ;; insn, which is true if the corresponding bit in the CC register is set. | |
| 931 (define_predicate "branch_positive_comparison_operator" | |
| 932 (and (match_operand 0 "branch_comparison_operator") | |
| 933 (match_code "eq,lt,gt,ltu,gtu,unordered"))) | |
| 934 | |
| 935 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL. | |
| 936 (define_predicate "load_multiple_operation" | |
| 937 (match_code "parallel") | |
| 938 { | |
| 939 int count = XVECLEN (op, 0); | |
| 940 unsigned int dest_regno; | |
| 941 rtx src_addr; | |
| 942 int i; | |
| 943 | |
| 944 /* Perform a quick check so we don't blow up below. */ | |
| 945 if (count <= 1 | |
| 946 || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
| 947 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
| 948 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
| 949 return 0; | |
| 950 | |
| 951 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
| 952 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
| 953 | |
| 954 for (i = 1; i < count; i++) | |
| 955 { | |
| 956 rtx elt = XVECEXP (op, 0, i); | |
| 957 | |
| 958 if (GET_CODE (elt) != SET | |
| 959 || GET_CODE (SET_DEST (elt)) != REG | |
| 960 || GET_MODE (SET_DEST (elt)) != SImode | |
| 961 || REGNO (SET_DEST (elt)) != dest_regno + i | |
| 962 || GET_CODE (SET_SRC (elt)) != MEM | |
| 963 || GET_MODE (SET_SRC (elt)) != SImode | |
| 964 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
| 965 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) | |
| 966 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT | |
| 967 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4) | |
| 968 return 0; | |
| 969 } | |
| 970 | |
| 971 return 1; | |
| 972 }) | |
| 973 | |
| 974 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL. | |
| 975 ;; The second vector element is a CLOBBER. | |
| 976 (define_predicate "store_multiple_operation" | |
| 977 (match_code "parallel") | |
| 978 { | |
| 979 int count = XVECLEN (op, 0) - 1; | |
| 980 unsigned int src_regno; | |
| 981 rtx dest_addr; | |
| 982 int i; | |
| 983 | |
| 984 /* Perform a quick check so we don't blow up below. */ | |
| 985 if (count <= 1 | |
| 986 || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
| 987 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
| 988 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
| 989 return 0; | |
| 990 | |
| 991 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
| 992 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
| 993 | |
| 994 for (i = 1; i < count; i++) | |
| 995 { | |
| 996 rtx elt = XVECEXP (op, 0, i + 1); | |
| 997 | |
| 998 if (GET_CODE (elt) != SET | |
| 999 || GET_CODE (SET_SRC (elt)) != REG | |
| 1000 || GET_MODE (SET_SRC (elt)) != SImode | |
| 1001 || REGNO (SET_SRC (elt)) != src_regno + i | |
| 1002 || GET_CODE (SET_DEST (elt)) != MEM | |
| 1003 || GET_MODE (SET_DEST (elt)) != SImode | |
| 1004 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
| 1005 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) | |
| 1006 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT | |
| 1007 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4) | |
| 1008 return 0; | |
| 1009 } | |
| 1010 | |
| 1011 return 1; | |
| 1012 }) | |
| 1013 | |
| 1014 ;; Return 1 if OP is valid for a save_world call in prologue, known to be | |
| 1015 ;; a PARLLEL. | |
| 1016 (define_predicate "save_world_operation" | |
| 1017 (match_code "parallel") | |
| 1018 { | |
| 1019 int index; | |
| 1020 int i; | |
| 1021 rtx elt; | |
| 1022 int count = XVECLEN (op, 0); | |
| 1023 | |
| 1024 if (count != 54) | |
| 1025 return 0; | |
| 1026 | |
| 1027 index = 0; | |
| 1028 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
| 1029 || GET_CODE (XVECEXP (op, 0, index++)) != USE) | |
| 1030 return 0; | |
| 1031 | |
| 1032 for (i=1; i <= 18; i++) | |
| 1033 { | |
| 1034 elt = XVECEXP (op, 0, index++); | |
| 1035 if (GET_CODE (elt) != SET | |
| 1036 || GET_CODE (SET_DEST (elt)) != MEM | |
| 1037 || ! memory_operand (SET_DEST (elt), DFmode) | |
| 1038 || GET_CODE (SET_SRC (elt)) != REG | |
| 1039 || GET_MODE (SET_SRC (elt)) != DFmode) | |
| 1040 return 0; | |
| 1041 } | |
| 1042 | |
| 1043 for (i=1; i <= 12; i++) | |
| 1044 { | |
| 1045 elt = XVECEXP (op, 0, index++); | |
| 1046 if (GET_CODE (elt) != SET | |
| 1047 || GET_CODE (SET_DEST (elt)) != MEM | |
| 1048 || GET_CODE (SET_SRC (elt)) != REG | |
| 1049 || GET_MODE (SET_SRC (elt)) != V4SImode) | |
| 1050 return 0; | |
| 1051 } | |
| 1052 | |
| 1053 for (i=1; i <= 19; i++) | |
| 1054 { | |
| 1055 elt = XVECEXP (op, 0, index++); | |
| 1056 if (GET_CODE (elt) != SET | |
| 1057 || GET_CODE (SET_DEST (elt)) != MEM | |
| 1058 || ! memory_operand (SET_DEST (elt), Pmode) | |
| 1059 || GET_CODE (SET_SRC (elt)) != REG | |
| 1060 || GET_MODE (SET_SRC (elt)) != Pmode) | |
| 1061 return 0; | |
| 1062 } | |
| 1063 | |
| 1064 elt = XVECEXP (op, 0, index++); | |
| 1065 if (GET_CODE (elt) != SET | |
| 1066 || GET_CODE (SET_DEST (elt)) != MEM | |
| 1067 || ! memory_operand (SET_DEST (elt), Pmode) | |
| 1068 || GET_CODE (SET_SRC (elt)) != REG | |
| 1069 || REGNO (SET_SRC (elt)) != CR2_REGNO | |
| 1070 || GET_MODE (SET_SRC (elt)) != Pmode) | |
| 1071 return 0; | |
| 1072 | |
| 1073 if (GET_CODE (XVECEXP (op, 0, index++)) != SET | |
| 1074 || GET_CODE (XVECEXP (op, 0, index++)) != SET) | |
| 1075 return 0; | |
| 1076 return 1; | |
| 1077 }) | |
| 1078 | |
| 1079 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be | |
| 1080 ;; a PARLLEL. | |
| 1081 (define_predicate "restore_world_operation" | |
| 1082 (match_code "parallel") | |
| 1083 { | |
| 1084 int index; | |
| 1085 int i; | |
| 1086 rtx elt; | |
| 1087 int count = XVECLEN (op, 0); | |
| 1088 | |
| 1089 if (count != 59) | |
| 1090 return 0; | |
| 1091 | |
| 1092 index = 0; | |
| 1093 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN | |
| 1094 || GET_CODE (XVECEXP (op, 0, index++)) != USE | |
| 1095 || GET_CODE (XVECEXP (op, 0, index++)) != USE | |
| 1096 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER) | |
| 1097 return 0; | |
| 1098 | |
| 1099 elt = XVECEXP (op, 0, index++); | |
| 1100 if (GET_CODE (elt) != SET | |
| 1101 || GET_CODE (SET_SRC (elt)) != MEM | |
| 1102 || ! memory_operand (SET_SRC (elt), Pmode) | |
| 1103 || GET_CODE (SET_DEST (elt)) != REG | |
| 1104 || REGNO (SET_DEST (elt)) != CR2_REGNO | |
| 1105 || GET_MODE (SET_DEST (elt)) != Pmode) | |
| 1106 return 0; | |
| 1107 | |
| 1108 for (i=1; i <= 19; i++) | |
| 1109 { | |
| 1110 elt = XVECEXP (op, 0, index++); | |
| 1111 if (GET_CODE (elt) != SET | |
| 1112 || GET_CODE (SET_SRC (elt)) != MEM | |
| 1113 || ! memory_operand (SET_SRC (elt), Pmode) | |
| 1114 || GET_CODE (SET_DEST (elt)) != REG | |
| 1115 || GET_MODE (SET_DEST (elt)) != Pmode) | |
| 1116 return 0; | |
| 1117 } | |
| 1118 | |
| 1119 for (i=1; i <= 12; i++) | |
| 1120 { | |
| 1121 elt = XVECEXP (op, 0, index++); | |
| 1122 if (GET_CODE (elt) != SET | |
| 1123 || GET_CODE (SET_SRC (elt)) != MEM | |
| 1124 || GET_CODE (SET_DEST (elt)) != REG | |
| 1125 || GET_MODE (SET_DEST (elt)) != V4SImode) | |
| 1126 return 0; | |
| 1127 } | |
| 1128 | |
| 1129 for (i=1; i <= 18; i++) | |
| 1130 { | |
| 1131 elt = XVECEXP (op, 0, index++); | |
| 1132 if (GET_CODE (elt) != SET | |
| 1133 || GET_CODE (SET_SRC (elt)) != MEM | |
| 1134 || ! memory_operand (SET_SRC (elt), DFmode) | |
| 1135 || GET_CODE (SET_DEST (elt)) != REG | |
| 1136 || GET_MODE (SET_DEST (elt)) != DFmode) | |
| 1137 return 0; | |
| 1138 } | |
| 1139 | |
| 1140 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
| 1141 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
| 1142 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
| 1143 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER | |
| 1144 || GET_CODE (XVECEXP (op, 0, index++)) != USE) | |
| 1145 return 0; | |
| 1146 return 1; | |
| 1147 }) | |
| 1148 | |
| 1149 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL. | |
| 1150 (define_predicate "vrsave_operation" | |
| 1151 (match_code "parallel") | |
| 1152 { | |
| 1153 int count = XVECLEN (op, 0); | |
| 1154 unsigned int dest_regno, src_regno; | |
| 1155 int i; | |
| 1156 | |
| 1157 if (count <= 1 | |
| 1158 || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
| 1159 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
| 1160 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE | |
| 1161 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE) | |
| 1162 return 0; | |
| 1163 | |
| 1164 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
| 1165 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1)); | |
| 1166 | |
| 1167 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO) | |
| 1168 return 0; | |
| 1169 | |
| 1170 for (i = 1; i < count; i++) | |
| 1171 { | |
| 1172 rtx elt = XVECEXP (op, 0, i); | |
| 1173 | |
| 1174 if (GET_CODE (elt) != CLOBBER | |
| 1175 && GET_CODE (elt) != SET) | |
| 1176 return 0; | |
| 1177 } | |
| 1178 | |
| 1179 return 1; | |
| 1180 }) | |
| 1181 | |
| 1182 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL. | |
| 1183 (define_predicate "mfcr_operation" | |
| 1184 (match_code "parallel") | |
| 1185 { | |
| 1186 int count = XVECLEN (op, 0); | |
| 1187 int i; | |
| 1188 | |
| 1189 /* Perform a quick check so we don't blow up below. */ | |
| 1190 if (count < 1 | |
| 1191 || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
| 1192 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
| 1193 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
| 1194 return 0; | |
| 1195 | |
| 1196 for (i = 0; i < count; i++) | |
| 1197 { | |
| 1198 rtx exp = XVECEXP (op, 0, i); | |
| 1199 rtx unspec; | |
| 1200 int maskval; | |
| 1201 rtx src_reg; | |
| 1202 | |
| 1203 src_reg = XVECEXP (SET_SRC (exp), 0, 0); | |
| 1204 | |
| 1205 if (GET_CODE (src_reg) != REG | |
| 1206 || GET_MODE (src_reg) != CCmode | |
| 1207 || ! CR_REGNO_P (REGNO (src_reg))) | |
| 1208 return 0; | |
| 1209 | |
| 1210 if (GET_CODE (exp) != SET | |
| 1211 || GET_CODE (SET_DEST (exp)) != REG | |
| 1212 || GET_MODE (SET_DEST (exp)) != SImode | |
| 1213 || ! INT_REGNO_P (REGNO (SET_DEST (exp)))) | |
| 1214 return 0; | |
| 1215 unspec = SET_SRC (exp); | |
| 1216 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg)); | |
| 1217 | |
| 1218 if (GET_CODE (unspec) != UNSPEC | |
| 1219 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR | |
| 1220 || XVECLEN (unspec, 0) != 2 | |
| 1221 || XVECEXP (unspec, 0, 0) != src_reg | |
| 1222 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
| 1223 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
| 1224 return 0; | |
| 1225 } | |
| 1226 return 1; | |
| 1227 }) | |
| 1228 | |
| 1229 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL. | |
| 1230 (define_predicate "mtcrf_operation" | |
| 1231 (match_code "parallel") | |
| 1232 { | |
| 1233 int count = XVECLEN (op, 0); | |
| 1234 int i; | |
| 1235 rtx src_reg; | |
| 1236 | |
| 1237 /* Perform a quick check so we don't blow up below. */ | |
| 1238 if (count < 1 | |
| 1239 || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
| 1240 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC | |
| 1241 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2) | |
| 1242 return 0; | |
| 1243 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0); | |
| 1244 | |
| 1245 if (GET_CODE (src_reg) != REG | |
| 1246 || GET_MODE (src_reg) != SImode | |
| 1247 || ! INT_REGNO_P (REGNO (src_reg))) | |
| 1248 return 0; | |
| 1249 | |
| 1250 for (i = 0; i < count; i++) | |
| 1251 { | |
| 1252 rtx exp = XVECEXP (op, 0, i); | |
| 1253 rtx unspec; | |
| 1254 int maskval; | |
| 1255 | |
| 1256 if (GET_CODE (exp) != SET | |
| 1257 || GET_CODE (SET_DEST (exp)) != REG | |
| 1258 || GET_MODE (SET_DEST (exp)) != CCmode | |
| 1259 || ! CR_REGNO_P (REGNO (SET_DEST (exp)))) | |
| 1260 return 0; | |
| 1261 unspec = SET_SRC (exp); | |
| 1262 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp))); | |
| 1263 | |
| 1264 if (GET_CODE (unspec) != UNSPEC | |
| 1265 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR | |
| 1266 || XVECLEN (unspec, 0) != 2 | |
| 1267 || XVECEXP (unspec, 0, 0) != src_reg | |
| 1268 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT | |
| 1269 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval) | |
| 1270 return 0; | |
| 1271 } | |
| 1272 return 1; | |
| 1273 }) | |
| 1274 | |
| 1275 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL. | |
| 1276 (define_predicate "lmw_operation" | |
| 1277 (match_code "parallel") | |
| 1278 { | |
| 1279 int count = XVECLEN (op, 0); | |
| 1280 unsigned int dest_regno; | |
| 1281 rtx src_addr; | |
| 1282 unsigned int base_regno; | |
| 1283 HOST_WIDE_INT offset; | |
| 1284 int i; | |
| 1285 | |
| 1286 /* Perform a quick check so we don't blow up below. */ | |
| 1287 if (count <= 1 | |
| 1288 || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
| 1289 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG | |
| 1290 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM) | |
| 1291 return 0; | |
| 1292 | |
| 1293 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0))); | |
| 1294 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0); | |
| 1295 | |
| 1296 if (dest_regno > 31 | |
| 1297 || count != 32 - (int) dest_regno) | |
| 1298 return 0; | |
| 1299 | |
| 1300 if (legitimate_indirect_address_p (src_addr, 0)) | |
| 1301 { | |
| 1302 offset = 0; | |
| 1303 base_regno = REGNO (src_addr); | |
| 1304 if (base_regno == 0) | |
| 1305 return 0; | |
| 1306 } | |
| 1307 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0)) | |
| 1308 { | |
| 1309 offset = INTVAL (XEXP (src_addr, 1)); | |
| 1310 base_regno = REGNO (XEXP (src_addr, 0)); | |
| 1311 } | |
| 1312 else | |
| 1313 return 0; | |
| 1314 | |
| 1315 for (i = 0; i < count; i++) | |
| 1316 { | |
| 1317 rtx elt = XVECEXP (op, 0, i); | |
| 1318 rtx newaddr; | |
| 1319 rtx addr_reg; | |
| 1320 HOST_WIDE_INT newoffset; | |
| 1321 | |
| 1322 if (GET_CODE (elt) != SET | |
| 1323 || GET_CODE (SET_DEST (elt)) != REG | |
| 1324 || GET_MODE (SET_DEST (elt)) != SImode | |
| 1325 || REGNO (SET_DEST (elt)) != dest_regno + i | |
| 1326 || GET_CODE (SET_SRC (elt)) != MEM | |
| 1327 || GET_MODE (SET_SRC (elt)) != SImode) | |
| 1328 return 0; | |
| 1329 newaddr = XEXP (SET_SRC (elt), 0); | |
| 1330 if (legitimate_indirect_address_p (newaddr, 0)) | |
| 1331 { | |
| 1332 newoffset = 0; | |
| 1333 addr_reg = newaddr; | |
| 1334 } | |
| 1335 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0)) | |
| 1336 { | |
| 1337 addr_reg = XEXP (newaddr, 0); | |
| 1338 newoffset = INTVAL (XEXP (newaddr, 1)); | |
| 1339 } | |
| 1340 else | |
| 1341 return 0; | |
| 1342 if (REGNO (addr_reg) != base_regno | |
| 1343 || newoffset != offset + 4 * i) | |
| 1344 return 0; | |
| 1345 } | |
| 1346 | |
| 1347 return 1; | |
| 1348 }) | |
| 1349 | |
| 1350 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL. | |
| 1351 (define_predicate "stmw_operation" | |
| 1352 (match_code "parallel") | |
| 1353 { | |
| 1354 int count = XVECLEN (op, 0); | |
| 1355 unsigned int src_regno; | |
| 1356 rtx dest_addr; | |
| 1357 unsigned int base_regno; | |
| 1358 HOST_WIDE_INT offset; | |
| 1359 int i; | |
| 1360 | |
| 1361 /* Perform a quick check so we don't blow up below. */ | |
| 1362 if (count <= 1 | |
| 1363 || GET_CODE (XVECEXP (op, 0, 0)) != SET | |
| 1364 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM | |
| 1365 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG) | |
| 1366 return 0; | |
| 1367 | |
| 1368 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0))); | |
| 1369 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0); | |
| 1370 | |
| 1371 if (src_regno > 31 | |
| 1372 || count != 32 - (int) src_regno) | |
| 1373 return 0; | |
| 1374 | |
| 1375 if (legitimate_indirect_address_p (dest_addr, 0)) | |
| 1376 { | |
| 1377 offset = 0; | |
| 1378 base_regno = REGNO (dest_addr); | |
| 1379 if (base_regno == 0) | |
| 1380 return 0; | |
| 1381 } | |
| 1382 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0)) | |
| 1383 { | |
| 1384 offset = INTVAL (XEXP (dest_addr, 1)); | |
| 1385 base_regno = REGNO (XEXP (dest_addr, 0)); | |
| 1386 } | |
| 1387 else | |
| 1388 return 0; | |
| 1389 | |
| 1390 for (i = 0; i < count; i++) | |
| 1391 { | |
| 1392 rtx elt = XVECEXP (op, 0, i); | |
| 1393 rtx newaddr; | |
| 1394 rtx addr_reg; | |
| 1395 HOST_WIDE_INT newoffset; | |
| 1396 | |
| 1397 if (GET_CODE (elt) != SET | |
| 1398 || GET_CODE (SET_SRC (elt)) != REG | |
| 1399 || GET_MODE (SET_SRC (elt)) != SImode | |
| 1400 || REGNO (SET_SRC (elt)) != src_regno + i | |
| 1401 || GET_CODE (SET_DEST (elt)) != MEM | |
| 1402 || GET_MODE (SET_DEST (elt)) != SImode) | |
| 1403 return 0; | |
| 1404 newaddr = XEXP (SET_DEST (elt), 0); | |
| 1405 if (legitimate_indirect_address_p (newaddr, 0)) | |
| 1406 { | |
| 1407 newoffset = 0; | |
| 1408 addr_reg = newaddr; | |
| 1409 } | |
| 1410 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0)) | |
| 1411 { | |
| 1412 addr_reg = XEXP (newaddr, 0); | |
| 1413 newoffset = INTVAL (XEXP (newaddr, 1)); | |
| 1414 } | |
| 1415 else | |
| 1416 return 0; | |
| 1417 if (REGNO (addr_reg) != base_regno | |
| 1418 || newoffset != offset + 4 * i) | |
| 1419 return 0; | |
| 1420 } | |
| 1421 | |
| 1422 return 1; | |
| 1423 }) |