Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/stormy16/stormy16.h @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | b7f97abdc517 |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 /* Xstormy16 cpu description. |
| 2 Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2007, | |
|
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3 2008, 2009, 2010, 2011 Free Software Foundation, Inc. |
| 0 | 4 Contributed by Red Hat, Inc. |
| 5 | |
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6 This file is part of GCC. |
| 0 | 7 |
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8 GCC is free software; you can redistribute it and/or modify |
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9 it under the terms of the GNU General Public License as published by |
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10 the Free Software Foundation; either version 3, or (at your option) |
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11 any later version. |
| 0 | 12 |
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13 GCC is distributed in the hope that it will be useful, |
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14 but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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16 GNU General Public License for more details. |
| 0 | 17 |
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18 You should have received a copy of the GNU General Public License |
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19 along with GCC; see the file COPYING3. If not see |
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20 <http://www.gnu.org/licenses/>. */ |
| 0 | 21 |
| 22 | |
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23 /* Driver configuration. */ |
| 0 | 24 |
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25 #undef ASM_SPEC |
| 0 | 26 #define ASM_SPEC "" |
| 27 | |
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28 #undef LINK_SPEC |
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29 #define LINK_SPEC "%{h*} %{v:-V} \ |
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30 %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}" |
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31 |
| 0 | 32 /* For xstormy16: |
| 33 - If -msim is specified, everything is built and linked as for the sim. | |
| 34 - If -T is specified, that linker script is used, and it should provide | |
| 35 appropriate libraries. | |
| 36 - If neither is specified, everything is built as for the sim, but no | |
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37 I/O support is assumed. */ |
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38 #undef LIB_SPEC |
| 0 | 39 #define LIB_SPEC "-( -lc %{msim:-lsim}%{!msim:%{!T*:-lnosys}} -)" |
| 40 | |
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41 #undef STARTFILE_SPEC |
| 0 | 42 #define STARTFILE_SPEC "crt0.o%s crti.o%s crtbegin.o%s" |
| 43 | |
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44 #undef ENDFILE_SPEC |
| 0 | 45 #define ENDFILE_SPEC "crtend.o%s crtn.o%s" |
| 46 | |
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47 |
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48 /* Run-time target specifications. */ |
| 0 | 49 |
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50 #define TARGET_CPU_CPP_BUILTINS() \ |
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51 do \ |
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52 { \ |
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53 builtin_define_std ("xstormy16"); \ |
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54 builtin_assert ("machine=xstormy16"); \ |
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55 builtin_assert ("cpu=xstormy16"); \ |
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56 } \ |
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57 while (0) |
| 0 | 58 |
| 59 #define TARGET_VERSION fprintf (stderr, " (xstormy16 cpu core)"); | |
| 60 | |
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61 /* Storage Layout. */ |
| 0 | 62 |
| 63 #define BITS_BIG_ENDIAN 1 | |
| 64 | |
| 65 #define BYTES_BIG_ENDIAN 0 | |
| 66 | |
| 67 #define WORDS_BIG_ENDIAN 0 | |
| 68 | |
| 69 #define UNITS_PER_WORD 2 | |
| 70 | |
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71 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
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72 do \ |
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73 { \ |
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74 if (GET_MODE_CLASS (MODE) == MODE_INT \ |
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75 && GET_MODE_SIZE (MODE) < 2) \ |
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76 (MODE) = HImode; \ |
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77 } \ |
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78 while (0) |
| 0 | 79 |
| 80 #define PARM_BOUNDARY 16 | |
| 81 | |
| 82 #define STACK_BOUNDARY 16 | |
| 83 | |
| 84 #define FUNCTION_BOUNDARY 16 | |
| 85 | |
| 86 #define BIGGEST_ALIGNMENT 16 | |
| 87 | |
| 88 #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
| 89 (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
| 90 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
| 91 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
| 92 | |
| 93 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
| 94 (TREE_CODE (EXP) == STRING_CST \ | |
| 95 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
| 96 | |
| 97 #define STRICT_ALIGNMENT 1 | |
| 98 | |
| 99 #define PCC_BITFIELD_TYPE_MATTERS 1 | |
| 100 | |
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101 /* Layout of Source Language Data Types. */ |
| 0 | 102 |
| 103 #define INT_TYPE_SIZE 16 | |
| 104 | |
| 105 #define SHORT_TYPE_SIZE 16 | |
| 106 | |
| 107 #define LONG_TYPE_SIZE 32 | |
| 108 | |
| 109 #define LONG_LONG_TYPE_SIZE 64 | |
| 110 | |
| 111 #define FLOAT_TYPE_SIZE 32 | |
| 112 | |
| 113 #define DOUBLE_TYPE_SIZE 64 | |
| 114 | |
| 115 #define LONG_DOUBLE_TYPE_SIZE 64 | |
| 116 | |
| 117 #define DEFAULT_SIGNED_CHAR 0 | |
| 118 | |
| 119 #define SIZE_TYPE "unsigned int" | |
| 120 | |
| 121 #define PTRDIFF_TYPE "int" | |
| 122 | |
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123 #undef WCHAR_TYPE |
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124 #define WCHAR_TYPE "long int" |
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125 |
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126 #undef WCHAR_TYPE_SIZE |
| 0 | 127 #define WCHAR_TYPE_SIZE 32 |
| 128 | |
| 129 | |
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130 /* Register Basics. */ |
| 0 | 131 |
| 132 #define FIRST_PSEUDO_REGISTER 19 | |
| 133 | |
| 134 #define FIXED_REGISTERS \ | |
| 135 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1 } | |
| 136 | |
| 137 #define CALL_USED_REGISTERS \ | |
| 138 { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1 } | |
| 139 | |
| 140 | |
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141 /* Order of allocation of registers. */ |
| 0 | 142 |
| 143 #define REG_ALLOC_ORDER { 7, 6, 5, 4, 3, 2, 1, 0, 9, 8, 10, 11, 12, 13, 14, 15, 16 } | |
| 144 | |
| 145 | |
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146 /* How Values Fit in Registers. */ |
| 0 | 147 |
| 148 #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
| 149 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
| 150 | |
| 151 #define HARD_REGNO_MODE_OK(REGNO, MODE) ((REGNO) != 16 || (MODE) == BImode) | |
| 152 | |
| 153 /* A C expression that is nonzero if it is desirable to choose register | |
| 154 allocation so as to avoid move instructions between a value of mode MODE1 | |
| 155 and a value of mode MODE2. | |
| 156 | |
| 157 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are | |
| 158 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be | |
| 159 zero. */ | |
| 160 #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) != BImode && (MODE2) != BImode) | |
| 161 | |
| 162 | |
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163 /* Register Classes. */ |
| 0 | 164 |
| 165 enum reg_class | |
| 166 { | |
| 167 NO_REGS, | |
| 168 R0_REGS, | |
| 169 R1_REGS, | |
| 170 TWO_REGS, | |
| 171 R2_REGS, | |
| 172 EIGHT_REGS, | |
| 173 R8_REGS, | |
| 174 ICALL_REGS, | |
| 175 GENERAL_REGS, | |
| 176 ALL_REGS, | |
| 177 LIM_REG_CLASSES | |
| 178 }; | |
| 179 | |
| 180 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) | |
| 181 | |
| 182 #define IRA_COVER_CLASSES \ | |
| 183 { \ | |
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184 GENERAL_REGS, LIM_REG_CLASSES \ |
| 0 | 185 } |
| 186 | |
| 187 #define REG_CLASS_NAMES \ | |
| 188 { \ | |
| 189 "NO_REGS", \ | |
| 190 "R0_REGS", \ | |
| 191 "R1_REGS", \ | |
| 192 "TWO_REGS", \ | |
| 193 "R2_REGS", \ | |
| 194 "EIGHT_REGS", \ | |
| 195 "R8_REGS", \ | |
| 196 "ICALL_REGS", \ | |
| 197 "GENERAL_REGS", \ | |
| 198 "ALL_REGS" \ | |
| 199 } | |
| 200 | |
| 201 #define REG_CLASS_CONTENTS \ | |
| 202 { \ | |
| 203 { 0x00000 }, \ | |
| 204 { 0x00001 }, \ | |
| 205 { 0x00002 }, \ | |
| 206 { 0x00003 }, \ | |
| 207 { 0x00004 }, \ | |
| 208 { 0x000FF }, \ | |
| 209 { 0x00100 }, \ | |
| 210 { 0x00300 }, \ | |
| 211 { 0x6FFFF }, \ | |
| 212 { (1 << FIRST_PSEUDO_REGISTER) - 1 } \ | |
| 213 } | |
| 214 | |
| 215 #define REGNO_REG_CLASS(REGNO) \ | |
| 216 ( (REGNO) == 0 ? R0_REGS \ | |
| 217 : (REGNO) == 1 ? R1_REGS \ | |
| 218 : (REGNO) == 2 ? R2_REGS \ | |
| 219 : (REGNO) < 8 ? EIGHT_REGS \ | |
| 220 : (REGNO) == 8 ? R8_REGS \ | |
| 221 : (REGNO) <= 18 ? GENERAL_REGS \ | |
| 222 : ALL_REGS) | |
| 223 | |
| 224 #define BASE_REG_CLASS GENERAL_REGS | |
| 225 | |
| 226 #define INDEX_REG_CLASS GENERAL_REGS | |
| 227 | |
| 228 #define REGNO_OK_FOR_BASE_P(NUM) 1 | |
| 229 | |
| 230 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM) | |
| 231 | |
| 232 /* This chip has the interesting property that only the first eight | |
| 233 registers can be moved to/from memory. */ | |
| 234 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ | |
| 235 xstormy16_secondary_reload_class (CLASS, MODE, X) | |
| 236 | |
| 237 #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
| 238 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
| 239 | |
| 240 | |
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241 /* Basic Stack Layout. */ |
| 0 | 242 |
| 243 /* We want to use post-increment instructions to push things on the stack, | |
| 244 because we don't have any pre-increment ones. */ | |
| 245 #define STACK_PUSH_CODE POST_INC | |
| 246 | |
| 247 #define FRAME_GROWS_DOWNWARD 0 | |
| 248 | |
| 249 #define ARGS_GROW_DOWNWARD 1 | |
| 250 | |
| 251 #define STARTING_FRAME_OFFSET 0 | |
| 252 | |
| 253 #define FIRST_PARM_OFFSET(FUNDECL) 0 | |
| 254 | |
| 255 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \ | |
| 256 ((COUNT) == 0 \ | |
| 257 ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \ | |
| 258 : NULL_RTX) | |
| 259 | |
| 260 #define INCOMING_RETURN_ADDR_RTX \ | |
| 261 gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-4))) | |
| 262 | |
| 263 #define INCOMING_FRAME_SP_OFFSET (xstormy16_interrupt_function_p () ? -6 : -4) | |
| 264 | |
| 265 | |
| 266 /* Register That Address the Stack Frame. */ | |
| 267 | |
| 268 #define STATIC_CHAIN_REGNUM 1 | |
| 269 #define HARD_FRAME_POINTER_REGNUM 13 | |
| 270 #define STACK_POINTER_REGNUM 15 | |
| 271 #define CARRY_REGNUM 16 | |
| 272 #define FRAME_POINTER_REGNUM 17 | |
| 273 #define ARG_POINTER_REGNUM 18 | |
| 274 | |
| 275 | |
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276 /* Eliminating the Frame Pointer and the Arg Pointer. */ |
| 0 | 277 |
| 278 #define ELIMINABLE_REGS \ | |
| 279 { \ | |
| 280 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 281 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
| 282 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 283 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
| 284 } | |
| 285 | |
| 286 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
| 287 (OFFSET) = xstormy16_initial_elimination_offset (FROM, TO) | |
| 288 | |
| 289 | |
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290 /* Passing Function Arguments on the Stack. */ |
| 0 | 291 |
| 292 #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1) | |
| 293 | |
| 294 | |
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295 /* Function Arguments in Registers. */ |
| 0 | 296 |
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297 #define NUM_ARGUMENT_REGISTERS 6 |
| 0 | 298 #define FIRST_ARGUMENT_REGISTER 2 |
| 299 | |
| 300 #define XSTORMY16_WORD_SIZE(TYPE, MODE) \ | |
| 301 ((((TYPE) ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \ | |
| 302 + 1) \ | |
| 303 / 2) | |
| 304 | |
| 305 /* For this platform, the value of CUMULATIVE_ARGS is the number of words | |
| 306 of arguments that have been passed in registers so far. */ | |
| 307 #define CUMULATIVE_ARGS int | |
| 308 | |
| 309 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ | |
| 310 (CUM) = 0 | |
| 311 | |
| 312 #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
| 313 ((REGNO) >= FIRST_ARGUMENT_REGISTER \ | |
| 314 && (REGNO) < FIRST_ARGUMENT_REGISTER + NUM_ARGUMENT_REGISTERS) | |
| 315 | |
| 316 | |
|
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317 /* How Scalar Function Values are Returned. */ |
| 0 | 318 |
| 319 /* The number of the hard register that is used to return a scalar value from a | |
| 320 function call. */ | |
| 321 #define RETURN_VALUE_REGNUM FIRST_ARGUMENT_REGISTER | |
| 322 | |
| 323 | |
|
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324 /* Function Entry and Exit. */ |
| 0 | 325 |
| 326 #define EPILOGUE_USES(REGNO) \ | |
| 327 xstormy16_epilogue_uses (REGNO) | |
| 328 | |
| 329 | |
| 330 /* Generating Code for Profiling. */ | |
| 331 | |
| 332 /* This declaration must be present, but it can be an abort if profiling is | |
| 333 not implemented. */ | |
| 334 | |
| 335 #define FUNCTION_PROFILER(FILE, LABELNO) xstormy16_function_profiler () | |
| 336 | |
| 337 | |
| 338 /* Trampolines for Nested Functions. */ | |
| 339 | |
| 340 #define TRAMPOLINE_SIZE 8 | |
| 341 #define TRAMPOLINE_ALIGNMENT 16 | |
| 342 | |
| 343 | |
|
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344 /* Addressing Modes. */ |
| 0 | 345 |
| 346 #define HAVE_POST_INCREMENT 1 | |
| 347 | |
| 348 #define HAVE_PRE_DECREMENT 1 | |
| 349 | |
| 350 #define MAX_REGS_PER_ADDRESS 1 | |
| 351 | |
| 352 #define LEGITIMATE_CONSTANT_P(X) 1 | |
| 353 | |
| 354 | |
|
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355 /* Describing Relative Costs of Operations. */ |
| 0 | 356 |
| 357 #define BRANCH_COST(speed_p, predictable_p) 5 | |
| 358 | |
| 359 #define SLOW_BYTE_ACCESS 0 | |
| 360 | |
| 361 #define NO_FUNCTION_CSE | |
| 362 | |
| 363 | |
| 364 /* Dividing the output into sections. */ | |
| 365 | |
| 366 #define TEXT_SECTION_ASM_OP ".text" | |
| 367 | |
| 368 #define DATA_SECTION_ASM_OP ".data" | |
| 369 | |
| 370 #define BSS_SECTION_ASM_OP "\t.section\t.bss" | |
| 371 | |
| 372 /* Define the pseudo-ops used to switch to the .ctors and .dtors sections. | |
| 373 There are no shared libraries on this target so these sections need | |
| 374 not be writable. | |
| 375 | |
| 376 Defined in elfos.h. */ | |
| 377 | |
| 378 #undef CTORS_SECTION_ASM_OP | |
| 379 #undef DTORS_SECTION_ASM_OP | |
| 380 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"a\"" | |
| 381 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"a\"" | |
| 382 | |
| 383 #define TARGET_ASM_INIT_SECTIONS xstormy16_asm_init_sections | |
| 384 | |
| 385 #define JUMP_TABLES_IN_TEXT_SECTION 1 | |
| 386 | |
| 387 /* The Overall Framework of an Assembler File. */ | |
| 388 | |
| 389 #define ASM_COMMENT_START ";" | |
| 390 | |
| 391 #define ASM_APP_ON "#APP\n" | |
| 392 | |
| 393 #define ASM_APP_OFF "#NO_APP\n" | |
| 394 | |
| 395 /* Output of Data. */ | |
| 396 | |
| 397 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '|') | |
| 398 | |
| 399 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ | |
| 400 xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1) | |
| 401 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ | |
| 402 xstormy16_asm_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0) | |
| 403 | |
| 404 | |
| 405 /* Output and Generation of Labels. */ | |
| 406 #define SYMBOL_FLAG_XSTORMY16_BELOW100 (SYMBOL_FLAG_MACH_DEP << 0) | |
| 407 | |
|
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408 #define ASM_OUTPUT_SYMBOL_REF(STREAM, SYMBOL) \ |
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409 do \ |
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410 { \ |
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411 const char *rn = XSTR (SYMBOL, 0); \ |
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412 \ |
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413 if (SYMBOL_REF_FUNCTION_P (SYMBOL)) \ |
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414 ASM_OUTPUT_LABEL_REF ((STREAM), rn); \ |
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415 else \ |
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416 assemble_name (STREAM, rn); \ |
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417 } \ |
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418 while (0) |
| 0 | 419 |
| 420 #define ASM_OUTPUT_LABEL_REF(STREAM, NAME) \ | |
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421 do \ |
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422 { \ |
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423 fputs ("@fptr(", STREAM); \ |
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424 assemble_name (STREAM, NAME); \ |
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425 fputc (')', STREAM); \ |
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426 } \ |
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427 while (0) |
| 0 | 428 |
| 429 /* Globalizing directive for a label. */ | |
| 430 #define GLOBAL_ASM_OP "\t.globl " | |
| 431 | |
| 432 | |
| 433 /* Output of Assembler Instructions. */ | |
| 434 | |
| 435 #define REGISTER_NAMES \ | |
| 436 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \ | |
| 437 "r11", "r12", "r13", "psw", "sp", "carry", "fp", "ap" } | |
| 438 | |
| 439 #define ADDITIONAL_REGISTER_NAMES \ | |
| 440 { { "r14", 14 }, \ | |
| 441 { "r15", 15 } } | |
| 442 | |
| 443 #define REGISTER_PREFIX "" | |
| 444 #define LOCAL_LABEL_PREFIX "." | |
| 445 #define USER_LABEL_PREFIX "" | |
| 446 #define IMMEDIATE_PREFIX "#" | |
| 447 | |
| 448 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ | |
| 449 fprintf (STREAM, "\tpush %d\n", REGNO) | |
| 450 | |
| 451 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ | |
| 452 fprintf (STREAM, "\tpop %d\n", REGNO) | |
| 453 | |
| 454 | |
| 455 /* Output of dispatch tables. */ | |
| 456 | |
| 457 /* This port does not use the ASM_OUTPUT_ADDR_VEC_ELT macro, because | |
| 458 this could cause label alignment to appear between the 'br' and the table, | |
| 459 which would be bad. Instead, it controls the output of the table | |
| 460 itself. */ | |
| 461 #define ASM_OUTPUT_ADDR_VEC(LABEL, BODY) \ | |
| 462 xstormy16_output_addr_vec (file, LABEL, BODY) | |
| 463 | |
| 464 /* Alignment for ADDR_VECs is the same as for code. */ | |
| 465 #define ADDR_VEC_ALIGN(ADDR_VEC) 1 | |
| 466 | |
| 467 | |
| 468 /* Assembler Commands for Exception Regions. */ | |
| 469 | |
| 470 #define DWARF2_UNWIND_INFO 0 | |
| 471 #define DWARF_CIE_DATA_ALIGNMENT 1 | |
| 472 | |
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473 #undef DONT_USE_BUILTIN_SETJMP |
| 0 | 474 #define JMP_BUF_SIZE 8 |
| 475 | |
| 476 /* Assembler Commands for Alignment. */ | |
| 477 | |
| 478 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ | |
| 479 fprintf ((STREAM), "\t.p2align %d\n", (POWER)) | |
| 480 | |
| 481 | |
| 482 /* Macros Affecting all Debug Formats. */ | |
| 483 | |
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484 #undef PREFERRED_DEBUGGING_TYPE |
| 0 | 485 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG |
| 486 | |
| 487 | |
| 488 /* Macros for SDB and Dwarf Output. */ | |
| 489 | |
| 490 /* Define this macro if addresses in Dwarf 2 debugging info should not | |
| 491 be the same size as pointers on the target architecture. The | |
| 492 macro's value should be the size, in bytes, to use for addresses in | |
| 493 the debugging info. | |
| 494 | |
| 495 Some architectures use word addresses to refer to code locations, | |
| 496 but Dwarf 2 info always uses byte addresses. On such machines, | |
| 497 Dwarf 2 addresses need to be larger than the architecture's | |
| 498 pointers. */ | |
| 499 #define DWARF2_ADDR_SIZE 4 | |
| 500 | |
| 501 | |
| 502 /* Miscellaneous Parameters. */ | |
| 503 | |
| 504 #define CASE_VECTOR_MODE SImode | |
| 505 | |
| 506 #define WORD_REGISTER_OPERATIONS | |
| 507 | |
| 508 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
| 509 | |
| 510 #define MOVE_MAX 2 | |
| 511 | |
| 512 #define SHIFT_COUNT_TRUNCATED 1 | |
| 513 | |
| 514 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
| 515 | |
| 516 #define Pmode HImode | |
| 517 | |
| 518 #define FUNCTION_MODE HImode | |
| 519 | |
| 520 #define NO_IMPLICIT_EXTERN_C |