Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/v850/v850.md @ 67:f6334be47118
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| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | 77e2b8dfacca |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 ;; GCC machine description for NEC V850 |
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2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2002, 2004, 2005, 2007, 2008, 2010 |
| 0 | 3 ;; Free Software Foundation, Inc. |
| 4 ;; Contributed by Jeff Law (law@cygnus.com). | |
| 5 | |
| 6 ;; This file is part of GCC. | |
| 7 | |
| 8 ;; GCC is free software; you can redistribute it and/or modify | |
| 9 ;; it under the terms of the GNU General Public License as published by | |
| 10 ;; the Free Software Foundation; either version 3, or (at your option) | |
| 11 ;; any later version. | |
| 12 | |
| 13 ;; GCC is distributed in the hope that it will be useful, | |
| 14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 ;; GNU General Public License for more details. | |
| 17 | |
| 18 ;; You should have received a copy of the GNU General Public License | |
| 19 ;; along with GCC; see the file COPYING3. If not see | |
| 20 ;; <http://www.gnu.org/licenses/>. | |
| 21 | |
| 22 ;; The original PO technology requires these to be ordered by speed, | |
| 23 ;; so that assigner will pick the fastest. | |
| 24 | |
| 25 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
| 26 | |
| 27 ;; The V851 manual states that the instruction address space is 16M; | |
| 28 ;; the various branch/call instructions only have a 22bit offset (4M range). | |
| 29 ;; | |
| 30 ;; One day we'll probably need to handle calls to targets more than 4M | |
| 31 ;; away. | |
| 32 | |
| 33 ;; The size of instructions in bytes. | |
| 34 | |
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35 ;;--------------------------------------------------------------------------- |
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36 ;; Constants |
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37 |
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38 ;; |
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39 (define_constants |
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40 [(ZERO_REGNUM 0) ; constant zero |
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41 (SP_REGNUM 3) ; Stack Pointer |
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42 (GP_REGNUM 4) ; GP Pointer |
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43 (EP_REGNUM 30) ; EP pointer |
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44 (LP_REGNUM 31) ; Return address register |
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45 (CC_REGNUM 32) ; Condition code pseudo register |
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46 (FCC_REGNUM 33) ; Floating Condition code pseudo register |
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47 ] |
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48 ) |
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49 |
| 0 | 50 (define_attr "length" "" |
| 51 (const_int 4)) | |
| 52 | |
| 53 (define_attr "long_calls" "yes,no" | |
| 54 (const (if_then_else (symbol_ref "TARGET_LONG_CALLS") | |
| 55 (const_string "yes") | |
| 56 (const_string "no")))) | |
| 57 | |
| 58 ;; Types of instructions (for scheduling purposes). | |
| 59 | |
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60 (define_attr "type" "load,store,bit1,mult,macc,div,fpu,single,other" |
| 0 | 61 (const_string "other")) |
| 62 | |
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63 (define_attr "cpu" "none,v850,v850e,v850e1,v850e2,v850e2v3" |
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64 (cond [(ne (symbol_ref "TARGET_V850") (const_int 0)) |
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65 (const_string "v850") |
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66 (ne (symbol_ref "TARGET_V850E") (const_int 0)) |
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67 (const_string "v850e") |
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68 (ne (symbol_ref "TARGET_V850E1") (const_int 0)) |
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69 (const_string "v850e1") |
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70 (ne (symbol_ref "TARGET_V850E2") (const_int 0)) |
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71 (const_string "v850e2") |
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72 (ne (symbol_ref "TARGET_V850E2") (const_int 0)) |
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73 (const_string "v850e2v3")] |
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74 (const_string "none"))) |
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75 |
| 0 | 76 ;; Condition code settings. |
| 77 ;; none - insn does not affect cc | |
| 78 ;; none_0hit - insn does not affect cc but it does modify operand 0 | |
| 79 ;; This attribute is used to keep track of when operand 0 changes. | |
| 80 ;; See the description of NOTICE_UPDATE_CC for more info. | |
| 81 ;; set_znv - sets z,n,v to usable values; c is unknown. | |
| 82 ;; set_zn - sets z,n to usable values; v,c is unknown. | |
| 83 ;; compare - compare instruction | |
| 84 ;; clobber - value of cc is unknown | |
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85 (define_attr "cc" "none,none_0hit,set_z,set_zn,set_znv,compare,clobber" |
| 0 | 86 (const_string "clobber")) |
| 87 | |
| 88 ;; Function units for the V850. As best as I can tell, there's | |
| 89 ;; a traditional memory load/use stall as well as a stall if | |
| 90 ;; the result of a multiply is used too early. | |
| 91 | |
| 92 (define_insn_reservation "v850_other" 1 | |
| 93 (eq_attr "type" "other") | |
| 94 "nothing") | |
| 95 (define_insn_reservation "v850_mult" 2 | |
| 96 (eq_attr "type" "mult") | |
| 97 "nothing") | |
| 98 (define_insn_reservation "v850_memory" 2 | |
| 99 (eq_attr "type" "load") | |
| 100 "nothing") | |
| 101 | |
| 102 (include "predicates.md") | |
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103 (include "constraints.md") |
| 0 | 104 |
| 105 ;; ---------------------------------------------------------------------- | |
| 106 ;; MOVE INSTRUCTIONS | |
| 107 ;; ---------------------------------------------------------------------- | |
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108 (define_insn "sign23byte_load" |
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109 [(set (match_operand:SI 0 "register_operand" "=r") |
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110 (sign_extend:SI |
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111 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r") |
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112 (match_operand 2 "disp23_operand" "W")))))] |
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113 "TARGET_V850E2V3" |
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114 "ld.b %2[%1],%0" |
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115 [(set_attr "length" "4") |
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116 (set_attr "cc" "none_0hit")]) |
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117 |
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118 (define_insn "unsign23byte_load" |
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119 [(set (match_operand:SI 0 "register_operand" "=r") |
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120 (zero_extend:SI |
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121 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r") |
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122 (match_operand 2 "disp23_operand" "W")))))] |
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123 "TARGET_V850E2V3" |
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124 "ld.bu %2[%1],%0" |
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125 [(set_attr "length" "4") |
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126 (set_attr "cc" "none_0hit")]) |
| 0 | 127 |
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128 (define_insn "sign23hword_load" |
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129 [(set (match_operand:SI 0 "register_operand" "=r") |
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130 (sign_extend:SI |
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131 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r") |
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132 (match_operand 2 "disp23_operand" "W")))))] |
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133 "TARGET_V850E2V3" |
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134 "ld.h %2[%1],%0" |
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135 [(set_attr "length" "4") |
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136 (set_attr "cc" "none_0hit")]) |
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137 |
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138 (define_insn "unsign23hword_load" |
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139 [(set (match_operand:SI 0 "register_operand" "=r") |
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140 (zero_extend:SI |
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141 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r") |
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142 (match_operand 2 "disp23_operand" "W")))))] |
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143 "TARGET_V850E2V3" |
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144 "ld.hu %2[%1],%0" |
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145 [(set_attr "length" "4") |
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146 (set_attr "cc" "none_0hit")]) |
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147 |
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148 (define_insn "23word_load" |
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149 [(set (match_operand:SI 0 "register_operand" "=r") |
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150 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") |
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151 (match_operand 2 "disp23_operand" "W"))))] |
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152 "TARGET_V850E2V3" |
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153 "ld.w %2[%1],%0" |
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154 [(set_attr "length" "4") |
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155 (set_attr "cc" "none_0hit")]) |
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156 |
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157 (define_insn "23byte_store" |
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158 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "r") |
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159 (match_operand 1 "disp23_operand" "W"))) |
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160 (match_operand:QI 2 "register_operand" "r"))] |
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161 "TARGET_V850E2V3" |
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162 "st.b %2,%1[%0]" |
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163 [(set_attr "length" "4") |
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164 (set_attr "cc" "none_0hit")]) |
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165 |
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166 (define_insn "23hword_store" |
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167 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "r") |
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168 (match_operand 1 "disp23_operand" "W"))) |
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169 (match_operand:HI 2 "register_operand" "r"))] |
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170 "TARGET_V850E2V3" |
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171 "st.h %2,%1[%0]" |
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172 [(set_attr "length" "4") |
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173 (set_attr "cc" "none_0hit")]) |
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174 |
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175 (define_insn "23word_store" |
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176 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r") |
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177 (match_operand 1 "disp23_operand" "W"))) |
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178 (match_operand:SI 2 "register_operand" "r"))] |
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179 "TARGET_V850E2V3" |
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180 "st.w %2,%1[%0]" |
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181 [(set_attr "length" "4") |
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182 (set_attr "cc" "none_0hit")]) |
| 0 | 183 ;; movqi |
| 184 | |
| 185 (define_expand "movqi" | |
| 186 [(set (match_operand:QI 0 "general_operand" "") | |
| 187 (match_operand:QI 1 "general_operand" ""))] | |
| 188 "" | |
| 189 " | |
| 190 { | |
| 191 /* One of the ops has to be in a register or 0 */ | |
| 192 if (!register_operand (operand0, QImode) | |
| 193 && !reg_or_0_operand (operand1, QImode)) | |
| 194 operands[1] = copy_to_mode_reg (QImode, operand1); | |
| 195 }") | |
| 196 | |
| 197 (define_insn "*movqi_internal" | |
| 198 [(set (match_operand:QI 0 "general_operand" "=r,r,r,Q,r,m,m") | |
| 199 (match_operand:QI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))] | |
| 200 "register_operand (operands[0], QImode) | |
| 201 || reg_or_0_operand (operands[1], QImode)" | |
| 202 "* return output_move_single (operands);" | |
| 203 [(set_attr "length" "2,4,2,2,4,4,4") | |
| 204 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") | |
|
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205 (set_attr "type" "other,other,load,other,load,store,store")]) |
| 0 | 206 |
| 207 ;; movhi | |
| 208 | |
| 209 (define_expand "movhi" | |
| 210 [(set (match_operand:HI 0 "general_operand" "") | |
| 211 (match_operand:HI 1 "general_operand" ""))] | |
| 212 "" | |
| 213 " | |
| 214 { | |
| 215 /* One of the ops has to be in a register or 0 */ | |
| 216 if (!register_operand (operand0, HImode) | |
| 217 && !reg_or_0_operand (operand1, HImode)) | |
| 218 operands[1] = copy_to_mode_reg (HImode, operand1); | |
| 219 }") | |
| 220 | |
| 221 (define_insn "*movhi_internal" | |
| 222 [(set (match_operand:HI 0 "general_operand" "=r,r,r,Q,r,m,m") | |
| 223 (match_operand:HI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))] | |
| 224 "register_operand (operands[0], HImode) | |
| 225 || reg_or_0_operand (operands[1], HImode)" | |
| 226 "* return output_move_single (operands);" | |
| 227 [(set_attr "length" "2,4,2,2,4,4,4") | |
| 228 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") | |
|
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229 (set_attr "type" "other,other,load,other,load,store,store")]) |
| 0 | 230 |
| 231 ;; movsi and helpers | |
| 232 | |
| 233 (define_insn "*movsi_high" | |
| 234 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 235 (high:SI (match_operand 1 "" "")))] | |
| 236 "" | |
| 237 "movhi hi(%1),%.,%0" | |
| 238 [(set_attr "length" "4") | |
| 239 (set_attr "cc" "none_0hit") | |
| 240 (set_attr "type" "other")]) | |
| 241 | |
| 242 (define_insn "*movsi_lo" | |
| 243 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 244 (lo_sum:SI (match_operand:SI 1 "register_operand" "r") | |
| 245 (match_operand:SI 2 "immediate_operand" "i")))] | |
| 246 "" | |
| 247 "movea lo(%2),%1,%0" | |
| 248 [(set_attr "length" "4") | |
| 249 (set_attr "cc" "none_0hit") | |
| 250 (set_attr "type" "other")]) | |
| 251 | |
| 252 (define_expand "movsi" | |
| 253 [(set (match_operand:SI 0 "general_operand" "") | |
| 254 (match_operand:SI 1 "general_operand" ""))] | |
| 255 "" | |
| 256 " | |
| 257 { | |
| 258 /* One of the ops has to be in a register or 0 */ | |
| 259 if (!register_operand (operand0, SImode) | |
| 260 && !reg_or_0_operand (operand1, SImode)) | |
| 261 operands[1] = copy_to_mode_reg (SImode, operand1); | |
| 262 | |
| 263 /* Some constants, as well as symbolic operands | |
| 264 must be done with HIGH & LO_SUM patterns. */ | |
| 265 if (CONSTANT_P (operands[1]) | |
| 266 && GET_CODE (operands[1]) != HIGH | |
|
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267 && ! (TARGET_V850E || TARGET_V850E2_ALL) |
| 0 | 268 && !special_symbolref_operand (operands[1], VOIDmode) |
| 269 && !(GET_CODE (operands[1]) == CONST_INT | |
| 270 && (CONST_OK_FOR_J (INTVAL (operands[1])) | |
| 271 || CONST_OK_FOR_K (INTVAL (operands[1])) | |
| 272 || CONST_OK_FOR_L (INTVAL (operands[1]))))) | |
| 273 { | |
| 274 rtx temp; | |
| 275 | |
| 276 if (reload_in_progress || reload_completed) | |
| 277 temp = operands[0]; | |
| 278 else | |
| 279 temp = gen_reg_rtx (SImode); | |
| 280 | |
| 281 emit_insn (gen_rtx_SET (SImode, temp, | |
| 282 gen_rtx_HIGH (SImode, operand1))); | |
| 283 emit_insn (gen_rtx_SET (SImode, operand0, | |
| 284 gen_rtx_LO_SUM (SImode, temp, operand1))); | |
| 285 DONE; | |
| 286 } | |
| 287 }") | |
| 288 | |
| 289 ;; This is the same as the following pattern, except that it includes | |
| 290 ;; support for arbitrary 32-bit immediates. | |
| 291 | |
| 292 ;; ??? This always loads addresses using hilo. If the only use of this address | |
| 293 ;; was in a load/store, then we would get smaller code if we only loaded the | |
| 294 ;; upper part with hi, and then put the lower part in the load/store insn. | |
| 295 | |
| 296 (define_insn "*movsi_internal_v850e" | |
| 297 [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m,r") | |
| 298 (match_operand:SI 1 "general_operand" "Jr,K,L,Q,Ir,m,R,r,I,i"))] | |
|
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299 "(TARGET_V850E || TARGET_V850E2_ALL) |
| 0 | 300 && (register_operand (operands[0], SImode) |
| 301 || reg_or_0_operand (operands[1], SImode))" | |
| 302 "* return output_move_single (operands);" | |
| 303 [(set_attr "length" "2,4,4,2,2,4,4,4,4,6") | |
| 304 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") | |
|
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305 (set_attr "type" "other,other,other,load,other,load,other,store,store,other")]) |
| 0 | 306 |
| 307 (define_insn "*movsi_internal" | |
| 308 [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m") | |
| 309 (match_operand:SI 1 "movsi_source_operand" "Jr,K,L,Q,Ir,m,R,r,I"))] | |
| 310 "register_operand (operands[0], SImode) | |
| 311 || reg_or_0_operand (operands[1], SImode)" | |
| 312 "* return output_move_single (operands);" | |
| 313 [(set_attr "length" "2,4,4,2,2,4,4,4,4") | |
| 314 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") | |
|
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315 (set_attr "type" "other,other,other,load,other,load,store,store,other")]) |
| 0 | 316 |
| 317 (define_insn "*movsf_internal" | |
| 318 [(set (match_operand:SF 0 "general_operand" "=r,r,r,r,r,Q,r,m,m,r") | |
| 319 (match_operand:SF 1 "general_operand" "Jr,K,L,n,Q,Ir,m,r,IG,iF"))] | |
| 320 "register_operand (operands[0], SFmode) | |
| 321 || reg_or_0_operand (operands[1], SFmode)" | |
| 322 "* return output_move_single (operands);" | |
| 323 [(set_attr "length" "2,4,4,8,2,2,4,4,4,8") | |
| 324 (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") | |
|
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325 (set_attr "type" "other,other,other,other,load,other,load,store,store,other")]) |
| 0 | 326 |
| 327 ;; ---------------------------------------------------------------------- | |
| 328 ;; TEST INSTRUCTIONS | |
| 329 ;; ---------------------------------------------------------------------- | |
| 330 | |
| 331 (define_insn "*v850_tst1" | |
|
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332 [(set (cc0) |
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333 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "m") |
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334 (const_int 1) |
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335 (match_operand:QI 1 "const_int_operand" "n")) |
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336 (const_int 0)))] |
| 0 | 337 "" |
| 338 "tst1 %1,%0" | |
| 339 [(set_attr "length" "4") | |
| 340 (set_attr "cc" "clobber")]) | |
| 341 | |
| 342 ;; This replaces ld.b;sar;andi with tst1;setf nz. | |
| 343 | |
| 344 (define_split | |
| 345 [(set (match_operand:SI 0 "register_operand" "") | |
|
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346 (compare (zero_extract:SI (match_operand:QI 1 "memory_operand" "") |
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347 (const_int 1) |
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348 (match_operand 2 "const_int_operand" "")) |
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349 (const_int 0)))] |
| 0 | 350 "" |
|
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351 [(set (cc0) (compare (zero_extract:SI (match_dup 1) |
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352 (const_int 1) |
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353 (match_dup 2)) |
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354 (const_int 0))) |
| 0 | 355 (set (match_dup 0) (ne:SI (cc0) (const_int 0)))]) |
| 356 | |
|
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357 (define_expand "cbranchsi4" |
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358 [(set (cc0) |
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359 (compare (match_operand:SI 1 "register_operand" "") |
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360 (match_operand:SI 2 "reg_or_int5_operand" ""))) |
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361 (set (pc) |
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362 (if_then_else |
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363 (match_operator 0 "ordered_comparison_operator" [(cc0) |
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364 (const_int 0)]) |
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365 (label_ref (match_operand 3 "" "")) |
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366 (pc)))] |
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367 "") |
| 0 | 368 |
|
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369 (define_expand "cstoresi4" |
| 0 | 370 [(set (cc0) |
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371 (compare (match_operand:SI 2 "register_operand" "") |
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372 (match_operand:SI 3 "reg_or_int5_operand" ""))) |
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373 (set (match_operand:SI 0 "register_operand") |
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374 (match_operator:SI 1 "ordered_comparison_operator" [(cc0) |
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375 (const_int 0)]))] |
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376 "") |
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377 |
|
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378 (define_expand "cmpsi" |
|
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379 [(set (cc0) |
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380 (compare (match_operand:SI 0 "register_operand" "r,r") |
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381 (match_operand:SI 1 "reg_or_int5_operand" "r,J")))] |
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382 "" |
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383 " |
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384 { |
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385 v850_compare_op0 = operands[0]; |
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386 v850_compare_op1 = operands[1]; |
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387 DONE; |
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388 }") |
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389 |
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390 (define_insn "cmpsi_insn" |
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391 [(set (cc0) |
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392 (compare (match_operand:SI 0 "register_operand" "r,r") |
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393 (match_operand:SI 1 "reg_or_int5_operand" "r,J")))] |
| 0 | 394 "" |
| 395 "@ | |
| 396 cmp %1,%0 | |
| 397 cmp %1,%0" | |
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398 [(set_attr "length" "2,2") |
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399 (set_attr "cc" "compare")]) |
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400 |
|
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401 (define_expand "cmpsf" |
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402 [(set (reg:CC CC_REGNUM) |
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403 (compare (match_operand:SF 0 "register_operand" "r") |
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404 (match_operand:SF 1 "register_operand" "r")))] |
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405 "TARGET_V850E2V3" |
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406 " |
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407 { |
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408 v850_compare_op0 = operands[0]; |
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409 v850_compare_op1 = operands[1]; |
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410 DONE; |
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411 }") |
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412 |
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413 (define_expand "cmpdf" |
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414 [(set (reg:CC CC_REGNUM) |
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415 (compare (match_operand:DF 0 "even_reg_operand" "r") |
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416 (match_operand:DF 1 "even_reg_operand" "r")))] |
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417 "TARGET_V850E2V3" |
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418 " |
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419 { |
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420 v850_compare_op0 = operands[0]; |
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421 v850_compare_op1 = operands[1]; |
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422 DONE; |
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423 }") |
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424 |
| 0 | 425 ;; ---------------------------------------------------------------------- |
| 426 ;; ADD INSTRUCTIONS | |
| 427 ;; ---------------------------------------------------------------------- | |
| 428 | |
| 429 (define_insn "addsi3" | |
| 430 [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
| 431 (plus:SI (match_operand:SI 1 "register_operand" "%0,r,r") | |
|
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432 (match_operand:SI 2 "nonmemory_operand" "rJ,K,U"))) |
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433 (clobber (reg:CC CC_REGNUM))] |
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434 |
| 0 | 435 "" |
| 436 "@ | |
| 437 add %2,%0 | |
| 438 addi %2,%1,%0 | |
| 439 addi %O2(%P2),%1,%0" | |
| 440 [(set_attr "length" "2,4,4") | |
| 441 (set_attr "cc" "set_zn,set_zn,set_zn")]) | |
| 442 | |
| 443 ;; ---------------------------------------------------------------------- | |
| 444 ;; SUBTRACT INSTRUCTIONS | |
| 445 ;; ---------------------------------------------------------------------- | |
| 446 | |
| 447 (define_insn "subsi3" | |
| 448 [(set (match_operand:SI 0 "register_operand" "=r,r") | |
| 449 (minus:SI (match_operand:SI 1 "register_operand" "0,r") | |
|
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450 (match_operand:SI 2 "register_operand" "r,0"))) |
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451 (clobber (reg:CC CC_REGNUM))] |
| 0 | 452 "" |
| 453 "@ | |
| 454 sub %2,%0 | |
| 455 subr %1,%0" | |
| 456 [(set_attr "length" "2,2") | |
|
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457 (set_attr "cc" "set_zn,set_zn")]) |
| 0 | 458 |
| 459 (define_insn "negsi2" | |
| 460 [(set (match_operand:SI 0 "register_operand" "=r") | |
|
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461 (neg:SI (match_operand:SI 1 "register_operand" "0"))) |
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462 (clobber (reg:CC CC_REGNUM))] |
| 0 | 463 "" |
| 464 "subr %.,%0" | |
| 465 [(set_attr "length" "2") | |
| 466 (set_attr "cc" "set_zn")]) | |
| 467 | |
| 468 ;; ---------------------------------------------------------------------- | |
| 469 ;; MULTIPLY INSTRUCTIONS | |
| 470 ;; ---------------------------------------------------------------------- | |
| 471 | |
| 472 (define_expand "mulhisi3" | |
| 473 [(set (match_operand:SI 0 "register_operand" "") | |
| 474 (mult:SI | |
| 475 (sign_extend:SI (match_operand:HI 1 "register_operand" "")) | |
| 476 (sign_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))] | |
| 477 "" | |
| 478 "if (GET_CODE (operands[2]) == CONST_INT) | |
| 479 { | |
| 480 emit_insn (gen_mulhisi3_internal2 (operands[0], operands[1], operands[2])); | |
| 481 DONE; | |
| 482 }") | |
| 483 | |
| 484 (define_insn "*mulhisi3_internal1" | |
| 485 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 486 (mult:SI | |
| 487 (sign_extend:SI (match_operand:HI 1 "register_operand" "%0")) | |
| 488 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))] | |
| 489 "" | |
| 490 "mulh %2,%0" | |
| 491 [(set_attr "length" "2") | |
| 492 (set_attr "cc" "none_0hit") | |
| 493 (set_attr "type" "mult")]) | |
| 494 | |
| 495 (define_insn "mulhisi3_internal2" | |
| 496 [(set (match_operand:SI 0 "register_operand" "=r,r") | |
| 497 (mult:SI | |
| 498 (sign_extend:SI (match_operand:HI 1 "register_operand" "%0,r")) | |
| 499 (match_operand:HI 2 "const_int_operand" "J,K")))] | |
| 500 "" | |
| 501 "@ | |
| 502 mulh %2,%0 | |
| 503 mulhi %2,%1,%0" | |
| 504 [(set_attr "length" "2,4") | |
| 505 (set_attr "cc" "none_0hit,none_0hit") | |
| 506 (set_attr "type" "mult")]) | |
| 507 | |
| 508 ;; ??? The scheduling info is probably wrong. | |
| 509 | |
| 510 ;; ??? This instruction can also generate the 32-bit highpart, but using it | |
| 511 ;; may increase code size counter to the desired result. | |
| 512 | |
| 513 ;; ??? This instructions can also give a DImode result. | |
| 514 | |
| 515 ;; ??? There is unsigned version, but it matters only for the DImode/highpart | |
| 516 ;; results. | |
| 517 | |
| 518 (define_insn "mulsi3" | |
| 519 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 520 (mult:SI (match_operand:SI 1 "register_operand" "%0") | |
| 521 (match_operand:SI 2 "reg_or_int9_operand" "rO")))] | |
|
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522 "(TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 523 "mul %2,%1,%." |
| 524 [(set_attr "length" "4") | |
| 525 (set_attr "cc" "none_0hit") | |
| 526 (set_attr "type" "mult")]) | |
| 527 | |
| 528 ;; ---------------------------------------------------------------------- | |
| 529 ;; DIVIDE INSTRUCTIONS | |
| 530 ;; ---------------------------------------------------------------------- | |
| 531 | |
| 532 ;; ??? These insns do set the Z/N condition codes, except that they are based | |
| 533 ;; on only one of the two results, so it doesn't seem to make sense to use | |
| 534 ;; them. | |
| 535 | |
| 536 ;; ??? The scheduling info is probably wrong. | |
| 537 | |
| 538 (define_insn "divmodsi4" | |
| 539 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 540 (div:SI (match_operand:SI 1 "register_operand" "0") | |
| 541 (match_operand:SI 2 "register_operand" "r"))) | |
| 542 (set (match_operand:SI 3 "register_operand" "=r") | |
| 543 (mod:SI (match_dup 1) | |
|
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544 (match_dup 2))) |
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545 (clobber (reg:CC CC_REGNUM))] |
| 0 | 546 "TARGET_V850E" |
| 547 "div %2,%0,%3" | |
| 548 [(set_attr "length" "4") | |
| 549 (set_attr "cc" "clobber") | |
|
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550 (set_attr "type" "div")]) |
| 0 | 551 |
| 552 (define_insn "udivmodsi4" | |
| 553 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 554 (udiv:SI (match_operand:SI 1 "register_operand" "0") | |
| 555 (match_operand:SI 2 "register_operand" "r"))) | |
| 556 (set (match_operand:SI 3 "register_operand" "=r") | |
| 557 (umod:SI (match_dup 1) | |
|
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558 (match_dup 2))) |
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559 (clobber (reg:CC CC_REGNUM))] |
| 0 | 560 "TARGET_V850E" |
| 561 "divu %2,%0,%3" | |
| 562 [(set_attr "length" "4") | |
| 563 (set_attr "cc" "clobber") | |
|
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564 (set_attr "type" "div")]) |
| 0 | 565 |
| 566 ;; ??? There is a 2 byte instruction for generating only the quotient. | |
| 567 ;; However, it isn't clear how to compute the length field correctly. | |
| 568 | |
| 569 (define_insn "divmodhi4" | |
| 570 [(set (match_operand:HI 0 "register_operand" "=r") | |
| 571 (div:HI (match_operand:HI 1 "register_operand" "0") | |
| 572 (match_operand:HI 2 "register_operand" "r"))) | |
| 573 (set (match_operand:HI 3 "register_operand" "=r") | |
| 574 (mod:HI (match_dup 1) | |
|
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575 (match_dup 2))) |
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576 (clobber (reg:CC CC_REGNUM))] |
| 0 | 577 "TARGET_V850E" |
| 578 "divh %2,%0,%3" | |
| 579 [(set_attr "length" "4") | |
| 580 (set_attr "cc" "clobber") | |
|
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581 (set_attr "type" "div")]) |
| 0 | 582 |
| 583 ;; Half-words are sign-extended by default, so we must zero extend to a word | |
| 584 ;; here before doing the divide. | |
| 585 | |
| 586 (define_insn "udivmodhi4" | |
| 587 [(set (match_operand:HI 0 "register_operand" "=r") | |
| 588 (udiv:HI (match_operand:HI 1 "register_operand" "0") | |
| 589 (match_operand:HI 2 "register_operand" "r"))) | |
| 590 (set (match_operand:HI 3 "register_operand" "=r") | |
| 591 (umod:HI (match_dup 1) | |
|
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592 (match_dup 2))) |
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593 (clobber (reg:CC CC_REGNUM))] |
| 0 | 594 "TARGET_V850E" |
| 595 "zxh %0 ; divhu %2,%0,%3" | |
| 596 [(set_attr "length" "4") | |
| 597 (set_attr "cc" "clobber") | |
|
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598 (set_attr "type" "div")]) |
| 0 | 599 |
| 600 ;; ---------------------------------------------------------------------- | |
| 601 ;; AND INSTRUCTIONS | |
| 602 ;; ---------------------------------------------------------------------- | |
| 603 | |
| 604 (define_insn "*v850_clr1_1" | |
| 605 [(set (match_operand:QI 0 "memory_operand" "=m") | |
| 606 (subreg:QI | |
| 607 (and:SI (subreg:SI (match_dup 0) 0) | |
|
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608 (match_operand:QI 1 "not_power_of_two_operand" "")) 0)) |
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609 (clobber (reg:CC CC_REGNUM))] |
| 0 | 610 "" |
| 611 "* | |
| 612 { | |
| 613 rtx xoperands[2]; | |
| 614 xoperands[0] = operands[0]; | |
| 615 xoperands[1] = GEN_INT (~INTVAL (operands[1]) & 0xff); | |
| 616 output_asm_insn (\"clr1 %M1,%0\", xoperands); | |
| 617 return \"\"; | |
| 618 }" | |
| 619 [(set_attr "length" "4") | |
|
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620 (set_attr "cc" "clobber") |
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621 (set_attr "type" "bit1")]) |
| 0 | 622 |
| 623 (define_insn "*v850_clr1_2" | |
| 624 [(set (match_operand:HI 0 "indirect_operand" "=m") | |
| 625 (subreg:HI | |
| 626 (and:SI (subreg:SI (match_dup 0) 0) | |
|
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627 (match_operand:HI 1 "not_power_of_two_operand" "")) 0)) |
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628 (clobber (reg:CC CC_REGNUM))] |
| 0 | 629 "" |
| 630 "* | |
| 631 { | |
| 632 int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffff); | |
| 633 | |
| 634 rtx xoperands[2]; | |
| 635 xoperands[0] = gen_rtx_MEM (QImode, | |
| 636 plus_constant (XEXP (operands[0], 0), log2 / 8)); | |
| 637 xoperands[1] = GEN_INT (log2 % 8); | |
| 638 output_asm_insn (\"clr1 %1,%0\", xoperands); | |
| 639 return \"\"; | |
| 640 }" | |
| 641 [(set_attr "length" "4") | |
|
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642 (set_attr "cc" "clobber") |
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643 (set_attr "type" "bit1")]) |
| 0 | 644 |
| 645 (define_insn "*v850_clr1_3" | |
| 646 [(set (match_operand:SI 0 "indirect_operand" "=m") | |
| 647 (and:SI (match_dup 0) | |
|
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648 (match_operand:SI 1 "not_power_of_two_operand" ""))) |
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649 (clobber (reg:CC CC_REGNUM))] |
| 0 | 650 "" |
| 651 "* | |
| 652 { | |
| 653 int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffffffff); | |
| 654 | |
| 655 rtx xoperands[2]; | |
| 656 xoperands[0] = gen_rtx_MEM (QImode, | |
| 657 plus_constant (XEXP (operands[0], 0), log2 / 8)); | |
| 658 xoperands[1] = GEN_INT (log2 % 8); | |
| 659 output_asm_insn (\"clr1 %1,%0\", xoperands); | |
| 660 return \"\"; | |
| 661 }" | |
| 662 [(set_attr "length" "4") | |
|
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663 (set_attr "cc" "clobber") |
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664 (set_attr "type" "bit1")]) |
| 0 | 665 |
| 666 (define_insn "andsi3" | |
| 667 [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
| 668 (and:SI (match_operand:SI 1 "register_operand" "%0,0,r") | |
|
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669 (match_operand:SI 2 "nonmemory_operand" "r,I,M"))) |
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670 (clobber (reg:CC CC_REGNUM))] |
| 0 | 671 "" |
| 672 "@ | |
| 673 and %2,%0 | |
| 674 and %.,%0 | |
| 675 andi %2,%1,%0" | |
| 676 [(set_attr "length" "2,2,4") | |
|
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677 (set_attr "cc" "set_zn")]) |
| 0 | 678 |
| 679 ;; ---------------------------------------------------------------------- | |
| 680 ;; OR INSTRUCTIONS | |
| 681 ;; ---------------------------------------------------------------------- | |
| 682 | |
| 683 (define_insn "*v850_set1_1" | |
| 684 [(set (match_operand:QI 0 "memory_operand" "=m") | |
| 685 (subreg:QI (ior:SI (subreg:SI (match_dup 0) 0) | |
|
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686 (match_operand 1 "power_of_two_operand" "")) 0)) |
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687 (clobber (reg:CC CC_REGNUM))] |
| 0 | 688 "" |
| 689 "set1 %M1,%0" | |
| 690 [(set_attr "length" "4") | |
|
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691 (set_attr "cc" "clobber") |
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692 (set_attr "type" "bit1")]) |
| 0 | 693 |
| 694 (define_insn "*v850_set1_2" | |
| 695 [(set (match_operand:HI 0 "indirect_operand" "=m") | |
| 696 (subreg:HI (ior:SI (subreg:SI (match_dup 0) 0) | |
| 697 (match_operand 1 "power_of_two_operand" "")) 0))] | |
| 698 "" | |
| 699 "* | |
| 700 { | |
| 701 int log2 = exact_log2 (INTVAL (operands[1])); | |
| 702 | |
| 703 if (log2 < 8) | |
| 704 return \"set1 %M1,%0\"; | |
| 705 else | |
| 706 { | |
| 707 rtx xoperands[2]; | |
| 708 xoperands[0] = gen_rtx_MEM (QImode, | |
| 709 plus_constant (XEXP (operands[0], 0), | |
| 710 log2 / 8)); | |
| 711 xoperands[1] = GEN_INT (log2 % 8); | |
| 712 output_asm_insn (\"set1 %1,%0\", xoperands); | |
| 713 } | |
| 714 return \"\"; | |
| 715 }" | |
| 716 [(set_attr "length" "4") | |
|
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717 (set_attr "cc" "clobber") |
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718 (set_attr "type" "bit1")]) |
| 0 | 719 |
| 720 (define_insn "*v850_set1_3" | |
| 721 [(set (match_operand:SI 0 "indirect_operand" "=m") | |
| 722 (ior:SI (match_dup 0) | |
|
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723 (match_operand 1 "power_of_two_operand" ""))) |
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724 (clobber (reg:CC CC_REGNUM))] |
| 0 | 725 "" |
| 726 "* | |
| 727 { | |
| 728 int log2 = exact_log2 (INTVAL (operands[1])); | |
| 729 | |
| 730 if (log2 < 8) | |
| 731 return \"set1 %M1,%0\"; | |
| 732 else | |
| 733 { | |
| 734 rtx xoperands[2]; | |
| 735 xoperands[0] = gen_rtx_MEM (QImode, | |
| 736 plus_constant (XEXP (operands[0], 0), | |
| 737 log2 / 8)); | |
| 738 xoperands[1] = GEN_INT (log2 % 8); | |
| 739 output_asm_insn (\"set1 %1,%0\", xoperands); | |
| 740 } | |
| 741 return \"\"; | |
| 742 }" | |
| 743 [(set_attr "length" "4") | |
|
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744 (set_attr "cc" "clobber") |
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745 (set_attr "type" "bit1")]) |
| 0 | 746 |
| 747 (define_insn "iorsi3" | |
| 748 [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
| 749 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r") | |
|
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750 (match_operand:SI 2 "nonmemory_operand" "r,I,M"))) |
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751 (clobber (reg:CC CC_REGNUM))] |
| 0 | 752 "" |
| 753 "@ | |
| 754 or %2,%0 | |
| 755 or %.,%0 | |
| 756 ori %2,%1,%0" | |
| 757 [(set_attr "length" "2,2,4") | |
|
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758 (set_attr "cc" "set_zn")]) |
| 0 | 759 |
| 760 ;; ---------------------------------------------------------------------- | |
| 761 ;; XOR INSTRUCTIONS | |
| 762 ;; ---------------------------------------------------------------------- | |
| 763 | |
| 764 (define_insn "*v850_not1_1" | |
| 765 [(set (match_operand:QI 0 "memory_operand" "=m") | |
| 766 (subreg:QI (xor:SI (subreg:SI (match_dup 0) 0) | |
|
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767 (match_operand 1 "power_of_two_operand" "")) 0)) |
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768 (clobber (reg:CC CC_REGNUM))] |
| 0 | 769 "" |
| 770 "not1 %M1,%0" | |
| 771 [(set_attr "length" "4") | |
|
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772 (set_attr "cc" "clobber") |
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773 (set_attr "type" "bit1")]) |
| 0 | 774 |
| 775 (define_insn "*v850_not1_2" | |
| 776 [(set (match_operand:HI 0 "indirect_operand" "=m") | |
| 777 (subreg:HI (xor:SI (subreg:SI (match_dup 0) 0) | |
| 778 (match_operand 1 "power_of_two_operand" "")) 0))] | |
| 779 "" | |
| 780 "* | |
| 781 { | |
| 782 int log2 = exact_log2 (INTVAL (operands[1])); | |
| 783 | |
| 784 if (log2 < 8) | |
| 785 return \"not1 %M1,%0\"; | |
| 786 else | |
| 787 { | |
| 788 rtx xoperands[2]; | |
| 789 xoperands[0] = gen_rtx_MEM (QImode, | |
| 790 plus_constant (XEXP (operands[0], 0), | |
| 791 log2 / 8)); | |
| 792 xoperands[1] = GEN_INT (log2 % 8); | |
| 793 output_asm_insn (\"not1 %1,%0\", xoperands); | |
| 794 } | |
| 795 return \"\"; | |
| 796 }" | |
| 797 [(set_attr "length" "4") | |
|
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798 (set_attr "cc" "clobber") |
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799 (set_attr "type" "bit1")]) |
| 0 | 800 |
| 801 (define_insn "*v850_not1_3" | |
| 802 [(set (match_operand:SI 0 "indirect_operand" "=m") | |
| 803 (xor:SI (match_dup 0) | |
|
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804 (match_operand 1 "power_of_two_operand" ""))) |
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805 (clobber (reg:CC CC_REGNUM))] |
| 0 | 806 "" |
| 807 "* | |
| 808 { | |
| 809 int log2 = exact_log2 (INTVAL (operands[1])); | |
| 810 | |
| 811 if (log2 < 8) | |
| 812 return \"not1 %M1,%0\"; | |
| 813 else | |
| 814 { | |
| 815 rtx xoperands[2]; | |
| 816 xoperands[0] = gen_rtx_MEM (QImode, | |
| 817 plus_constant (XEXP (operands[0], 0), | |
| 818 log2 / 8)); | |
| 819 xoperands[1] = GEN_INT (log2 % 8); | |
| 820 output_asm_insn (\"not1 %1,%0\", xoperands); | |
| 821 } | |
| 822 return \"\"; | |
| 823 }" | |
| 824 [(set_attr "length" "4") | |
|
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825 (set_attr "cc" "clobber") |
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|
826 (set_attr "type" "bit1")]) |
| 0 | 827 |
| 828 (define_insn "xorsi3" | |
| 829 [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
| 830 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r") | |
|
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|
831 (match_operand:SI 2 "nonmemory_operand" "r,I,M"))) |
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|
832 (clobber (reg:CC CC_REGNUM))] |
| 0 | 833 "" |
| 834 "@ | |
| 835 xor %2,%0 | |
| 836 xor %.,%0 | |
| 837 xori %2,%1,%0" | |
| 838 [(set_attr "length" "2,2,4") | |
|
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|
839 (set_attr "cc" "set_zn")]) |
| 0 | 840 |
| 841 ;; ---------------------------------------------------------------------- | |
| 842 ;; NOT INSTRUCTIONS | |
| 843 ;; ---------------------------------------------------------------------- | |
| 844 | |
| 845 (define_insn "one_cmplsi2" | |
| 846 [(set (match_operand:SI 0 "register_operand" "=r") | |
|
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847 (not:SI (match_operand:SI 1 "register_operand" "r"))) |
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848 (clobber (reg:CC CC_REGNUM))] |
| 0 | 849 "" |
| 850 "not %1,%0" | |
| 851 [(set_attr "length" "2") | |
|
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852 (set_attr "cc" "set_zn")]) |
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|
853 |
| 0 | 854 ;; ----------------------------------------------------------------- |
| 855 ;; BIT FIELDS | |
| 856 ;; ----------------------------------------------------------------- | |
| 857 | |
| 858 ;; ??? Is it worth defining insv and extv for the V850 series?!? | |
| 859 | |
| 860 ;; An insv pattern would be useful, but does not get used because | |
| 861 ;; store_bit_field never calls insv when storing a constant value into a | |
| 862 ;; single-bit bitfield. | |
| 863 | |
| 864 ;; extv/extzv patterns would be useful, but do not get used because | |
| 865 ;; optimize_bitfield_compare in fold-const usually converts single | |
| 866 ;; bit extracts into an AND with a mask. | |
| 867 | |
| 868 ;; ----------------------------------------------------------------- | |
| 869 ;; Scc INSTRUCTIONS | |
| 870 ;; ----------------------------------------------------------------- | |
| 871 | |
|
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872 (define_insn "*setcc" |
| 0 | 873 [(set (match_operand:SI 0 "register_operand" "=r") |
|
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874 (match_operator:SI 1 "comparison_operator" |
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875 [(cc0) (const_int 0)]))] |
| 0 | 876 "" |
| 877 "* | |
| 878 { | |
|
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879 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 |
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880 && (GET_CODE (operands[1]) == GT |
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881 || GET_CODE (operands[1]) == GE |
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882 || GET_CODE (operands[1]) == LE |
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883 || GET_CODE (operands[1]) == LT)) |
| 0 | 884 return 0; |
| 885 | |
|
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886 return \"setf %c1,%0\"; |
| 0 | 887 }" |
| 888 [(set_attr "length" "4") | |
| 889 (set_attr "cc" "none_0hit")]) | |
| 890 | |
|
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891 (define_insn "setf_insn" |
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892 [(set (match_operand:SI 0 "register_operand" "=r") |
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893 (match_operator:SI 1 "comparison_operator" |
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894 [(reg:CC CC_REGNUM) (const_int 0)]))] |
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895 "" |
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|
896 "setf %b1,%0" |
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897 [(set_attr "length" "4") |
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898 (set_attr "cc" "none_0hit")]) |
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899 |
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900 (define_insn "set_z_insn" |
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901 [(set (match_operand:SI 0 "register_operand" "=r") |
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902 (match_operand 1 "v850_float_z_comparison_operator" ""))] |
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903 "TARGET_V850E2V3" |
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|
904 "setf z,%0" |
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905 [(set_attr "length" "4") |
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906 (set_attr "cc" "none_0hit")]) |
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|
907 |
|
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908 (define_insn "set_nz_insn" |
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909 [(set (match_operand:SI 0 "register_operand" "=r") |
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|
910 (match_operand 1 "v850_float_nz_comparison_operator" ""))] |
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|
911 "TARGET_V850E2V3" |
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|
912 "setf nz,%0" |
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913 [(set_attr "length" "4") |
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914 (set_attr "cc" "none_0hit")]) |
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|
915 |
| 0 | 916 ;; ---------------------------------------------------------------------- |
| 917 ;; CONDITIONAL MOVE INSTRUCTIONS | |
| 918 ;; ---------------------------------------------------------------------- | |
| 919 | |
| 920 ;; Instructions using cc0 aren't allowed to have input reloads, so we must | |
| 921 ;; hide the fact that this instruction uses cc0. We do so by including the | |
| 922 ;; compare instruction inside it. | |
| 923 | |
| 924 (define_expand "movsicc" | |
| 925 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 926 (if_then_else:SI | |
|
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|
927 (match_operand 1 "comparison_operator") |
| 0 | 928 (match_operand:SI 2 "reg_or_const_operand" "rJ") |
| 929 (match_operand:SI 3 "reg_or_const_operand" "rI")))] | |
|
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|
930 "(TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 931 " |
| 932 { | |
| 933 if ( (GET_CODE (operands[2]) == CONST_INT | |
| 934 && GET_CODE (operands[3]) == CONST_INT)) | |
| 935 { | |
| 936 int o2 = INTVAL (operands[2]); | |
| 937 int o3 = INTVAL (operands[3]); | |
| 938 | |
| 939 if (o2 == 1 && o3 == 0) | |
| 940 FAIL; /* setf */ | |
| 941 if (o3 == 1 && o2 == 0) | |
| 942 FAIL; /* setf */ | |
| 943 if (o2 == 0 && (o3 < -16 || o3 > 15) && exact_log2 (o3) >= 0) | |
| 944 FAIL; /* setf + shift */ | |
| 945 if (o3 == 0 && (o2 < -16 || o2 > 15) && exact_log2 (o2) >=0) | |
| 946 FAIL; /* setf + shift */ | |
| 947 if (o2 != 0) | |
| 948 operands[2] = copy_to_mode_reg (SImode, operands[2]); | |
| 949 if (o3 !=0 ) | |
| 950 operands[3] = copy_to_mode_reg (SImode, operands[3]); | |
| 951 } | |
| 952 else | |
| 953 { | |
| 954 if (GET_CODE (operands[2]) != REG) | |
| 955 operands[2] = copy_to_mode_reg (SImode,operands[2]); | |
| 956 if (GET_CODE (operands[3]) != REG) | |
| 957 operands[3] = copy_to_mode_reg (SImode, operands[3]); | |
| 958 } | |
| 959 }") | |
| 960 | |
| 961 ;; ??? Clobbering the condition codes is overkill. | |
| 962 | |
| 963 ;; ??? We sometimes emit an unnecessary compare instruction because the | |
| 964 ;; condition codes may have already been set by an earlier instruction, | |
| 965 ;; but we have no code here to avoid the compare if it is unnecessary. | |
| 966 | |
|
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|
967 (define_insn "movsicc_normal_cc" |
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968 [(set (match_operand:SI 0 "register_operand" "=r") |
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969 (if_then_else:SI |
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970 (match_operator 1 "comparison_operator" |
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971 [(reg:CC CC_REGNUM) (const_int 0)]) |
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972 (match_operand:SI 2 "reg_or_int5_operand" "rJ") |
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973 (match_operand:SI 3 "reg_or_0_operand" "rI")))] |
|
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974 "(TARGET_V850E || TARGET_V850E2_ALL)" |
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|
975 "cmov %c1,%2,%z3,%0"; |
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976 [(set_attr "length" "6") |
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|
977 (set_attr "cc" "compare")]) |
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|
978 |
|
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|
979 (define_insn "movsicc_reversed_cc" |
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980 [(set (match_operand:SI 0 "register_operand" "=r") |
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981 (if_then_else:SI |
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|
982 (match_operator 1 "comparison_operator" |
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983 [(reg:CC CC_REGNUM) (const_int 0)]) |
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984 (match_operand:SI 2 "reg_or_0_operand" "rI") |
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985 (match_operand:SI 3 "reg_or_int5_operand" "rJ")))] |
|
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986 "(TARGET_V850E || TARGET_V850E2_ALL)" |
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|
987 "cmov %C1,%3,%z2,%0" |
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|
988 [(set_attr "length" "6") |
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|
989 (set_attr "cc" "compare")]) |
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|
990 |
| 0 | 991 (define_insn "*movsicc_normal" |
| 992 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 993 (if_then_else:SI | |
| 994 (match_operator 1 "comparison_operator" | |
| 995 [(match_operand:SI 4 "register_operand" "r") | |
| 996 (match_operand:SI 5 "reg_or_int5_operand" "rJ")]) | |
| 997 (match_operand:SI 2 "reg_or_int5_operand" "rJ") | |
| 998 (match_operand:SI 3 "reg_or_0_operand" "rI")))] | |
|
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|
999 "(TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 1000 "cmp %5,%4 ; cmov %c1,%2,%z3,%0" |
| 1001 [(set_attr "length" "6") | |
| 1002 (set_attr "cc" "clobber")]) | |
| 1003 | |
| 1004 (define_insn "*movsicc_reversed" | |
| 1005 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1006 (if_then_else:SI | |
| 1007 (match_operator 1 "comparison_operator" | |
| 1008 [(match_operand:SI 4 "register_operand" "r") | |
| 1009 (match_operand:SI 5 "reg_or_int5_operand" "rJ")]) | |
| 1010 (match_operand:SI 2 "reg_or_0_operand" "rI") | |
| 1011 (match_operand:SI 3 "reg_or_int5_operand" "rJ")))] | |
|
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1012 "(TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 1013 "cmp %5,%4 ; cmov %C1,%3,%z2,%0" |
| 1014 [(set_attr "length" "6") | |
| 1015 (set_attr "cc" "clobber")]) | |
| 1016 | |
| 1017 (define_insn "*movsicc_tst1" | |
| 1018 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1019 (if_then_else:SI | |
| 1020 (match_operator 1 "comparison_operator" | |
| 1021 [(zero_extract:SI | |
| 1022 (match_operand:QI 2 "memory_operand" "m") | |
| 1023 (const_int 1) | |
| 1024 (match_operand 3 "const_int_operand" "n")) | |
| 1025 (const_int 0)]) | |
| 1026 (match_operand:SI 4 "reg_or_int5_operand" "rJ") | |
| 1027 (match_operand:SI 5 "reg_or_0_operand" "rI")))] | |
|
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|
1028 "(TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 1029 "tst1 %3,%2 ; cmov %c1,%4,%z5,%0" |
| 1030 [(set_attr "length" "8") | |
| 1031 (set_attr "cc" "clobber")]) | |
| 1032 | |
| 1033 (define_insn "*movsicc_tst1_reversed" | |
| 1034 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1035 (if_then_else:SI | |
| 1036 (match_operator 1 "comparison_operator" | |
| 1037 [(zero_extract:SI | |
| 1038 (match_operand:QI 2 "memory_operand" "m") | |
| 1039 (const_int 1) | |
| 1040 (match_operand 3 "const_int_operand" "n")) | |
| 1041 (const_int 0)]) | |
| 1042 (match_operand:SI 4 "reg_or_0_operand" "rI") | |
| 1043 (match_operand:SI 5 "reg_or_int5_operand" "rJ")))] | |
|
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1044 "(TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 1045 "tst1 %3,%2 ; cmov %C1,%5,%z4,%0" |
| 1046 [(set_attr "length" "8") | |
| 1047 (set_attr "cc" "clobber")]) | |
| 1048 | |
| 1049 ;; Matching for sasf requires combining 4 instructions, so we provide a | |
| 1050 ;; dummy pattern to match the first 3, which will always be turned into the | |
| 1051 ;; second pattern by subsequent combining. As above, we must include the | |
| 1052 ;; comparison to avoid input reloads in an insn using cc0. | |
| 1053 | |
|
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1054 (define_insn "*sasf" |
| 0 | 1055 [(set (match_operand:SI 0 "register_operand" "=r") |
| 1056 (ior:SI | |
| 1057 (match_operator 1 "comparison_operator" | |
| 1058 [(match_operand:SI 3 "register_operand" "r") | |
| 1059 (match_operand:SI 4 "reg_or_int5_operand" "rJ")]) | |
| 1060 (ashift:SI (match_operand:SI 2 "register_operand" "0") | |
|
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1061 (const_int 1)))) |
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1062 (clobber (reg:CC CC_REGNUM))] |
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1063 "(TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 1064 "cmp %4,%3 ; sasf %c1,%0" |
| 1065 [(set_attr "length" "6") | |
| 1066 (set_attr "cc" "clobber")]) | |
| 1067 | |
| 1068 (define_split | |
| 1069 [(set (match_operand:SI 0 "register_operand" "") | |
| 1070 (if_then_else:SI | |
| 1071 (match_operator 1 "comparison_operator" | |
| 1072 [(match_operand:SI 4 "register_operand" "") | |
| 1073 (match_operand:SI 5 "reg_or_int5_operand" "")]) | |
| 1074 (match_operand:SI 2 "const_int_operand" "") | |
|
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1075 (match_operand:SI 3 "const_int_operand" ""))) |
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1076 (clobber (reg:CC CC_REGNUM))] |
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1077 "(TARGET_V850E || TARGET_V850E2_ALL) |
| 0 | 1078 && ((INTVAL (operands[2]) ^ INTVAL (operands[3])) == 1) |
| 1079 && ((INTVAL (operands[2]) + INTVAL (operands[3])) != 1) | |
| 1080 && (GET_CODE (operands[5]) == CONST_INT | |
| 1081 || REGNO (operands[0]) != REGNO (operands[5])) | |
| 1082 && REGNO (operands[0]) != REGNO (operands[4])" | |
| 1083 [(set (match_dup 0) (match_dup 6)) | |
|
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1084 (parallel [(set (match_dup 0) |
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1085 (ior:SI (match_op_dup 7 [(match_dup 4) (match_dup 5)]) |
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1086 (ashift:SI (match_dup 0) (const_int 1)))) |
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1087 (clobber (reg:CC CC_REGNUM))])] |
| 0 | 1088 " |
| 1089 { | |
| 1090 operands[6] = GEN_INT (INTVAL (operands[2]) >> 1); | |
| 1091 if (INTVAL (operands[2]) & 0x1) | |
| 1092 operands[7] = operands[1]; | |
| 1093 else | |
| 1094 operands[7] = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])), | |
| 1095 GET_MODE (operands[1]), | |
| 1096 XEXP (operands[1], 0), XEXP (operands[1], 1)); | |
| 1097 }") | |
|
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1098 |
| 0 | 1099 ;; --------------------------------------------------------------------- |
| 1100 ;; BYTE SWAP INSTRUCTIONS | |
| 1101 ;; --------------------------------------------------------------------- | |
| 1102 (define_expand "rotlhi3" | |
|
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1103 [(parallel [(set (match_operand:HI 0 "register_operand" "") |
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1104 (rotate:HI (match_operand:HI 1 "register_operand" "") |
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1105 (match_operand:HI 2 "const_int_operand" ""))) |
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1106 (clobber (reg:CC CC_REGNUM))])] |
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1107 "(TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 1108 " |
| 1109 { | |
| 1110 if (INTVAL (operands[2]) != 8) | |
| 1111 FAIL; | |
| 1112 }") | |
| 1113 | |
| 1114 (define_insn "*rotlhi3_8" | |
| 1115 [(set (match_operand:HI 0 "register_operand" "=r") | |
| 1116 (rotate:HI (match_operand:HI 1 "register_operand" "r") | |
|
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1117 (const_int 8))) |
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1118 (clobber (reg:CC CC_REGNUM))] |
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1119 "(TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 1120 "bsh %1,%0" |
| 1121 [(set_attr "length" "4") | |
| 1122 (set_attr "cc" "clobber")]) | |
| 1123 | |
| 1124 (define_expand "rotlsi3" | |
|
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1125 [(parallel [(set (match_operand:SI 0 "register_operand" "") |
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1126 (rotate:SI (match_operand:SI 1 "register_operand" "") |
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1127 (match_operand:SI 2 "const_int_operand" ""))) |
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1128 (clobber (reg:CC CC_REGNUM))])] |
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1129 "(TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 1130 " |
| 1131 { | |
| 1132 if (INTVAL (operands[2]) != 16) | |
| 1133 FAIL; | |
| 1134 }") | |
| 1135 | |
| 1136 (define_insn "*rotlsi3_16" | |
| 1137 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1138 (rotate:SI (match_operand:SI 1 "register_operand" "r") | |
|
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1139 (const_int 16))) |
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1140 (clobber (reg:CC CC_REGNUM))] |
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1141 "(TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 1142 "hsw %1,%0" |
| 1143 [(set_attr "length" "4") | |
| 1144 (set_attr "cc" "clobber")]) | |
|
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1145 |
| 0 | 1146 ;; ---------------------------------------------------------------------- |
| 1147 ;; JUMP INSTRUCTIONS | |
| 1148 ;; ---------------------------------------------------------------------- | |
| 1149 | |
| 1150 ;; Conditional jump instructions | |
| 1151 | |
| 1152 (define_insn "*branch_normal" | |
| 1153 [(set (pc) | |
| 1154 (if_then_else (match_operator 1 "comparison_operator" | |
| 1155 [(cc0) (const_int 0)]) | |
| 1156 (label_ref (match_operand 0 "" "")) | |
| 1157 (pc)))] | |
| 1158 "" | |
| 1159 "* | |
| 1160 { | |
| 1161 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 | |
| 1162 && (GET_CODE (operands[1]) == GT | |
| 1163 || GET_CODE (operands[1]) == GE | |
| 1164 || GET_CODE (operands[1]) == LE | |
| 1165 || GET_CODE (operands[1]) == LT)) | |
| 1166 return 0; | |
| 1167 | |
| 1168 if (get_attr_length (insn) == 2) | |
| 1169 return \"b%b1 %l0\"; | |
| 1170 else | |
| 1171 return \"b%B1 .+6 ; jr %l0\"; | |
| 1172 }" | |
| 1173 [(set (attr "length") | |
| 1174 (if_then_else (lt (abs (minus (match_dup 0) (pc))) | |
| 1175 (const_int 256)) | |
| 1176 (const_int 2) | |
| 1177 (const_int 6))) | |
| 1178 (set_attr "cc" "none")]) | |
| 1179 | |
| 1180 (define_insn "*branch_invert" | |
| 1181 [(set (pc) | |
| 1182 (if_then_else (match_operator 1 "comparison_operator" | |
| 1183 [(cc0) (const_int 0)]) | |
| 1184 (pc) | |
| 1185 (label_ref (match_operand 0 "" ""))))] | |
| 1186 "" | |
| 1187 "* | |
| 1188 { | |
| 1189 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 | |
| 1190 && (GET_CODE (operands[1]) == GT | |
| 1191 || GET_CODE (operands[1]) == GE | |
| 1192 || GET_CODE (operands[1]) == LE | |
| 1193 || GET_CODE (operands[1]) == LT)) | |
| 1194 return 0; | |
| 1195 if (get_attr_length (insn) == 2) | |
| 1196 return \"b%B1 %l0\"; | |
| 1197 else | |
| 1198 return \"b%b1 .+6 ; jr %l0\"; | |
| 1199 }" | |
| 1200 [(set (attr "length") | |
| 1201 (if_then_else (lt (abs (minus (match_dup 0) (pc))) | |
| 1202 (const_int 256)) | |
| 1203 (const_int 2) | |
| 1204 (const_int 6))) | |
| 1205 (set_attr "cc" "none")]) | |
| 1206 | |
|
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1207 (define_insn "branch_z_normal" |
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1208 [(set (pc) |
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1209 (if_then_else (match_operand 1 "v850_float_z_comparison_operator" "") |
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1210 (label_ref (match_operand 0 "" "")) |
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1211 (pc)))] |
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1212 "TARGET_V850E2V3" |
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1213 "* |
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1214 { |
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1215 if (get_attr_length (insn) == 2) |
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1216 return \"bz %l0\"; |
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1217 else |
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1218 return \"bnz 1f ; jr %l0 ; 1:\"; |
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1219 }" |
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1220 [(set (attr "length") |
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1221 (if_then_else (lt (abs (minus (match_dup 0) (pc))) |
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1222 (const_int 256)) |
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1223 (const_int 2) |
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1224 (const_int 6))) |
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1225 (set_attr "cc" "none")]) |
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1226 |
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1227 (define_insn "*branch_z_invert" |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1228 [(set (pc) |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1229 (if_then_else (match_operand 1 "v850_float_z_comparison_operator" "") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1230 (pc) |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1231 (label_ref (match_operand 0 "" ""))))] |
|
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parents:
55
diff
changeset
|
1232 "TARGET_V850E2V3" |
|
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parents:
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diff
changeset
|
1233 "* |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1234 { |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1235 if (get_attr_length (insn) == 2) |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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|
1236 return \"bnz %l0\"; |
|
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parents:
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diff
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|
1237 else |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
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|
1238 return \"bz 1f ; jr %l0 ; 1:\"; |
|
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parents:
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diff
changeset
|
1239 }" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1240 [(set (attr "length") |
|
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parents:
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changeset
|
1241 (if_then_else (lt (abs (minus (match_dup 0) (pc))) |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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|
1242 (const_int 256)) |
|
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parents:
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diff
changeset
|
1243 (const_int 2) |
|
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parents:
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diff
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|
1244 (const_int 6))) |
|
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|
1245 (set_attr "cc" "none")]) |
|
f6334be47118
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parents:
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diff
changeset
|
1246 |
|
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parents:
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diff
changeset
|
1247 (define_insn "branch_nz_normal" |
|
f6334be47118
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parents:
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diff
changeset
|
1248 [(set (pc) |
|
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|
1249 (if_then_else (match_operand 1 "v850_float_nz_comparison_operator" "") |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
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|
1250 (label_ref (match_operand 0 "" "")) |
|
f6334be47118
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diff
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|
1251 (pc)))] |
|
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diff
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|
1252 "TARGET_V850E2V3" |
|
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|
1253 "* |
|
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parents:
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diff
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|
1254 { |
|
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parents:
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diff
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|
1255 if (get_attr_length (insn) == 2) |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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|
1256 return \"bnz %l0\"; |
|
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parents:
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diff
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|
1257 else |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
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|
1258 return \"bz 1f ; jr %l0 ; 1:\"; |
|
f6334be47118
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parents:
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diff
changeset
|
1259 }" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
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|
1260 [(set (attr "length") |
|
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parents:
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diff
changeset
|
1261 (if_then_else (lt (abs (minus (match_dup 0) (pc))) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
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parents:
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diff
changeset
|
1262 (const_int 256)) |
|
f6334be47118
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parents:
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diff
changeset
|
1263 (const_int 2) |
|
f6334be47118
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parents:
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diff
changeset
|
1264 (const_int 6))) |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
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|
1265 (set_attr "cc" "none")]) |
|
f6334be47118
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parents:
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diff
changeset
|
1266 |
|
f6334be47118
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parents:
55
diff
changeset
|
1267 (define_insn "*branch_nz_invert" |
|
f6334be47118
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parents:
55
diff
changeset
|
1268 [(set (pc) |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
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|
1269 (if_then_else (match_operand 1 "v850_float_nz_comparison_operator" "") |
|
f6334be47118
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parents:
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diff
changeset
|
1270 (pc) |
|
f6334be47118
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parents:
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diff
changeset
|
1271 (label_ref (match_operand 0 "" ""))))] |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1272 "TARGET_V850E2V3" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1273 "* |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1274 { |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
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|
1275 if (get_attr_length (insn) == 2) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1276 return \"bz %l0\"; |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1277 else |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1278 return \"bnz 1f ; jr %l0 ; 1:\"; |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1279 }" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1280 [(set (attr "length") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1281 (if_then_else (lt (abs (minus (match_dup 0) (pc))) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
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parents:
55
diff
changeset
|
1282 (const_int 256)) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1283 (const_int 2) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
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parents:
55
diff
changeset
|
1284 (const_int 6))) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
changeset
|
1285 (set_attr "cc" "none")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1286 |
| 0 | 1287 ;; Unconditional and other jump instructions. |
| 1288 | |
| 1289 (define_insn "jump" | |
| 1290 [(set (pc) | |
| 1291 (label_ref (match_operand 0 "" "")))] | |
| 1292 "" | |
| 1293 "* | |
| 1294 { | |
|
67
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1295 if (get_attr_length (insn) == 2) |
| 0 | 1296 return \"br %0\"; |
| 1297 else | |
| 1298 return \"jr %0\"; | |
| 1299 }" | |
| 1300 [(set (attr "length") | |
| 1301 (if_then_else (lt (abs (minus (match_dup 0) (pc))) | |
| 1302 (const_int 256)) | |
| 1303 (const_int 2) | |
| 1304 (const_int 4))) | |
| 1305 (set_attr "cc" "none")]) | |
| 1306 | |
| 1307 (define_insn "indirect_jump" | |
| 1308 [(set (pc) (match_operand:SI 0 "register_operand" "r"))] | |
| 1309 "" | |
| 1310 "jmp %0" | |
| 1311 [(set_attr "length" "2") | |
| 1312 (set_attr "cc" "none")]) | |
| 1313 | |
| 1314 (define_insn "tablejump" | |
| 1315 [(set (pc) (match_operand:SI 0 "register_operand" "r")) | |
| 1316 (use (label_ref (match_operand 1 "" "")))] | |
| 1317 "" | |
| 1318 "jmp %0" | |
| 1319 [(set_attr "length" "2") | |
| 1320 (set_attr "cc" "none")]) | |
| 1321 | |
| 1322 (define_insn "switch" | |
| 1323 [(set (pc) | |
| 1324 (plus:SI | |
| 1325 (sign_extend:SI | |
|
67
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diff
changeset
|
1326 (mem:HI |
|
f6334be47118
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diff
changeset
|
1327 (plus:SI (ashift:SI (match_operand:SI 0 "register_operand" "r") |
|
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diff
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|
1328 (const_int 1)) |
|
f6334be47118
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diff
changeset
|
1329 (label_ref (match_operand 1 "" ""))))) |
|
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55
diff
changeset
|
1330 (label_ref (match_dup 1))))] |
|
f6334be47118
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55
diff
changeset
|
1331 "(TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 1332 "switch %0" |
| 1333 [(set_attr "length" "2") | |
| 1334 (set_attr "cc" "none")]) | |
| 1335 | |
| 1336 (define_expand "casesi" | |
| 1337 [(match_operand:SI 0 "register_operand" "") | |
| 1338 (match_operand:SI 1 "register_operand" "") | |
| 1339 (match_operand:SI 2 "register_operand" "") | |
| 1340 (match_operand 3 "" "") (match_operand 4 "" "")] | |
| 1341 "" | |
| 1342 " | |
| 1343 { | |
| 1344 rtx reg = gen_reg_rtx (SImode); | |
| 1345 rtx tableaddress = gen_reg_rtx (SImode); | |
|
55
77e2b8dfacca
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0
diff
changeset
|
1346 rtx test; |
| 0 | 1347 rtx mem; |
| 1348 | |
| 1349 /* Subtract the lower bound from the index. */ | |
| 1350 emit_insn (gen_subsi3 (reg, operands[0], operands[1])); | |
|
55
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diff
changeset
|
1351 |
|
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0
diff
changeset
|
1352 /* Compare the result against the number of table entries; |
|
77e2b8dfacca
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parents:
0
diff
changeset
|
1353 branch to the default label if out of range of the table. */ |
|
77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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0
diff
changeset
|
1354 test = gen_rtx_fmt_ee (GTU, VOIDmode, reg, operands[2]); |
|
77e2b8dfacca
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diff
changeset
|
1355 emit_jump_insn (gen_cbranchsi4 (test, reg, operands[2], operands[4])); |
| 0 | 1356 |
| 1357 /* Shift index for the table array access. */ | |
| 1358 emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1))); | |
| 1359 /* Load the table address into a pseudo. */ | |
| 1360 emit_insn (gen_movsi (tableaddress, | |
| 1361 gen_rtx_LABEL_REF (Pmode, operands[3]))); | |
| 1362 /* Add the table address to the index. */ | |
| 1363 emit_insn (gen_addsi3 (reg, reg, tableaddress)); | |
| 1364 /* Load the table entry. */ | |
| 1365 mem = gen_const_mem (CASE_VECTOR_MODE, reg); | |
| 1366 if (! TARGET_BIG_SWITCH) | |
| 1367 { | |
| 1368 rtx reg2 = gen_reg_rtx (HImode); | |
| 1369 emit_insn (gen_movhi (reg2, mem)); | |
| 1370 emit_insn (gen_extendhisi2 (reg, reg2)); | |
| 1371 } | |
| 1372 else | |
| 1373 emit_insn (gen_movsi (reg, mem)); | |
| 1374 /* Add the table address. */ | |
| 1375 emit_insn (gen_addsi3 (reg, reg, tableaddress)); | |
| 1376 /* Branch to the switch label. */ | |
| 1377 emit_jump_insn (gen_tablejump (reg, operands[3])); | |
| 1378 DONE; | |
| 1379 }") | |
| 1380 | |
| 1381 ;; Call subroutine with no return value. | |
| 1382 | |
| 1383 (define_expand "call" | |
| 1384 [(call (match_operand:QI 0 "general_operand" "") | |
| 1385 (match_operand:SI 1 "general_operand" ""))] | |
| 1386 "" | |
| 1387 " | |
| 1388 { | |
| 1389 if (! call_address_operand (XEXP (operands[0], 0), QImode) | |
| 1390 || TARGET_LONG_CALLS) | |
| 1391 XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0)); | |
| 1392 if (TARGET_LONG_CALLS) | |
| 1393 emit_call_insn (gen_call_internal_long (XEXP (operands[0], 0), operands[1])); | |
| 1394 else | |
| 1395 emit_call_insn (gen_call_internal_short (XEXP (operands[0], 0), operands[1])); | |
| 1396 | |
| 1397 DONE; | |
| 1398 }") | |
| 1399 | |
| 1400 (define_insn "call_internal_short" | |
| 1401 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r")) | |
| 1402 (match_operand:SI 1 "general_operand" "g,g")) | |
| 1403 (clobber (reg:SI 31))] | |
| 1404 "! TARGET_LONG_CALLS" | |
| 1405 "@ | |
| 1406 jarl %0,r31 | |
| 1407 jarl .+4,r31 ; add 4,r31 ; jmp %0" | |
|
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|
1408 [(set_attr "length" "4,8") |
|
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|
1409 (set_attr "cc" "clobber,clobber")] |
| 0 | 1410 ) |
| 1411 | |
| 1412 (define_insn "call_internal_long" | |
| 1413 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r")) | |
| 1414 (match_operand:SI 1 "general_operand" "g,g")) | |
| 1415 (clobber (reg:SI 31))] | |
| 1416 "TARGET_LONG_CALLS" | |
| 1417 "* | |
| 1418 { | |
| 1419 if (which_alternative == 0) | |
| 1420 { | |
| 1421 if (GET_CODE (operands[0]) == REG) | |
| 1422 return \"jarl %0,r31\"; | |
| 1423 else | |
| 1424 return \"movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11\"; | |
| 1425 } | |
| 1426 else | |
| 1427 return \"jarl .+4,r31 ; add 4,r31 ; jmp %0\"; | |
| 1428 }" | |
|
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|
1429 [(set_attr "length" "16,8") |
|
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|
1430 (set_attr "cc" "clobber,clobber")] |
| 0 | 1431 ) |
| 1432 | |
| 1433 ;; Call subroutine, returning value in operand 0 | |
| 1434 ;; (which must be a hard register). | |
| 1435 | |
| 1436 (define_expand "call_value" | |
| 1437 [(set (match_operand 0 "" "") | |
| 1438 (call (match_operand:QI 1 "general_operand" "") | |
| 1439 (match_operand:SI 2 "general_operand" "")))] | |
| 1440 "" | |
| 1441 " | |
| 1442 { | |
| 1443 if (! call_address_operand (XEXP (operands[1], 0), QImode) | |
| 1444 || TARGET_LONG_CALLS) | |
| 1445 XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0)); | |
| 1446 if (TARGET_LONG_CALLS) | |
| 1447 emit_call_insn (gen_call_value_internal_long (operands[0], | |
| 1448 XEXP (operands[1], 0), | |
| 1449 operands[2])); | |
| 1450 else | |
| 1451 emit_call_insn (gen_call_value_internal_short (operands[0], | |
| 1452 XEXP (operands[1], 0), | |
| 1453 operands[2])); | |
| 1454 DONE; | |
| 1455 }") | |
| 1456 | |
| 1457 (define_insn "call_value_internal_short" | |
| 1458 [(set (match_operand 0 "" "=r,r") | |
| 1459 (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r")) | |
| 1460 (match_operand:SI 2 "general_operand" "g,g"))) | |
| 1461 (clobber (reg:SI 31))] | |
| 1462 "! TARGET_LONG_CALLS" | |
| 1463 "@ | |
| 1464 jarl %1,r31 | |
| 1465 jarl .+4,r31 ; add 4,r31 ; jmp %1" | |
|
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|
1466 [(set_attr "length" "4,8") |
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|
1467 (set_attr "cc" "clobber,clobber")] |
| 0 | 1468 ) |
| 1469 | |
| 1470 (define_insn "call_value_internal_long" | |
| 1471 [(set (match_operand 0 "" "=r,r") | |
| 1472 (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r")) | |
| 1473 (match_operand:SI 2 "general_operand" "g,g"))) | |
| 1474 (clobber (reg:SI 31))] | |
| 1475 "TARGET_LONG_CALLS" | |
| 1476 "* | |
| 1477 { | |
| 1478 if (which_alternative == 0) | |
| 1479 { | |
| 1480 if (GET_CODE (operands[1]) == REG) | |
| 1481 return \"jarl %1, r31\"; | |
| 1482 else | |
| 1483 /* Reload can generate this pattern.... */ | |
| 1484 return \"movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11\"; | |
| 1485 } | |
| 1486 else | |
| 1487 return \"jarl .+4, r31 ; add 4, r31 ; jmp %1\"; | |
| 1488 }" | |
|
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|
1489 [(set_attr "length" "16,8") |
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|
1490 (set_attr "cc" "clobber,clobber")] |
| 0 | 1491 ) |
| 1492 | |
| 1493 (define_insn "nop" | |
| 1494 [(const_int 0)] | |
| 1495 "" | |
| 1496 "nop" | |
| 1497 [(set_attr "length" "2") | |
| 1498 (set_attr "cc" "none")]) | |
| 1499 | |
| 1500 ;; ---------------------------------------------------------------------- | |
| 1501 ;; EXTEND INSTRUCTIONS | |
| 1502 ;; ---------------------------------------------------------------------- | |
| 1503 | |
| 1504 (define_insn "" | |
| 1505 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") | |
| 1506 (zero_extend:SI | |
|
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|
1507 (match_operand:HI 1 "nonimmediate_operand" "0,r,T,m"))) |
|
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|
1508 (clobber (reg:CC CC_REGNUM))] |
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|
1509 "(TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 1510 "@ |
| 1511 zxh %0 | |
| 1512 andi 65535,%1,%0 | |
| 1513 sld.hu %1,%0 | |
| 1514 ld.hu %1,%0" | |
| 1515 [(set_attr "length" "2,4,2,4") | |
|
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|
1516 (set_attr "cc" "none_0hit,set_zn,none_0hit,none_0hit")]) |
| 0 | 1517 |
| 1518 (define_insn "zero_extendhisi2" | |
| 1519 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1520 (zero_extend:SI | |
|
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|
1521 (match_operand:HI 1 "register_operand" "r"))) |
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|
1522 (clobber (reg:CC CC_REGNUM))] |
| 0 | 1523 "" |
| 1524 "andi 65535,%1,%0" | |
| 1525 [(set_attr "length" "4") | |
|
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|
1526 (set_attr "cc" "set_zn")]) |
| 0 | 1527 |
| 1528 (define_insn "" | |
| 1529 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") | |
| 1530 (zero_extend:SI | |
|
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|
1531 (match_operand:QI 1 "nonimmediate_operand" "0,r,T,m"))) |
|
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|
1532 (clobber (reg:CC CC_REGNUM))] |
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|
1533 "(TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 1534 "@ |
| 1535 zxb %0 | |
| 1536 andi 255,%1,%0 | |
| 1537 sld.bu %1,%0 | |
| 1538 ld.bu %1,%0" | |
| 1539 [(set_attr "length" "2,4,2,4") | |
|
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|
1540 (set_attr "cc" "none_0hit,set_zn,none_0hit,none_0hit")]) |
| 0 | 1541 |
| 1542 (define_insn "zero_extendqisi2" | |
| 1543 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1544 (zero_extend:SI | |
|
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|
1545 (match_operand:QI 1 "register_operand" "r"))) |
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|
1546 (clobber (reg:CC CC_REGNUM))] |
| 0 | 1547 "" |
| 1548 "andi 255,%1,%0" | |
| 1549 [(set_attr "length" "4") | |
|
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|
1550 (set_attr "cc" "set_zn")]) |
| 0 | 1551 |
| 1552 ;;- sign extension instructions | |
| 1553 | |
| 1554 ;; ??? The extendhisi2 pattern should not emit shifts for v850e? | |
| 1555 | |
| 1556 (define_insn "*extendhisi_insn" | |
| 1557 [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
|
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|
1558 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,Q,m"))) |
|
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|
1559 (clobber (reg:CC CC_REGNUM))] |
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|
1560 "(TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 1561 "@ |
| 1562 sxh %0 | |
| 1563 sld.h %1,%0 | |
| 1564 ld.h %1,%0" | |
| 1565 [(set_attr "length" "2,2,4") | |
| 1566 (set_attr "cc" "none_0hit,none_0hit,none_0hit")]) | |
| 1567 | |
| 1568 ;; ??? This is missing a sign extend from memory pattern to match the ld.h | |
| 1569 ;; instruction. | |
| 1570 | |
| 1571 (define_expand "extendhisi2" | |
|
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|
1572 [(parallel [(set (match_dup 2) |
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|
1573 (ashift:SI (match_operand:HI 1 "register_operand" "") |
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|
1574 (const_int 16))) |
|
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|
1575 (clobber (reg:CC CC_REGNUM))]) |
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|
1576 (parallel [(set (match_operand:SI 0 "register_operand" "") |
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|
1577 (ashiftrt:SI (match_dup 2) |
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|
1578 (const_int 16))) |
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|
1579 (clobber (reg:CC CC_REGNUM))])] |
| 0 | 1580 "" |
| 1581 " | |
| 1582 { | |
| 1583 operands[1] = gen_lowpart (SImode, operands[1]); | |
| 1584 operands[2] = gen_reg_rtx (SImode); | |
| 1585 }") | |
| 1586 | |
| 1587 ;; ??? The extendqisi2 pattern should not emit shifts for v850e? | |
| 1588 | |
| 1589 (define_insn "*extendqisi_insn" | |
| 1590 [(set (match_operand:SI 0 "register_operand" "=r,r,r") | |
|
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|
1591 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,Q,m"))) |
|
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|
1592 (clobber (reg:CC CC_REGNUM))] |
|
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|
1593 "(TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 1594 "@ |
| 1595 sxb %0 | |
| 1596 sld.b %1,%0 | |
| 1597 ld.b %1,%0" | |
| 1598 [(set_attr "length" "2,2,4") | |
| 1599 (set_attr "cc" "none_0hit,none_0hit,none_0hit")]) | |
| 1600 | |
| 1601 ;; ??? This is missing a sign extend from memory pattern to match the ld.b | |
| 1602 ;; instruction. | |
| 1603 | |
| 1604 (define_expand "extendqisi2" | |
|
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|
1605 [(parallel [(set (match_dup 2) |
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|
1606 (ashift:SI (match_operand:QI 1 "register_operand" "") |
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|
1607 (const_int 24))) |
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|
1608 (clobber (reg:CC CC_REGNUM))]) |
|
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|
1609 (parallel [(set (match_operand:SI 0 "register_operand" "") |
|
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|
1610 (ashiftrt:SI (match_dup 2) |
|
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|
1611 (const_int 24))) |
|
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|
1612 (clobber (reg:CC CC_REGNUM))])] |
| 0 | 1613 "" |
| 1614 " | |
| 1615 { | |
| 1616 operands[1] = gen_lowpart (SImode, operands[1]); | |
| 1617 operands[2] = gen_reg_rtx (SImode); | |
| 1618 }") | |
| 1619 | |
| 1620 ;; ---------------------------------------------------------------------- | |
| 1621 ;; SHIFTS | |
| 1622 ;; ---------------------------------------------------------------------- | |
| 1623 | |
| 1624 (define_insn "ashlsi3" | |
| 1625 [(set (match_operand:SI 0 "register_operand" "=r,r") | |
|
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|
1626 (ashift:SI |
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|
1627 (match_operand:SI 1 "register_operand" "0,0") |
|
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|
1628 (match_operand:SI 2 "nonmemory_operand" "r,N"))) |
|
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|
1629 (clobber (reg:CC CC_REGNUM))] |
| 0 | 1630 "" |
| 1631 "@ | |
| 1632 shl %2,%0 | |
| 1633 shl %2,%0" | |
| 1634 [(set_attr "length" "4,2") | |
|
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|
1635 (set_attr "cc" "set_zn")]) |
|
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|
1636 |
|
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|
1637 (define_insn "ashlsi3_v850e2" |
|
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|
1638 [(set (match_operand:SI 0 "register_operand" "=r") |
|
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|
1639 (ashift:SI |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
changeset
|
1640 (match_operand:SI 1 "register_operand" "r") |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
changeset
|
1641 (match_operand:SI 2 "nonmemory_operand" "r"))) |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
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|
1642 (clobber (reg:CC CC_REGNUM))] |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
changeset
|
1643 "TARGET_V850E2_ALL" |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1644 "shl %2,%1,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1645 [(set_attr "length" "4") |
| 0 | 1646 (set_attr "cc" "set_znv")]) |
| 1647 | |
| 1648 (define_insn "lshrsi3" | |
| 1649 [(set (match_operand:SI 0 "register_operand" "=r,r") | |
|
67
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diff
changeset
|
1650 (lshiftrt:SI |
|
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55
diff
changeset
|
1651 (match_operand:SI 1 "register_operand" "0,0") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
changeset
|
1652 (match_operand:SI 2 "nonmemory_operand" "r,N"))) |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
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|
1653 (clobber (reg:CC CC_REGNUM))] |
| 0 | 1654 "" |
| 1655 "@ | |
| 1656 shr %2,%0 | |
| 1657 shr %2,%0" | |
| 1658 [(set_attr "length" "4,2") | |
|
67
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55
diff
changeset
|
1659 (set_attr "cc" "set_zn")]) |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
changeset
|
1660 |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
changeset
|
1661 (define_insn "lshrsi3_v850e2" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
changeset
|
1662 [(set (match_operand:SI 0 "register_operand" "=r") |
|
f6334be47118
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changeset
|
1663 (lshiftrt:SI |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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changeset
|
1664 (match_operand:SI 1 "register_operand" "r") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
changeset
|
1665 (match_operand:SI 2 "nonmemory_operand" "r"))) |
|
f6334be47118
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|
1666 (clobber (reg:CC CC_REGNUM))] |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff
changeset
|
1667 "TARGET_V850E2_ALL" |
|
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changeset
|
1668 "shr %2,%1,%0" |
|
f6334be47118
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|
1669 [(set_attr "length" "4") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
1670 (set_attr "cc" "set_zn")]) |
| 0 | 1671 |
| 1672 (define_insn "ashrsi3" | |
| 1673 [(set (match_operand:SI 0 "register_operand" "=r,r") | |
|
67
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changeset
|
1674 (ashiftrt:SI |
|
f6334be47118
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changeset
|
1675 (match_operand:SI 1 "register_operand" "0,0") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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changeset
|
1676 (match_operand:SI 2 "nonmemory_operand" "r,N"))) |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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|
1677 (clobber (reg:CC CC_REGNUM))] |
| 0 | 1678 "" |
| 1679 "@ | |
| 1680 sar %2,%0 | |
| 1681 sar %2,%0" | |
| 1682 [(set_attr "length" "4,2") | |
|
67
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
changeset
|
1683 (set_attr "cc" "set_zn, set_zn")]) |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1684 |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1685 (define_insn "ashrsi3_v850e2" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1686 [(set (match_operand:SI 0 "register_operand" "=r") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1687 (ashiftrt:SI |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
changeset
|
1688 (match_operand:SI 1 "register_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1689 (match_operand:SI 2 "nonmemory_operand" "r"))) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1690 (clobber (reg:CC CC_REGNUM))] |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1691 "TARGET_V850E2_ALL" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
changeset
|
1692 "sar %2,%1,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1693 [(set_attr "length" "4") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1694 (set_attr "cc" "set_zn")]) |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1695 |
|
f6334be47118
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parents:
55
diff
changeset
|
1696 ;; ---------------------------------------------------------------------- |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
1697 ;; FIND FIRST BIT INSTRUCTION |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1698 ;; ---------------------------------------------------------------------- |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1699 |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1700 (define_insn "ffssi2" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1701 [(set (match_operand:SI 0 "register_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1702 (ffs:SI (match_operand:SI 1 "register_operand" "r"))) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1703 (clobber (reg:CC CC_REGNUM))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1704 "TARGET_V850E2_ALL" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1705 "sch1r %1,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1706 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1707 (set_attr "cc" "clobber")]) |
| 0 | 1708 |
| 1709 ;; ---------------------------------------------------------------------- | |
| 1710 ;; PROLOGUE/EPILOGUE | |
| 1711 ;; ---------------------------------------------------------------------- | |
| 1712 (define_expand "prologue" | |
| 1713 [(const_int 0)] | |
| 1714 "" | |
| 1715 "expand_prologue (); DONE;") | |
| 1716 | |
| 1717 (define_expand "epilogue" | |
| 1718 [(return)] | |
| 1719 "" | |
| 1720 " | |
| 1721 { | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1722 expand_epilogue (); |
| 0 | 1723 DONE; |
| 1724 }") | |
| 1725 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1726 (define_insn "return_simple" |
| 0 | 1727 [(return)] |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1728 "reload_completed" |
| 0 | 1729 "jmp [r31]" |
| 1730 [(set_attr "length" "2") | |
| 1731 (set_attr "cc" "none")]) | |
| 1732 | |
| 1733 (define_insn "return_internal" | |
| 1734 [(return) | |
| 1735 (use (reg:SI 31))] | |
| 1736 "" | |
| 1737 "jmp [r31]" | |
| 1738 [(set_attr "length" "2") | |
| 1739 (set_attr "cc" "none")]) | |
| 1740 | |
|
67
f6334be47118
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diff
changeset
|
1741 ;; ---------------------------------------------------------------------- |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1742 ;; v850e2V3 floating-point hardware support |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
changeset
|
1743 ;; ---------------------------------------------------------------------- |
| 0 | 1744 |
|
67
f6334be47118
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diff
changeset
|
1745 |
|
f6334be47118
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55
diff
changeset
|
1746 (define_insn "addsf3" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1747 [(set (match_operand:SF 0 "register_operand" "=r") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
changeset
|
1748 (plus:SF (match_operand:SF 1 "register_operand" "r") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
changeset
|
1749 (match_operand:SF 2 "register_operand" "r")))] |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1750 "TARGET_V850E2V3" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1751 "addf.s %1,%2,%0" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
changeset
|
1752 [(set_attr "length" "4") |
|
f6334be47118
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55
diff
changeset
|
1753 (set_attr "cc" "none_0hit") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
changeset
|
1754 (set_attr "type" "fpu")]) |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1755 |
|
f6334be47118
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parents:
55
diff
changeset
|
1756 (define_insn "adddf3" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1757 [(set (match_operand:DF 0 "even_reg_operand" "=r") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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55
diff
changeset
|
1758 (plus:DF (match_operand:DF 1 "even_reg_operand" "r") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1759 (match_operand:DF 2 "even_reg_operand" "r")))] |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1760 "TARGET_V850E2V3" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1761 "addf.d %1,%2,%0" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1762 [(set_attr "length" "4") |
|
f6334be47118
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parents:
55
diff
changeset
|
1763 (set_attr "cc" "none_0hit") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1764 (set_attr "type" "fpu")]) |
|
f6334be47118
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parents:
55
diff
changeset
|
1765 |
|
f6334be47118
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parents:
55
diff
changeset
|
1766 (define_insn "subsf3" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1767 [(set (match_operand:SF 0 "register_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1768 (minus:SF (match_operand:SF 1 "register_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1769 (match_operand:SF 2 "register_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1770 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1771 "subf.s %2,%1,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1772 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1773 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1774 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1775 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1776 (define_insn "subdf3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1777 [(set (match_operand:DF 0 "even_reg_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1778 (minus:DF (match_operand:DF 1 "even_reg_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1779 (match_operand:DF 2 "even_reg_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1780 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1781 "subf.d %2,%1,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1782 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1783 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1784 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1785 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1786 (define_insn "mulsf3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1787 [(set (match_operand:SF 0 "register_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1788 (mult:SF (match_operand:SF 1 "register_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1789 (match_operand:SF 2 "register_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1790 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1791 "mulf.s %1,%2,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1792 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1793 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1794 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1795 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1796 (define_insn "muldf3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1797 [(set (match_operand:DF 0 "even_reg_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1798 (mult:DF (match_operand:DF 1 "even_reg_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1799 (match_operand:DF 2 "even_reg_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1800 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1801 "mulf.d %1,%2,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1802 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1803 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1804 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1805 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1806 (define_insn "divsf3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1807 [(set (match_operand:SF 0 "register_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1808 (div:SF (match_operand:SF 1 "register_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1809 (match_operand:SF 2 "register_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1810 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1811 "divf.s %2,%1,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1812 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1813 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1814 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1815 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1816 (define_insn "divdf3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1817 [(set (match_operand:DF 0 "register_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1818 (div:DF (match_operand:DF 1 "even_reg_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1819 (match_operand:DF 2 "even_reg_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1820 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1821 "divf.d %2,%1,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1822 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1823 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1824 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1825 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1826 (define_insn "minsf3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1827 [(set (match_operand:SF 0 "register_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1828 (smin:SF (match_operand:SF 1 "reg_or_0_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1829 (match_operand:SF 2 "reg_or_0_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1830 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1831 "minf.s %z1,%z2,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1832 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1833 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1834 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1835 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1836 (define_insn "mindf3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1837 [(set (match_operand:DF 0 "even_reg_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1838 (smin:DF (match_operand:DF 1 "even_reg_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1839 (match_operand:DF 2 "even_reg_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1840 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1841 "minf.d %1,%2,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1842 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1843 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1844 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1845 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1846 (define_insn "maxsf3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1847 [(set (match_operand:SF 0 "register_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1848 (smax:SF (match_operand:SF 1 "reg_or_0_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1849 (match_operand:SF 2 "reg_or_0_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1850 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1851 "maxf.s %z1,%z2,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1852 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
1853 (set_attr "cc" "none_0hit") |
|
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1854 (set_attr "type" "fpu")]) |
|
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|
1855 |
|
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|
1856 (define_insn "maxdf3" |
|
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1857 [(set (match_operand:DF 0 "even_reg_operand" "=r") |
|
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|
1858 (smax:DF (match_operand:DF 1 "even_reg_operand" "r") |
|
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1859 (match_operand:DF 2 "even_reg_operand" "r")))] |
|
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|
1860 "TARGET_V850E2V3" |
|
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|
1861 "maxf.d %1,%2,%0" |
|
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|
1862 [(set_attr "length" "4") |
|
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|
1863 (set_attr "cc" "none_0hit") |
|
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|
1864 (set_attr "type" "fpu")]) |
|
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|
1865 |
|
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|
1866 (define_insn "abssf2" |
|
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1867 [(set (match_operand:SF 0 "register_operand" "=r") |
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1868 (abs:SF (match_operand:SF 1 "register_operand" "r")))] |
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|
1869 "TARGET_V850E2V3" |
|
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|
1870 "absf.s %1,%0" |
|
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|
1871 [(set_attr "length" "4") |
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1872 (set_attr "cc" "none_0hit") |
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|
1873 (set_attr "type" "fpu")]) |
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|
1874 |
|
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1875 (define_insn "absdf2" |
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1876 [(set (match_operand:DF 0 "even_reg_operand" "=r") |
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|
1877 (abs:DF (match_operand:DF 1 "even_reg_operand" "r")))] |
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|
1878 "TARGET_V850E2V3" |
|
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|
1879 "absf.d %1,%0" |
|
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1880 [(set_attr "length" "4") |
|
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1881 (set_attr "cc" "none_0hit") |
|
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|
1882 (set_attr "type" "fpu")]) |
|
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|
1883 |
|
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|
1884 (define_insn "negsf2" |
|
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1885 [(set (match_operand:SF 0 "register_operand" "=r") |
|
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|
1886 (neg:SF (match_operand:SF 1 "register_operand" "r")))] |
|
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1887 "TARGET_V850E2V3" |
|
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1888 "negf.s %1,%0" |
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1889 [(set_attr "length" "4") |
|
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1890 (set_attr "cc" "none_0hit") |
|
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1891 (set_attr "type" "fpu")]) |
|
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|
1892 |
|
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1893 (define_insn "negdf2" |
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1894 [(set (match_operand:DF 0 "even_reg_operand" "=r") |
|
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1895 (neg:DF (match_operand:DF 1 "even_reg_operand" "r")))] |
|
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|
1896 "TARGET_V850E2V3" |
|
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|
1897 "negf.d %1,%0" |
|
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1898 [(set_attr "length" "4") |
|
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1899 (set_attr "cc" "none_0hit") |
|
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1900 (set_attr "type" "fpu")]) |
|
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|
1901 |
|
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|
1902 ;; square-root |
|
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|
1903 (define_insn "sqrtsf2" |
|
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1904 [(set (match_operand:SF 0 "register_operand" "=r") |
|
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|
1905 (sqrt:SF (match_operand:SF 1 "register_operand" "r")))] |
|
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|
1906 "TARGET_V850E2V3" |
|
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|
1907 "sqrtf.s %1,%0" |
|
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1908 [(set_attr "length" "4") |
|
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1909 (set_attr "cc" "none_0hit") |
|
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1910 (set_attr "type" "fpu")]) |
|
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changeset
|
1911 |
|
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diff
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|
1912 (define_insn "sqrtdf2" |
|
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1913 [(set (match_operand:DF 0 "even_reg_operand" "=r") |
|
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1914 (sqrt:DF (match_operand:DF 1 "even_reg_operand" "r")))] |
|
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1915 "TARGET_V850E2V3" |
|
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|
1916 "sqrtf.d %1,%0" |
|
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1917 [(set_attr "length" "4") |
|
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1918 (set_attr "cc" "none_0hit") |
|
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1919 (set_attr "type" "fpu")]) |
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1920 |
|
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1921 ;; float -> int |
|
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1922 (define_insn "fix_truncsfsi2" |
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1923 [(set (match_operand:SI 0 "register_operand" "=r") |
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1924 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "r"))))] |
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1925 "TARGET_V850E2V3" |
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1926 "trncf.sw %1,%0" |
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1927 [(set_attr "length" "4") |
|
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1928 (set_attr "cc" "none_0hit") |
|
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1929 (set_attr "type" "fpu")]) |
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|
1930 |
|
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1931 (define_insn "fix_truncdfsi2" |
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1932 [(set (match_operand:SI 0 "register_operand" "=r") |
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1933 (fix:SI (fix:DF (match_operand:DF 1 "even_reg_operand" "r"))))] |
|
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1934 "TARGET_V850E2V3" |
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1935 "trncf.dw %1,%0" |
|
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1936 [(set_attr "length" "4") |
|
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1937 (set_attr "cc" "none_0hit") |
|
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1938 (set_attr "type" "fpu")]) |
|
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|
1939 |
|
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1940 ;; int -> float |
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1941 (define_insn "floatsisf2" |
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1942 [(set (match_operand:SF 0 "register_operand" "=r") |
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1943 (float:SF (match_operand:SI 1 "reg_or_0_operand" "rI")))] |
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1944 "TARGET_V850E2V3" |
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1945 "cvtf.ws %z1, %0" |
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1946 [(set_attr "length" "4") |
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1947 (set_attr "cc" "none_0hit") |
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1948 (set_attr "type" "fpu")]) |
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1949 |
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1950 (define_insn "floatsidf2" |
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1951 [(set (match_operand:DF 0 "even_reg_operand" "=r") |
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1952 (float:DF (match_operand:SI 1 "reg_or_0_operand" "rI")))] |
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1953 "TARGET_V850E2V3" |
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1954 "cvtf.wd %z1,%0" |
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1955 [(set_attr "length" "4") |
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1956 (set_attr "cc" "none_0hit") |
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1957 (set_attr "type" "fpu")]) |
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1958 |
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1959 ;; single-float -> double-float |
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1960 (define_insn "extendsfdf2" |
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1961 [(set (match_operand:DF 0 "even_reg_operand" "=r") |
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1962 (float_extend:DF |
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1963 (match_operand:SF 1 "reg_or_0_operand" "rI")))] |
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1964 "TARGET_V850E2V3" |
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1965 "cvtf.sd %z1,%0" |
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1966 [(set_attr "length" "4") |
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1967 (set_attr "cc" "none_0hit") |
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1968 (set_attr "type" "fpu")]) |
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1969 |
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1970 ;; double-float -> single-float |
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1971 (define_insn "truncdfsf2" |
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1972 [(set (match_operand:SF 0 "register_operand" "=r") |
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1973 (float_truncate:SF |
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1974 (match_operand:DF 1 "even_reg_operand" "r")))] |
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1975 "TARGET_V850E2V3" |
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1976 "cvtf.ds %1,%0" |
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1977 [(set_attr "length" "4") |
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1978 (set_attr "cc" "none_0hit") |
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1979 (set_attr "type" "fpu")]) |
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1980 |
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1981 ;; |
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1982 ;; ---------------- special insns |
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1983 ;; |
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1984 |
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1985 ;;; reciprocal |
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1986 (define_insn "recipsf2" |
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1987 [(set (match_operand:SF 0 "register_operand" "=r") |
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1988 (div:SF (match_operand:SF 1 "const_float_1_operand" "") |
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1989 (match_operand:SF 2 "register_operand" "r")))] |
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1990 "TARGET_V850E2V3" |
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1991 "recipf.s %2,%0" |
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1992 [(set_attr "length" "4") |
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1993 (set_attr "cc" "none_0hit") |
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1994 (set_attr "type" "fpu")]) |
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1995 |
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1996 (define_insn "recipdf2" |
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1997 [(set (match_operand:DF 0 "even_reg_operand" "=r") |
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1998 (div:DF (match_operand:DF 1 "const_float_1_operand" "") |
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1999 (match_operand:DF 2 "even_reg_operand" "r")))] |
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2000 "TARGET_V850E2V3" |
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2001 "recipf.d %2,%0" |
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2002 [(set_attr "length" "4") |
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2003 (set_attr "cc" "none_0hit") |
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2004 (set_attr "type" "fpu")]) |
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2005 |
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2006 ;;; reciprocal of square-root |
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2007 (define_insn "rsqrtsf2" |
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2008 [(set (match_operand:SF 0 "register_operand" "=r") |
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2009 (div:SF (match_operand:SF 1 "const_float_1_operand" "") |
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2010 (sqrt:SF (match_operand:SF 2 "register_operand" "r"))))] |
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2011 "TARGET_V850E2V3" |
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2012 "rsqrtf.s %2,%0" |
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2013 [(set_attr "length" "4") |
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2014 (set_attr "cc" "none_0hit") |
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2015 (set_attr "type" "fpu")]) |
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2016 |
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2017 (define_insn "rsqrtdf2" |
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2018 [(set (match_operand:DF 0 "even_reg_operand" "=r") |
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2019 (div:DF (match_operand:DF 1 "const_float_1_operand" "") |
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2020 (sqrt:DF (match_operand:DF 2 "even_reg_operand" "r"))))] |
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2021 "TARGET_V850E2V3" |
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2022 "rsqrtf.d %2,%0" |
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2023 [(set_attr "length" "4") |
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2024 (set_attr "cc" "none_0hit") |
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2025 (set_attr "type" "fpu")]) |
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2026 |
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2027 ;;; multiply-add |
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2028 (define_insn "fmasf4" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2029 [(set (match_operand:SF 0 "register_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2030 (fma:SF (match_operand:SF 1 "register_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2031 (match_operand:SF 2 "register_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2032 (match_operand:SF 3 "register_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2033 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2034 "maddf.s %2,%1,%3,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2035 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2036 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2037 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2038 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2039 ;;; multiply-subtract |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2040 (define_insn "fmssf4" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2041 [(set (match_operand:SF 0 "register_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2042 (fma:SF (match_operand:SF 1 "register_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2043 (match_operand:SF 2 "register_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2044 (neg:SF (match_operand:SF 3 "register_operand" "r"))))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2045 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2046 "msubf.s %2,%1,%3,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2047 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2048 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2049 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2050 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2051 ;;; negative-multiply-add |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2052 (define_insn "fnmasf4" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2053 [(set (match_operand:SF 0 "register_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2054 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2055 (match_operand:SF 2 "register_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2056 (match_operand:SF 3 "register_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2057 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2058 "nmaddf.s %2,%1,%3,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2059 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2060 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2061 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2062 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2063 ;; negative-multiply-subtract |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2064 (define_insn "fnmssf4" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2065 [(set (match_operand:SF 0 "register_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2066 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "r")) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2067 (match_operand:SF 2 "register_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2068 (neg:SF (match_operand:SF 3 "register_operand" "r"))))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2069 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2070 "nmsubf.s %2,%1,%3,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2071 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2072 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2073 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2074 ; |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2075 ; ---------------- comparison/conditionals |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2076 ; |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2077 ; SF |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2078 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2079 (define_insn "cmpsf_le_insn" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2080 [(set (reg:CC_FPU_LE FCC_REGNUM) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2081 (compare:CC_FPU_LE (match_operand:SF 0 "register_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2082 (match_operand:SF 1 "register_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2083 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2084 "cmpf.s le,%z0,%z1" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2085 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2086 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2087 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2088 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2089 (define_insn "cmpsf_lt_insn" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2090 [(set (reg:CC_FPU_LT FCC_REGNUM) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2091 (compare:CC_FPU_LT (match_operand:SF 0 "register_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2092 (match_operand:SF 1 "register_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2093 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2094 "cmpf.s lt,%z0,%z1" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2095 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2096 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2097 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2098 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2099 (define_insn "cmpsf_ge_insn" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2100 [(set (reg:CC_FPU_GE FCC_REGNUM) |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2101 (compare:CC_FPU_GE (match_operand:SF 0 "register_operand" "r") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2102 (match_operand:SF 1 "register_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2103 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2104 "cmpf.s ge,%z0,%z1" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2105 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2106 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2107 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2108 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2109 (define_insn "cmpsf_gt_insn" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2110 [(set (reg:CC_FPU_GT FCC_REGNUM) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2111 (compare:CC_FPU_GT (match_operand:SF 0 "register_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2112 (match_operand:SF 1 "register_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2113 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2114 "cmpf.s gt,%z0,%z1" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2115 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2116 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2117 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2118 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2119 (define_insn "cmpsf_eq_insn" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2120 [(set (reg:CC_FPU_EQ FCC_REGNUM) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2121 (compare:CC_FPU_EQ (match_operand:SF 0 "register_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2122 (match_operand:SF 1 "register_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2123 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2124 "cmpf.s eq,%z0,%z1" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2125 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2126 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2127 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2128 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2129 (define_insn "cmpsf_ne_insn" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2130 [(set (reg:CC_FPU_NE FCC_REGNUM) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2131 (compare:CC_FPU_NE (match_operand:SF 0 "register_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2132 (match_operand:SF 1 "register_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2133 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2134 "cmpf.s neq,%z0,%z1" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2135 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2136 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2137 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2138 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2139 ; DF |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2140 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2141 (define_insn "cmpdf_le_insn" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2142 [(set (reg:CC_FPU_LE FCC_REGNUM) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2143 (compare:CC_FPU_LE (match_operand:DF 0 "even_reg_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2144 (match_operand:DF 1 "even_reg_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2145 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2146 "cmpf.d le,%z0,%z1" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2147 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2148 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2149 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2150 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2151 (define_insn "cmpdf_lt_insn" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2152 [(set (reg:CC_FPU_LT FCC_REGNUM) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2153 (compare:CC_FPU_LT (match_operand:DF 0 "even_reg_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2154 (match_operand:DF 1 "even_reg_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2155 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2156 "cmpf.d lt,%z0,%z1" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2157 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2158 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2159 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2160 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2161 (define_insn "cmpdf_ge_insn" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2162 [(set (reg:CC_FPU_GE FCC_REGNUM) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2163 (compare:CC_FPU_GE (match_operand:DF 0 "even_reg_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2164 (match_operand:DF 1 "even_reg_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2165 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2166 "cmpf.d ge,%z0,%z1" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2167 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2168 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2169 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2170 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2171 (define_insn "cmpdf_gt_insn" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2172 [(set (reg:CC_FPU_GT FCC_REGNUM) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2173 (compare:CC_FPU_GT (match_operand:DF 0 "even_reg_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2174 (match_operand:DF 1 "even_reg_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2175 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2176 "cmpf.d gt,%z0,%z1" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2177 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2178 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2179 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2180 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2181 (define_insn "cmpdf_eq_insn" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2182 [(set (reg:CC_FPU_EQ FCC_REGNUM) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2183 (compare:CC_FPU_EQ (match_operand:DF 0 "even_reg_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2184 (match_operand:DF 1 "even_reg_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2185 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2186 "cmpf.d eq,%z0,%z1" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2187 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2188 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2189 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2190 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2191 (define_insn "cmpdf_ne_insn" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2192 [(set (reg:CC_FPU_NE FCC_REGNUM) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2193 (compare:CC_FPU_NE (match_operand:DF 0 "even_reg_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2194 (match_operand:DF 1 "even_reg_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2195 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2196 "cmpf.d neq,%z0,%z1" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2197 [(set_attr "length" "4") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2198 (set_attr "cc" "none_0hit") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2199 (set_attr "type" "fpu")]) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
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|
2200 |
|
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changeset
|
2201 |
|
f6334be47118
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parents:
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changeset
|
2202 ;; |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
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|
2203 ;; Transfer a v850e2v3 fcc to the Z bit of CC0 (this is necessary to do a |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
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changeset
|
2204 ;; conditional branch based on a floating-point compare) |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
2205 ;; |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2206 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2207 (define_insn "trfsr" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2208 [(set (match_operand 0 "" "") (match_operand 1 "" ""))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2209 "TARGET_V850E2V3 |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
2210 && GET_MODE(operands[0]) == GET_MODE(operands[1]) |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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|
2211 && GET_CODE(operands[0]) == REG && REGNO (operands[0]) == CC_REGNUM |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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|
2212 && GET_CODE(operands[1]) == REG && REGNO (operands[1]) == FCC_REGNUM |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
2213 && (GET_MODE(operands[0]) == CC_FPU_LEmode |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
2214 || GET_MODE(operands[0]) == CC_FPU_GEmode |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
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changeset
|
2215 || GET_MODE(operands[0]) == CC_FPU_LTmode |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
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changeset
|
2216 || GET_MODE(operands[0]) == CC_FPU_GTmode |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
2217 || GET_MODE(operands[0]) == CC_FPU_EQmode |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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|
2218 || GET_MODE(operands[0]) == CC_FPU_NEmode)" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
2219 "trfsr" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
2220 [(set_attr "length" "4") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
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changeset
|
2221 (set_attr "cc" "set_z") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
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changeset
|
2222 (set_attr "type" "fpu")]) |
|
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parents:
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changeset
|
2223 |
|
f6334be47118
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parents:
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changeset
|
2224 ;; |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
2225 ;; Floating-point conditional moves for the v850e2v3. |
|
f6334be47118
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parents:
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|
2226 ;; |
|
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
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changeset
|
2227 |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
2228 ;; The actual v850e2v3 conditional move instructions |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
2229 ;; |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2230 (define_insn "movsfcc_z_insn" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
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changeset
|
2231 [(set (match_operand:SF 0 "register_operand" "=r") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2232 (if_then_else:SF |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2233 (match_operand 3 "v850_float_z_comparison_operator" "") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
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changeset
|
2234 (match_operand:SF 1 "reg_or_0_operand" "rIG") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
2235 (match_operand:SF 2 "reg_or_0_operand" "rIG")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2236 "TARGET_V850E2V3" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2237 "cmovf.s 0,%z1,%z2,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
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changeset
|
2238 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
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changeset
|
2239 |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
2240 (define_insn "movsfcc_nz_insn" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
2241 [(set (match_operand:SF 0 "register_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
2242 (if_then_else:SF |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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changeset
|
2243 (match_operand 3 "v850_float_nz_comparison_operator" "") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2244 (match_operand:SF 1 "reg_or_0_operand" "rIG") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2245 (match_operand:SF 2 "reg_or_0_operand" "rIG")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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diff
changeset
|
2246 "TARGET_V850E2V3" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2247 "cmovf.s 0,%z2,%z1,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2248 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2249 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2250 (define_insn "movdfcc_z_insn" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2251 [(set (match_operand:DF 0 "even_reg_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2252 (if_then_else:DF |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2253 (match_operand 3 "v850_float_z_comparison_operator" "") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2254 (match_operand:DF 1 "even_reg_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2255 (match_operand:DF 2 "even_reg_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2256 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2257 "cmovf.d 0,%z1,%z2,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2258 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2259 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2260 (define_insn "movdfcc_nz_insn" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2261 [(set (match_operand:DF 0 "even_reg_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2262 (if_then_else:DF |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2263 (match_operand 3 "v850_float_nz_comparison_operator" "") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2264 (match_operand:DF 1 "even_reg_operand" "r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2265 (match_operand:DF 2 "even_reg_operand" "r")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2266 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2267 "cmovf.d 0,%z2,%z1,%0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2268 [(set_attr "cc" "clobber")]) ;; ??? or none_0hit |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2269 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2270 (define_insn "movedfcc_z_zero" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2271 [(set (match_operand:DF 0 "register_operand" "=r") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2272 (if_then_else:DF |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2273 (match_operand 3 "v850_float_z_comparison_operator" "") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2274 (match_operand:DF 1 "reg_or_0_operand" "rIG") |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2275 (match_operand:DF 2 "reg_or_0_operand" "rIG")))] |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2276 "TARGET_V850E2V3" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2277 "cmovf.s 0,%z1,%z2,%0 ; cmovf.s 0,%Z1,%Z2,%R0" |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2278 [(set_attr "length" "8") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2279 (set_attr "cc" "clobber")]) ;; ??? or none_0hit |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2280 |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2281 (define_insn "movedfcc_nz_zero" |
|
f6334be47118
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2282 [(set (match_operand:DF 0 "register_operand" "=r") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2283 (if_then_else:DF |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2284 (match_operand 3 "v850_float_nz_comparison_operator" "") |
|
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2285 (match_operand:DF 1 "reg_or_0_operand" "rIG") |
|
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|
2286 (match_operand:DF 2 "reg_or_0_operand" "rIG")))] |
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|
2287 "TARGET_V850E2V3" |
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|
2288 "cmovf.s 0,%z2,%z1,%0 ; cmovf.s 0,%Z2,%Z1,%R0" |
|
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|
2289 [(set_attr "length" "8") |
|
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|
2290 (set_attr "cc" "clobber")]) ;; ??? or none_0hit |
|
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|
2291 |
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|
2292 |
| 0 | 2293 ;; ---------------------------------------------------------------------- |
| 2294 ;; HELPER INSTRUCTIONS for saving the prologue and epilogue registers | |
| 2295 ;; ---------------------------------------------------------------------- | |
| 2296 | |
| 2297 ;; This pattern will match a stack adjust RTX followed by any number of push | |
| 2298 ;; RTXs. These RTXs will then be turned into a suitable call to a worker | |
| 2299 ;; function. | |
| 2300 | |
| 2301 ;; | |
| 2302 ;; Actually, convert the RTXs into a PREPARE instruction. | |
| 2303 ;; | |
|
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|
2304 |
| 0 | 2305 (define_insn "" |
| 2306 [(match_parallel 0 "pattern_is_ok_for_prepare" | |
| 2307 [(set (reg:SI 3) | |
| 2308 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i"))) | |
| 2309 (set (mem:SI (plus:SI (reg:SI 3) | |
| 2310 (match_operand:SI 2 "immediate_operand" "i"))) | |
| 2311 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])] | |
|
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|
2312 "TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 2313 "* return construct_prepare_instruction (operands[0]); |
| 2314 " | |
| 2315 [(set_attr "length" "4") | |
|
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|
2316 (set_attr "cc" "clobber")]) |
| 0 | 2317 |
| 2318 (define_insn "" | |
| 2319 [(match_parallel 0 "pattern_is_ok_for_prologue" | |
| 2320 [(set (reg:SI 3) | |
| 2321 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i"))) | |
| 2322 (set (mem:SI (plus:SI (reg:SI 3) | |
| 2323 (match_operand:SI 2 "immediate_operand" "i"))) | |
| 2324 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])] | |
|
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|
2325 "TARGET_PROLOG_FUNCTION" |
| 0 | 2326 "* return construct_save_jarl (operands[0]); |
| 2327 " | |
| 2328 [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes") | |
| 2329 (const_string "16") | |
| 2330 (const_string "4"))) | |
| 2331 (set_attr "cc" "clobber")]) | |
| 2332 | |
| 2333 ;; | |
| 2334 ;; Actually, turn the RTXs into a DISPOSE instruction. | |
| 2335 ;; | |
| 2336 (define_insn "" | |
| 2337 [(match_parallel 0 "pattern_is_ok_for_dispose" | |
| 2338 [(return) | |
| 2339 (set (reg:SI 3) | |
| 2340 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i"))) | |
| 2341 (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r") | |
| 2342 (mem:SI (plus:SI (reg:SI 3) | |
| 2343 (match_operand:SI 3 "immediate_operand" "i"))))])] | |
|
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|
2344 "TARGET_PROLOG_FUNCTION && (TARGET_V850E || TARGET_V850E2_ALL)" |
| 0 | 2345 "* return construct_dispose_instruction (operands[0]); |
| 2346 " | |
| 2347 [(set_attr "length" "4") | |
|
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|
2348 (set_attr "cc" "clobber")]) |
| 0 | 2349 |
| 2350 ;; This pattern will match a return RTX followed by any number of pop RTXs | |
| 2351 ;; and possible a stack adjustment as well. These RTXs will be turned into | |
| 2352 ;; a suitable call to a worker function. | |
| 2353 | |
| 2354 (define_insn "" | |
| 2355 [(match_parallel 0 "pattern_is_ok_for_epilogue" | |
| 2356 [(return) | |
| 2357 (set (reg:SI 3) | |
| 2358 (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i"))) | |
| 2359 (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r") | |
| 2360 (mem:SI (plus:SI (reg:SI 3) | |
| 2361 (match_operand:SI 3 "immediate_operand" "i"))))])] | |
|
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|
2362 "TARGET_PROLOG_FUNCTION" |
| 0 | 2363 "* return construct_restore_jr (operands[0]); |
| 2364 " | |
| 2365 [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes") | |
| 2366 (const_string "12") | |
| 2367 (const_string "4"))) | |
| 2368 (set_attr "cc" "clobber")]) | |
| 2369 | |
| 2370 ;; Initialize an interrupt function. Do not depend on TARGET_PROLOG_FUNCTION. | |
| 2371 (define_insn "callt_save_interrupt" | |
| 2372 [(unspec_volatile [(const_int 0)] 2)] | |
|
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|
2373 "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT" |
| 0 | 2374 ;; The CALLT instruction stores the next address of CALLT to CTPC register |
| 2375 ;; without saving its previous value. So if the interrupt handler | |
| 2376 ;; or its caller could possibly execute the CALLT insn, save_interrupt | |
| 2377 ;; MUST NOT be called via CALLT. | |
| 2378 "* | |
| 2379 { | |
|
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|
2380 output_asm_insn (\"addi -28, sp, sp\", operands); |
|
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|
2381 output_asm_insn (\"st.w r1, 24[sp]\", operands); |
| 0 | 2382 output_asm_insn (\"st.w r10, 12[sp]\", operands); |
|
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|
2383 output_asm_insn (\"st.w r11, 16[sp]\", operands); |
| 0 | 2384 output_asm_insn (\"stsr ctpc, r10\", operands); |
|
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|
2385 output_asm_insn (\"st.w r10, 20[sp]\", operands); |
| 0 | 2386 output_asm_insn (\"stsr ctpsw, r10\", operands); |
|
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|
2387 output_asm_insn (\"st.w r10, 24[sp]\", operands); |
| 0 | 2388 output_asm_insn (\"callt ctoff(__callt_save_interrupt)\", operands); |
| 2389 return \"\"; | |
| 2390 }" | |
| 2391 [(set_attr "length" "26") | |
|
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|
2392 (set_attr "cc" "clobber")]) |
| 0 | 2393 |
| 2394 (define_insn "callt_return_interrupt" | |
| 2395 [(unspec_volatile [(const_int 0)] 3)] | |
|
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|
2396 "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT" |
| 0 | 2397 "callt ctoff(__callt_return_interrupt)" |
| 2398 [(set_attr "length" "2") | |
| 2399 (set_attr "cc" "clobber")]) | |
| 2400 | |
| 2401 (define_insn "save_interrupt" | |
|
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|
2402 [(set (reg:SI 3) (plus:SI (reg:SI 3) (const_int -20))) |
|
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|
2403 (set (mem:SI (plus:SI (reg:SI 3) (const_int -20))) (reg:SI 30)) |
|
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|
2404 (set (mem:SI (plus:SI (reg:SI 3) (const_int -16))) (reg:SI 4)) |
|
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|
2405 (set (mem:SI (plus:SI (reg:SI 3) (const_int -12))) (reg:SI 1)) |
|
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|
2406 (set (mem:SI (plus:SI (reg:SI 3) (const_int -8))) (reg:SI 10)) |
|
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|
2407 (set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 11))] |
| 0 | 2408 "" |
| 2409 "* | |
| 2410 { | |
| 2411 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) | |
|
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|
2412 return \"addi -20,sp,sp \; st.w r11,16[sp] \; st.w r10,12[sp] \; jarl __save_interrupt,r10\"; |
| 0 | 2413 else |
| 2414 { | |
|
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|
2415 output_asm_insn (\"addi -20, sp, sp\", operands); |
|
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|
2416 output_asm_insn (\"st.w r11, 16[sp]\", operands); |
| 0 | 2417 output_asm_insn (\"st.w r10, 12[sp]\", operands); |
| 2418 output_asm_insn (\"st.w ep, 0[sp]\", operands); | |
| 2419 output_asm_insn (\"st.w gp, 4[sp]\", operands); | |
| 2420 output_asm_insn (\"st.w r1, 8[sp]\", operands); | |
| 2421 output_asm_insn (\"movhi hi(__ep), r0, ep\", operands); | |
| 2422 output_asm_insn (\"movea lo(__ep), ep, ep\", operands); | |
| 2423 output_asm_insn (\"movhi hi(__gp), r0, gp\", operands); | |
| 2424 output_asm_insn (\"movea lo(__gp), gp, gp\", operands); | |
| 2425 return \"\"; | |
| 2426 } | |
| 2427 }" | |
| 2428 [(set (attr "length") | |
| 2429 (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0)) | |
| 2430 (const_int 10) | |
| 2431 (const_int 34))) | |
| 2432 (set_attr "cc" "clobber")]) | |
| 2433 | |
| 2434 ;; Restore r1, r4, r10, and return from the interrupt | |
| 2435 (define_insn "return_interrupt" | |
| 2436 [(return) | |
|
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|
2437 (set (reg:SI 3) (plus:SI (reg:SI 3) (const_int 20))) |
|
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|
2438 (set (reg:SI 11) (mem:SI (plus:SI (reg:SI 3) (const_int 16)))) |
| 0 | 2439 (set (reg:SI 10) (mem:SI (plus:SI (reg:SI 3) (const_int 12)))) |
| 2440 (set (reg:SI 1) (mem:SI (plus:SI (reg:SI 3) (const_int 8)))) | |
| 2441 (set (reg:SI 4) (mem:SI (plus:SI (reg:SI 3) (const_int 4)))) | |
| 2442 (set (reg:SI 30) (mem:SI (reg:SI 3)))] | |
| 2443 "" | |
| 2444 "* | |
| 2445 { | |
| 2446 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) | |
| 2447 return \"jr __return_interrupt\"; | |
| 2448 else | |
| 2449 { | |
| 2450 output_asm_insn (\"ld.w 0[sp], ep\", operands); | |
| 2451 output_asm_insn (\"ld.w 4[sp], gp\", operands); | |
| 2452 output_asm_insn (\"ld.w 8[sp], r1\", operands); | |
| 2453 output_asm_insn (\"ld.w 12[sp], r10\", operands); | |
|
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|
2454 output_asm_insn (\"ld.w 16[sp], r11\", operands); |
|
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|
2455 output_asm_insn (\"addi 20, sp, sp\", operands); |
| 0 | 2456 output_asm_insn (\"reti\", operands); |
| 2457 return \"\"; | |
| 2458 } | |
| 2459 }" | |
| 2460 [(set (attr "length") | |
| 2461 (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0)) | |
| 2462 (const_int 4) | |
| 2463 (const_int 24))) | |
| 2464 (set_attr "cc" "clobber")]) | |
| 2465 | |
| 2466 ;; Save all registers except for the registers saved in save_interrupt when | |
| 2467 ;; an interrupt function makes a call. | |
| 2468 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
| 2469 ;; all of memory. This blocks insns from being moved across this point. | |
| 2470 ;; This is needed because the rest of the compiler is not ready to handle | |
| 2471 ;; insns this complicated. | |
| 2472 | |
| 2473 (define_insn "callt_save_all_interrupt" | |
| 2474 [(unspec_volatile [(const_int 0)] 0)] | |
|
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|
2475 "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT" |
| 0 | 2476 "callt ctoff(__callt_save_all_interrupt)" |
| 2477 [(set_attr "length" "2") | |
| 2478 (set_attr "cc" "none")]) | |
| 2479 | |
| 2480 (define_insn "save_all_interrupt" | |
| 2481 [(unspec_volatile [(const_int 0)] 0)] | |
| 2482 "" | |
| 2483 "* | |
| 2484 { | |
| 2485 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) | |
| 2486 return \"jarl __save_all_interrupt,r10\"; | |
| 2487 | |
| 2488 output_asm_insn (\"addi -120, sp, sp\", operands); | |
| 2489 | |
| 2490 if (TARGET_EP) | |
| 2491 { | |
| 2492 output_asm_insn (\"mov ep, r1\", operands); | |
| 2493 output_asm_insn (\"mov sp, ep\", operands); | |
| 2494 output_asm_insn (\"sst.w r31, 116[ep]\", operands); | |
| 2495 output_asm_insn (\"sst.w r2, 112[ep]\", operands); | |
| 2496 output_asm_insn (\"sst.w gp, 108[ep]\", operands); | |
| 2497 output_asm_insn (\"sst.w r6, 104[ep]\", operands); | |
| 2498 output_asm_insn (\"sst.w r7, 100[ep]\", operands); | |
| 2499 output_asm_insn (\"sst.w r8, 96[ep]\", operands); | |
| 2500 output_asm_insn (\"sst.w r9, 92[ep]\", operands); | |
| 2501 output_asm_insn (\"sst.w r11, 88[ep]\", operands); | |
| 2502 output_asm_insn (\"sst.w r12, 84[ep]\", operands); | |
| 2503 output_asm_insn (\"sst.w r13, 80[ep]\", operands); | |
| 2504 output_asm_insn (\"sst.w r14, 76[ep]\", operands); | |
| 2505 output_asm_insn (\"sst.w r15, 72[ep]\", operands); | |
| 2506 output_asm_insn (\"sst.w r16, 68[ep]\", operands); | |
| 2507 output_asm_insn (\"sst.w r17, 64[ep]\", operands); | |
| 2508 output_asm_insn (\"sst.w r18, 60[ep]\", operands); | |
| 2509 output_asm_insn (\"sst.w r19, 56[ep]\", operands); | |
| 2510 output_asm_insn (\"sst.w r20, 52[ep]\", operands); | |
| 2511 output_asm_insn (\"sst.w r21, 48[ep]\", operands); | |
| 2512 output_asm_insn (\"sst.w r22, 44[ep]\", operands); | |
| 2513 output_asm_insn (\"sst.w r23, 40[ep]\", operands); | |
| 2514 output_asm_insn (\"sst.w r24, 36[ep]\", operands); | |
| 2515 output_asm_insn (\"sst.w r25, 32[ep]\", operands); | |
| 2516 output_asm_insn (\"sst.w r26, 28[ep]\", operands); | |
| 2517 output_asm_insn (\"sst.w r27, 24[ep]\", operands); | |
| 2518 output_asm_insn (\"sst.w r28, 20[ep]\", operands); | |
| 2519 output_asm_insn (\"sst.w r29, 16[ep]\", operands); | |
| 2520 output_asm_insn (\"mov r1, ep\", operands); | |
| 2521 } | |
| 2522 else | |
| 2523 { | |
| 2524 output_asm_insn (\"st.w r31, 116[sp]\", operands); | |
| 2525 output_asm_insn (\"st.w r2, 112[sp]\", operands); | |
| 2526 output_asm_insn (\"st.w gp, 108[sp]\", operands); | |
| 2527 output_asm_insn (\"st.w r6, 104[sp]\", operands); | |
| 2528 output_asm_insn (\"st.w r7, 100[sp]\", operands); | |
| 2529 output_asm_insn (\"st.w r8, 96[sp]\", operands); | |
| 2530 output_asm_insn (\"st.w r9, 92[sp]\", operands); | |
| 2531 output_asm_insn (\"st.w r11, 88[sp]\", operands); | |
| 2532 output_asm_insn (\"st.w r12, 84[sp]\", operands); | |
| 2533 output_asm_insn (\"st.w r13, 80[sp]\", operands); | |
| 2534 output_asm_insn (\"st.w r14, 76[sp]\", operands); | |
| 2535 output_asm_insn (\"st.w r15, 72[sp]\", operands); | |
| 2536 output_asm_insn (\"st.w r16, 68[sp]\", operands); | |
| 2537 output_asm_insn (\"st.w r17, 64[sp]\", operands); | |
| 2538 output_asm_insn (\"st.w r18, 60[sp]\", operands); | |
| 2539 output_asm_insn (\"st.w r19, 56[sp]\", operands); | |
| 2540 output_asm_insn (\"st.w r20, 52[sp]\", operands); | |
| 2541 output_asm_insn (\"st.w r21, 48[sp]\", operands); | |
| 2542 output_asm_insn (\"st.w r22, 44[sp]\", operands); | |
| 2543 output_asm_insn (\"st.w r23, 40[sp]\", operands); | |
| 2544 output_asm_insn (\"st.w r24, 36[sp]\", operands); | |
| 2545 output_asm_insn (\"st.w r25, 32[sp]\", operands); | |
| 2546 output_asm_insn (\"st.w r26, 28[sp]\", operands); | |
| 2547 output_asm_insn (\"st.w r27, 24[sp]\", operands); | |
| 2548 output_asm_insn (\"st.w r28, 20[sp]\", operands); | |
| 2549 output_asm_insn (\"st.w r29, 16[sp]\", operands); | |
| 2550 } | |
| 2551 | |
| 2552 return \"\"; | |
| 2553 }" | |
| 2554 [(set (attr "length") | |
| 2555 (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0)) | |
| 2556 (const_int 4) | |
| 2557 (const_int 62) | |
| 2558 )) | |
| 2559 (set_attr "cc" "clobber")]) | |
| 2560 | |
| 2561 (define_insn "_save_all_interrupt" | |
| 2562 [(unspec_volatile [(const_int 0)] 0)] | |
| 2563 "TARGET_V850 && ! TARGET_LONG_CALLS" | |
| 2564 "jarl __save_all_interrupt,r10" | |
| 2565 [(set_attr "length" "4") | |
| 2566 (set_attr "cc" "clobber")]) | |
| 2567 | |
| 2568 ;; Restore all registers saved when an interrupt function makes a call. | |
| 2569 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
| 2570 ;; all of memory. This blocks insns from being moved across this point. | |
| 2571 ;; This is needed because the rest of the compiler is not ready to handle | |
| 2572 ;; insns this complicated. | |
| 2573 | |
| 2574 (define_insn "callt_restore_all_interrupt" | |
| 2575 [(unspec_volatile [(const_int 0)] 1)] | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
|
2576 "(TARGET_V850E || TARGET_V850E2_ALL) && !TARGET_DISABLE_CALLT" |
| 0 | 2577 "callt ctoff(__callt_restore_all_interrupt)" |
| 2578 [(set_attr "length" "2") | |
| 2579 (set_attr "cc" "none")]) | |
| 2580 | |
| 2581 (define_insn "restore_all_interrupt" | |
| 2582 [(unspec_volatile [(const_int 0)] 1)] | |
| 2583 "" | |
| 2584 "* | |
| 2585 { | |
| 2586 if (TARGET_PROLOG_FUNCTION && !TARGET_LONG_CALLS) | |
| 2587 return \"jarl __restore_all_interrupt,r10\"; | |
| 2588 | |
| 2589 if (TARGET_EP) | |
| 2590 { | |
| 2591 output_asm_insn (\"mov ep, r1\", operands); | |
| 2592 output_asm_insn (\"mov sp, ep\", operands); | |
| 2593 output_asm_insn (\"sld.w 116[ep], r31\", operands); | |
| 2594 output_asm_insn (\"sld.w 112[ep], r2\", operands); | |
| 2595 output_asm_insn (\"sld.w 108[ep], gp\", operands); | |
| 2596 output_asm_insn (\"sld.w 104[ep], r6\", operands); | |
| 2597 output_asm_insn (\"sld.w 100[ep], r7\", operands); | |
| 2598 output_asm_insn (\"sld.w 96[ep], r8\", operands); | |
| 2599 output_asm_insn (\"sld.w 92[ep], r9\", operands); | |
| 2600 output_asm_insn (\"sld.w 88[ep], r11\", operands); | |
| 2601 output_asm_insn (\"sld.w 84[ep], r12\", operands); | |
| 2602 output_asm_insn (\"sld.w 80[ep], r13\", operands); | |
| 2603 output_asm_insn (\"sld.w 76[ep], r14\", operands); | |
| 2604 output_asm_insn (\"sld.w 72[ep], r15\", operands); | |
| 2605 output_asm_insn (\"sld.w 68[ep], r16\", operands); | |
| 2606 output_asm_insn (\"sld.w 64[ep], r17\", operands); | |
| 2607 output_asm_insn (\"sld.w 60[ep], r18\", operands); | |
| 2608 output_asm_insn (\"sld.w 56[ep], r19\", operands); | |
| 2609 output_asm_insn (\"sld.w 52[ep], r20\", operands); | |
| 2610 output_asm_insn (\"sld.w 48[ep], r21\", operands); | |
| 2611 output_asm_insn (\"sld.w 44[ep], r22\", operands); | |
| 2612 output_asm_insn (\"sld.w 40[ep], r23\", operands); | |
| 2613 output_asm_insn (\"sld.w 36[ep], r24\", operands); | |
| 2614 output_asm_insn (\"sld.w 32[ep], r25\", operands); | |
| 2615 output_asm_insn (\"sld.w 28[ep], r26\", operands); | |
| 2616 output_asm_insn (\"sld.w 24[ep], r27\", operands); | |
| 2617 output_asm_insn (\"sld.w 20[ep], r28\", operands); | |
| 2618 output_asm_insn (\"sld.w 16[ep], r29\", operands); | |
| 2619 output_asm_insn (\"mov r1, ep\", operands); | |
| 2620 } | |
| 2621 else | |
| 2622 { | |
| 2623 output_asm_insn (\"ld.w 116[sp], r31\", operands); | |
| 2624 output_asm_insn (\"ld.w 112[sp], r2\", operands); | |
| 2625 output_asm_insn (\"ld.w 108[sp], gp\", operands); | |
| 2626 output_asm_insn (\"ld.w 104[sp], r6\", operands); | |
| 2627 output_asm_insn (\"ld.w 100[sp], r7\", operands); | |
| 2628 output_asm_insn (\"ld.w 96[sp], r8\", operands); | |
| 2629 output_asm_insn (\"ld.w 92[sp], r9\", operands); | |
| 2630 output_asm_insn (\"ld.w 88[sp], r11\", operands); | |
| 2631 output_asm_insn (\"ld.w 84[sp], r12\", operands); | |
| 2632 output_asm_insn (\"ld.w 80[sp], r13\", operands); | |
| 2633 output_asm_insn (\"ld.w 76[sp], r14\", operands); | |
| 2634 output_asm_insn (\"ld.w 72[sp], r15\", operands); | |
| 2635 output_asm_insn (\"ld.w 68[sp], r16\", operands); | |
| 2636 output_asm_insn (\"ld.w 64[sp], r17\", operands); | |
| 2637 output_asm_insn (\"ld.w 60[sp], r18\", operands); | |
| 2638 output_asm_insn (\"ld.w 56[sp], r19\", operands); | |
| 2639 output_asm_insn (\"ld.w 52[sp], r20\", operands); | |
| 2640 output_asm_insn (\"ld.w 48[sp], r21\", operands); | |
| 2641 output_asm_insn (\"ld.w 44[sp], r22\", operands); | |
| 2642 output_asm_insn (\"ld.w 40[sp], r23\", operands); | |
| 2643 output_asm_insn (\"ld.w 36[sp], r24\", operands); | |
| 2644 output_asm_insn (\"ld.w 32[sp], r25\", operands); | |
| 2645 output_asm_insn (\"ld.w 28[sp], r26\", operands); | |
| 2646 output_asm_insn (\"ld.w 24[sp], r27\", operands); | |
| 2647 output_asm_insn (\"ld.w 20[sp], r28\", operands); | |
| 2648 output_asm_insn (\"ld.w 16[sp], r29\", operands); | |
| 2649 } | |
| 2650 output_asm_insn (\"addi 120, sp, sp\", operands); | |
| 2651 return \"\"; | |
| 2652 }" | |
| 2653 [(set (attr "length") | |
| 2654 (if_then_else (ne (symbol_ref "TARGET_LONG_CALLS") (const_int 0)) | |
| 2655 (const_int 4) | |
| 2656 (const_int 62) | |
| 2657 )) | |
| 2658 (set_attr "cc" "clobber")]) | |
| 2659 | |
| 2660 (define_insn "_restore_all_interrupt" | |
| 2661 [(unspec_volatile [(const_int 0)] 1)] | |
| 2662 "TARGET_V850 && ! TARGET_LONG_CALLS" | |
| 2663 "jarl __restore_all_interrupt,r10" | |
| 2664 [(set_attr "length" "4") | |
| 2665 (set_attr "cc" "clobber")]) | |
| 2666 | |
| 2667 |