Mercurial > hg > CbC > CbC_gcc
annotate gcc/ira-lives.c @ 67:f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
| author | nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp> |
|---|---|
| date | Tue, 22 Mar 2011 17:18:12 +0900 |
| parents | b7f97abdc517 |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 /* IRA processing allocno lives to build allocno live ranges. |
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2 Copyright (C) 2006, 2007, 2008, 2009, 2010 |
| 0 | 3 Free Software Foundation, Inc. |
| 4 Contributed by Vladimir Makarov <vmakarov@redhat.com>. | |
| 5 | |
| 6 This file is part of GCC. | |
| 7 | |
| 8 GCC is free software; you can redistribute it and/or modify it under | |
| 9 the terms of the GNU General Public License as published by the Free | |
| 10 Software Foundation; either version 3, or (at your option) any later | |
| 11 version. | |
| 12 | |
| 13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 14 WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 16 for more details. | |
| 17 | |
| 18 You should have received a copy of the GNU General Public License | |
| 19 along with GCC; see the file COPYING3. If not see | |
| 20 <http://www.gnu.org/licenses/>. */ | |
| 21 | |
| 22 #include "config.h" | |
| 23 #include "system.h" | |
| 24 #include "coretypes.h" | |
| 25 #include "tm.h" | |
| 26 #include "regs.h" | |
| 27 #include "rtl.h" | |
| 28 #include "tm_p.h" | |
| 29 #include "target.h" | |
| 30 #include "flags.h" | |
| 31 #include "except.h" | |
| 32 #include "hard-reg-set.h" | |
| 33 #include "basic-block.h" | |
| 34 #include "insn-config.h" | |
| 35 #include "recog.h" | |
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36 #include "diagnostic-core.h" |
| 0 | 37 #include "params.h" |
| 38 #include "df.h" | |
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39 #include "sbitmap.h" |
| 0 | 40 #include "sparseset.h" |
| 41 #include "ira-int.h" | |
| 42 | |
| 43 /* The code in this file is similar to one in global but the code | |
| 44 works on the allocno basis and creates live ranges instead of | |
| 45 pseudo-register conflicts. */ | |
| 46 | |
| 47 /* Program points are enumerated by numbers from range | |
| 48 0..IRA_MAX_POINT-1. There are approximately two times more program | |
| 49 points than insns. Program points are places in the program where | |
| 50 liveness info can be changed. In most general case (there are more | |
| 51 complicated cases too) some program points correspond to places | |
| 52 where input operand dies and other ones correspond to places where | |
| 53 output operands are born. */ | |
| 54 int ira_max_point; | |
| 55 | |
| 56 /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno | |
| 57 live ranges with given start/finish point. */ | |
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58 live_range_t *ira_start_point_ranges, *ira_finish_point_ranges; |
| 0 | 59 |
| 60 /* Number of the current program point. */ | |
| 61 static int curr_point; | |
| 62 | |
| 63 /* Point where register pressure excess started or -1 if there is no | |
| 64 register pressure excess. Excess pressure for a register class at | |
| 65 some point means that there are more allocnos of given register | |
| 66 class living at the point than number of hard-registers of the | |
| 67 class available for the allocation. It is defined only for cover | |
| 68 classes. */ | |
| 69 static int high_pressure_start_point[N_REG_CLASSES]; | |
| 70 | |
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71 /* Objects live at current point in the scan. */ |
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72 static sparseset objects_live; |
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73 |
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74 /* A temporary bitmap used in functions that wish to avoid visiting an allocno |
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75 multiple times. */ |
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76 static sparseset allocnos_processed; |
| 0 | 77 |
| 78 /* Set of hard regs (except eliminable ones) currently live. */ | |
| 79 static HARD_REG_SET hard_regs_live; | |
| 80 | |
| 81 /* The loop tree node corresponding to the current basic block. */ | |
| 82 static ira_loop_tree_node_t curr_bb_node; | |
| 83 | |
| 84 /* The number of the last processed call. */ | |
| 85 static int last_call_num; | |
| 86 /* The number of last call at which given allocno was saved. */ | |
| 87 static int *allocno_saved_at_call; | |
| 88 | |
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89 /* Record the birth of hard register REGNO, updating hard_regs_live and |
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90 hard reg conflict information for living allocnos. */ |
| 0 | 91 static void |
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92 make_hard_regno_born (int regno) |
| 0 | 93 { |
| 94 unsigned int i; | |
| 95 | |
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96 SET_HARD_REG_BIT (hard_regs_live, regno); |
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97 EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
| 0 | 98 { |
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99 ira_object_t obj = ira_object_id_map[i]; |
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100 SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno); |
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101 SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno); |
| 0 | 102 } |
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103 } |
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104 |
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105 /* Process the death of hard register REGNO. This updates |
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106 hard_regs_live. */ |
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107 static void |
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108 make_hard_regno_dead (int regno) |
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109 { |
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110 CLEAR_HARD_REG_BIT (hard_regs_live, regno); |
| 0 | 111 } |
| 112 | |
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113 /* Record the birth of object OBJ. Set a bit for it in objects_live, |
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114 start a new live range for it if necessary and update hard register |
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115 conflicts. */ |
| 0 | 116 static void |
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117 make_object_born (ira_object_t obj) |
| 0 | 118 { |
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119 live_range_t lr = OBJECT_LIVE_RANGES (obj); |
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120 |
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121 sparseset_set_bit (objects_live, OBJECT_CONFLICT_ID (obj)); |
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122 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), hard_regs_live); |
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123 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), hard_regs_live); |
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124 |
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125 if (lr == NULL |
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126 || (lr->finish != curr_point && lr->finish + 1 != curr_point)) |
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127 ira_add_live_range_to_object (obj, curr_point, -1); |
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128 } |
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129 |
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130 /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno |
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131 associated with object OBJ. */ |
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132 static void |
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133 update_allocno_pressure_excess_length (ira_object_t obj) |
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134 { |
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135 ira_allocno_t a = OBJECT_ALLOCNO (obj); |
| 0 | 136 int start, i; |
| 137 enum reg_class cover_class, cl; | |
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138 live_range_t p; |
| 0 | 139 |
| 140 cover_class = ALLOCNO_COVER_CLASS (a); | |
| 141 for (i = 0; | |
| 142 (cl = ira_reg_class_super_classes[cover_class][i]) != LIM_REG_CLASSES; | |
| 143 i++) | |
| 144 { | |
| 145 if (high_pressure_start_point[cl] < 0) | |
| 146 continue; | |
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147 p = OBJECT_LIVE_RANGES (obj); |
| 0 | 148 ira_assert (p != NULL); |
| 149 start = (high_pressure_start_point[cl] > p->start | |
| 150 ? high_pressure_start_point[cl] : p->start); | |
| 151 ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1; | |
| 152 } | |
| 153 } | |
| 154 | |
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155 /* Process the death of object OBJ, which is associated with allocno |
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156 A. This finishes the current live range for it. */ |
| 0 | 157 static void |
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158 make_object_dead (ira_object_t obj) |
| 0 | 159 { |
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160 live_range_t lr; |
| 0 | 161 |
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162 sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj)); |
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163 lr = OBJECT_LIVE_RANGES (obj); |
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164 ira_assert (lr != NULL); |
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165 lr->finish = curr_point; |
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166 update_allocno_pressure_excess_length (obj); |
| 0 | 167 } |
| 168 | |
| 169 /* The current register pressures for each cover class for the current | |
| 170 basic block. */ | |
| 171 static int curr_reg_pressure[N_REG_CLASSES]; | |
| 172 | |
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173 /* Record that register pressure for COVER_CLASS increased by N |
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174 registers. Update the current register pressure, maximal register |
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175 pressure for the current BB and the start point of the register |
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176 pressure excess. */ |
| 0 | 177 static void |
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178 inc_register_pressure (enum reg_class cover_class, int n) |
| 0 | 179 { |
| 180 int i; | |
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181 enum reg_class cl; |
| 0 | 182 |
| 183 for (i = 0; | |
| 184 (cl = ira_reg_class_super_classes[cover_class][i]) != LIM_REG_CLASSES; | |
| 185 i++) | |
| 186 { | |
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187 curr_reg_pressure[cl] += n; |
| 0 | 188 if (high_pressure_start_point[cl] < 0 |
| 189 && (curr_reg_pressure[cl] > ira_available_class_regs[cl])) | |
| 190 high_pressure_start_point[cl] = curr_point; | |
| 191 if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl]) | |
| 192 curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl]; | |
| 193 } | |
| 194 } | |
| 195 | |
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196 /* Record that register pressure for COVER_CLASS has decreased by |
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197 NREGS registers; update current register pressure, start point of |
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198 the register pressure excess, and register pressure excess length |
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199 for living allocnos. */ |
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200 |
| 0 | 201 static void |
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202 dec_register_pressure (enum reg_class cover_class, int nregs) |
| 0 | 203 { |
| 204 int i; | |
| 205 unsigned int j; | |
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206 enum reg_class cl; |
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207 bool set_p = false; |
| 0 | 208 |
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209 for (i = 0; |
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210 (cl = ira_reg_class_super_classes[cover_class][i]) != LIM_REG_CLASSES; |
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211 i++) |
| 0 | 212 { |
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213 curr_reg_pressure[cl] -= nregs; |
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214 ira_assert (curr_reg_pressure[cl] >= 0); |
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215 if (high_pressure_start_point[cl] >= 0 |
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216 && curr_reg_pressure[cl] <= ira_available_class_regs[cl]) |
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217 set_p = true; |
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218 } |
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219 if (set_p) |
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220 { |
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221 EXECUTE_IF_SET_IN_SPARSESET (objects_live, j) |
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222 update_allocno_pressure_excess_length (ira_object_id_map[j]); |
| 0 | 223 for (i = 0; |
| 224 (cl = ira_reg_class_super_classes[cover_class][i]) | |
| 225 != LIM_REG_CLASSES; | |
| 226 i++) | |
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227 if (high_pressure_start_point[cl] >= 0 |
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228 && curr_reg_pressure[cl] <= ira_available_class_regs[cl]) |
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229 high_pressure_start_point[cl] = -1; |
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230 } |
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231 } |
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232 |
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233 /* Mark the pseudo register REGNO as live. Update all information about |
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234 live ranges and register pressure. */ |
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235 static void |
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236 mark_pseudo_regno_live (int regno) |
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237 { |
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238 ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
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239 int i, n, nregs; |
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240 enum reg_class cl; |
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241 |
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242 if (a == NULL) |
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243 return; |
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244 |
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245 /* Invalidate because it is referenced. */ |
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246 allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; |
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247 |
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248 n = ALLOCNO_NUM_OBJECTS (a); |
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249 cl = ALLOCNO_COVER_CLASS (a); |
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250 nregs = ira_reg_class_nregs[cl][ALLOCNO_MODE (a)]; |
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251 if (n > 1) |
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252 { |
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253 /* We track every subobject separately. */ |
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254 gcc_assert (nregs == n); |
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255 nregs = 1; |
| 0 | 256 } |
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257 |
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258 for (i = 0; i < n; i++) |
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259 { |
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260 ira_object_t obj = ALLOCNO_OBJECT (a, i); |
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261 if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) |
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262 continue; |
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263 |
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264 inc_register_pressure (cl, nregs); |
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265 make_object_born (obj); |
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266 } |
| 0 | 267 } |
| 268 | |
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269 /* Like mark_pseudo_regno_live, but try to only mark one subword of |
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270 the pseudo as live. SUBWORD indicates which; a value of 0 |
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271 indicates the low part. */ |
| 0 | 272 static void |
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273 mark_pseudo_regno_subword_live (int regno, int subword) |
| 0 | 274 { |
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275 ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
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276 int n, nregs; |
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277 enum reg_class cl; |
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278 ira_object_t obj; |
| 0 | 279 |
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280 if (a == NULL) |
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281 return; |
| 0 | 282 |
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283 /* Invalidate because it is referenced. */ |
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284 allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; |
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285 |
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286 n = ALLOCNO_NUM_OBJECTS (a); |
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287 if (n == 1) |
| 0 | 288 { |
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289 mark_pseudo_regno_live (regno); |
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290 return; |
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291 } |
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292 |
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293 cl = ALLOCNO_COVER_CLASS (a); |
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294 nregs = ira_reg_class_nregs[cl][ALLOCNO_MODE (a)]; |
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295 gcc_assert (nregs == n); |
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296 obj = ALLOCNO_OBJECT (a, subword); |
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297 |
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298 if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) |
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299 return; |
| 0 | 300 |
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301 inc_register_pressure (cl, nregs); |
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302 make_object_born (obj); |
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303 } |
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304 |
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305 /* Mark the register REG as live. Store a 1 in hard_regs_live for |
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306 this register, record how many consecutive hardware registers it |
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307 actually needs. */ |
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308 static void |
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309 mark_hard_reg_live (rtx reg) |
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310 { |
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311 int regno = REGNO (reg); |
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312 |
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313 if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) |
| 0 | 314 { |
| 315 int last = regno + hard_regno_nregs[regno][GET_MODE (reg)]; | |
| 316 | |
| 317 while (regno < last) | |
| 318 { | |
| 319 if (! TEST_HARD_REG_BIT (hard_regs_live, regno) | |
| 320 && ! TEST_HARD_REG_BIT (eliminable_regset, regno)) | |
| 321 { | |
|
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322 enum reg_class cover_class = ira_hard_regno_cover_class[regno]; |
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323 inc_register_pressure (cover_class, 1); |
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324 make_hard_regno_born (regno); |
| 0 | 325 } |
| 326 regno++; | |
| 327 } | |
| 328 } | |
| 329 } | |
| 330 | |
|
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331 /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's |
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332 register number; ORIG_REG is the access in the insn, which may be a |
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333 subreg. */ |
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334 static void |
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335 mark_pseudo_reg_live (rtx orig_reg, unsigned regno) |
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336 { |
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337 if (df_read_modify_subreg_p (orig_reg)) |
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338 { |
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339 mark_pseudo_regno_subword_live (regno, |
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340 subreg_lowpart_p (orig_reg) ? 0 : 1); |
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341 } |
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342 else |
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343 mark_pseudo_regno_live (regno); |
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344 } |
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345 |
| 0 | 346 /* Mark the register referenced by use or def REF as live. */ |
| 347 static void | |
| 348 mark_ref_live (df_ref ref) | |
| 349 { | |
|
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350 rtx reg = DF_REF_REG (ref); |
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351 rtx orig_reg = reg; |
| 0 | 352 |
| 353 if (GET_CODE (reg) == SUBREG) | |
| 354 reg = SUBREG_REG (reg); | |
|
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355 |
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356 if (REGNO (reg) >= FIRST_PSEUDO_REGISTER) |
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357 mark_pseudo_reg_live (orig_reg, REGNO (reg)); |
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358 else |
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359 mark_hard_reg_live (reg); |
| 0 | 360 } |
| 361 | |
|
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362 /* Mark the pseudo register REGNO as dead. Update all information about |
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363 live ranges and register pressure. */ |
| 0 | 364 static void |
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365 mark_pseudo_regno_dead (int regno) |
| 0 | 366 { |
|
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367 ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
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368 int n, i, nregs; |
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369 enum reg_class cl; |
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370 |
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371 if (a == NULL) |
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372 return; |
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373 |
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374 /* Invalidate because it is referenced. */ |
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375 allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; |
| 0 | 376 |
|
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377 n = ALLOCNO_NUM_OBJECTS (a); |
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378 cl = ALLOCNO_COVER_CLASS (a); |
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379 nregs = ira_reg_class_nregs[cl][ALLOCNO_MODE (a)]; |
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380 if (n > 1) |
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381 { |
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382 /* We track every subobject separately. */ |
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383 gcc_assert (nregs == n); |
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384 nregs = 1; |
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385 } |
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386 for (i = 0; i < n; i++) |
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387 { |
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388 ira_object_t obj = ALLOCNO_OBJECT (a, i); |
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389 if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) |
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390 continue; |
| 0 | 391 |
|
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392 dec_register_pressure (cl, nregs); |
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393 make_object_dead (obj); |
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394 } |
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395 } |
| 0 | 396 |
|
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397 /* Like mark_pseudo_regno_dead, but called when we know that only part of the |
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398 register dies. SUBWORD indicates which; a value of 0 indicates the low part. */ |
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399 static void |
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400 mark_pseudo_regno_subword_dead (int regno, int subword) |
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401 { |
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402 ira_allocno_t a = ira_curr_regno_allocno_map[regno]; |
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403 int n, nregs; |
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404 enum reg_class cl; |
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405 ira_object_t obj; |
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406 |
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407 if (a == NULL) |
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408 return; |
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409 |
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410 /* Invalidate because it is referenced. */ |
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411 allocno_saved_at_call[ALLOCNO_NUM (a)] = 0; |
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412 |
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413 n = ALLOCNO_NUM_OBJECTS (a); |
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414 if (n == 1) |
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415 /* The allocno as a whole doesn't die in this case. */ |
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416 return; |
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417 |
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418 cl = ALLOCNO_COVER_CLASS (a); |
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419 nregs = ira_reg_class_nregs[cl][ALLOCNO_MODE (a)]; |
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420 gcc_assert (nregs == n); |
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421 |
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422 obj = ALLOCNO_OBJECT (a, subword); |
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423 if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj))) |
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424 return; |
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425 |
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426 dec_register_pressure (cl, 1); |
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427 make_object_dead (obj); |
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428 } |
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429 |
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430 /* Mark the hard register REG as dead. Store a 0 in hard_regs_live for the |
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431 register. */ |
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432 static void |
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433 mark_hard_reg_dead (rtx reg) |
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434 { |
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435 int regno = REGNO (reg); |
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436 |
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437 if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno)) |
| 0 | 438 { |
| 439 int last = regno + hard_regno_nregs[regno][GET_MODE (reg)]; | |
| 440 | |
| 441 while (regno < last) | |
| 442 { | |
| 443 if (TEST_HARD_REG_BIT (hard_regs_live, regno)) | |
| 444 { | |
|
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445 enum reg_class cover_class = ira_hard_regno_cover_class[regno]; |
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446 dec_register_pressure (cover_class, 1); |
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447 make_hard_regno_dead (regno); |
| 0 | 448 } |
| 449 regno++; | |
| 450 } | |
| 451 } | |
| 452 } | |
| 453 | |
|
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454 /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's |
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455 register number; ORIG_REG is the access in the insn, which may be a |
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456 subreg. */ |
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457 static void |
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458 mark_pseudo_reg_dead (rtx orig_reg, unsigned regno) |
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459 { |
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460 if (df_read_modify_subreg_p (orig_reg)) |
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461 { |
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462 mark_pseudo_regno_subword_dead (regno, |
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463 subreg_lowpart_p (orig_reg) ? 0 : 1); |
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464 } |
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465 else |
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466 mark_pseudo_regno_dead (regno); |
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467 } |
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468 |
| 0 | 469 /* Mark the register referenced by definition DEF as dead, if the |
| 470 definition is a total one. */ | |
| 471 static void | |
| 472 mark_ref_dead (df_ref def) | |
| 473 { | |
|
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474 rtx reg = DF_REF_REG (def); |
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475 rtx orig_reg = reg; |
| 0 | 476 |
|
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477 if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL)) |
| 0 | 478 return; |
| 479 | |
| 480 if (GET_CODE (reg) == SUBREG) | |
| 481 reg = SUBREG_REG (reg); | |
|
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482 |
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483 if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL) |
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484 && (GET_CODE (orig_reg) != SUBREG |
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485 || REGNO (reg) < FIRST_PSEUDO_REGISTER |
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486 || !df_read_modify_subreg_p (orig_reg))) |
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487 return; |
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488 |
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489 if (REGNO (reg) >= FIRST_PSEUDO_REGISTER) |
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490 mark_pseudo_reg_dead (orig_reg, REGNO (reg)); |
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491 else |
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492 mark_hard_reg_dead (reg); |
| 0 | 493 } |
| 494 | |
|
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495 /* If REG is a pseudo or a subreg of it, and the class of its allocno |
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496 intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the |
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497 rtx actually accessed, it may be indentical to DREG or a subreg of it. |
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498 Advance the current program point before making the conflict if |
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499 ADVANCE_P. Return TRUE if we will need to advance the current |
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500 program point. */ |
| 0 | 501 static bool |
|
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502 make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg, |
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503 bool advance_p) |
| 0 | 504 { |
|
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505 rtx orig_reg = reg; |
| 0 | 506 ira_allocno_t a; |
| 507 | |
| 508 if (GET_CODE (reg) == SUBREG) | |
| 509 reg = SUBREG_REG (reg); | |
|
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510 |
| 0 | 511 if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER) |
| 512 return advance_p; | |
|
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513 |
| 0 | 514 a = ira_curr_regno_allocno_map[REGNO (reg)]; |
| 515 if (! reg_classes_intersect_p (cl, ALLOCNO_COVER_CLASS (a))) | |
| 516 return advance_p; | |
| 517 | |
| 518 if (advance_p) | |
| 519 curr_point++; | |
| 520 | |
|
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521 mark_pseudo_reg_live (orig_reg, REGNO (reg)); |
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522 mark_pseudo_reg_live (orig_dreg, REGNO (dreg)); |
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523 mark_pseudo_reg_dead (orig_reg, REGNO (reg)); |
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524 mark_pseudo_reg_dead (orig_dreg, REGNO (dreg)); |
| 0 | 525 |
| 526 return false; | |
| 527 } | |
| 528 | |
| 529 /* Check and make if necessary conflicts for pseudo DREG of class | |
| 530 DEF_CL of the current insn with input operand USE of class USE_CL. | |
|
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531 ORIG_DREG is the rtx actually accessed, it may be indentical to |
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532 DREG or a subreg of it. Advance the current program point before |
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533 making the conflict if ADVANCE_P. Return TRUE if we will need to |
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534 advance the current program point. */ |
| 0 | 535 static bool |
|
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536 check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg, |
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537 enum reg_class def_cl, int use, |
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538 enum reg_class use_cl, bool advance_p) |
| 0 | 539 { |
| 540 if (! reg_classes_intersect_p (def_cl, use_cl)) | |
| 541 return advance_p; | |
|
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542 |
| 0 | 543 advance_p = make_pseudo_conflict (recog_data.operand[use], |
|
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544 use_cl, dreg, orig_dreg, advance_p); |
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545 |
| 0 | 546 /* Reload may end up swapping commutative operands, so you |
| 547 have to take both orderings into account. The | |
| 548 constraints for the two operands can be completely | |
| 549 different. (Indeed, if the constraints for the two | |
| 550 operands are the same for all alternatives, there's no | |
| 551 point marking them as commutative.) */ | |
|
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552 if (use < recog_data.n_operands - 1 |
| 0 | 553 && recog_data.constraints[use][0] == '%') |
| 554 advance_p | |
| 555 = make_pseudo_conflict (recog_data.operand[use + 1], | |
|
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556 use_cl, dreg, orig_dreg, advance_p); |
| 0 | 557 if (use >= 1 |
| 558 && recog_data.constraints[use - 1][0] == '%') | |
| 559 advance_p | |
| 560 = make_pseudo_conflict (recog_data.operand[use - 1], | |
|
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|
561 use_cl, dreg, orig_dreg, advance_p); |
| 0 | 562 return advance_p; |
| 563 } | |
| 564 | |
| 565 /* Check and make if necessary conflicts for definition DEF of class | |
| 566 DEF_CL of the current insn with input operands. Process only | |
| 567 constraints of alternative ALT. */ | |
| 568 static void | |
| 569 check_and_make_def_conflict (int alt, int def, enum reg_class def_cl) | |
| 570 { | |
| 571 int use, use_match; | |
| 572 ira_allocno_t a; | |
| 573 enum reg_class use_cl, acl; | |
| 574 bool advance_p; | |
| 575 rtx dreg = recog_data.operand[def]; | |
|
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576 rtx orig_dreg = dreg; |
|
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577 |
| 0 | 578 if (def_cl == NO_REGS) |
| 579 return; | |
|
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580 |
| 0 | 581 if (GET_CODE (dreg) == SUBREG) |
| 582 dreg = SUBREG_REG (dreg); | |
|
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583 |
| 0 | 584 if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER) |
| 585 return; | |
|
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586 |
| 0 | 587 a = ira_curr_regno_allocno_map[REGNO (dreg)]; |
| 588 acl = ALLOCNO_COVER_CLASS (a); | |
| 589 if (! reg_classes_intersect_p (acl, def_cl)) | |
| 590 return; | |
|
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591 |
| 0 | 592 advance_p = true; |
|
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593 |
| 0 | 594 for (use = 0; use < recog_data.n_operands; use++) |
| 595 { | |
|
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596 int alt1; |
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597 |
| 0 | 598 if (use == def || recog_data.operand_type[use] == OP_OUT) |
| 36 | 599 continue; |
|
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600 |
| 0 | 601 if (recog_op_alt[use][alt].anything_ok) |
| 602 use_cl = ALL_REGS; | |
| 603 else | |
| 604 use_cl = recog_op_alt[use][alt].cl; | |
|
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605 |
|
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606 /* If there's any alternative that allows USE to match DEF, do not |
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607 record a conflict. If that causes us to create an invalid |
|
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608 instruction due to the earlyclobber, reload must fix it up. */ |
|
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609 for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++) |
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610 if (recog_op_alt[use][alt1].matches == def |
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611 || (use < recog_data.n_operands - 1 |
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612 && recog_data.constraints[use][0] == '%' |
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613 && recog_op_alt[use + 1][alt1].matches == def) |
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614 || (use >= 1 |
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615 && recog_data.constraints[use - 1][0] == '%' |
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616 && recog_op_alt[use - 1][alt1].matches == def)) |
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617 break; |
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618 |
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619 if (alt1 < recog_data.n_alternatives) |
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620 continue; |
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621 |
|
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622 advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl, |
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623 use, use_cl, advance_p); |
|
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624 |
| 0 | 625 if ((use_match = recog_op_alt[use][alt].matches) >= 0) |
| 626 { | |
| 627 if (use_match == def) | |
| 36 | 628 continue; |
|
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629 |
| 0 | 630 if (recog_op_alt[use_match][alt].anything_ok) |
| 631 use_cl = ALL_REGS; | |
| 632 else | |
| 633 use_cl = recog_op_alt[use_match][alt].cl; | |
|
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634 advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl, |
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|
635 use, use_cl, advance_p); |
| 0 | 636 } |
| 637 } | |
| 638 } | |
| 639 | |
| 640 /* Make conflicts of early clobber pseudo registers of the current | |
| 641 insn with its inputs. Avoid introducing unnecessary conflicts by | |
| 642 checking classes of the constraints and pseudos because otherwise | |
| 643 significant code degradation is possible for some targets. */ | |
| 644 static void | |
| 645 make_early_clobber_and_input_conflicts (void) | |
| 646 { | |
| 647 int alt; | |
| 648 int def, def_match; | |
| 649 enum reg_class def_cl; | |
| 650 | |
| 651 for (alt = 0; alt < recog_data.n_alternatives; alt++) | |
| 652 for (def = 0; def < recog_data.n_operands; def++) | |
| 653 { | |
| 654 def_cl = NO_REGS; | |
| 655 if (recog_op_alt[def][alt].earlyclobber) | |
| 656 { | |
| 657 if (recog_op_alt[def][alt].anything_ok) | |
| 658 def_cl = ALL_REGS; | |
| 659 else | |
| 660 def_cl = recog_op_alt[def][alt].cl; | |
| 661 check_and_make_def_conflict (alt, def, def_cl); | |
| 662 } | |
| 663 if ((def_match = recog_op_alt[def][alt].matches) >= 0 | |
| 664 && (recog_op_alt[def_match][alt].earlyclobber | |
| 665 || recog_op_alt[def][alt].earlyclobber)) | |
| 666 { | |
| 667 if (recog_op_alt[def_match][alt].anything_ok) | |
| 668 def_cl = ALL_REGS; | |
| 669 else | |
| 670 def_cl = recog_op_alt[def_match][alt].cl; | |
| 671 check_and_make_def_conflict (alt, def, def_cl); | |
| 672 } | |
| 673 } | |
| 674 } | |
| 675 | |
| 676 /* Mark early clobber hard registers of the current INSN as live (if | |
| 677 LIVE_P) or dead. Return true if there are such registers. */ | |
| 678 static bool | |
| 679 mark_hard_reg_early_clobbers (rtx insn, bool live_p) | |
| 680 { | |
| 681 df_ref *def_rec; | |
| 682 bool set_p = false; | |
| 683 | |
| 684 for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++) | |
| 685 if (DF_REF_FLAGS_IS_SET (*def_rec, DF_REF_MUST_CLOBBER)) | |
| 686 { | |
| 687 rtx dreg = DF_REF_REG (*def_rec); | |
|
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688 |
| 0 | 689 if (GET_CODE (dreg) == SUBREG) |
| 690 dreg = SUBREG_REG (dreg); | |
| 691 if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER) | |
| 692 continue; | |
| 693 | |
| 694 /* Hard register clobbers are believed to be early clobber | |
| 695 because there is no way to say that non-operand hard | |
|
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696 register clobbers are not early ones. */ |
| 0 | 697 if (live_p) |
| 698 mark_ref_live (*def_rec); | |
| 699 else | |
| 700 mark_ref_dead (*def_rec); | |
| 701 set_p = true; | |
| 702 } | |
| 703 | |
| 704 return set_p; | |
| 705 } | |
| 706 | |
| 707 /* Checks that CONSTRAINTS permits to use only one hard register. If | |
| 708 it is so, the function returns the class of the hard register. | |
| 709 Otherwise it returns NO_REGS. */ | |
| 710 static enum reg_class | |
| 711 single_reg_class (const char *constraints, rtx op, rtx equiv_const) | |
| 712 { | |
| 713 int ignore_p; | |
| 714 enum reg_class cl, next_cl; | |
| 715 int c; | |
| 716 | |
| 717 cl = NO_REGS; | |
| 718 for (ignore_p = false; | |
| 719 (c = *constraints); | |
| 720 constraints += CONSTRAINT_LEN (c, constraints)) | |
| 721 if (c == '#') | |
| 722 ignore_p = true; | |
| 723 else if (c == ',') | |
| 724 ignore_p = false; | |
| 725 else if (! ignore_p) | |
| 726 switch (c) | |
| 727 { | |
| 728 case ' ': | |
| 729 case '\t': | |
| 730 case '=': | |
| 731 case '+': | |
| 732 case '*': | |
| 733 case '&': | |
| 734 case '%': | |
| 735 case '!': | |
| 736 case '?': | |
| 737 break; | |
| 738 case 'i': | |
| 739 if (CONSTANT_P (op) | |
| 740 || (equiv_const != NULL_RTX && CONSTANT_P (equiv_const))) | |
| 741 return NO_REGS; | |
| 742 break; | |
| 743 | |
| 744 case 'n': | |
|
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745 if (CONST_INT_P (op) |
| 0 | 746 || (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode) |
| 747 || (equiv_const != NULL_RTX | |
|
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748 && (CONST_INT_P (equiv_const) |
| 0 | 749 || (GET_CODE (equiv_const) == CONST_DOUBLE |
| 750 && GET_MODE (equiv_const) == VOIDmode)))) | |
| 751 return NO_REGS; | |
| 752 break; | |
|
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753 |
| 0 | 754 case 's': |
|
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|
755 if ((CONSTANT_P (op) && !CONST_INT_P (op) |
| 0 | 756 && (GET_CODE (op) != CONST_DOUBLE || GET_MODE (op) != VOIDmode)) |
| 757 || (equiv_const != NULL_RTX | |
| 758 && CONSTANT_P (equiv_const) | |
|
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759 && !CONST_INT_P (equiv_const) |
| 0 | 760 && (GET_CODE (equiv_const) != CONST_DOUBLE |
| 761 || GET_MODE (equiv_const) != VOIDmode))) | |
| 762 return NO_REGS; | |
| 763 break; | |
|
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764 |
| 0 | 765 case 'I': |
| 766 case 'J': | |
| 767 case 'K': | |
| 768 case 'L': | |
| 769 case 'M': | |
| 770 case 'N': | |
| 771 case 'O': | |
| 772 case 'P': | |
|
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773 if ((CONST_INT_P (op) |
| 0 | 774 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, constraints)) |
| 775 || (equiv_const != NULL_RTX | |
|
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776 && CONST_INT_P (equiv_const) |
| 0 | 777 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (equiv_const), |
| 778 c, constraints))) | |
| 779 return NO_REGS; | |
| 780 break; | |
|
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781 |
| 0 | 782 case 'E': |
| 783 case 'F': | |
| 784 if (GET_CODE (op) == CONST_DOUBLE | |
| 785 || (GET_CODE (op) == CONST_VECTOR | |
| 786 && GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT) | |
| 787 || (equiv_const != NULL_RTX | |
| 788 && (GET_CODE (equiv_const) == CONST_DOUBLE | |
| 789 || (GET_CODE (equiv_const) == CONST_VECTOR | |
| 790 && (GET_MODE_CLASS (GET_MODE (equiv_const)) | |
| 791 == MODE_VECTOR_FLOAT))))) | |
| 792 return NO_REGS; | |
| 793 break; | |
|
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794 |
| 0 | 795 case 'G': |
| 796 case 'H': | |
| 797 if ((GET_CODE (op) == CONST_DOUBLE | |
| 798 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, constraints)) | |
| 799 || (equiv_const != NULL_RTX | |
| 800 && GET_CODE (equiv_const) == CONST_DOUBLE | |
| 801 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (equiv_const, | |
| 802 c, constraints))) | |
| 803 return NO_REGS; | |
| 804 /* ??? what about memory */ | |
| 805 case 'r': | |
| 806 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': | |
| 807 case 'h': case 'j': case 'k': case 'l': | |
| 808 case 'q': case 't': case 'u': | |
| 809 case 'v': case 'w': case 'x': case 'y': case 'z': | |
| 810 case 'A': case 'B': case 'C': case 'D': | |
| 811 case 'Q': case 'R': case 'S': case 'T': case 'U': | |
| 812 case 'W': case 'Y': case 'Z': | |
| 813 next_cl = (c == 'r' | |
| 814 ? GENERAL_REGS | |
| 815 : REG_CLASS_FROM_CONSTRAINT (c, constraints)); | |
| 816 if ((cl != NO_REGS && next_cl != cl) | |
|
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817 || (ira_available_class_regs[next_cl] |
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|
818 > ira_reg_class_nregs[next_cl][GET_MODE (op)])) |
| 0 | 819 return NO_REGS; |
| 820 cl = next_cl; | |
| 821 break; | |
|
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822 |
| 0 | 823 case '0': case '1': case '2': case '3': case '4': |
| 824 case '5': case '6': case '7': case '8': case '9': | |
| 825 next_cl | |
| 826 = single_reg_class (recog_data.constraints[c - '0'], | |
| 827 recog_data.operand[c - '0'], NULL_RTX); | |
|
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828 if ((cl != NO_REGS && next_cl != cl) |
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829 || next_cl == NO_REGS |
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830 || (ira_available_class_regs[next_cl] |
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|
831 > ira_reg_class_nregs[next_cl][GET_MODE (op)])) |
| 0 | 832 return NO_REGS; |
| 833 cl = next_cl; | |
| 834 break; | |
|
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|
835 |
| 0 | 836 default: |
| 837 return NO_REGS; | |
| 838 } | |
| 839 return cl; | |
| 840 } | |
| 841 | |
| 842 /* The function checks that operand OP_NUM of the current insn can use | |
| 843 only one hard register. If it is so, the function returns the | |
| 844 class of the hard register. Otherwise it returns NO_REGS. */ | |
| 845 static enum reg_class | |
| 846 single_reg_operand_class (int op_num) | |
| 847 { | |
| 848 if (op_num < 0 || recog_data.n_alternatives == 0) | |
| 849 return NO_REGS; | |
| 850 return single_reg_class (recog_data.constraints[op_num], | |
| 851 recog_data.operand[op_num], NULL_RTX); | |
| 852 } | |
| 853 | |
|
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854 /* The function sets up hard register set *SET to hard registers which |
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855 might be used by insn reloads because the constraints are too |
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856 strict. */ |
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857 void |
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858 ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set) |
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859 { |
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860 int i, c, regno = 0; |
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861 bool ignore_p; |
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862 enum reg_class cl; |
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863 rtx op; |
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864 enum machine_mode mode; |
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865 |
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866 CLEAR_HARD_REG_SET (*set); |
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867 for (i = 0; i < recog_data.n_operands; i++) |
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868 { |
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869 op = recog_data.operand[i]; |
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870 |
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871 if (GET_CODE (op) == SUBREG) |
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872 op = SUBREG_REG (op); |
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873 |
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874 if (GET_CODE (op) == SCRATCH |
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875 || (REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER)) |
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876 { |
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877 const char *p = recog_data.constraints[i]; |
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878 |
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879 mode = (GET_CODE (op) == SCRATCH |
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880 ? GET_MODE (op) : PSEUDO_REGNO_MODE (regno)); |
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881 cl = NO_REGS; |
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882 for (ignore_p = false; (c = *p); p += CONSTRAINT_LEN (c, p)) |
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883 if (c == '#') |
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884 ignore_p = true; |
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885 else if (c == ',') |
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886 ignore_p = false; |
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887 else if (! ignore_p) |
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888 switch (c) |
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889 { |
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890 case 'r': |
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891 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': |
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892 case 'h': case 'j': case 'k': case 'l': |
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893 case 'q': case 't': case 'u': |
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894 case 'v': case 'w': case 'x': case 'y': case 'z': |
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895 case 'A': case 'B': case 'C': case 'D': |
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896 case 'Q': case 'R': case 'S': case 'T': case 'U': |
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897 case 'W': case 'Y': case 'Z': |
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898 cl = (c == 'r' |
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899 ? GENERAL_REGS |
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900 : REG_CLASS_FROM_CONSTRAINT (c, p)); |
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901 if (cl != NO_REGS |
|
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902 /* There is no register pressure problem if all of the |
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903 regs in this class are fixed. */ |
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904 && ira_available_class_regs[cl] != 0 |
|
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905 && (ira_available_class_regs[cl] |
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906 <= ira_reg_class_nregs[cl][mode])) |
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907 IOR_HARD_REG_SET (*set, reg_class_contents[cl]); |
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908 break; |
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909 } |
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910 } |
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911 } |
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912 } |
| 0 | 913 /* Processes input operands, if IN_P, or output operands otherwise of |
| 914 the current insn with FREQ to find allocno which can use only one | |
| 915 hard register and makes other currently living allocnos conflicting | |
| 916 with the hard register. */ | |
| 917 static void | |
| 918 process_single_reg_class_operands (bool in_p, int freq) | |
| 919 { | |
|
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920 int i, regno; |
| 0 | 921 unsigned int px; |
|
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922 enum reg_class cl; |
| 0 | 923 rtx operand; |
| 924 ira_allocno_t operand_a, a; | |
| 925 | |
| 926 for (i = 0; i < recog_data.n_operands; i++) | |
| 927 { | |
| 928 operand = recog_data.operand[i]; | |
| 929 if (in_p && recog_data.operand_type[i] != OP_IN | |
| 930 && recog_data.operand_type[i] != OP_INOUT) | |
| 931 continue; | |
| 932 if (! in_p && recog_data.operand_type[i] != OP_OUT | |
| 933 && recog_data.operand_type[i] != OP_INOUT) | |
| 934 continue; | |
| 935 cl = single_reg_operand_class (i); | |
| 936 if (cl == NO_REGS) | |
| 937 continue; | |
| 938 | |
| 939 operand_a = NULL; | |
| 940 | |
| 941 if (GET_CODE (operand) == SUBREG) | |
| 942 operand = SUBREG_REG (operand); | |
|
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943 |
| 0 | 944 if (REG_P (operand) |
| 945 && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER) | |
| 946 { | |
| 947 enum reg_class cover_class; | |
| 948 | |
| 949 operand_a = ira_curr_regno_allocno_map[regno]; | |
| 950 cover_class = ALLOCNO_COVER_CLASS (operand_a); | |
| 951 if (ira_class_subset_p[cl][cover_class] | |
|
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952 && ira_class_hard_regs_num[cl] != 0) |
| 0 | 953 { |
|
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954 /* View the desired allocation of OPERAND as: |
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955 |
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956 (REG:YMODE YREGNO), |
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957 |
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958 a simplification of: |
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959 |
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960 (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */ |
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961 enum machine_mode ymode, xmode; |
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962 int xregno, yregno; |
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963 HOST_WIDE_INT offset; |
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964 |
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965 xmode = recog_data.operand_mode[i]; |
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966 xregno = ira_class_hard_regs[cl][0]; |
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967 ymode = ALLOCNO_MODE (operand_a); |
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968 offset = subreg_lowpart_offset (ymode, xmode); |
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969 yregno = simplify_subreg_regno (xregno, xmode, offset, ymode); |
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970 if (yregno >= 0 |
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971 && ira_class_hard_reg_index[cover_class][yregno] >= 0) |
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972 { |
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973 int cost; |
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974 |
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975 ira_allocate_and_set_costs |
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976 (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a), |
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977 cover_class, 0); |
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978 cost |
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979 = (freq |
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980 * (in_p |
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981 ? ira_get_register_move_cost (xmode, cover_class, cl) |
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982 : ira_get_register_move_cost (xmode, cl, |
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983 cover_class))); |
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984 ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a) |
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985 [ira_class_hard_reg_index[cover_class][yregno]] -= cost; |
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986 } |
| 0 | 987 } |
| 988 } | |
| 989 | |
|
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990 EXECUTE_IF_SET_IN_SPARSESET (objects_live, px) |
| 0 | 991 { |
|
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992 ira_object_t obj = ira_object_id_map[px]; |
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993 a = OBJECT_ALLOCNO (obj); |
| 0 | 994 if (a != operand_a) |
| 995 { | |
| 996 /* We could increase costs of A instead of making it | |
| 997 conflicting with the hard register. But it works worse | |
| 998 because it will be spilled in reload in anyway. */ | |
|
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999 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), |
| 0 | 1000 reg_class_contents[cl]); |
|
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1001 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), |
| 0 | 1002 reg_class_contents[cl]); |
| 1003 } | |
| 1004 } | |
| 1005 } | |
| 1006 } | |
| 1007 | |
|
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1008 /* Return true when one of the predecessor edges of BB is marked with |
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1009 EDGE_ABNORMAL_CALL or EDGE_EH. */ |
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1010 static bool |
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1011 bb_has_abnormal_call_pred (basic_block bb) |
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1012 { |
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1013 edge e; |
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1014 edge_iterator ei; |
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1015 |
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1016 FOR_EACH_EDGE (e, ei, bb->preds) |
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1017 { |
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1018 if (e->flags & (EDGE_ABNORMAL_CALL | EDGE_EH)) |
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1019 return true; |
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1020 } |
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1021 return false; |
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1022 } |
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1023 |
| 0 | 1024 /* Process insns of the basic block given by its LOOP_TREE_NODE to |
| 1025 update allocno live ranges, allocno hard register conflicts, | |
| 1026 intersected calls, and register pressure info for allocnos for the | |
| 1027 basic block for and regions containing the basic block. */ | |
| 1028 static void | |
| 1029 process_bb_node_lives (ira_loop_tree_node_t loop_tree_node) | |
| 1030 { | |
| 1031 int i, freq; | |
| 1032 unsigned int j; | |
| 1033 basic_block bb; | |
| 1034 rtx insn; | |
| 1035 bitmap_iterator bi; | |
| 1036 bitmap reg_live_out; | |
| 1037 unsigned int px; | |
| 1038 bool set_p; | |
| 1039 | |
| 1040 bb = loop_tree_node->bb; | |
| 1041 if (bb != NULL) | |
| 1042 { | |
| 1043 for (i = 0; i < ira_reg_class_cover_size; i++) | |
| 1044 { | |
| 1045 curr_reg_pressure[ira_reg_class_cover[i]] = 0; | |
| 1046 high_pressure_start_point[ira_reg_class_cover[i]] = -1; | |
| 1047 } | |
| 1048 curr_bb_node = loop_tree_node; | |
| 1049 reg_live_out = DF_LR_OUT (bb); | |
|
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1050 sparseset_clear (objects_live); |
| 0 | 1051 REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out); |
| 1052 AND_COMPL_HARD_REG_SET (hard_regs_live, eliminable_regset); | |
| 1053 AND_COMPL_HARD_REG_SET (hard_regs_live, ira_no_alloc_regs); | |
| 1054 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
| 1055 if (TEST_HARD_REG_BIT (hard_regs_live, i)) | |
| 1056 { | |
| 1057 enum reg_class cover_class, cl; | |
|
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1058 |
| 0 | 1059 cover_class = ira_class_translate[REGNO_REG_CLASS (i)]; |
| 1060 for (j = 0; | |
| 1061 (cl = ira_reg_class_super_classes[cover_class][j]) | |
| 1062 != LIM_REG_CLASSES; | |
| 1063 j++) | |
| 1064 { | |
| 1065 curr_reg_pressure[cl]++; | |
| 1066 if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl]) | |
| 1067 curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl]; | |
| 1068 ira_assert (curr_reg_pressure[cl] | |
| 1069 <= ira_available_class_regs[cl]); | |
| 1070 } | |
| 1071 } | |
| 1072 EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi) | |
|
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1073 mark_pseudo_regno_live (j); |
|
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1074 |
| 0 | 1075 freq = REG_FREQ_FROM_BB (bb); |
| 1076 if (freq == 0) | |
| 1077 freq = 1; | |
| 1078 | |
| 1079 /* Invalidate all allocno_saved_at_call entries. */ | |
| 1080 last_call_num++; | |
| 1081 | |
| 1082 /* Scan the code of this basic block, noting which allocnos and | |
| 1083 hard regs are born or die. | |
| 1084 | |
| 1085 Note that this loop treats uninitialized values as live until | |
| 1086 the beginning of the block. For example, if an instruction | |
| 1087 uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever | |
| 1088 set, FOO will remain live until the beginning of the block. | |
| 1089 Likewise if FOO is not set at all. This is unnecessarily | |
| 1090 pessimistic, but it probably doesn't matter much in practice. */ | |
| 1091 FOR_BB_INSNS_REVERSE (bb, insn) | |
| 1092 { | |
| 1093 df_ref *def_rec, *use_rec; | |
| 1094 bool call_p; | |
|
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1095 |
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1096 if (!NONDEBUG_INSN_P (insn)) |
| 0 | 1097 continue; |
|
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1098 |
| 0 | 1099 if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) |
| 1100 fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n", | |
| 1101 INSN_UID (insn), loop_tree_node->parent->loop->num, | |
| 1102 curr_point); | |
| 1103 | |
| 1104 /* Mark each defined value as live. We need to do this for | |
| 1105 unused values because they still conflict with quantities | |
| 1106 that are live at the time of the definition. | |
| 1107 | |
| 1108 Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such | |
| 1109 references represent the effect of the called function | |
| 1110 on a call-clobbered register. Marking the register as | |
| 1111 live would stop us from allocating it to a call-crossing | |
| 1112 allocno. */ | |
| 1113 call_p = CALL_P (insn); | |
| 1114 for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++) | |
| 1115 if (!call_p || !DF_REF_FLAGS_IS_SET (*def_rec, DF_REF_MAY_CLOBBER)) | |
| 1116 mark_ref_live (*def_rec); | |
| 1117 | |
| 1118 /* If INSN has multiple outputs, then any value used in one | |
| 1119 of the outputs conflicts with the other outputs. Model this | |
| 1120 by making the used value live during the output phase. | |
| 1121 | |
| 1122 It is unsafe to use !single_set here since it will ignore | |
| 1123 an unused output. Just because an output is unused does | |
| 1124 not mean the compiler can assume the side effect will not | |
| 1125 occur. Consider if ALLOCNO appears in the address of an | |
| 1126 output and we reload the output. If we allocate ALLOCNO | |
| 1127 to the same hard register as an unused output we could | |
| 1128 set the hard register before the output reload insn. */ | |
| 1129 if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) | |
| 1130 for (use_rec = DF_INSN_USES (insn); *use_rec; use_rec++) | |
| 1131 { | |
| 1132 int i; | |
| 1133 rtx reg; | |
| 1134 | |
| 1135 reg = DF_REF_REG (*use_rec); | |
| 1136 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
| 1137 { | |
| 1138 rtx set; | |
| 1139 | |
| 1140 set = XVECEXP (PATTERN (insn), 0, i); | |
| 1141 if (GET_CODE (set) == SET | |
| 1142 && reg_overlap_mentioned_p (reg, SET_DEST (set))) | |
| 1143 { | |
| 1144 /* After the previous loop, this is a no-op if | |
| 1145 REG is contained within SET_DEST (SET). */ | |
| 1146 mark_ref_live (*use_rec); | |
| 1147 break; | |
| 1148 } | |
| 1149 } | |
| 1150 } | |
|
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1151 |
| 0 | 1152 extract_insn (insn); |
| 1153 preprocess_constraints (); | |
| 1154 process_single_reg_class_operands (false, freq); | |
|
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1155 |
| 0 | 1156 /* See which defined values die here. */ |
| 1157 for (def_rec = DF_INSN_DEFS (insn); *def_rec; def_rec++) | |
| 1158 if (!call_p || !DF_REF_FLAGS_IS_SET (*def_rec, DF_REF_MAY_CLOBBER)) | |
| 1159 mark_ref_dead (*def_rec); | |
| 1160 | |
| 1161 if (call_p) | |
| 1162 { | |
| 1163 last_call_num++; | |
|
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1164 sparseset_clear (allocnos_processed); |
| 0 | 1165 /* The current set of live allocnos are live across the call. */ |
|
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1166 EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
| 0 | 1167 { |
|
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1168 ira_object_t obj = ira_object_id_map[i]; |
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1169 ira_allocno_t a = OBJECT_ALLOCNO (obj); |
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1170 int num = ALLOCNO_NUM (a); |
|
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1171 |
|
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1172 /* Don't allocate allocnos that cross setjmps or any |
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1173 call, if this function receives a nonlocal |
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1174 goto. */ |
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1175 if (cfun->has_nonlocal_label |
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1176 || find_reg_note (insn, REG_SETJMP, |
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1177 NULL_RTX) != NULL_RTX) |
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1178 { |
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1179 SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj)); |
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1180 SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)); |
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1181 } |
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1182 if (can_throw_internal (insn)) |
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1183 { |
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1184 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj), |
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1185 call_used_reg_set); |
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1186 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), |
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1187 call_used_reg_set); |
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1188 } |
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1189 |
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1190 if (sparseset_bit_p (allocnos_processed, num)) |
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1191 continue; |
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1192 sparseset_set_bit (allocnos_processed, num); |
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1193 |
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1194 if (allocno_saved_at_call[num] != last_call_num) |
| 0 | 1195 /* Here we are mimicking caller-save.c behaviour |
| 1196 which does not save hard register at a call if | |
| 1197 it was saved on previous call in the same basic | |
| 1198 block and the hard register was not mentioned | |
| 1199 between the two calls. */ | |
| 1200 ALLOCNO_CALL_FREQ (a) += freq; | |
| 1201 /* Mark it as saved at the next call. */ | |
|
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1202 allocno_saved_at_call[num] = last_call_num + 1; |
| 0 | 1203 ALLOCNO_CALLS_CROSSED_NUM (a)++; |
| 1204 } | |
| 1205 } | |
|
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1206 |
| 0 | 1207 make_early_clobber_and_input_conflicts (); |
| 1208 | |
| 1209 curr_point++; | |
| 1210 | |
| 1211 /* Mark each used value as live. */ | |
| 1212 for (use_rec = DF_INSN_USES (insn); *use_rec; use_rec++) | |
| 1213 mark_ref_live (*use_rec); | |
| 1214 | |
| 1215 process_single_reg_class_operands (true, freq); | |
|
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1216 |
| 0 | 1217 set_p = mark_hard_reg_early_clobbers (insn, true); |
| 1218 | |
| 1219 if (set_p) | |
| 1220 { | |
| 1221 mark_hard_reg_early_clobbers (insn, false); | |
| 1222 | |
| 1223 /* Mark each hard reg as live again. For example, a | |
| 1224 hard register can be in clobber and in an insn | |
| 1225 input. */ | |
| 1226 for (use_rec = DF_INSN_USES (insn); *use_rec; use_rec++) | |
| 1227 { | |
| 1228 rtx ureg = DF_REF_REG (*use_rec); | |
|
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1229 |
| 0 | 1230 if (GET_CODE (ureg) == SUBREG) |
| 1231 ureg = SUBREG_REG (ureg); | |
| 1232 if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER) | |
| 1233 continue; | |
|
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1234 |
| 0 | 1235 mark_ref_live (*use_rec); |
| 1236 } | |
| 1237 } | |
| 1238 | |
| 1239 curr_point++; | |
| 1240 } | |
| 1241 | |
| 1242 #ifdef EH_RETURN_DATA_REGNO | |
| 1243 if (bb_has_eh_pred (bb)) | |
| 1244 for (j = 0; ; ++j) | |
| 1245 { | |
| 1246 unsigned int regno = EH_RETURN_DATA_REGNO (j); | |
| 1247 if (regno == INVALID_REGNUM) | |
| 1248 break; | |
|
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1249 make_hard_regno_born (regno); |
| 0 | 1250 } |
| 1251 #endif | |
| 1252 | |
| 1253 /* Allocnos can't go in stack regs at the start of a basic block | |
| 1254 that is reached by an abnormal edge. Likewise for call | |
| 1255 clobbered regs, because caller-save, fixup_abnormal_edges and | |
| 1256 possibly the table driven EH machinery are not quite ready to | |
| 1257 handle such allocnos live across such edges. */ | |
| 1258 if (bb_has_abnormal_pred (bb)) | |
| 1259 { | |
| 1260 #ifdef STACK_REGS | |
|
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1261 EXECUTE_IF_SET_IN_SPARSESET (objects_live, px) |
| 0 | 1262 { |
|
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1263 ira_allocno_t a = OBJECT_ALLOCNO (ira_object_id_map[px]); |
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1264 ALLOCNO_NO_STACK_REG_P (a) = true; |
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1265 ALLOCNO_TOTAL_NO_STACK_REG_P (a) = true; |
| 0 | 1266 } |
| 1267 for (px = FIRST_STACK_REG; px <= LAST_STACK_REG; px++) | |
|
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1268 make_hard_regno_born (px); |
| 0 | 1269 #endif |
| 1270 /* No need to record conflicts for call clobbered regs if we | |
| 1271 have nonlocal labels around, as we don't ever try to | |
| 1272 allocate such regs in this case. */ | |
|
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1273 if (!cfun->has_nonlocal_label && bb_has_abnormal_call_pred (bb)) |
| 0 | 1274 for (px = 0; px < FIRST_PSEUDO_REGISTER; px++) |
| 1275 if (call_used_regs[px]) | |
|
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1276 make_hard_regno_born (px); |
| 0 | 1277 } |
| 1278 | |
|
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1279 EXECUTE_IF_SET_IN_SPARSESET (objects_live, i) |
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1280 make_object_dead (ira_object_id_map[i]); |
| 0 | 1281 |
| 1282 curr_point++; | |
| 1283 | |
| 1284 } | |
| 1285 /* Propagate register pressure to upper loop tree nodes: */ | |
| 1286 if (loop_tree_node != ira_loop_tree_root) | |
| 1287 for (i = 0; i < ira_reg_class_cover_size; i++) | |
| 1288 { | |
| 1289 enum reg_class cover_class; | |
| 1290 | |
| 1291 cover_class = ira_reg_class_cover[i]; | |
| 1292 if (loop_tree_node->reg_pressure[cover_class] | |
| 1293 > loop_tree_node->parent->reg_pressure[cover_class]) | |
| 1294 loop_tree_node->parent->reg_pressure[cover_class] | |
| 1295 = loop_tree_node->reg_pressure[cover_class]; | |
| 1296 } | |
| 1297 } | |
| 1298 | |
| 1299 /* Create and set up IRA_START_POINT_RANGES and | |
| 1300 IRA_FINISH_POINT_RANGES. */ | |
| 1301 static void | |
| 1302 create_start_finish_chains (void) | |
| 1303 { | |
|
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1304 ira_object_t obj; |
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1305 ira_object_iterator oi; |
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1306 live_range_t r; |
| 0 | 1307 |
| 1308 ira_start_point_ranges | |
|
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1309 = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t)); |
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1310 memset (ira_start_point_ranges, 0, ira_max_point * sizeof (live_range_t)); |
| 0 | 1311 ira_finish_point_ranges |
|
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1312 = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t)); |
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1313 memset (ira_finish_point_ranges, 0, ira_max_point * sizeof (live_range_t)); |
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1314 FOR_EACH_OBJECT (obj, oi) |
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1315 for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) |
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1316 { |
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1317 r->start_next = ira_start_point_ranges[r->start]; |
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1318 ira_start_point_ranges[r->start] = r; |
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1319 r->finish_next = ira_finish_point_ranges[r->finish]; |
| 0 | 1320 ira_finish_point_ranges[r->finish] = r; |
|
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1321 } |
| 0 | 1322 } |
| 1323 | |
| 1324 /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after | |
| 1325 new live ranges and program points were added as a result if new | |
| 1326 insn generation. */ | |
| 1327 void | |
| 1328 ira_rebuild_start_finish_chains (void) | |
| 1329 { | |
| 1330 ira_free (ira_finish_point_ranges); | |
| 1331 ira_free (ira_start_point_ranges); | |
| 1332 create_start_finish_chains (); | |
| 1333 } | |
| 1334 | |
| 1335 /* Compress allocno live ranges by removing program points where | |
| 1336 nothing happens. */ | |
| 1337 static void | |
| 1338 remove_some_program_points_and_update_live_ranges (void) | |
| 1339 { | |
| 1340 unsigned i; | |
| 1341 int n; | |
| 1342 int *map; | |
|
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1343 ira_object_t obj; |
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1344 ira_object_iterator oi; |
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1345 live_range_t r; |
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1346 sbitmap born_or_dead, born, dead; |
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1347 sbitmap_iterator sbi; |
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1348 bool born_p, dead_p, prev_born_p, prev_dead_p; |
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1349 |
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1350 born = sbitmap_alloc (ira_max_point); |
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1351 dead = sbitmap_alloc (ira_max_point); |
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1352 sbitmap_zero (born); |
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1353 sbitmap_zero (dead); |
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1354 FOR_EACH_OBJECT (obj, oi) |
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1355 for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) |
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1356 { |
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1357 ira_assert (r->start <= r->finish); |
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1358 SET_BIT (born, r->start); |
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1359 SET_BIT (dead, r->finish); |
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1360 } |
|
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1361 |
|
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1362 born_or_dead = sbitmap_alloc (ira_max_point); |
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1363 sbitmap_a_or_b (born_or_dead, born, dead); |
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1364 map = (int *) ira_allocate (sizeof (int) * ira_max_point); |
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1365 n = -1; |
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1366 prev_born_p = prev_dead_p = false; |
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1367 EXECUTE_IF_SET_IN_SBITMAP (born_or_dead, 0, i, sbi) |
| 0 | 1368 { |
|
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1369 born_p = TEST_BIT (born, i); |
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1370 dead_p = TEST_BIT (dead, i); |
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1371 if ((prev_born_p && ! prev_dead_p && born_p && ! dead_p) |
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1372 || (prev_dead_p && ! prev_born_p && dead_p && ! born_p)) |
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1373 map[i] = n; |
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1374 else |
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1375 map[i] = ++n; |
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1376 prev_born_p = born_p; |
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1377 prev_dead_p = dead_p; |
| 0 | 1378 } |
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1379 sbitmap_free (born_or_dead); |
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1380 sbitmap_free (born); |
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1381 sbitmap_free (dead); |
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1382 n++; |
| 0 | 1383 if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL) |
| 1384 fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n", | |
| 1385 ira_max_point, n, 100 * n / ira_max_point); | |
| 1386 ira_max_point = n; | |
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1387 |
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1388 FOR_EACH_OBJECT (obj, oi) |
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1389 for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next) |
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1390 { |
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1391 r->start = map[r->start]; |
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1392 r->finish = map[r->finish]; |
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1393 } |
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1394 |
| 0 | 1395 ira_free (map); |
| 1396 } | |
| 1397 | |
| 1398 /* Print live ranges R to file F. */ | |
| 1399 void | |
|
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1400 ira_print_live_range_list (FILE *f, live_range_t r) |
| 0 | 1401 { |
| 1402 for (; r != NULL; r = r->next) | |
| 1403 fprintf (f, " [%d..%d]", r->start, r->finish); | |
| 1404 fprintf (f, "\n"); | |
| 1405 } | |
| 1406 | |
| 1407 /* Print live ranges R to stderr. */ | |
| 1408 void | |
|
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1409 ira_debug_live_range_list (live_range_t r) |
| 0 | 1410 { |
| 1411 ira_print_live_range_list (stderr, r); | |
| 1412 } | |
| 1413 | |
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1414 /* Print live ranges of object OBJ to file F. */ |
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1415 static void |
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1416 print_object_live_ranges (FILE *f, ira_object_t obj) |
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1417 { |
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1418 ira_print_live_range_list (f, OBJECT_LIVE_RANGES (obj)); |
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1419 } |
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1420 |
| 0 | 1421 /* Print live ranges of allocno A to file F. */ |
| 1422 static void | |
| 1423 print_allocno_live_ranges (FILE *f, ira_allocno_t a) | |
| 1424 { | |
|
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1425 int n = ALLOCNO_NUM_OBJECTS (a); |
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1426 int i; |
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1427 for (i = 0; i < n; i++) |
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1428 { |
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1429 fprintf (f, " a%d(r%d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); |
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1430 if (n > 1) |
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1431 fprintf (f, " [%d]", i); |
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1432 fprintf (f, "):"); |
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1433 print_object_live_ranges (f, ALLOCNO_OBJECT (a, i)); |
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1434 } |
| 0 | 1435 } |
| 1436 | |
| 1437 /* Print live ranges of allocno A to stderr. */ | |
| 1438 void | |
| 1439 ira_debug_allocno_live_ranges (ira_allocno_t a) | |
| 1440 { | |
| 1441 print_allocno_live_ranges (stderr, a); | |
| 1442 } | |
| 1443 | |
| 1444 /* Print live ranges of all allocnos to file F. */ | |
| 1445 static void | |
| 1446 print_live_ranges (FILE *f) | |
| 1447 { | |
| 1448 ira_allocno_t a; | |
| 1449 ira_allocno_iterator ai; | |
| 1450 | |
| 1451 FOR_EACH_ALLOCNO (a, ai) | |
| 1452 print_allocno_live_ranges (f, a); | |
| 1453 } | |
| 1454 | |
| 1455 /* Print live ranges of all allocnos to stderr. */ | |
| 1456 void | |
| 1457 ira_debug_live_ranges (void) | |
| 1458 { | |
| 1459 print_live_ranges (stderr); | |
| 1460 } | |
| 1461 | |
| 1462 /* The main entry function creates live ranges, set up | |
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1463 CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and |
| 0 | 1464 calculate register pressure info. */ |
| 1465 void | |
| 1466 ira_create_allocno_live_ranges (void) | |
| 1467 { | |
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1468 objects_live = sparseset_alloc (ira_objects_num); |
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1469 allocnos_processed = sparseset_alloc (ira_allocnos_num); |
| 0 | 1470 curr_point = 0; |
| 1471 last_call_num = 0; | |
| 1472 allocno_saved_at_call | |
| 1473 = (int *) ira_allocate (ira_allocnos_num * sizeof (int)); | |
| 1474 memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int)); | |
| 1475 ira_traverse_loop_tree (true, ira_loop_tree_root, NULL, | |
| 1476 process_bb_node_lives); | |
| 1477 ira_max_point = curr_point; | |
| 1478 create_start_finish_chains (); | |
| 1479 if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
| 1480 print_live_ranges (ira_dump_file); | |
| 1481 /* Clean up. */ | |
| 1482 ira_free (allocno_saved_at_call); | |
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1483 sparseset_free (objects_live); |
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1484 sparseset_free (allocnos_processed); |
| 0 | 1485 } |
| 1486 | |
| 1487 /* Compress allocno live ranges. */ | |
| 1488 void | |
| 1489 ira_compress_allocno_live_ranges (void) | |
| 1490 { | |
| 1491 remove_some_program_points_and_update_live_ranges (); | |
| 1492 ira_rebuild_start_finish_chains (); | |
| 1493 if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) | |
| 1494 { | |
| 1495 fprintf (ira_dump_file, "Ranges after the compression:\n"); | |
| 1496 print_live_ranges (ira_dump_file); | |
| 1497 } | |
| 1498 } | |
| 1499 | |
| 1500 /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */ | |
| 1501 void | |
| 1502 ira_finish_allocno_live_ranges (void) | |
| 1503 { | |
| 1504 ira_free (ira_finish_point_ranges); | |
| 1505 ira_free (ira_start_point_ranges); | |
| 1506 } |