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1 /* Machine description for AArch64 architecture.
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2 Copyright (C) 2009-2020 Free Software Foundation, Inc.
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3 Contributed by ARM Ltd.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it
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8 under the terms of the GNU General Public License as published by
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9 the Free Software Foundation; either version 3, or (at your option)
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10 any later version.
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11
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12 GCC is distributed in the hope that it will be useful, but
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13 WITHOUT ANY WARRANTY; without even the implied warranty of
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14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 General Public License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21 /* Important note about Carry generation in AArch64.
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22
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23 Unlike some architectures, the C flag generated by a subtract
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24 operation, or a simple compare operation is set to 1 if the result
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25 does not overflow in an unsigned sense. That is, if there is no
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26 borrow needed from a higher word. That means that overflow from
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27 addition will set C, but overflow from a subtraction will clear C.
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28 We use CC_Cmode to represent detection of overflow from addition as
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29 CCmode is used for 'normal' compare (subtraction) operations. For
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30 ADC, the representation becomes more complex still, since we cannot
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31 use the normal idiom of comparing the result to one of the input
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32 operands; instead we use CC_ADCmode to represent this case. */
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33 CC_MODE (CCFP);
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34 CC_MODE (CCFPE);
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35 CC_MODE (CC_SWP);
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36 CC_MODE (CC_NZC); /* Only N, Z and C bits of condition flags are valid.
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37 (Used with SVE predicate tests.) */
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38 CC_MODE (CC_NZ); /* Only N and Z bits of condition flags are valid. */
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39 CC_MODE (CC_Z); /* Only Z bit of condition flags is valid. */
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40 CC_MODE (CC_C); /* C represents unsigned overflow of a simple addition. */
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41 CC_MODE (CC_ADC); /* Unsigned overflow from an ADC (add with carry). */
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42 CC_MODE (CC_V); /* Only V bit of condition flags is valid. */
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43
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44 /* Half-precision floating point for __fp16. */
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45 FLOAT_MODE (HF, 2, 0);
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46 ADJUST_FLOAT_FORMAT (HF, &ieee_half_format);
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47
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48 /* Vector modes. */
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49
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50 VECTOR_BOOL_MODE (VNx16BI, 16, 2);
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51 VECTOR_BOOL_MODE (VNx8BI, 8, 2);
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52 VECTOR_BOOL_MODE (VNx4BI, 4, 2);
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53 VECTOR_BOOL_MODE (VNx2BI, 2, 2);
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54
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55 ADJUST_NUNITS (VNx16BI, aarch64_sve_vg * 8);
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56 ADJUST_NUNITS (VNx8BI, aarch64_sve_vg * 4);
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57 ADJUST_NUNITS (VNx4BI, aarch64_sve_vg * 2);
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58 ADJUST_NUNITS (VNx2BI, aarch64_sve_vg);
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59
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60 ADJUST_ALIGNMENT (VNx16BI, 2);
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61 ADJUST_ALIGNMENT (VNx8BI, 2);
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62 ADJUST_ALIGNMENT (VNx4BI, 2);
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63 ADJUST_ALIGNMENT (VNx2BI, 2);
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64
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65 /* Bfloat16 modes. */
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66 FLOAT_MODE (BF, 2, 0);
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67 ADJUST_FLOAT_FORMAT (BF, &arm_bfloat_half_format);
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68
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69 VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI. */
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70 VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI. */
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71 VECTOR_MODES (FLOAT, 8); /* V2SF. */
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72 VECTOR_MODES (FLOAT, 16); /* V4SF V2DF. */
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73 VECTOR_MODE (FLOAT, DF, 1); /* V1DF. */
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74 VECTOR_MODE (FLOAT, HF, 2); /* V2HF. */
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75
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76 /* Oct Int: 256-bit integer mode needed for 32-byte vector arguments. */
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77 INT_MODE (OI, 32);
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78
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79 /* Opaque integer modes for 3 or 4 Neon q-registers / 6 or 8 Neon d-registers
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80 (2 d-regs = 1 q-reg = TImode). */
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81 INT_MODE (CI, 48);
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82 INT_MODE (XI, 64);
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83
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84 /* Define SVE modes for NVECS vectors. VB, VH, VS and VD are the prefixes
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85 for 8-bit, 16-bit, 32-bit and 64-bit elements respectively. It isn't
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86 strictly necessary to set the alignment here, since the default would
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87 be clamped to BIGGEST_ALIGNMENT anyhow, but it seems clearer. */
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88 #define SVE_MODES(NVECS, VB, VH, VS, VD) \
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89 VECTOR_MODES_WITH_PREFIX (VNx, INT, 16 * NVECS, 0); \
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90 VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 16 * NVECS, 0); \
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91 \
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92 ADJUST_NUNITS (VB##QI, aarch64_sve_vg * NVECS * 8); \
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93 ADJUST_NUNITS (VH##HI, aarch64_sve_vg * NVECS * 4); \
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94 ADJUST_NUNITS (VS##SI, aarch64_sve_vg * NVECS * 2); \
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95 ADJUST_NUNITS (VD##DI, aarch64_sve_vg * NVECS); \
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96 ADJUST_NUNITS (VH##BF, aarch64_sve_vg * NVECS * 4); \
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97 ADJUST_NUNITS (VH##HF, aarch64_sve_vg * NVECS * 4); \
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98 ADJUST_NUNITS (VS##SF, aarch64_sve_vg * NVECS * 2); \
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99 ADJUST_NUNITS (VD##DF, aarch64_sve_vg * NVECS); \
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100 \
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101 ADJUST_ALIGNMENT (VB##QI, 16); \
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102 ADJUST_ALIGNMENT (VH##HI, 16); \
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103 ADJUST_ALIGNMENT (VS##SI, 16); \
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104 ADJUST_ALIGNMENT (VD##DI, 16); \
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105 ADJUST_ALIGNMENT (VH##BF, 16); \
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106 ADJUST_ALIGNMENT (VH##HF, 16); \
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107 ADJUST_ALIGNMENT (VS##SF, 16); \
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108 ADJUST_ALIGNMENT (VD##DF, 16);
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109
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110 /* Give SVE vectors the names normally used for 256-bit vectors.
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111 The actual number depends on command-line flags. */
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112 SVE_MODES (1, VNx16, VNx8, VNx4, VNx2)
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113 SVE_MODES (2, VNx32, VNx16, VNx8, VNx4)
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114 SVE_MODES (3, VNx48, VNx24, VNx12, VNx6)
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115 SVE_MODES (4, VNx64, VNx32, VNx16, VNx8)
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116
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117 /* Partial SVE vectors:
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118
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119 VNx2QI VNx4QI VNx8QI
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120 VNx2HI VNx4HI
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121 VNx2SI
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122
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123 In memory they occupy contiguous locations, in the same way as fixed-length
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124 vectors. E.g. VNx8QImode is half the size of VNx16QImode.
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125
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126 Passing 1 as the final argument ensures that the modes come after all
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127 other modes in the GET_MODE_WIDER chain, so that we never pick them
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128 in preference to a full vector mode. */
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129 VECTOR_MODES_WITH_PREFIX (VNx, INT, 2, 1);
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130 VECTOR_MODES_WITH_PREFIX (VNx, INT, 4, 1);
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131 VECTOR_MODES_WITH_PREFIX (VNx, INT, 8, 1);
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132 VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 4, 1);
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133 VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 8, 1);
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134
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135 ADJUST_NUNITS (VNx2QI, aarch64_sve_vg);
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136 ADJUST_NUNITS (VNx2HI, aarch64_sve_vg);
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137 ADJUST_NUNITS (VNx2SI, aarch64_sve_vg);
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138 ADJUST_NUNITS (VNx2HF, aarch64_sve_vg);
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139 ADJUST_NUNITS (VNx2SF, aarch64_sve_vg);
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140
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141 ADJUST_NUNITS (VNx4QI, aarch64_sve_vg * 2);
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142 ADJUST_NUNITS (VNx4HI, aarch64_sve_vg * 2);
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143 ADJUST_NUNITS (VNx4HF, aarch64_sve_vg * 2);
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144
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145 ADJUST_NUNITS (VNx8QI, aarch64_sve_vg * 4);
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146
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147 ADJUST_ALIGNMENT (VNx2QI, 1);
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148 ADJUST_ALIGNMENT (VNx4QI, 1);
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149 ADJUST_ALIGNMENT (VNx8QI, 1);
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150
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151 ADJUST_ALIGNMENT (VNx2HI, 2);
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152 ADJUST_ALIGNMENT (VNx4HI, 2);
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153 ADJUST_ALIGNMENT (VNx2HF, 2);
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154 ADJUST_ALIGNMENT (VNx4HF, 2);
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155
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156 ADJUST_ALIGNMENT (VNx2SI, 4);
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157 ADJUST_ALIGNMENT (VNx2SF, 4);
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158
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159 /* Quad float: 128-bit floating mode for long doubles. */
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160 FLOAT_MODE (TF, 16, ieee_quad_format);
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161
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162 /* A 4-tuple of SVE vectors with the maximum -msve-vector-bits= setting.
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163 Note that this is a limit only on the compile-time sizes of modes;
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164 it is not a limit on the runtime sizes, since VL-agnostic code
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165 must work with arbitary vector lengths. */
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166 #define MAX_BITSIZE_MODE_ANY_MODE (2048 * 4)
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167
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168 /* Coefficient 1 is multiplied by the number of 128-bit chunks in an
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169 SVE vector (referred to as "VQ") minus one. */
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170 #define NUM_POLY_INT_COEFFS 2
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