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1 ;; ARM Cortex-A7 pipeline description
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2 ;; Copyright (C) 2012-2020 Free Software Foundation, Inc.
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3 ;;
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4 ;; Contributed by ARM Ltd.
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5 ;; Based on cortex-a5.md which was originally contributed by CodeSourcery.
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6 ;;
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7 ;; This file is part of GCC.
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8 ;;
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9 ;; GCC is free software; you can redistribute it and/or modify it
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10 ;; under the terms of the GNU General Public License as published by
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11 ;; the Free Software Foundation; either version 3, or (at your option)
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12 ;; any later version.
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13 ;;
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14 ;; GCC is distributed in the hope that it will be useful, but
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15 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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17 ;; General Public License for more details.
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18 ;;
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19 ;; You should have received a copy of the GNU General Public License
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20 ;; along with GCC; see the file COPYING3. If not see
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21 ;; <http://www.gnu.org/licenses/>.
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22
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23 (define_attr "cortex_a7_neon_type"
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24 "neon_mul, neon_mla, neon_other"
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25 (cond [
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26 (eq_attr "type" "neon_mul_b, neon_mul_b_q,\
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27 neon_mul_h, neon_mul_h_q,\
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28 neon_mul_s, neon_mul_s_q,\
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29 neon_mul_b_long, neon_mul_h_long,\
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30 neon_mul_s_long, neon_mul_h_scalar,\
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31 neon_mul_h_scalar_q, neon_mul_s_scalar,\
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32 neon_mul_s_scalar_q, neon_mul_h_scalar_long,\
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33 neon_mul_s_scalar_long,\
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34 neon_sat_mul_b, neon_sat_mul_b_q,\
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35 neon_sat_mul_h, neon_sat_mul_h_q,\
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36 neon_sat_mul_s, neon_sat_mul_s_q,\
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37 neon_sat_mul_b_long, neon_sat_mul_h_long,\
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38 neon_sat_mul_s_long,\
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39 neon_sat_mul_h_scalar, neon_sat_mul_h_scalar_q,\
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40 neon_sat_mul_s_scalar, neon_sat_mul_s_scalar_q,\
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41 neon_sat_mul_h_scalar_long,\
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42 neon_sat_mul_s_scalar_long,\
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43 neon_fp_mul_s, neon_fp_mul_s_q,\
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44 neon_fp_mul_s_scalar, neon_fp_mul_s_scalar_q")
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45 (const_string "neon_mul")
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46 (eq_attr "type" "neon_mla_b, neon_mla_b_q, neon_mla_h,\
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47 neon_mla_h_q, neon_mla_s, neon_mla_s_q,\
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48 neon_mla_b_long, neon_mla_h_long,\
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49 neon_mla_s_long,\
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50 neon_mla_h_scalar, neon_mla_h_scalar_q,\
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51 neon_mla_s_scalar, neon_mla_s_scalar_q,\
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52 neon_mla_h_scalar_long, neon_mla_s_scalar_long,\
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53 neon_sat_mla_b_long, neon_sat_mla_h_long,\
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54 neon_sat_mla_s_long,\
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55 neon_sat_mla_h_scalar_long,\
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56 neon_sat_mla_s_scalar_long,\
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57 neon_fp_mla_s, neon_fp_mla_s_q,\
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58 neon_fp_mla_s_scalar, neon_fp_mla_s_scalar_q")
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59 (const_string "neon_mla")]
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60 (const_string "neon_other")))
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61
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62 (define_automaton "cortex_a7")
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63
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64 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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65 ;; Functional units.
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66 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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67
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68 ;; The Cortex-A7 pipeline integer and vfp pipeline.
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69 ;; The decode is the same for all instructions, so do not model it.
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70 ;; We only model the first execution stage because
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71 ;; instructions always advance one stage per cycle in order.
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72 ;; We model all of the LS, Branch, ALU, MAC and FPU pipelines together.
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73
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74 (define_cpu_unit "cortex_a7_ex1, cortex_a7_ex2" "cortex_a7")
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75
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76 (define_reservation "cortex_a7_both" "cortex_a7_ex1+cortex_a7_ex2")
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77
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78 (define_cpu_unit "cortex_a7_branch" "cortex_a7")
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79
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80 ;; Cortex-A7 is in order and can dual-issue under limited circumstances.
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81 ;; ex2 can be reserved only after ex1 is reserved.
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82
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83 (final_presence_set "cortex_a7_ex2" "cortex_a7_ex1")
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84
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85 ;; Pseudo-unit for blocking the multiply pipeline when a double-precision
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86 ;; multiply is in progress.
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87
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88 (define_cpu_unit "cortex_a7_fpmul_pipe" "cortex_a7")
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89
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90 ;; The floating-point add pipeline (ex1/f1 stage), used to model the usage
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91 ;; of the add pipeline by fmac instructions, etc.
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92
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93 (define_cpu_unit "cortex_a7_fpadd_pipe" "cortex_a7")
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94
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95 ;; Floating-point div/sqrt (long latency, out-of-order completion).
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96
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97 (define_cpu_unit "cortex_a7_fp_div_sqrt" "cortex_a7")
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98
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99 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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100 ;; Branches.
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101 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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102
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103 ;; A direct branch can dual issue either as younger or older instruction,
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104 ;; but branches cannot dual issue with branches.
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105 ;; No latency as there is no result.
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106
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107 (define_insn_reservation "cortex_a7_branch" 0
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108 (and (eq_attr "tune" "cortexa7")
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109 (eq_attr "type" "branch"))
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110 "(cortex_a7_ex2|cortex_a7_ex1)+cortex_a7_branch")
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111
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112 ;; Call cannot dual-issue as an older instruction. It can dual-issue
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113 ;; as a younger instruction, or single-issue. Call cannot dual-issue
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114 ;; with another branch instruction. The result is available the next
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115 ;; cycle.
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116 (define_insn_reservation "cortex_a7_call" 1
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117 (and (eq_attr "tune" "cortexa7")
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118 (eq_attr "type" "call"))
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119 "(cortex_a7_ex2|cortex_a7_both)+cortex_a7_branch")
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120
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121 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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122 ;; ALU instructions.
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123 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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124
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125 ;; ALU instruction with an immediate operand can dual-issue.
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126 (define_insn_reservation "cortex_a7_alu_imm" 2
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127 (and (eq_attr "tune" "cortexa7")
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128 (ior (eq_attr "type" "adr,alu_imm,alus_imm,logic_imm,logics_imm,\
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129 mov_imm,mvn_imm,extend")
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130 (and (eq_attr "type" "mov_reg,mov_shift,mov_shift_reg")
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131 (not (eq_attr "length" "8")))))
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132 "cortex_a7_ex2|cortex_a7_ex1")
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133
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134 ;; ALU instruction with register operands can dual-issue
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135 ;; with a younger immediate-based instruction.
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136 (define_insn_reservation "cortex_a7_alu_sreg" 2
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137 (and (eq_attr "tune" "cortexa7")
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138 (eq_attr "type" "alu_sreg,alus_sreg,logic_reg,logics_reg,\
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139 adc_imm,adcs_imm,adc_reg,adcs_reg,\
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140 bfm,clz,rbit,rev,alu_dsp_reg,\
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141 shift_imm,shift_reg,mov_reg,mvn_reg"))
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142 "cortex_a7_ex1")
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143
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144 (define_insn_reservation "cortex_a7_alu_shift" 2
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145 (and (eq_attr "tune" "cortexa7")
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146 (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
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147 logic_shift_imm,logics_shift_imm,\
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148 alu_shift_reg,alus_shift_reg,\
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149 logic_shift_reg,logics_shift_reg,\
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150 mov_shift,mov_shift_reg,\
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151 mvn_shift,mvn_shift_reg,\
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152 mrs,multiple"))
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153 "cortex_a7_ex1")
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154
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155 ;; Forwarding path for unshifted operands.
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156 (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_alu_shift"
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157 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_mul")
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158
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159 (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_alu_shift"
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160 "cortex_a7_store*"
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161 "arm_no_early_store_addr_dep")
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162
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163 (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_alu_shift"
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164 "cortex_a7_alu_shift"
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165 "arm_no_early_alu_shift_dep")
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166
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167 ;; The multiplier pipeline can forward results from wr stage only so
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168 ;; there's no need to specify bypasses.
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169 ;; Multiply instructions cannot dual-issue.
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170
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171 (define_insn_reservation "cortex_a7_mul" 2
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172 (and (eq_attr "tune" "cortexa7")
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173 (ior (eq_attr "mul32" "yes")
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174 (eq_attr "widen_mul64" "yes")))
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175 "cortex_a7_both")
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176
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177 ;; Forward the result of a multiply operation to the accumulator
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178 ;; of the following multiply and accumulate instruction.
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179 (define_bypass 1 "cortex_a7_mul"
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180 "cortex_a7_mul"
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181 "arm_mac_accumulator_is_result")
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182
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183 ;; The latency depends on the operands, so we use an estimate here.
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184 (define_insn_reservation "cortex_a7_idiv" 5
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185 (and (eq_attr "tune" "cortexa7")
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186 (eq_attr "type" "udiv,sdiv"))
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187 "cortex_a7_both*5")
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188
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189 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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190 ;; Load/store instructions.
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191 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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192
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193 ;; Address-generation happens in the issue stage.
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194 ;; Double-word accesses can be issued in a single cycle,
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195 ;; and occupy only one pipeline stage.
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196
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197 (define_insn_reservation "cortex_a7_load1" 2
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198 (and (eq_attr "tune" "cortexa7")
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199 (eq_attr "type" "load_byte,load_4"))
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200 "cortex_a7_ex1")
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201
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202 (define_insn_reservation "cortex_a7_store1" 0
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203 (and (eq_attr "tune" "cortexa7")
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204 (eq_attr "type" "store_4"))
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205 "cortex_a7_ex1")
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206
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207 (define_insn_reservation "cortex_a7_load2" 2
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208 (and (eq_attr "tune" "cortexa7")
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209 (eq_attr "type" "load_8"))
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210 "cortex_a7_both")
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211
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212 (define_insn_reservation "cortex_a7_store2" 0
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213 (and (eq_attr "tune" "cortexa7")
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214 (eq_attr "type" "store_8"))
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215 "cortex_a7_both")
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216
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217 (define_insn_reservation "cortex_a7_load3" 3
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218 (and (eq_attr "tune" "cortexa7")
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219 (eq_attr "type" "load_12"))
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220 "cortex_a7_both, cortex_a7_ex1")
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221
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222 (define_insn_reservation "cortex_a7_store3" 0
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223 (and (eq_attr "tune" "cortexa7")
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224 (eq_attr "type" "store_16"))
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225 "cortex_a7_both, cortex_a7_ex1")
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226
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227 (define_insn_reservation "cortex_a7_load4" 3
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228 (and (eq_attr "tune" "cortexa7")
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229 (eq_attr "type" "load_16"))
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230 "cortex_a7_both, cortex_a7_both")
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231
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232 (define_insn_reservation "cortex_a7_store4" 0
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233 (and (eq_attr "tune" "cortexa7")
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234 (eq_attr "type" "store_12"))
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235 "cortex_a7_both, cortex_a7_both")
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236
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237 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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238 ;; Floating-point arithmetic.
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239 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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240 ;; Neon integer, neon floating point, and single-precision floating
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241 ;; point instructions of the same type have the same timing
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242 ;; characteristics, but neon instructions cannot dual-issue.
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243
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244 (define_insn_reservation "cortex_a7_fpalu" 4
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245 (and (eq_attr "tune" "cortexa7")
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246 (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov,\
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247 f_cvt, f_cvtf2i, f_cvti2f, fcmps, fcmpd"))
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248 "cortex_a7_ex1+cortex_a7_fpadd_pipe")
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249
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250 ;; For fconsts and fconstd, 8-bit immediate data is passed directly from
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251 ;; f1 to f3 (which I think reduces the latency by one cycle).
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252
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253 (define_insn_reservation "cortex_a7_fconst" 3
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254 (and (eq_attr "tune" "cortexa7")
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255 (eq_attr "type" "fconsts,fconstd"))
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256 "cortex_a7_ex1+cortex_a7_fpadd_pipe")
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257
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258 ;; We should try not to attempt to issue a single-precision multiplication in
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259 ;; the middle of a double-precision multiplication operation (the usage of
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260 ;; cortex_a7_fpmul_pipe).
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261
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262 (define_insn_reservation "cortex_a7_fpmuls" 4
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263 (and (eq_attr "tune" "cortexa7")
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264 (eq_attr "type" "fmuls"))
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265 "cortex_a7_ex1+cortex_a7_fpmul_pipe")
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266
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267 (define_insn_reservation "cortex_a7_neon_mul" 4
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268 (and (eq_attr "tune" "cortexa7")
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269 (eq_attr "cortex_a7_neon_type" "neon_mul"))
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270 "(cortex_a7_both+cortex_a7_fpmul_pipe)*2")
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271
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272 (define_insn_reservation "cortex_a7_fpmacs" 8
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273 (and (eq_attr "tune" "cortexa7")
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274 (eq_attr "type" "fmacs,ffmas"))
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275 "cortex_a7_ex1+cortex_a7_fpmul_pipe")
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276
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277 (define_insn_reservation "cortex_a7_neon_mla" 8
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278 (and (eq_attr "tune" "cortexa7")
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279 (eq_attr "cortex_a7_neon_type" "neon_mla"))
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280 "cortex_a7_both+cortex_a7_fpmul_pipe")
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281
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282 (define_bypass 4 "cortex_a7_fpmacs,cortex_a7_neon_mla"
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283 "cortex_a7_fpmacs,cortex_a7_neon_mla"
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284 "arm_mac_accumulator_is_result")
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285
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286 ;; Non-multiply instructions can issue between two cycles of a
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287 ;; double-precision multiply.
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288
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289 (define_insn_reservation "cortex_a7_fpmuld" 7
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290 (and (eq_attr "tune" "cortexa7")
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291 (eq_attr "type" "fmuld"))
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292 "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*3")
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293
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294 (define_insn_reservation "cortex_a7_fpmacd" 11
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295 (and (eq_attr "tune" "cortexa7")
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296 (eq_attr "type" "fmacd"))
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297 "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*3")
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298
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299 (define_insn_reservation "cortex_a7_fpfmad" 8
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300 (and (eq_attr "tune" "cortexa7")
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301 (eq_attr "type" "ffmad"))
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302 "cortex_a7_ex1+cortex_a7_fpmul_pipe, cortex_a7_fpmul_pipe*4")
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303
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304 (define_bypass 7 "cortex_a7_fpmacd"
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305 "cortex_a7_fpmacd,cortex_a7_fpfmad"
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306 "arm_mac_accumulator_is_result")
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307
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308 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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309 ;; Floating-point divide/square root instructions.
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310 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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311
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312 (define_insn_reservation "cortex_a7_fdivs" 16
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313 (and (eq_attr "tune" "cortexa7")
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314 (eq_attr "type" "fdivs, fsqrts"))
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315 "cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 13")
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316
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317 (define_insn_reservation "cortex_a7_fdivd" 31
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318 (and (eq_attr "tune" "cortexa7")
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319 (eq_attr "type" "fdivd, fsqrtd"))
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320 "cortex_a7_ex1+cortex_a7_fp_div_sqrt, cortex_a7_fp_div_sqrt * 28")
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321
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322 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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323 ;; VFP to/from core transfers.
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324 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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325
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326 ;; Core-to-VFP transfers.
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327
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328 (define_insn_reservation "cortex_a7_r2f" 4
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329 (and (eq_attr "tune" "cortexa7")
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330 (eq_attr "type" "f_mcr,f_mcrr"))
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331 "cortex_a7_both")
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332
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333 (define_insn_reservation "cortex_a7_f2r" 2
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334 (and (eq_attr "tune" "cortexa7")
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335 (eq_attr "type" "f_mrc,f_mrrc"))
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336 "cortex_a7_ex1")
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337
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338 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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339 ;; VFP flag transfer.
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340 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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341
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342 ;; Fuxne: The flag forwarding from fmstat to the second instruction is
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343 ;; not modeled at present.
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344
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345 (define_insn_reservation "cortex_a7_f_flags" 4
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346 (and (eq_attr "tune" "cortexa7")
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347 (eq_attr "type" "f_flag"))
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348 "cortex_a7_ex1")
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349
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350 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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351 ;; VFP load/store.
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352 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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353
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354 (define_insn_reservation "cortex_a7_f_loads" 4
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355 (and (eq_attr "tune" "cortexa7")
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356 (eq_attr "type" "f_loads"))
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357 "cortex_a7_ex1")
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358
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359 (define_insn_reservation "cortex_a7_f_loadd" 4
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360 (and (eq_attr "tune" "cortexa7")
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361 (eq_attr "type" "f_loadd"))
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362 "cortex_a7_both")
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363
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364 (define_insn_reservation "cortex_a7_f_stores" 0
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365 (and (eq_attr "tune" "cortexa7")
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366 (eq_attr "type" "f_stores"))
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367 "cortex_a7_ex1")
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368
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369 (define_insn_reservation "cortex_a7_f_stored" 0
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370 (and (eq_attr "tune" "cortexa7")
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371 (eq_attr "type" "f_stored"))
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372 "cortex_a7_both")
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373
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374 ;; Load-to-use for floating-point values has a penalty of one cycle,
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375 ;; i.e. a latency of two.
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376
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377 (define_bypass 2 "cortex_a7_f_loads, cortex_a7_f_loadd"
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378 "cortex_a7_fpalu,\
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379 cortex_a7_fpmuls,cortex_a7_fpmacs,\
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380 cortex_a7_fpmuld,cortex_a7_fpmacd, cortex_a7_fpfmad,\
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381 cortex_a7_fdivs, cortex_a7_fdivd,\
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382 cortex_a7_f2r")
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383
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384 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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385 ;; NEON
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386 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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387
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388 ;; Simple modeling for all neon instructions not covered earlier.
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389
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390 (define_insn_reservation "cortex_a7_neon" 4
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391 (and (eq_attr "tune" "cortexa7")
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392 (and (eq_attr "is_neon_type" "yes")
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393 (eq_attr "cortex_a7_neon_type" "neon_other")))
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394 "cortex_a7_both*2")
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