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1 ;; Code and mode itertator and attribute definitions for the ARM backend
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145
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2 ;; Copyright (C) 2010-2020 Free Software Foundation, Inc.
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3 ;; Contributed by ARM Ltd.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
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15 ;; License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21
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22 ;;----------------------------------------------------------------------------
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23 ;; Mode iterators
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24 ;;----------------------------------------------------------------------------
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25
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26 ;; A list of modes that are exactly 64 bits in size. This is used to expand
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27 ;; some splits that are the same for all modes when operating on ARM
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28 ;; registers.
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29 (define_mode_iterator ANY64 [DI DF V8QI V4HI V4HF V2SI V2SF])
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30
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31 ;; Additional definition of ANY64 that also includes the special V4BF mode.
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32 ;; BFmode is allowed only on define_split between ARM registers.
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33 (define_mode_iterator ANY64_BF [DI DF V8QI V4HI V4BF V4HF V2SI V2SF])
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34
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35 (define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF])
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36
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37 ;; A list of integer modes that are up to one word long
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38 (define_mode_iterator QHSI [QI HI SI])
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39
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40 ;; A list of integer modes that are half and one word long
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41 (define_mode_iterator HSI [HI SI])
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42
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43 ;; A list of integer modes that are less than a word
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44 (define_mode_iterator NARROW [QI HI])
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45
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46 ;; A list of all the integer modes up to 64bit
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47 (define_mode_iterator QHSD [QI HI SI DI])
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48
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49 ;; A list of the 32bit and 64bit integer modes
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50 (define_mode_iterator SIDI [SI DI])
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51
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52 ;; A list of atomic compare and swap success return modes
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53 (define_mode_iterator CCSI [(CC_Z "TARGET_32BIT") (SI "TARGET_THUMB1")])
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54
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55 ;; A list of modes which the VFP unit can handle
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56 (define_mode_iterator SDF [(SF "") (DF "TARGET_VFP_DOUBLE")])
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57
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58 ;; Integer element sizes implemented by IWMMXT.
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59 (define_mode_iterator VMMX [V2SI V4HI V8QI])
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60
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111
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61 (define_mode_iterator VMMX2 [V4HI V2SI])
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62
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63 ;; Integer element sizes for shifts.
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64 (define_mode_iterator VSHFT [V4HI V2SI DI])
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65
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66 ;; Integer and float modes supported by Neon and IWMMXT.
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67 (define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
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68
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69 ;; Integer and float modes supported by Neon and IWMMXT, except V2DI.
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70 (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF])
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71
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72 ;; Integer modes supported by Neon and IWMMXT
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73 (define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI])
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74
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75 ;; Integer modes supported by Neon and IWMMXT, except V2DI
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76 (define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI])
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77
|
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111
|
78 ;; Double-width vector modes, on which we support arithmetic (no HF!)
|
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79 (define_mode_iterator VD [V8QI V4HI V2SI V2SF])
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80
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111
|
81 ;; Double-width vector modes plus 64-bit elements for vreinterpret + vcreate.
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|
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82 (define_mode_iterator VD_RE [V8QI V4HI V2SI V2SF DI])
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|
|
83
|
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84 ;; Double-width vector modes plus 64-bit elements.
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85 (define_mode_iterator VDX [V8QI V4HI V4HF V2SI V2SF DI])
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|
|
86
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145
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87 ;; Double-width vector modes plus 64-bit elements,
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|
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88 ;; with V4BFmode added, suitable for moves.
|
|
|
89 (define_mode_iterator VDXMOV [V8QI V4HI V4HF V4BF V2SI V2SF DI])
|
|
|
90
|
|
111
|
91 ;; Double-width vector modes, with V4HF - for vldN_lane and vstN_lane.
|
|
|
92 (define_mode_iterator VD_LANE [V8QI V4HI V4HF V2SI V2SF])
|
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93
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94 ;; Double-width vector modes without floating-point elements.
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95 (define_mode_iterator VDI [V8QI V4HI V2SI])
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96
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|
97 ;; Quad-width vector modes supporting arithmetic (no HF!).
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98 (define_mode_iterator VQ [V16QI V8HI V4SI V4SF])
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99
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100 ;; Quad-width vector modes, including V8HF.
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101 (define_mode_iterator VQ2 [V16QI V8HI V8HF V4SI V4SF])
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|
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102
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103 ;; Quad-width vector modes with 16- or 32-bit elements
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104 (define_mode_iterator VQ_HS [V8HI V8HF V4SI V4SF])
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|
|
105
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106 ;; Quad-width vector modes plus 64-bit elements.
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111
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107 (define_mode_iterator VQX [V16QI V8HI V8HF V4SI V4SF V2DI])
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108
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109 ;; Quad-width vector modes without floating-point elements.
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110 (define_mode_iterator VQI [V16QI V8HI V4SI])
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111
|
|
145
|
112 ;; Quad-width vector modes, with TImode and V8BFmode added, suitable for moves.
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|
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113 (define_mode_iterator VQXMOV [V16QI V8HI V8HF V8BF V4SI V4SF V2DI TI])
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114
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115 ;; Opaque structure types wider than TImode.
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116 (define_mode_iterator VSTRUCT [EI OI CI XI])
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117
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118 ;; Opaque structure types used in table lookups (except vtbl1/vtbx1).
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119 (define_mode_iterator VTAB [TI EI OI])
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120
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121 ;; Widenable modes.
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122 (define_mode_iterator VW [V8QI V4HI V2SI])
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123
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124 ;; Narrowable modes.
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125 (define_mode_iterator VN [V8HI V4SI V2DI])
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126
|
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127 ;; All supported vector modes (except singleton DImode).
|
|
111
|
128 (define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V4HF V8HF V2SF V4SF V2DI])
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129
|
|
131
|
130 ;; All supported floating-point vector modes (except V2DF).
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|
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131 (define_mode_iterator VF [(V4HF "TARGET_NEON_FP16INST")
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|
|
132 (V8HF "TARGET_NEON_FP16INST") V2SF V4SF])
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|
|
133
|
|
145
|
134 ;; Double vector modes.
|
|
|
135 (define_mode_iterator VDF [V2SF V4HF])
|
|
|
136
|
|
|
137 ;; Quad vector Float modes with half/single elements.
|
|
|
138 (define_mode_iterator VQ_HSF [V8HF V4SF])
|
|
|
139
|
|
|
140
|
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141 ;; All supported vector modes (except those with 64-bit integer elements).
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142 (define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF])
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|
143
|
|
111
|
144 ;; All supported vector modes including 16-bit float modes.
|
|
|
145 (define_mode_iterator VDQWH [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF
|
|
|
146 V8HF V4HF])
|
|
|
147
|
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148 ;; Supported integer vector modes (not 64 bit elements).
|
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149 (define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI])
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|
150
|
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|
151 ;; Supported integer vector modes (not singleton DI)
|
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152 (define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
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|
153
|
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parents:
diff
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|
154 ;; Vector modes, including 64-bit integer elements.
|
|
111
|
155 (define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI
|
|
|
156 V4HF V8HF V2SF V4SF DI V2DI])
|
68
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|
157
|
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parents:
diff
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|
158 ;; Vector modes including 64-bit integer elements, but no floats.
|
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diff
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|
159 (define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI])
|
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parents:
diff
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|
160
|
|
111
|
161 ;; Vector modes for H, S and D types.
|
|
|
162 (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
|
|
|
163
|
68
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|
164 ;; Vector modes for float->int conversions.
|
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diff
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|
165 (define_mode_iterator VCVTF [V2SF V4SF])
|
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diff
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|
166
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
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|
167 ;; Vector modes form int->float conversions.
|
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parents:
diff
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|
168 (define_mode_iterator VCVTI [V2SI V4SI])
|
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diff
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|
169
|
|
111
|
170 ;; Vector modes for int->half conversions.
|
|
|
171 (define_mode_iterator VCVTHI [V4HI V8HI])
|
|
|
172
|
68
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|
173 ;; Vector modes for doubleword multiply-accumulate, etc. insns.
|
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parents:
diff
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|
174 (define_mode_iterator VMD [V4HI V2SI V2SF])
|
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parents:
diff
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|
175
|
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parents:
diff
changeset
|
176 ;; Vector modes for quadword multiply-accumulate, etc. insns.
|
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parents:
diff
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|
177 (define_mode_iterator VMQ [V8HI V4SI V4SF])
|
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diff
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|
178
|
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parents:
diff
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|
179 ;; Above modes combined.
|
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180 (define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF])
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181
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182 ;; As VMD, but integer modes only.
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183 (define_mode_iterator VMDI [V4HI V2SI])
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184
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185 ;; As VMQ, but integer modes only.
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186 (define_mode_iterator VMQI [V8HI V4SI])
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187
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188 ;; Above modes combined.
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189 (define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI])
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190
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191 ;; Modes with 8-bit and 16-bit elements.
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192 (define_mode_iterator VX [V8QI V4HI V16QI V8HI])
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193
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194 ;; Modes with 8-bit elements.
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195 (define_mode_iterator VE [V8QI V16QI])
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196
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145
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197 ;; V2DI only (for use with @ patterns).
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198 (define_mode_iterator V2DI_ONLY [V2DI])
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199
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200 ;; Modes with 64-bit elements only.
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201 (define_mode_iterator V64 [DI V2DI])
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202
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203 ;; Modes with 32-bit elements only.
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204 (define_mode_iterator V32 [V2SI V2SF V4SI V4SF])
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205
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206 ;; Modes with 8-bit, 16-bit and 32-bit elements.
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207 (define_mode_iterator VU [V16QI V8HI V4SI])
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111
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208
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209 ;; Vector modes for 16-bit floating-point support.
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210 (define_mode_iterator VH [V8HF V4HF])
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211
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145
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212 ;; 16-bit floating-point vector modes suitable for moving (includes BFmode).
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213 (define_mode_iterator VHFBF [V8HF V4HF V4BF V8BF])
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214
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215 ;; 16-bit floating-point scalar modes suitable for moving (includes BFmode).
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216 (define_mode_iterator HFBF [HF BF])
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217
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111
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218 ;; Iterators used for fixed-point support.
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219 (define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA])
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220
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221 (define_mode_iterator ADDSUB [V4QQ V2HQ V2HA])
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222
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223 (define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA])
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224
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|
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225 (define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA])
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226
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227 (define_mode_iterator QMUL [HQ HA])
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228
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229 ;; Modes for polynomial or float values.
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230 (define_mode_iterator VPF [V8QI V16QI V2SF V4SF])
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231
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232 ;;----------------------------------------------------------------------------
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233 ;; Code iterators
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234 ;;----------------------------------------------------------------------------
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235
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111
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236 ;; The signed gt, ge comparisons
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237 (define_code_iterator GTGE [gt ge])
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238
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239 ;; The signed gt, ge, lt, le comparisons
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240 (define_code_iterator GLTE [gt ge lt le])
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241
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242 ;; The unsigned gt, ge comparisons
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243 (define_code_iterator GTUGEU [gtu geu])
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244
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245 ;; Comparisons for vc<cmp>
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246 (define_code_iterator COMPARISONS [eq gt ge le lt])
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247
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248 ;; A list of ...
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111
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249 (define_code_iterator IOR_XOR [ior xor])
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250
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145
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251 (define_code_iterator LOGICAL [and ior xor])
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252
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253 ;; Operations on two halves of a quadword vector.
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111
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254 (define_code_iterator VQH_OPS [plus smin smax umin umax])
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68
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255
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256 ;; Operations on two halves of a quadword vector,
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257 ;; without unsigned variants (for use with *SFmode pattern).
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111
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258 (define_code_iterator VQHS_OPS [plus smin smax])
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259
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260 ;; A list of widening operators
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261 (define_code_iterator SE [sign_extend zero_extend])
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262
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111
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263 ;; Right shifts
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264 (define_code_iterator RSHIFTS [ashiftrt lshiftrt])
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265
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266 ;; Iterator for integer conversions
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267 (define_code_iterator FIXUORS [fix unsigned_fix])
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268
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269 ;; Binary operators whose second operand can be shifted.
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270 (define_code_iterator SHIFTABLE_OPS [plus minus ior xor and])
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271
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272 ;; Operations on the sign of a number.
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273 (define_code_iterator ABSNEG [abs neg])
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274
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131
|
275 ;; The PLUS and MINUS operators.
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276 (define_code_iterator PLUSMINUS [plus minus])
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277
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111
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278 ;; Conversions.
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279 (define_code_iterator FCVT [unsigned_float float])
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280
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145
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281 ;; Saturating addition, subtraction
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282 (define_code_iterator SSPLUSMINUS [ss_plus ss_minus])
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283
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111
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284 ;; plus and minus are the only SHIFTABLE_OPS for which Thumb2 allows
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145
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285 ;; a stack pointer operand. The minus operation is a candidate for an rsub
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111
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286 ;; and hence only plus is supported.
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287 (define_code_attr t2_binop0
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288 [(plus "rk") (minus "r") (ior "r") (xor "r") (and "r")])
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289
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290 ;; The instruction to use when a SHIFTABLE_OPS has a shift operation as
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291 ;; its first operand.
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292 (define_code_attr arith_shift_insn
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293 [(plus "add") (minus "rsb") (ior "orr") (xor "eor") (and "and")])
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294
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295 (define_code_attr cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le")
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296 (gtu "gt") (geu "ge")])
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297
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|
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298 (define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")])
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299
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131
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300 (define_code_attr vfml_op [(plus "a") (minus "s")])
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301
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145
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302 (define_code_attr ss_op [(ss_plus "qadd") (ss_minus "qsub")])
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303
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111
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304 ;;----------------------------------------------------------------------------
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305 ;; Int iterators
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306 ;;----------------------------------------------------------------------------
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307
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308 (define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM
|
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309 UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA])
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310
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311 (define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE
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312 UNSPEC_VCLT UNSPEC_VCLE])
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313
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|
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314 (define_int_iterator NEON_VACMP [UNSPEC_VCAGE UNSPEC_VCAGT])
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315
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|
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316 (define_int_iterator NEON_VAGLTE [UNSPEC_VCAGE UNSPEC_VCAGT
|
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317 UNSPEC_VCALE UNSPEC_VCALT])
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318
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|
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319 (define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA])
|
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320
|
|
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321 (define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM
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322 UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN])
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323
|
|
|
324 (define_int_iterator NEON_VCVT [UNSPEC_NVRINTP UNSPEC_NVRINTM UNSPEC_NVRINTA])
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325
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|
|
326 (define_int_iterator VADDL [UNSPEC_VADDL_S UNSPEC_VADDL_U])
|
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|
327
|
|
|
328 (define_int_iterator VADDW [UNSPEC_VADDW_S UNSPEC_VADDW_U])
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329
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|
330 (define_int_iterator VHADD [UNSPEC_VRHADD_S UNSPEC_VRHADD_U
|
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331 UNSPEC_VHADD_S UNSPEC_VHADD_U])
|
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332
|
|
|
333 (define_int_iterator VQADD [UNSPEC_VQADD_S UNSPEC_VQADD_U])
|
|
|
334
|
|
|
335 (define_int_iterator VADDHN [UNSPEC_VADDHN UNSPEC_VRADDHN])
|
|
|
336
|
|
|
337 (define_int_iterator VMLAL [UNSPEC_VMLAL_S UNSPEC_VMLAL_U])
|
|
|
338
|
|
|
339 (define_int_iterator VMLAL_LANE [UNSPEC_VMLAL_S_LANE UNSPEC_VMLAL_U_LANE])
|
|
|
340
|
|
|
341 (define_int_iterator VMLSL [UNSPEC_VMLSL_S UNSPEC_VMLSL_U])
|
|
|
342
|
|
|
343 (define_int_iterator VMLSL_LANE [UNSPEC_VMLSL_S_LANE UNSPEC_VMLSL_U_LANE])
|
|
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344
|
|
|
345 (define_int_iterator VQDMULH [UNSPEC_VQDMULH UNSPEC_VQRDMULH])
|
|
|
346
|
|
|
347 (define_int_iterator VQDMULH_LANE [UNSPEC_VQDMULH_LANE UNSPEC_VQRDMULH_LANE])
|
|
|
348
|
|
|
349 (define_int_iterator VMULL [UNSPEC_VMULL_S UNSPEC_VMULL_U UNSPEC_VMULL_P])
|
|
|
350
|
|
|
351 (define_int_iterator VMULL_LANE [UNSPEC_VMULL_S_LANE UNSPEC_VMULL_U_LANE])
|
|
|
352
|
|
|
353 (define_int_iterator VSUBL [UNSPEC_VSUBL_S UNSPEC_VSUBL_U])
|
|
|
354
|
|
|
355 (define_int_iterator VSUBW [UNSPEC_VSUBW_S UNSPEC_VSUBW_U])
|
|
|
356
|
|
|
357 (define_int_iterator VHSUB [UNSPEC_VHSUB_S UNSPEC_VHSUB_U])
|
|
|
358
|
|
|
359 (define_int_iterator VQSUB [UNSPEC_VQSUB_S UNSPEC_VQSUB_U])
|
|
|
360
|
|
|
361 (define_int_iterator VSUBHN [UNSPEC_VSUBHN UNSPEC_VRSUBHN])
|
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|
362
|
|
145
|
363 (define_int_iterator VABAL [UNSPEC_VABAL_S UNSPEC_VABAL_U])
|
|
|
364
|
|
111
|
365 (define_int_iterator VABD [UNSPEC_VABD_S UNSPEC_VABD_U])
|
|
|
366
|
|
|
367 (define_int_iterator VABDL [UNSPEC_VABDL_S UNSPEC_VABDL_U])
|
|
|
368
|
|
|
369 (define_int_iterator VMAXMIN [UNSPEC_VMAX UNSPEC_VMAX_U
|
|
|
370 UNSPEC_VMIN UNSPEC_VMIN_U])
|
|
|
371
|
|
|
372 (define_int_iterator VMAXMINF [UNSPEC_VMAX UNSPEC_VMIN])
|
|
|
373
|
|
|
374 (define_int_iterator VMAXMINFNM [UNSPEC_VMAXNM UNSPEC_VMINNM])
|
|
|
375
|
|
|
376 (define_int_iterator VPADDL [UNSPEC_VPADDL_S UNSPEC_VPADDL_U])
|
|
|
377
|
|
|
378 (define_int_iterator VPADAL [UNSPEC_VPADAL_S UNSPEC_VPADAL_U])
|
|
|
379
|
|
|
380 (define_int_iterator VPMAXMIN [UNSPEC_VPMAX UNSPEC_VPMAX_U
|
|
|
381 UNSPEC_VPMIN UNSPEC_VPMIN_U])
|
|
|
382
|
|
|
383 (define_int_iterator VPMAXMINF [UNSPEC_VPMAX UNSPEC_VPMIN])
|
|
|
384
|
|
|
385 (define_int_iterator VCVT_US [UNSPEC_VCVT_S UNSPEC_VCVT_U])
|
|
|
386
|
|
|
387 (define_int_iterator VCVT_US_N [UNSPEC_VCVT_S_N UNSPEC_VCVT_U_N])
|
|
|
388
|
|
|
389 (define_int_iterator VCVT_HF_US_N [UNSPEC_VCVT_HF_S_N UNSPEC_VCVT_HF_U_N])
|
|
|
390
|
|
|
391 (define_int_iterator VCVT_SI_US_N [UNSPEC_VCVT_SI_S_N UNSPEC_VCVT_SI_U_N])
|
|
|
392
|
|
|
393 (define_int_iterator VCVT_HF_US [UNSPEC_VCVTA_S UNSPEC_VCVTA_U
|
|
|
394 UNSPEC_VCVTM_S UNSPEC_VCVTM_U
|
|
|
395 UNSPEC_VCVTN_S UNSPEC_VCVTN_U
|
|
|
396 UNSPEC_VCVTP_S UNSPEC_VCVTP_U])
|
|
|
397
|
|
|
398 (define_int_iterator VCVTH_US [UNSPEC_VCVTH_S UNSPEC_VCVTH_U])
|
|
|
399
|
|
|
400 ;; Operators for FP16 instructions.
|
|
|
401 (define_int_iterator FP16_RND [UNSPEC_VRND UNSPEC_VRNDA
|
|
|
402 UNSPEC_VRNDM UNSPEC_VRNDN
|
|
|
403 UNSPEC_VRNDP UNSPEC_VRNDX])
|
|
|
404
|
|
|
405 (define_int_iterator VQMOVN [UNSPEC_VQMOVN_S UNSPEC_VQMOVN_U])
|
|
|
406
|
|
|
407 (define_int_iterator VMOVL [UNSPEC_VMOVL_S UNSPEC_VMOVL_U])
|
|
|
408
|
|
|
409 (define_int_iterator VSHL [UNSPEC_VSHL_S UNSPEC_VSHL_U
|
|
|
410 UNSPEC_VRSHL_S UNSPEC_VRSHL_U])
|
|
|
411
|
|
|
412 (define_int_iterator VQSHL [UNSPEC_VQSHL_S UNSPEC_VQSHL_U
|
|
|
413 UNSPEC_VQRSHL_S UNSPEC_VQRSHL_U])
|
|
|
414
|
|
|
415 (define_int_iterator VSHR_N [UNSPEC_VSHR_S_N UNSPEC_VSHR_U_N
|
|
|
416 UNSPEC_VRSHR_S_N UNSPEC_VRSHR_U_N])
|
|
|
417
|
|
|
418 (define_int_iterator VSHRN_N [UNSPEC_VSHRN_N UNSPEC_VRSHRN_N])
|
|
|
419
|
|
|
420 (define_int_iterator VQSHRN_N [UNSPEC_VQSHRN_S_N UNSPEC_VQSHRN_U_N
|
|
|
421 UNSPEC_VQRSHRN_S_N UNSPEC_VQRSHRN_U_N])
|
|
|
422
|
|
|
423 (define_int_iterator VQSHRUN_N [UNSPEC_VQSHRUN_N UNSPEC_VQRSHRUN_N])
|
|
|
424
|
|
|
425 (define_int_iterator VQSHL_N [UNSPEC_VQSHL_S_N UNSPEC_VQSHL_U_N])
|
|
|
426
|
|
|
427 (define_int_iterator VSHLL_N [UNSPEC_VSHLL_S_N UNSPEC_VSHLL_U_N])
|
|
|
428
|
|
|
429 (define_int_iterator VSRA_N [UNSPEC_VSRA_S_N UNSPEC_VSRA_U_N
|
|
|
430 UNSPEC_VRSRA_S_N UNSPEC_VRSRA_U_N])
|
|
|
431
|
|
|
432 (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
|
|
|
433 UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW])
|
|
|
434
|
|
145
|
435 (define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
|
|
111
|
436
|
|
145
|
437 (define_int_iterator CRYPTO_AES [UNSPEC_AESD UNSPEC_AESE])
|
|
|
438
|
|
|
439 (define_int_iterator CRYPTO_BINARY [UNSPEC_SHA1SU1 UNSPEC_SHA256SU0])
|
|
111
|
440
|
|
|
441 (define_int_iterator CRYPTO_TERNARY [UNSPEC_SHA1SU0 UNSPEC_SHA256H
|
|
|
442 UNSPEC_SHA256H2 UNSPEC_SHA256SU1])
|
|
|
443
|
|
|
444 (define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M
|
|
|
445 UNSPEC_SHA1P])
|
|
|
446
|
|
145
|
447 (define_int_iterator USXTB16 [UNSPEC_SXTB16 UNSPEC_UXTB16])
|
|
|
448 (define_int_iterator SIMD32_NOGE_BINOP
|
|
|
449 [UNSPEC_QADD8 UNSPEC_QSUB8 UNSPEC_SHADD8
|
|
|
450 UNSPEC_SHSUB8 UNSPEC_UHADD8 UNSPEC_UHSUB8
|
|
|
451 UNSPEC_UQADD8 UNSPEC_UQSUB8
|
|
|
452 UNSPEC_QADD16 UNSPEC_QASX UNSPEC_QSAX
|
|
|
453 UNSPEC_QSUB16 UNSPEC_SHADD16 UNSPEC_SHASX
|
|
|
454 UNSPEC_SHSAX UNSPEC_SHSUB16 UNSPEC_UHADD16
|
|
|
455 UNSPEC_UHASX UNSPEC_UHSAX UNSPEC_UHSUB16
|
|
|
456 UNSPEC_UQADD16 UNSPEC_UQASX UNSPEC_UQSAX
|
|
|
457 UNSPEC_UQSUB16 UNSPEC_SMUSD UNSPEC_SMUSDX
|
|
|
458 UNSPEC_SXTAB16 UNSPEC_UXTAB16 UNSPEC_USAD8])
|
|
|
459
|
|
|
460 (define_int_iterator SIMD32_DIMODE [UNSPEC_SMLALD UNSPEC_SMLALDX
|
|
|
461 UNSPEC_SMLSLD UNSPEC_SMLSLDX])
|
|
|
462
|
|
|
463 (define_int_iterator SMLAWBT [UNSPEC_SMLAWB UNSPEC_SMLAWT])
|
|
|
464
|
|
|
465 (define_int_iterator SIMD32_GE [UNSPEC_SADD8 UNSPEC_SSUB8 UNSPEC_UADD8
|
|
|
466 UNSPEC_USUB8 UNSPEC_SADD16 UNSPEC_SASX
|
|
|
467 UNSPEC_SSAX UNSPEC_SSUB16 UNSPEC_UADD16
|
|
|
468 UNSPEC_UASX UNSPEC_USAX UNSPEC_USUB16])
|
|
|
469
|
|
|
470 (define_int_iterator SIMD32_TERNOP_Q [UNSPEC_SMLAD UNSPEC_SMLADX UNSPEC_SMLSD
|
|
|
471 UNSPEC_SMLSDX])
|
|
|
472
|
|
|
473 (define_int_iterator SIMD32_BINOP_Q [UNSPEC_SMUAD UNSPEC_SMUADX])
|
|
|
474
|
|
|
475 (define_int_iterator USSAT16 [UNSPEC_SSAT16 UNSPEC_USAT16])
|
|
|
476
|
|
111
|
477 (define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH])
|
|
|
478
|
|
|
479 (define_int_iterator VFM_LANE_AS [UNSPEC_VFMA_LANE UNSPEC_VFMS_LANE])
|
|
|
480
|
|
|
481 (define_int_iterator DOTPROD [UNSPEC_DOT_S UNSPEC_DOT_U])
|
|
|
482
|
|
145
|
483 (define_int_iterator DOTPROD_I8MM [UNSPEC_DOT_US UNSPEC_DOT_SU])
|
|
|
484
|
|
131
|
485 (define_int_iterator VFMLHALVES [UNSPEC_VFML_LO UNSPEC_VFML_HI])
|
|
|
486
|
|
145
|
487 (define_int_iterator VCADD [UNSPEC_VCADD90 UNSPEC_VCADD270])
|
|
|
488 (define_int_iterator VCMLA [UNSPEC_VCMLA UNSPEC_VCMLA90 UNSPEC_VCMLA180 UNSPEC_VCMLA270])
|
|
|
489
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
490 ;;----------------------------------------------------------------------------
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
491 ;; Mode attributes
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
492 ;;----------------------------------------------------------------------------
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
493
|
|
111
|
494 ;; Determine name of atomic compare and swap from success result mode. This
|
|
|
495 ;; distinguishes between 16-bit Thumb and 32-bit Thumb/ARM.
|
|
|
496 (define_mode_attr arch [(CC_Z "32") (SI "t1")])
|
|
|
497
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
498 ;; Determine element size suffix from vector mode.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
499 (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
500
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
501 ;; vtbl<n> suffix for NEON vector modes.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
502 (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
503
|
|
145
|
504 ;; fp16 or bf16 marker for 16-bit float modes.
|
|
|
505 (define_mode_attr fporbf [(HF "fp16") (BF "bf16")])
|
|
|
506
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
507 ;; (Opposite) mode to convert to/from for NEON mode conversions.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
508 (define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
509 (V4SI "V4SF") (V4SF "V4SI")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
510
|
|
111
|
511 ;; As above but in lower case.
|
|
|
512 (define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si")
|
|
|
513 (V4SI "v4sf") (V4SF "v4si")])
|
|
|
514
|
|
|
515 ;; (Opposite) mode to convert to/from for vector-half mode conversions.
|
|
|
516 (define_mode_attr VH_CVTTO [(V4HI "V4HF") (V4HF "V4HI")
|
|
|
517 (V8HI "V8HF") (V8HF "V8HI")])
|
|
|
518
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
519 ;; Define element mode for each vector mode.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
520 (define_mode_attr V_elem [(V8QI "QI") (V16QI "QI")
|
|
111
|
521 (V4HI "HI") (V8HI "HI")
|
|
|
522 (V4HF "HF") (V8HF "HF")
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
523 (V2SI "SI") (V4SI "SI")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
524 (V2SF "SF") (V4SF "SF")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
525 (DI "DI") (V2DI "DI")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
526
|
|
111
|
527 ;; As above but in lower case.
|
|
|
528 (define_mode_attr V_elem_l [(V8QI "qi") (V16QI "qi")
|
|
|
529 (V4HI "hi") (V8HI "hi")
|
|
|
530 (V4HF "hf") (V8HF "hf")
|
|
|
531 (V2SI "si") (V4SI "si")
|
|
|
532 (V2SF "sf") (V4SF "sf")
|
|
|
533 (DI "di") (V2DI "di")])
|
|
|
534
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
535 ;; Element modes for vector extraction, padded up to register size.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
536
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
537 (define_mode_attr V_ext [(V8QI "SI") (V16QI "SI")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
538 (V4HI "SI") (V8HI "SI")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
539 (V2SI "SI") (V4SI "SI")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
540 (V2SF "SF") (V4SF "SF")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
541 (DI "DI") (V2DI "DI")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
542
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
543 ;; Mode of pair of elements for each vector mode, to define transfer
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
544 ;; size for structure lane/dup loads and stores.
|
|
111
|
545 (define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI")
|
|
|
546 (V4HI "SI") (V8HI "SI")
|
|
|
547 (V4HF "SF") (V8HF "SF")
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
548 (V2SI "V2SI") (V4SI "V2SI")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
549 (V2SF "V2SF") (V4SF "V2SF")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
550 (DI "V2DI") (V2DI "V2DI")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
551
|
|
131
|
552 ;; Mode mapping for VFM[A,S]L instructions.
|
|
|
553 (define_mode_attr VFML [(V2SF "V4HF") (V4SF "V8HF")])
|
|
|
554
|
|
|
555 ;; Mode mapping for VFM[A,S]L instructions for the vec_select result.
|
|
|
556 (define_mode_attr VFMLSEL [(V2SF "V2HF") (V4SF "V4HF")])
|
|
|
557
|
|
|
558 ;; Mode mapping for VFM[A,S]L instructions for some awkward lane-wise forms.
|
|
|
559 (define_mode_attr VFMLSEL2 [(V2SF "V8HF") (V4SF "V4HF")])
|
|
|
560
|
|
|
561 ;; Same as the above, but lowercase.
|
|
|
562 (define_mode_attr vfmlsel2 [(V2SF "v8hf") (V4SF "v4hf")])
|
|
|
563
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
564 ;; Similar, for three elements.
|
|
111
|
565 (define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK")
|
|
|
566 (V4HI "BLK") (V8HI "BLK")
|
|
|
567 (V4HF "BLK") (V8HF "BLK")
|
|
|
568 (V2SI "BLK") (V4SI "BLK")
|
|
|
569 (V2SF "BLK") (V4SF "BLK")
|
|
|
570 (DI "EI") (V2DI "EI")])
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
571
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
572 ;; Similar, for four elements.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
573 (define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI")
|
|
111
|
574 (V4HI "V4HI") (V8HI "V4HI")
|
|
|
575 (V4HF "V4HF") (V8HF "V4HF")
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
576 (V2SI "V4SI") (V4SI "V4SI")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
577 (V2SF "V4SF") (V4SF "V4SF")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
578 (DI "OI") (V2DI "OI")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
579
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
580 ;; Register width from element mode
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
581 (define_mode_attr V_reg [(V8QI "P") (V16QI "q")
|
|
111
|
582 (V4HI "P") (V8HI "q")
|
|
|
583 (V4HF "P") (V8HF "q")
|
|
|
584 (V2SI "P") (V4SI "q")
|
|
|
585 (V2SF "P") (V4SF "q")
|
|
|
586 (DI "P") (V2DI "q")
|
|
131
|
587 (V2HF "") (SF "")
|
|
|
588 (DF "P") (HF "")])
|
|
|
589
|
|
|
590 ;; Output template to select the high VFP register of a mult-register value.
|
|
|
591 (define_mode_attr V_hi [(V2SF "p") (V4SF "f")])
|
|
|
592
|
|
|
593 ;; Output template to select the low VFP register of a mult-register value.
|
|
|
594 (define_mode_attr V_lo [(V2SF "") (V4SF "e")])
|
|
|
595
|
|
|
596 ;; Helper attribute for printing output templates for awkward forms of
|
|
|
597 ;; vfmlal/vfmlsl intrinsics.
|
|
|
598 (define_mode_attr V_lane_reg [(V2SF "") (V4SF "P")])
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
599
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
600 ;; Wider modes with the same number of elements.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
601 (define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
602
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
603 ;; Narrower modes with the same number of elements.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
604 (define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
605
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
606 ;; Narrower modes with double the number of elements.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
607 (define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
608 (V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
609
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
610 ;; Modes with half the number of equal-sized elements.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
611 (define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI")
|
|
111
|
612 (V8HF "V4HF") (V4SI "V2SI")
|
|
|
613 (V4SF "V2SF") (V2DF "DF")
|
|
|
614 (V2DI "DI") (V4HF "HF")])
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
615
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
616 ;; Same, but lower-case.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
617 (define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
618 (V4SI "v2si") (V4SF "v2sf")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
619 (V2DI "di")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
620
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
621 ;; Modes with twice the number of equal-sized elements.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
622 (define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI")
|
|
111
|
623 (V2SI "V4SI") (V4HF "V8HF")
|
|
|
624 (V2SF "V4SF") (DF "V2DF")
|
|
|
625 (DI "V2DI")])
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
626
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
627 ;; Same, but lower-case.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
628 (define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
629 (V2SI "v4si") (V2SF "v4sf")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
630 (DI "v2di")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
631
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
632 ;; Modes with double-width elements.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
633 (define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
634 (V4HI "V2SI") (V8HI "V4SI")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
635 (V2SI "DI") (V4SI "V2DI")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
636
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
637 ;; Double-sized modes with the same element size.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
638 ;; Used for neon_vdup_lane, where the second operand is double-sized
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
639 ;; even when the first one is quad.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
640 (define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI")
|
|
111
|
641 (V4SI "V2SI") (V4SF "V2SF")
|
|
|
642 (V8QI "V8QI") (V4HI "V4HI")
|
|
|
643 (V2SI "V2SI") (V2SF "V2SF")
|
|
|
644 (V8HF "V4HF") (V4HF "V4HF")])
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
645
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
646 ;; Mode of result of comparison operations (and bit-select operand 1).
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
647 (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
|
|
111
|
648 (V4HI "V4HI") (V8HI "V8HI")
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
649 (V2SI "V2SI") (V4SI "V4SI")
|
|
111
|
650 (V4HF "V4HI") (V8HF "V8HI")
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
651 (V2SF "V2SI") (V4SF "V4SI")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
652 (DI "DI") (V2DI "V2DI")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
653
|
|
111
|
654 (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi")
|
|
|
655 (V4HI "v4hi") (V8HI "v8hi")
|
|
|
656 (V2SI "v2si") (V4SI "v4si")
|
|
|
657 (DI "di") (V2DI "v2di")
|
|
|
658 (V2SF "v2si") (V4SF "v4si")])
|
|
|
659
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
660 ;; Get element type from double-width mode, for operations where we
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
661 ;; don't care about signedness.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
662 (define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8")
|
|
111
|
663 (V4HI "i16") (V8HI "i16")
|
|
|
664 (V2SI "i32") (V4SI "i32")
|
|
|
665 (DI "i64") (V2DI "i64")
|
|
|
666 (V2SF "f32") (V4SF "f32")
|
|
|
667 (SF "f32") (DF "f64")
|
|
|
668 (HF "f16") (V4HF "f16")
|
|
|
669 (V8HF "f16")])
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
670
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
671 ;; Same, but for operations which work on signed values.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
672 (define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8")
|
|
111
|
673 (V4HI "s16") (V8HI "s16")
|
|
|
674 (V2SI "s32") (V4SI "s32")
|
|
|
675 (DI "s64") (V2DI "s64")
|
|
|
676 (V2SF "f32") (V4SF "f32")
|
|
|
677 (HF "f16") (V4HF "f16")
|
|
|
678 (V8HF "f16")])
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
679
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
680 ;; Same, but for operations which work on unsigned values.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
681 (define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
682 (V4HI "u16") (V8HI "u16")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
683 (V2SI "u32") (V4SI "u32")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
684 (DI "u64") (V2DI "u64")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
685 (V2SF "f32") (V4SF "f32")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
686
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
687 ;; Element types for extraction of unsigned scalars.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
688 (define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
689 (V4HI "u16") (V8HI "u16")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
690 (V2SI "32") (V4SI "32")
|
|
111
|
691 (V4HF "u16") (V8HF "u16")
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
692 (V2SF "32") (V4SF "32")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
693
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
694 (define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8")
|
|
111
|
695 (V4HI "16") (V8HI "16")
|
|
|
696 (V2SI "32") (V4SI "32")
|
|
|
697 (DI "64") (V2DI "64")
|
|
|
698 (V4HF "16") (V8HF "16")
|
|
|
699 (V2SF "32") (V4SF "32")])
|
|
|
700
|
|
|
701 (define_mode_attr V_elem_ch [(V8QI "b") (V16QI "b")
|
|
|
702 (V4HI "h") (V8HI "h")
|
|
|
703 (V2SI "s") (V4SI "s")
|
|
|
704 (DI "d") (V2DI "d")
|
|
|
705 (V2SF "s") (V4SF "s")
|
|
|
706 (V2SF "s") (V4SF "s")])
|
|
|
707
|
|
|
708 (define_mode_attr VH_elem_ch [(V4HI "s") (V8HI "s")
|
|
|
709 (V4HF "s") (V8HF "s")
|
|
|
710 (HF "s")])
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
711
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
712 ;; Element sizes for duplicating ARM registers to all elements of a vector.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
713 (define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
714
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
715 ;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.)
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
716 (define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
717 (V4HI "TI") (V8HI "OI")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
718 (V2SI "TI") (V4SI "OI")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
719 (V2SF "TI") (V4SF "OI")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
720 (DI "TI") (V2DI "OI")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
721
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
722 ;; Same, but lower-case.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
723 (define_mode_attr V_pair [(V8QI "ti") (V16QI "oi")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
724 (V4HI "ti") (V8HI "oi")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
725 (V2SI "ti") (V4SI "oi")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
726 (V2SF "ti") (V4SF "oi")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
727 (DI "ti") (V2DI "oi")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
728
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
729 ;; Extra suffix on some 64-bit insn names (to avoid collision with standard
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
730 ;; names which we don't want to define).
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
731 (define_mode_attr V_suf64 [(V8QI "") (V16QI "")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
732 (V4HI "") (V8HI "")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
733 (V2SI "") (V4SI "")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
734 (V2SF "") (V4SF "")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
735 (DI "_neon") (V2DI "")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
736
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
737
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
738 ;; Scalars to be presented to scalar multiplication instructions
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
739 ;; must satisfy the following constraints.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
740 ;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
741 ;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
742
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
743 ;; This mode attribute is used to obtain the correct register constraints.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
744
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
745 (define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t")
|
|
111
|
746 (V8HI "x") (V4SI "t") (V4SF "t")
|
|
|
747 (V8HF "x") (V4HF "x")])
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
748
|
|
111
|
749 ;; Predicates used for setting type for neon instructions
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
750
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
751 (define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false")
|
|
111
|
752 (V4HI "false") (V8HI "false")
|
|
|
753 (V2SI "false") (V4SI "false")
|
|
|
754 (V4HF "true") (V8HF "true")
|
|
|
755 (V2SF "true") (V4SF "true")
|
|
|
756 (DI "false") (V2DI "false")])
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
757
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
758 (define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true")
|
|
111
|
759 (V4HI "true") (V8HI "true")
|
|
|
760 (V2SI "false") (V4SI "false")
|
|
|
761 (V2SF "false") (V4SF "false")
|
|
|
762 (DI "false") (V2DI "false")])
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
763
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
764 (define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false")
|
|
111
|
765 (V4HI "true") (V8HI "false")
|
|
|
766 (V2SI "true") (V4SI "false")
|
|
|
767 (V2SF "true") (V4SF "false")
|
|
|
768 (DI "true") (V2DI "false")
|
|
|
769 (V4HF "true") (V8HF "false")])
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
770
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
771 (define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16")
|
|
111
|
772 (V4HF "4") (V8HF "8")
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
773 (V4HI "4") (V8HI "8")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
774 (V2SI "2") (V4SI "4")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
775 (V2SF "2") (V4SF "4")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
776 (DI "1") (V2DI "2")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
777 (DF "1") (V2DF "2")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
778
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
779 ;; Same as V_widen, but lower-case.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
780 (define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
781
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
782 ;; Widen. Result is half the number of elements, but widened to double-width.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
783 (define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
784
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
785 ;; Conditions to be used in extend<mode>di patterns.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
786 (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
787 (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
788 (QI "&& arm_arch6")])
|
|
111
|
789 (define_mode_attr qhs_zextenddi_op [(SI "s_register_operand")
|
|
|
790 (HI "nonimmediate_operand")
|
|
|
791 (QI "nonimmediate_operand")])
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
792 (define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
793 (HI "nonimmediate_operand")
|
|
111
|
794 (QI "arm_reg_or_extendqisi_mem_op")])
|
|
145
|
795 (define_mode_attr qhs_extenddi_cstr [(SI "0,r,r") (HI "0,rm,rm") (QI "0,rUq,rm")])
|
|
|
796 (define_mode_attr qhs_zextenddi_cstr [(SI "0,r") (HI "0,rm") (QI "0,rm")])
|
|
111
|
797
|
|
|
798 ;; Mode attributes used for fixed-point support.
|
|
|
799 (define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16")
|
|
|
800 (V2UHA "16") (UHA "16")
|
|
|
801 (V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16")
|
|
|
802 (V2HA "16") (HA "16") (SQ "") (SA "")])
|
|
|
803
|
|
145
|
804 (define_mode_attr qaddsub_clob_q [(V4UQQ "0") (V2UHQ "0") (UQQ "0") (UHQ "0")
|
|
|
805 (V2UHA "0") (UHA "0")
|
|
|
806 (V4QQ "0") (V2HQ "0") (QQ "0") (HQ "0")
|
|
|
807 (V2HA "0") (HA "0") (SQ "ARM_Q_BIT_READ")
|
|
|
808 (SA "ARM_Q_BIT_READ")])
|
|
|
809
|
|
111
|
810 ;; Mode attribute for vshll.
|
|
|
811 (define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")])
|
|
|
812
|
|
|
813 ;; Mode attributes used for VFP support.
|
|
|
814 (define_mode_attr F_constraint [(SF "t") (DF "w")])
|
|
|
815 (define_mode_attr vfp_type [(SF "s") (DF "d")])
|
|
|
816 (define_mode_attr vfp_double_cond [(SF "") (DF "&& TARGET_VFP_DOUBLE")])
|
|
145
|
817 (define_mode_attr VF_constraint [(V4HF "t") (V8HF "t") (V2SF "t") (V4SF "w")])
|
|
111
|
818
|
|
|
819 ;; Mode attribute used to build the "type" attribute.
|
|
|
820 (define_mode_attr q [(V8QI "") (V16QI "_q")
|
|
|
821 (V4HI "") (V8HI "_q")
|
|
|
822 (V2SI "") (V4SI "_q")
|
|
|
823 (V4HF "") (V8HF "_q")
|
|
|
824 (V2SF "") (V4SF "_q")
|
|
|
825 (V4HF "") (V8HF "_q")
|
|
145
|
826 (V4BF "") (V8BF "_q")
|
|
111
|
827 (DI "") (V2DI "_q")
|
|
|
828 (DF "") (V2DF "_q")
|
|
|
829 (HF "")])
|
|
|
830
|
|
|
831 (define_mode_attr pf [(V8QI "p") (V16QI "p") (V2SF "f") (V4SF "f")])
|
|
|
832
|
|
|
833 (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
|
|
|
834 (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
835
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
836 ;;----------------------------------------------------------------------------
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
837 ;; Code attributes
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
838 ;;----------------------------------------------------------------------------
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
839
|
|
145
|
840 ;; Determine the mode of a 'wide compare', ie where the carry flag is
|
|
|
841 ;; propagated into the comparison.
|
|
|
842 (define_code_attr CC_EXTEND [(sign_extend "CC_NV") (zero_extend "CC_B")])
|
|
|
843
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
844 ;; Assembler mnemonics for vqh_ops and vqhs_ops iterators.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
845 (define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
846 (umin "vmin") (umax "vmax")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
847
|
|
111
|
848 ;; Type attributes for vqh_ops and vqhs_ops iterators.
|
|
|
849 (define_code_attr VQH_type [(plus "add") (smin "minmax") (smax "minmax")
|
|
|
850 (umin "minmax") (umax "minmax")])
|
|
|
851
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
852 ;; Signs of above, where relevant.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
853 (define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u")
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
854 (umax "u")])
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
855
|
|
145
|
856 ;; Map rtl operator codes to optab names
|
|
|
857 (define_code_attr optab
|
|
|
858 [(and "and")
|
|
|
859 (ior "ior")
|
|
|
860 (xor "xor")])
|
68
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
861
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
862 ;; Assembler mnemonics for signedness of widening operations.
|
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
863 (define_code_attr US [(sign_extend "s") (zero_extend "u")])
|
|
145
|
864 (define_code_attr Us [(sign_extend "") (zero_extend "u")])
|
|
111
|
865
|
|
|
866 ;; Signedness suffix for float->fixed conversions. Empty for signed
|
|
|
867 ;; conversion.
|
|
|
868 (define_code_attr su_optab [(fix "") (unsigned_fix "u")])
|
|
|
869
|
|
|
870 ;; Sign prefix to use in instruction type suffixes, i.e. s32, u32.
|
|
|
871 (define_code_attr su [(fix "s") (unsigned_fix "u")])
|
|
|
872
|
|
|
873 ;; Right shifts
|
|
|
874 (define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")])
|
|
|
875 (define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")])
|
|
|
876
|
|
|
877 ;; String reprentations of operations on the sign of a number.
|
|
|
878 (define_code_attr absneg_str [(abs "abs") (neg "neg")])
|
|
|
879
|
|
|
880 ;; Conversions.
|
|
|
881 (define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")])
|
|
|
882
|
|
|
883 (define_code_attr float_sup [(unsigned_float "u") (float "s")])
|
|
|
884
|
|
|
885 (define_code_attr float_SUP [(unsigned_float "U") (float "S")])
|
|
|
886
|
|
|
887 ;;----------------------------------------------------------------------------
|
|
|
888 ;; Int attributes
|
|
|
889 ;;----------------------------------------------------------------------------
|
|
|
890
|
|
|
891 ;; Mapping between vector UNSPEC operations and the signed ('s'),
|
|
|
892 ;; unsigned ('u'), poly ('p') or float ('f') nature of their data type.
|
|
|
893 (define_int_attr sup [
|
|
145
|
894 (UNSPEC_SXTB16 "s") (UNSPEC_UXTB16 "u")
|
|
111
|
895 (UNSPEC_VADDL_S "s") (UNSPEC_VADDL_U "u")
|
|
|
896 (UNSPEC_VADDW_S "s") (UNSPEC_VADDW_U "u")
|
|
|
897 (UNSPEC_VRHADD_S "s") (UNSPEC_VRHADD_U "u")
|
|
|
898 (UNSPEC_VHADD_S "s") (UNSPEC_VHADD_U "u")
|
|
|
899 (UNSPEC_VQADD_S "s") (UNSPEC_VQADD_U "u")
|
|
|
900 (UNSPEC_VMLAL_S "s") (UNSPEC_VMLAL_U "u")
|
|
|
901 (UNSPEC_VMLAL_S_LANE "s") (UNSPEC_VMLAL_U_LANE "u")
|
|
|
902 (UNSPEC_VMLSL_S "s") (UNSPEC_VMLSL_U "u")
|
|
|
903 (UNSPEC_VMLSL_S_LANE "s") (UNSPEC_VMLSL_U_LANE "u")
|
|
|
904 (UNSPEC_VMULL_S "s") (UNSPEC_VMULL_U "u") (UNSPEC_VMULL_P "p")
|
|
|
905 (UNSPEC_VMULL_S_LANE "s") (UNSPEC_VMULL_U_LANE "u")
|
|
|
906 (UNSPEC_VSUBL_S "s") (UNSPEC_VSUBL_U "u")
|
|
|
907 (UNSPEC_VSUBW_S "s") (UNSPEC_VSUBW_U "u")
|
|
|
908 (UNSPEC_VHSUB_S "s") (UNSPEC_VHSUB_U "u")
|
|
|
909 (UNSPEC_VQSUB_S "s") (UNSPEC_VQSUB_U "u")
|
|
145
|
910 (UNSPEC_VABAL_S "s") (UNSPEC_VABAL_U "u")
|
|
111
|
911 (UNSPEC_VABD_S "s") (UNSPEC_VABD_U "u")
|
|
|
912 (UNSPEC_VABDL_S "s") (UNSPEC_VABDL_U "u")
|
|
|
913 (UNSPEC_VMAX "s") (UNSPEC_VMAX_U "u")
|
|
|
914 (UNSPEC_VMIN "s") (UNSPEC_VMIN_U "u")
|
|
|
915 (UNSPEC_VPADDL_S "s") (UNSPEC_VPADDL_U "u")
|
|
|
916 (UNSPEC_VPADAL_S "s") (UNSPEC_VPADAL_U "u")
|
|
|
917 (UNSPEC_VPMAX "s") (UNSPEC_VPMAX_U "u")
|
|
|
918 (UNSPEC_VPMIN "s") (UNSPEC_VPMIN_U "u")
|
|
|
919 (UNSPEC_VCVT_S "s") (UNSPEC_VCVT_U "u")
|
|
|
920 (UNSPEC_VCVTA_S "s") (UNSPEC_VCVTA_U "u")
|
|
|
921 (UNSPEC_VCVTM_S "s") (UNSPEC_VCVTM_U "u")
|
|
|
922 (UNSPEC_VCVTN_S "s") (UNSPEC_VCVTN_U "u")
|
|
|
923 (UNSPEC_VCVTP_S "s") (UNSPEC_VCVTP_U "u")
|
|
|
924 (UNSPEC_VCVT_S_N "s") (UNSPEC_VCVT_U_N "u")
|
|
|
925 (UNSPEC_VCVT_HF_S_N "s") (UNSPEC_VCVT_HF_U_N "u")
|
|
|
926 (UNSPEC_VCVT_SI_S_N "s") (UNSPEC_VCVT_SI_U_N "u")
|
|
|
927 (UNSPEC_VQMOVN_S "s") (UNSPEC_VQMOVN_U "u")
|
|
|
928 (UNSPEC_VMOVL_S "s") (UNSPEC_VMOVL_U "u")
|
|
|
929 (UNSPEC_VSHL_S "s") (UNSPEC_VSHL_U "u")
|
|
|
930 (UNSPEC_VRSHL_S "s") (UNSPEC_VRSHL_U "u")
|
|
|
931 (UNSPEC_VQSHL_S "s") (UNSPEC_VQSHL_U "u")
|
|
|
932 (UNSPEC_VQRSHL_S "s") (UNSPEC_VQRSHL_U "u")
|
|
|
933 (UNSPEC_VSHR_S_N "s") (UNSPEC_VSHR_U_N "u")
|
|
|
934 (UNSPEC_VRSHR_S_N "s") (UNSPEC_VRSHR_U_N "u")
|
|
|
935 (UNSPEC_VQSHRN_S_N "s") (UNSPEC_VQSHRN_U_N "u")
|
|
|
936 (UNSPEC_VQRSHRN_S_N "s") (UNSPEC_VQRSHRN_U_N "u")
|
|
|
937 (UNSPEC_VQSHL_S_N "s") (UNSPEC_VQSHL_U_N "u")
|
|
|
938 (UNSPEC_VSHLL_S_N "s") (UNSPEC_VSHLL_U_N "u")
|
|
|
939 (UNSPEC_VSRA_S_N "s") (UNSPEC_VSRA_U_N "u")
|
|
|
940 (UNSPEC_VRSRA_S_N "s") (UNSPEC_VRSRA_U_N "u")
|
|
|
941 (UNSPEC_VCVTH_S "s") (UNSPEC_VCVTH_U "u")
|
|
|
942 (UNSPEC_DOT_S "s") (UNSPEC_DOT_U "u")
|
|
145
|
943 (UNSPEC_DOT_US "us") (UNSPEC_DOT_SU "su")
|
|
|
944 (UNSPEC_SSAT16 "s") (UNSPEC_USAT16 "u")
|
|
111
|
945 ])
|
|
|
946
|
|
131
|
947 (define_int_attr vfml_half
|
|
|
948 [(UNSPEC_VFML_HI "high") (UNSPEC_VFML_LO "low")])
|
|
|
949
|
|
|
950 (define_int_attr vfml_half_selector
|
|
|
951 [(UNSPEC_VFML_HI "true") (UNSPEC_VFML_LO "false")])
|
|
|
952
|
|
111
|
953 (define_int_attr vcvth_op
|
|
|
954 [(UNSPEC_VCVTA_S "a") (UNSPEC_VCVTA_U "a")
|
|
|
955 (UNSPEC_VCVTM_S "m") (UNSPEC_VCVTM_U "m")
|
|
|
956 (UNSPEC_VCVTN_S "n") (UNSPEC_VCVTN_U "n")
|
|
|
957 (UNSPEC_VCVTP_S "p") (UNSPEC_VCVTP_U "p")])
|
|
|
958
|
|
|
959 (define_int_attr fp16_rnd_str
|
|
|
960 [(UNSPEC_VRND "rnd") (UNSPEC_VRNDA "rnda")
|
|
|
961 (UNSPEC_VRNDM "rndm") (UNSPEC_VRNDN "rndn")
|
|
|
962 (UNSPEC_VRNDP "rndp") (UNSPEC_VRNDX "rndx")])
|
|
|
963
|
|
|
964 (define_int_attr fp16_rnd_insn
|
|
|
965 [(UNSPEC_VRND "vrintz") (UNSPEC_VRNDA "vrinta")
|
|
|
966 (UNSPEC_VRNDM "vrintm") (UNSPEC_VRNDN "vrintn")
|
|
|
967 (UNSPEC_VRNDP "vrintp") (UNSPEC_VRNDX "vrintx")])
|
|
|
968
|
|
|
969 (define_int_attr cmp_op_unsp [(UNSPEC_VCEQ "eq") (UNSPEC_VCGT "gt")
|
|
|
970 (UNSPEC_VCGE "ge") (UNSPEC_VCLE "le")
|
|
|
971 (UNSPEC_VCLT "lt") (UNSPEC_VCAGE "ge")
|
|
|
972 (UNSPEC_VCAGT "gt") (UNSPEC_VCALE "le")
|
|
|
973 (UNSPEC_VCALT "lt")])
|
|
|
974
|
|
|
975 (define_int_attr r [
|
|
|
976 (UNSPEC_VRHADD_S "r") (UNSPEC_VRHADD_U "r")
|
|
|
977 (UNSPEC_VHADD_S "") (UNSPEC_VHADD_U "")
|
|
|
978 (UNSPEC_VADDHN "") (UNSPEC_VRADDHN "r")
|
|
|
979 (UNSPEC_VQDMULH "") (UNSPEC_VQRDMULH "r")
|
|
|
980 (UNSPEC_VQDMULH_LANE "") (UNSPEC_VQRDMULH_LANE "r")
|
|
|
981 (UNSPEC_VSUBHN "") (UNSPEC_VRSUBHN "r")
|
|
|
982 ])
|
|
|
983
|
|
|
984 (define_int_attr maxmin [
|
|
|
985 (UNSPEC_VMAX "max") (UNSPEC_VMAX_U "max")
|
|
|
986 (UNSPEC_VMIN "min") (UNSPEC_VMIN_U "min")
|
|
|
987 (UNSPEC_VPMAX "max") (UNSPEC_VPMAX_U "max")
|
|
|
988 (UNSPEC_VPMIN "min") (UNSPEC_VPMIN_U "min")
|
|
|
989 ])
|
|
|
990
|
|
|
991 (define_int_attr fmaxmin [
|
|
|
992 (UNSPEC_VMAXNM "fmax") (UNSPEC_VMINNM "fmin")])
|
|
|
993
|
|
|
994 (define_int_attr fmaxmin_op [
|
|
|
995 (UNSPEC_VMAXNM "vmaxnm") (UNSPEC_VMINNM "vminnm")
|
|
|
996 ])
|
|
|
997
|
|
|
998 (define_int_attr shift_op [
|
|
|
999 (UNSPEC_VSHL_S "shl") (UNSPEC_VSHL_U "shl")
|
|
|
1000 (UNSPEC_VRSHL_S "rshl") (UNSPEC_VRSHL_U "rshl")
|
|
|
1001 (UNSPEC_VQSHL_S "qshl") (UNSPEC_VQSHL_U "qshl")
|
|
|
1002 (UNSPEC_VQRSHL_S "qrshl") (UNSPEC_VQRSHL_U "qrshl")
|
|
|
1003 (UNSPEC_VSHR_S_N "shr") (UNSPEC_VSHR_U_N "shr")
|
|
|
1004 (UNSPEC_VRSHR_S_N "rshr") (UNSPEC_VRSHR_U_N "rshr")
|
|
|
1005 (UNSPEC_VSHRN_N "shrn") (UNSPEC_VRSHRN_N "rshrn")
|
|
|
1006 (UNSPEC_VQRSHRN_S_N "qrshrn") (UNSPEC_VQRSHRN_U_N "qrshrn")
|
|
|
1007 (UNSPEC_VQSHRN_S_N "qshrn") (UNSPEC_VQSHRN_U_N "qshrn")
|
|
|
1008 (UNSPEC_VQSHRUN_N "qshrun") (UNSPEC_VQRSHRUN_N "qrshrun")
|
|
|
1009 (UNSPEC_VSRA_S_N "sra") (UNSPEC_VSRA_U_N "sra")
|
|
|
1010 (UNSPEC_VRSRA_S_N "rsra") (UNSPEC_VRSRA_U_N "rsra")
|
|
|
1011 ])
|
|
|
1012
|
|
|
1013 ;; Standard names for floating point to integral rounding instructions.
|
|
|
1014 (define_int_attr vrint_pattern [(UNSPEC_VRINTZ "btrunc") (UNSPEC_VRINTP "ceil")
|
|
|
1015 (UNSPEC_VRINTA "round") (UNSPEC_VRINTM "floor")
|
|
|
1016 (UNSPEC_VRINTR "nearbyint") (UNSPEC_VRINTX "rint")])
|
|
|
1017
|
|
|
1018 ;; Suffixes for vrint instructions specifying rounding modes.
|
|
|
1019 (define_int_attr vrint_variant [(UNSPEC_VRINTZ "z") (UNSPEC_VRINTP "p")
|
|
|
1020 (UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m")
|
|
|
1021 (UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")])
|
|
|
1022
|
|
|
1023 ;; Some of the vrint instuctions are predicable.
|
|
|
1024 (define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no")
|
|
|
1025 (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no")
|
|
|
1026 (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")])
|
|
|
1027
|
|
|
1028 (define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional")
|
|
|
1029 (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional")
|
|
|
1030 (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")])
|
|
|
1031
|
|
|
1032 (define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p")
|
|
|
1033 (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m")
|
|
|
1034 (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")])
|
|
|
1035
|
|
|
1036 (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
|
|
|
1037 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32CB "crc32cb")
|
|
|
1038 (UNSPEC_CRC32CH "crc32ch") (UNSPEC_CRC32CW "crc32cw")])
|
|
|
1039
|
|
|
1040 (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
|
|
|
1041 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32CB "QI")
|
|
|
1042 (UNSPEC_CRC32CH "HI") (UNSPEC_CRC32CW "SI")])
|
|
|
1043
|
|
|
1044 (define_int_attr crypto_pattern [(UNSPEC_SHA1H "sha1h") (UNSPEC_AESMC "aesmc")
|
|
|
1045 (UNSPEC_AESIMC "aesimc") (UNSPEC_AESD "aesd")
|
|
|
1046 (UNSPEC_AESE "aese") (UNSPEC_SHA1SU1 "sha1su1")
|
|
|
1047 (UNSPEC_SHA256SU0 "sha256su0") (UNSPEC_SHA1C "sha1c")
|
|
|
1048 (UNSPEC_SHA1M "sha1m") (UNSPEC_SHA1P "sha1p")
|
|
|
1049 (UNSPEC_SHA1SU0 "sha1su0") (UNSPEC_SHA256H "sha256h")
|
|
|
1050 (UNSPEC_SHA256H2 "sha256h2")
|
|
|
1051 (UNSPEC_SHA256SU1 "sha256su1")])
|
|
|
1052
|
|
|
1053 (define_int_attr crypto_type
|
|
|
1054 [(UNSPEC_AESE "crypto_aese") (UNSPEC_AESD "crypto_aese")
|
|
|
1055 (UNSPEC_AESMC "crypto_aesmc") (UNSPEC_AESIMC "crypto_aesmc")
|
|
|
1056 (UNSPEC_SHA1C "crypto_sha1_slow") (UNSPEC_SHA1P "crypto_sha1_slow")
|
|
|
1057 (UNSPEC_SHA1M "crypto_sha1_slow") (UNSPEC_SHA1SU1 "crypto_sha1_fast")
|
|
|
1058 (UNSPEC_SHA1SU0 "crypto_sha1_xor") (UNSPEC_SHA256H "crypto_sha256_slow")
|
|
|
1059 (UNSPEC_SHA256H2 "crypto_sha256_slow") (UNSPEC_SHA256SU0 "crypto_sha256_fast")
|
|
|
1060 (UNSPEC_SHA256SU1 "crypto_sha256_slow")])
|
|
|
1061
|
|
|
1062 (define_int_attr crypto_size_sfx [(UNSPEC_SHA1H "32") (UNSPEC_AESMC "8")
|
|
|
1063 (UNSPEC_AESIMC "8") (UNSPEC_AESD "8")
|
|
|
1064 (UNSPEC_AESE "8") (UNSPEC_SHA1SU1 "32")
|
|
|
1065 (UNSPEC_SHA256SU0 "32") (UNSPEC_SHA1C "32")
|
|
|
1066 (UNSPEC_SHA1M "32") (UNSPEC_SHA1P "32")
|
|
|
1067 (UNSPEC_SHA1SU0 "32") (UNSPEC_SHA256H "32")
|
|
|
1068 (UNSPEC_SHA256H2 "32") (UNSPEC_SHA256SU1 "32")])
|
|
|
1069
|
|
|
1070 (define_int_attr crypto_mode [(UNSPEC_SHA1H "V4SI") (UNSPEC_AESMC "V16QI")
|
|
|
1071 (UNSPEC_AESIMC "V16QI") (UNSPEC_AESD "V16QI")
|
|
|
1072 (UNSPEC_AESE "V16QI") (UNSPEC_SHA1SU1 "V4SI")
|
|
|
1073 (UNSPEC_SHA256SU0 "V4SI") (UNSPEC_SHA1C "V4SI")
|
|
|
1074 (UNSPEC_SHA1M "V4SI") (UNSPEC_SHA1P "V4SI")
|
|
|
1075 (UNSPEC_SHA1SU0 "V4SI") (UNSPEC_SHA256H "V4SI")
|
|
|
1076 (UNSPEC_SHA256H2 "V4SI") (UNSPEC_SHA256SU1 "V4SI")])
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|
1077
|
|
145
|
1078 (define_int_attr rot [(UNSPEC_VCADD90 "90")
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|
1079 (UNSPEC_VCADD270 "270")
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|
1080 (UNSPEC_VCMLA "0")
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|
1081 (UNSPEC_VCMLA90 "90")
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|
1082 (UNSPEC_VCMLA180 "180")
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|
1083 (UNSPEC_VCMLA270 "270")])
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1084
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1085 (define_int_attr simd32_op [(UNSPEC_QADD8 "qadd8") (UNSPEC_QSUB8 "qsub8")
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1086 (UNSPEC_SHADD8 "shadd8") (UNSPEC_SHSUB8 "shsub8")
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|
1087 (UNSPEC_UHADD8 "uhadd8") (UNSPEC_UHSUB8 "uhsub8")
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|
1088 (UNSPEC_UQADD8 "uqadd8") (UNSPEC_UQSUB8 "uqsub8")
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|
1089 (UNSPEC_QADD16 "qadd16") (UNSPEC_QASX "qasx")
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|
1090 (UNSPEC_QSAX "qsax") (UNSPEC_QSUB16 "qsub16")
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|
1091 (UNSPEC_SHADD16 "shadd16") (UNSPEC_SHASX "shasx")
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|
1092 (UNSPEC_SHSAX "shsax") (UNSPEC_SHSUB16 "shsub16")
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|
1093 (UNSPEC_UHADD16 "uhadd16") (UNSPEC_UHASX "uhasx")
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|
1094 (UNSPEC_UHSAX "uhsax") (UNSPEC_UHSUB16 "uhsub16")
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|
|
1095 (UNSPEC_UQADD16 "uqadd16") (UNSPEC_UQASX "uqasx")
|
|
|
1096 (UNSPEC_UQSAX "uqsax") (UNSPEC_UQSUB16 "uqsub16")
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|
|
1097 (UNSPEC_SMUSD "smusd") (UNSPEC_SMUSDX "smusdx")
|
|
|
1098 (UNSPEC_SXTAB16 "sxtab16") (UNSPEC_UXTAB16 "uxtab16")
|
|
|
1099 (UNSPEC_USAD8 "usad8") (UNSPEC_SMLALD "smlald")
|
|
|
1100 (UNSPEC_SMLALDX "smlaldx") (UNSPEC_SMLSLD "smlsld")
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|
|
1101 (UNSPEC_SMLSLDX "smlsldx")(UNSPEC_SADD8 "sadd8")
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|
|
1102 (UNSPEC_UADD8 "uadd8") (UNSPEC_SSUB8 "ssub8")
|
|
|
1103 (UNSPEC_USUB8 "usub8") (UNSPEC_SADD16 "sadd16")
|
|
|
1104 (UNSPEC_SASX "sasx") (UNSPEC_SSAX "ssax")
|
|
|
1105 (UNSPEC_SSUB16 "ssub16") (UNSPEC_UADD16 "uadd16")
|
|
|
1106 (UNSPEC_UASX "uasx") (UNSPEC_USAX "usax")
|
|
|
1107 (UNSPEC_USUB16 "usub16") (UNSPEC_SMLAD "smlad")
|
|
|
1108 (UNSPEC_SMLADX "smladx") (UNSPEC_SMLSD "smlsd")
|
|
|
1109 (UNSPEC_SMLSDX "smlsdx") (UNSPEC_SMUAD "smuad")
|
|
|
1110 (UNSPEC_SMUADX "smuadx") (UNSPEC_SSAT16 "ssat16")
|
|
|
1111 (UNSPEC_USAT16 "usat16")])
|
|
|
1112
|
|
111
|
1113 ;; Both kinds of return insn.
|
|
|
1114 (define_code_iterator RETURNS [return simple_return])
|
|
|
1115 (define_code_attr return_str [(return "") (simple_return "simple_")])
|
|
|
1116 (define_code_attr return_simple_p [(return "false") (simple_return "true")])
|
|
|
1117 (define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)")
|
|
|
1118 (simple_return " && use_simple_return_p ()")])
|
|
|
1119 (define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)")
|
|
|
1120 (simple_return " && use_simple_return_p ()")])
|
|
|
1121
|
|
|
1122 ;; Attributes for VQRDMLAH/VQRDMLSH
|
|
|
1123 (define_int_attr neon_rdma_as [(UNSPEC_VQRDMLAH "a") (UNSPEC_VQRDMLSH "s")])
|
|
|
1124
|
|
|
1125 ;; Attributes for VFMA_LANE/ VFMS_LANE
|
|
|
1126 (define_int_attr neon_vfm_lane_as
|
|
|
1127 [(UNSPEC_VFMA_LANE "a") (UNSPEC_VFMS_LANE "s")])
|
|
|
1128
|
|
|
1129 ;; An iterator for the CDP coprocessor instructions
|
|
|
1130 (define_int_iterator CDPI [VUNSPEC_CDP VUNSPEC_CDP2])
|
|
|
1131 (define_int_attr cdp [(VUNSPEC_CDP "cdp") (VUNSPEC_CDP2 "cdp2")])
|
|
|
1132 (define_int_attr CDP [(VUNSPEC_CDP "CDP") (VUNSPEC_CDP2 "CDP2")])
|
|
|
1133
|
|
|
1134 ;; An iterator for the LDC coprocessor instruction
|
|
|
1135 (define_int_iterator LDCI [VUNSPEC_LDC VUNSPEC_LDC2
|
|
|
1136 VUNSPEC_LDCL VUNSPEC_LDC2L])
|
|
|
1137 (define_int_attr ldc [(VUNSPEC_LDC "ldc") (VUNSPEC_LDC2 "ldc2")
|
|
|
1138 (VUNSPEC_LDCL "ldcl") (VUNSPEC_LDC2L "ldc2l")])
|
|
|
1139 (define_int_attr LDC [(VUNSPEC_LDC "LDC") (VUNSPEC_LDC2 "LDC2")
|
|
|
1140 (VUNSPEC_LDCL "LDCL") (VUNSPEC_LDC2L "LDC2L")])
|
|
|
1141
|
|
|
1142 ;; An iterator for the STC coprocessor instructions
|
|
|
1143 (define_int_iterator STCI [VUNSPEC_STC VUNSPEC_STC2
|
|
|
1144 VUNSPEC_STCL VUNSPEC_STC2L])
|
|
|
1145 (define_int_attr stc [(VUNSPEC_STC "stc") (VUNSPEC_STC2 "stc2")
|
|
|
1146 (VUNSPEC_STCL "stcl") (VUNSPEC_STC2L "stc2l")])
|
|
|
1147 (define_int_attr STC [(VUNSPEC_STC "STC") (VUNSPEC_STC2 "STC2")
|
|
|
1148 (VUNSPEC_STCL "STCL") (VUNSPEC_STC2L "STC2L")])
|
|
|
1149
|
|
|
1150 ;; An iterator for the MCR coprocessor instructions
|
|
|
1151 (define_int_iterator MCRI [VUNSPEC_MCR VUNSPEC_MCR2])
|
|
|
1152
|
|
|
1153 (define_int_attr mcr [(VUNSPEC_MCR "mcr") (VUNSPEC_MCR2 "mcr2")])
|
|
|
1154 (define_int_attr MCR [(VUNSPEC_MCR "MCR") (VUNSPEC_MCR2 "MCR2")])
|
|
|
1155
|
|
|
1156 ;; An iterator for the MRC coprocessor instructions
|
|
|
1157 (define_int_iterator MRCI [VUNSPEC_MRC VUNSPEC_MRC2])
|
|
|
1158
|
|
|
1159 (define_int_attr mrc [(VUNSPEC_MRC "mrc") (VUNSPEC_MRC2 "mrc2")])
|
|
|
1160 (define_int_attr MRC [(VUNSPEC_MRC "MRC") (VUNSPEC_MRC2 "MRC2")])
|
|
|
1161
|
|
|
1162 ;; An iterator for the MCRR coprocessor instructions
|
|
|
1163 (define_int_iterator MCRRI [VUNSPEC_MCRR VUNSPEC_MCRR2])
|
|
|
1164
|
|
|
1165 (define_int_attr mcrr [(VUNSPEC_MCRR "mcrr") (VUNSPEC_MCRR2 "mcrr2")])
|
|
|
1166 (define_int_attr MCRR [(VUNSPEC_MCRR "MCRR") (VUNSPEC_MCRR2 "MCRR2")])
|
|
|
1167
|
|
|
1168 ;; An iterator for the MRRC coprocessor instructions
|
|
|
1169 (define_int_iterator MRRCI [VUNSPEC_MRRC VUNSPEC_MRRC2])
|
|
|
1170
|
|
|
1171 (define_int_attr mrrc [(VUNSPEC_MRRC "mrrc") (VUNSPEC_MRRC2 "mrrc2")])
|
|
|
1172 (define_int_attr MRRC [(VUNSPEC_MRRC "MRRC") (VUNSPEC_MRRC2 "MRRC2")])
|
|
|
1173
|
|
|
1174 (define_int_attr opsuffix [(UNSPEC_DOT_S "s8")
|
|
145
|
1175 (UNSPEC_DOT_U "u8")
|
|
|
1176 (UNSPEC_DOT_US "s8")
|
|
|
1177 (UNSPEC_DOT_SU "u8")
|
|
|
1178 ])
|
|
|
1179
|
|
|
1180 (define_int_attr smlaw_op [(UNSPEC_SMLAWB "smlawb") (UNSPEC_SMLAWT "smlawt")])
|
