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1 ;; Instruction Classification for ARM for GNU compiler.
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2
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145
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3 ;; Copyright (C) 1991-2020 Free Software Foundation, Inc.
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111
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4 ;; Contributed by ARM Ltd.
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5
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6 ;; This file is part of GCC.
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7
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8 ;; GCC is free software; you can redistribute it and/or modify it
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9 ;; under the terms of the GNU General Public License as published
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10 ;; by the Free Software Foundation; either version 3, or (at your
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11 ;; option) any later version.
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12
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13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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16 ;; License for more details.
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17
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 ; TYPE attribute is used to classify instructions for use in scheduling.
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23 ;
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24 ; Instruction classification:
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25 ;
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26 ; adc_imm add/subtract with carry and with an immediate operand.
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27 ; adc_reg add/subtract with carry and no immediate operand.
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28 ; adcs_imm as adc_imm, setting condition flags.
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29 ; adcs_reg as adc_reg, setting condition flags.
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30 ; adr calculate address.
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31 ; alu_ext From ARMv8-A: any arithmetic instruction that has a
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32 ; sign/zero-extended.
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33 ; AArch64 Only.
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34 ; source operand
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35 ; alu_imm any arithmetic instruction that doesn't have a shifted
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36 ; operand and has an immediate operand. This
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37 ; excludes MOV, MVN and RSB(S) immediate.
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38 ; alu_sreg any arithmetic instruction that doesn't have a shifted
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39 ; or an immediate operand. This excludes
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40 ; MOV and MVN but includes MOVT. This also excludes
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41 ; DSP-kind instructions. This is also the default.
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42 ; alu_shift_imm any arithmetic instruction that has a source operand
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43 ; shifted by a constant. This excludes simple shifts.
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44 ; alu_shift_reg as alu_shift_imm, with the shift amount specified in a
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45 ; register.
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46 ; alu_dsp_reg any DSP-kind instruction like QSUB8.
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47 ; alus_ext From ARMv8-A: as alu_ext, setting condition flags.
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48 ; AArch64 Only.
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49 ; alus_imm as alu_imm, setting condition flags.
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50 ; alus_sreg as alu_sreg, setting condition flags.
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51 ; alus_shift_imm as alu_shift_imm, setting condition flags.
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52 ; alus_shift_reg as alu_shift_reg, setting condition flags.
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53 ; bfm bitfield move operation.
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54 ; bfx bitfield extract operation.
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55 ; block blockage insn, this blocks all functional units.
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56 ; branch branch.
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57 ; call subroutine call.
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58 ; clz count leading zeros (CLZ).
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59 ; csel From ARMv8-A: conditional select.
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60 ; extend extend instruction (SXTB, SXTH, UXTB, UXTH).
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61 ; f_cvt conversion between float representations.
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62 ; f_cvtf2i conversion between float and integral types.
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63 ; f_cvti2f conversion between integral and float types.
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64 ; f_flag transfer of co-processor flags to the CPSR.
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65 ; f_load[d,s] double/single load from memory. Used for VFP unit.
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66 ; f_mcr transfer arm to vfp reg.
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67 ; f_mcrr transfer two arm regs to vfp reg.
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68 ; f_minmax[d,s] double/single floating point minimum/maximum.
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69 ; f_mrc transfer vfp to arm reg.
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70 ; f_mrrc transfer vfp to two arm regs.
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71 ; f_rint[d,s] double/single floating point rount to integral.
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72 ; f_store[d,s] double/single store to memory. Used for VFP unit.
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73 ; fadd[d,s] double/single floating-point scalar addition.
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74 ; fccmp[d,s] From ARMv8-A: floating-point conditional compare.
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75 ; fcmp[d,s] double/single floating-point compare.
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76 ; fconst[d,s] double/single load immediate.
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77 ; fcsel From ARMv8-A: Floating-point conditional select.
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78 ; fdiv[d,s] double/single precision floating point division.
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79 ; ffarith[d,s] double/single floating point abs/neg/cpy.
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80 ; ffma[d,s] double/single floating point fused multiply-accumulate.
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81 ; float floating point arithmetic operation.
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82 ; fmac[d,s] double/single floating point multiply-accumulate.
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83 ; fmov floating point to floating point register move.
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84 ; fmul[d,s] double/single floating point multiply.
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85 ; fsqrt[d,s] double/single precision floating point square root.
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86 ; load_acq load-acquire.
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87 ; load_byte load 1 byte from memory.
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88 ; load_4 load 4 bytes from memory.
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89 ; load_8 load 8 bytes from memory.
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90 ; load_12 load 12 bytes from memory.
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91 ; load_16 load 16 bytes from memory.
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92 ; logic_imm any logical instruction that doesn't have a shifted
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93 ; operand and has an immediate operand.
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94 ; logic_reg any logical instruction that doesn't have a shifted
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95 ; operand or an immediate operand.
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96 ; logic_shift_imm any logical instruction that has a source operand
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97 ; shifted by a constant. This excludes simple shifts.
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98 ; logic_shift_reg as logic_shift_imm, with the shift amount specified in a
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99 ; register.
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100 ; logics_imm as logic_imm, setting condition flags.
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101 ; logics_reg as logic_reg, setting condition flags.
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102 ; logics_shift_imm as logic_shift_imm, setting condition flags.
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103 ; logics_shift_reg as logic_shift_reg, setting condition flags.
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104 ; mla integer multiply accumulate.
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105 ; mlas integer multiply accumulate, flag setting.
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106 ; mov_imm simple MOV instruction that moves an immediate to
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107 ; register. This includes MOVW, but not MOVT.
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108 ; mov_reg simple MOV instruction that moves a register to another
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109 ; register. This includes MOVW, but not MOVT.
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110 ; mov_shift simple MOV instruction, shifted operand by a constant.
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111 ; mov_shift_reg simple MOV instruction, shifted operand by a register.
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112 ; mrs system/special/co-processor register move.
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113 ; mul integer multiply.
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114 ; muls integer multiply, flag setting.
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115 ; multiple more than one instruction, candidate for future
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116 ; splitting, or better modeling.
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117 ; mvn_imm inverting move instruction, immediate.
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118 ; mvn_reg inverting move instruction, register.
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119 ; mvn_shift inverting move instruction, shifted operand by a constant.
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120 ; mvn_shift_reg inverting move instruction, shifted operand by a register.
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121 ; no_insn an insn which does not represent an instruction in the
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122 ; final output, thus having no impact on scheduling.
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123 ; rbit reverse bits.
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124 ; rev reverse bytes.
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125 ; rotate_imm rotate by immediate.
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126 ; sdiv signed division.
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127 ; shift_imm simple shift operation (LSL, LSR, ASR, ROR) with an
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128 ; immediate.
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129 ; shift_reg simple shift by a register.
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130 ; smlad signed multiply accumulate dual.
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131 ; smladx signed multiply accumulate dual reverse.
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132 ; smlal signed multiply accumulate long.
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133 ; smlald signed multiply accumulate long dual.
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134 ; smlals signed multiply accumulate long, flag setting.
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135 ; smlalxy signed multiply accumulate, 16x16-bit, 64-bit accumulate.
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136 ; smlawx signed multiply accumulate, 32x16-bit, 32-bit accumulate.
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137 ; smlawy signed multiply accumulate wide, 32x16-bit,
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138 ; 32-bit accumulate.
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139 ; smlaxy signed multiply accumulate, 16x16-bit, 32-bit accumulate.
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140 ; smlsd signed multiply subtract dual.
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141 ; smlsdx signed multiply subtract dual reverse.
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142 ; smlsld signed multiply subtract long dual.
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143 ; smmla signed most significant word multiply accumulate.
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144 ; smmul signed most significant word multiply.
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145 ; smmulr signed most significant word multiply, rounded.
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146 ; smuad signed dual multiply add.
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147 ; smuadx signed dual multiply add reverse.
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148 ; smull signed multiply long.
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149 ; smulls signed multiply long, flag setting.
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150 ; smulwy signed multiply wide, 32x16-bit, 32-bit accumulate.
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151 ; smulxy signed multiply, 16x16-bit, 32-bit accumulate.
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152 ; smusd signed dual multiply subtract.
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153 ; smusdx signed dual multiply subtract reverse.
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154 ; store_rel store-release.
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155 ; store_4 store 4 bytes to memory.
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156 ; store_8 store 8 bytes to memory.
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157 ; store_12 store 12 bytes to memory.
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158 ; store_16 store 16 bytes (or more) to memory.
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159 ; trap cause a trap in the kernel.
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160 ; udiv unsigned division.
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161 ; umaal unsigned multiply accumulate accumulate long.
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162 ; umlal unsigned multiply accumulate long.
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163 ; umlals unsigned multiply accumulate long, flag setting.
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164 ; umull unsigned multiply long.
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165 ; umulls unsigned multiply long, flag setting.
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166 ; untyped insn without type information - default, and error,
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167 ; case.
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168 ;
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169 ; The classification below is for instructions used by the Wireless MMX
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170 ; Technology. Each attribute value is used to classify an instruction of the
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171 ; same name or family.
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172 ;
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173 ; wmmx_tandc
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174 ; wmmx_tbcst
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175 ; wmmx_textrc
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176 ; wmmx_textrm
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177 ; wmmx_tinsr
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178 ; wmmx_tmcr
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179 ; wmmx_tmcrr
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180 ; wmmx_tmia
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181 ; wmmx_tmiaph
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182 ; wmmx_tmiaxy
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183 ; wmmx_tmrc
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184 ; wmmx_tmrrc
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185 ; wmmx_tmovmsk
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186 ; wmmx_torc
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187 ; wmmx_torvsc
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188 ; wmmx_wabs
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189 ; wmmx_wdiff
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190 ; wmmx_wacc
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191 ; wmmx_wadd
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192 ; wmmx_waddbhus
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193 ; wmmx_waddsubhx
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194 ; wmmx_waligni
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195 ; wmmx_walignr
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196 ; wmmx_wand
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197 ; wmmx_wandn
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198 ; wmmx_wavg2
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199 ; wmmx_wavg4
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200 ; wmmx_wcmpeq
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201 ; wmmx_wcmpgt
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202 ; wmmx_wmac
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203 ; wmmx_wmadd
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204 ; wmmx_wmax
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205 ; wmmx_wmerge
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206 ; wmmx_wmiawxy
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207 ; wmmx_wmiaxy
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208 ; wmmx_wmin
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209 ; wmmx_wmov
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210 ; wmmx_wmul
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211 ; wmmx_wmulw
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212 ; wmmx_wldr
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213 ; wmmx_wor
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214 ; wmmx_wpack
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215 ; wmmx_wqmiaxy
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216 ; wmmx_wqmulm
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217 ; wmmx_wqmulwm
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218 ; wmmx_wror
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219 ; wmmx_wsad
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220 ; wmmx_wshufh
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221 ; wmmx_wsll
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222 ; wmmx_wsra
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223 ; wmmx_wsrl
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224 ; wmmx_wstr
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225 ; wmmx_wsub
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226 ; wmmx_wsubaddhx
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227 ; wmmx_wunpckeh
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228 ; wmmx_wunpckel
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229 ; wmmx_wunpckih
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230 ; wmmx_wunpckil
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231 ; wmmx_wxor
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232 ;
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233 ; The classification below is for NEON instructions.
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234 ;
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235 ; neon_add
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236 ; neon_add_q
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237 ; neon_add_widen
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238 ; neon_add_long
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239 ; neon_qadd
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240 ; neon_qadd_q
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241 ; neon_add_halve
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242 ; neon_add_halve_q
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243 ; neon_add_halve_narrow_q
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244 ; neon_sub
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245 ; neon_sub_q
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246 ; neon_sub_widen
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247 ; neon_sub_long
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248 ; neon_qsub
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249 ; neon_qsub_q
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250 ; neon_sub_halve
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251 ; neon_sub_halve_q
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252 ; neon_sub_halve_narrow_q
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253 ; neon_abs
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254 ; neon_abs_q
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255 ; neon_neg
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256 ; neon_neg_q
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257 ; neon_qneg
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258 ; neon_qneg_q
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259 ; neon_qabs
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260 ; neon_qabs_q
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261 ; neon_abd
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262 ; neon_abd_q
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263 ; neon_abd_long
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264 ; neon_minmax
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265 ; neon_minmax_q
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266 ; neon_compare
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267 ; neon_compare_q
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268 ; neon_compare_zero
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269 ; neon_compare_zero_q
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270 ; neon_arith_acc
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271 ; neon_arith_acc_q
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272 ; neon_reduc_add
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273 ; neon_reduc_add_q
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274 ; neon_reduc_add_long
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275 ; neon_reduc_add_acc
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276 ; neon_reduc_add_acc_q
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277 ; neon_reduc_minmax
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278 ; neon_reduc_minmax_q
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279 ; neon_logic
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280 ; neon_logic_q
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281 ; neon_tst
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282 ; neon_tst_q
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283 ; neon_shift_imm
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284 ; neon_shift_imm_q
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285 ; neon_shift_imm_narrow_q
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286 ; neon_shift_imm_long
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287 ; neon_shift_reg
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288 ; neon_shift_reg_q
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289 ; neon_shift_acc
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290 ; neon_shift_acc_q
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291 ; neon_sat_shift_imm
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292 ; neon_sat_shift_imm_q
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293 ; neon_sat_shift_imm_narrow_q
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294 ; neon_sat_shift_reg
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295 ; neon_sat_shift_reg_q
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296 ; neon_ins
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297 ; neon_ins_q
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298 ; neon_move
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299 ; neon_move_q
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300 ; neon_move_narrow_q
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301 ; neon_permute
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302 ; neon_permute_q
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303 ; neon_zip
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304 ; neon_zip_q
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305 ; neon_tbl1
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306 ; neon_tbl1_q
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307 ; neon_tbl2
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308 ; neon_tbl2_q
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309 ; neon_tbl3
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310 ; neon_tbl3_q
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311 ; neon_tbl4
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312 ; neon_tbl4_q
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313 ; neon_bsl
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314 ; neon_bsl_q
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315 ; neon_cls
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316 ; neon_cls_q
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317 ; neon_cnt
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318 ; neon_cnt_q
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319 ; neon_dot
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320 ; neon_dot_q
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321 ; neon_ext
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322 ; neon_ext_q
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323 ; neon_rbit
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324 ; neon_rbit_q
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325 ; neon_rev
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326 ; neon_rev_q
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327 ; neon_mul_b
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328 ; neon_mul_b_q
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329 ; neon_mul_h
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330 ; neon_mul_h_q
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331 ; neon_mul_s
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332 ; neon_mul_s_q
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333 ; neon_mul_b_long
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334 ; neon_mul_h_long
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335 ; neon_mul_s_long
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336 ; neon_mul_d_long
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337 ; neon_mul_h_scalar
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338 ; neon_mul_h_scalar_q
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339 ; neon_mul_s_scalar
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340 ; neon_mul_s_scalar_q
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341 ; neon_mul_h_scalar_long
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342 ; neon_mul_s_scalar_long
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343 ; neon_sat_mul_b
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344 ; neon_sat_mul_b_q
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345 ; neon_sat_mul_h
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346 ; neon_sat_mul_h_q
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347 ; neon_sat_mul_s
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348 ; neon_sat_mul_s_q
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349 ; neon_sat_mul_b_long
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350 ; neon_sat_mul_h_long
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351 ; neon_sat_mul_s_long
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352 ; neon_sat_mul_h_scalar
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353 ; neon_sat_mul_h_scalar_q
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354 ; neon_sat_mul_s_scalar
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355 ; neon_sat_mul_s_scalar_q
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356 ; neon_sat_mul_h_scalar_long
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357 ; neon_sat_mul_s_scalar_long
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358 ; neon_mla_b
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359 ; neon_mla_b_q
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360 ; neon_mla_h
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361 ; neon_mla_h_q
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362 ; neon_mla_s
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363 ; neon_mla_s_q
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364 ; neon_mla_b_long
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365 ; neon_mla_h_long
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366 ; neon_mla_s_long
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367 ; neon_mla_h_scalar
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368 ; neon_mla_h_scalar_q
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369 ; neon_mla_s_scalar
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370 ; neon_mla_s_scalar_q
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371 ; neon_mla_h_scalar_long
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372 ; neon_mla_s_scalar_long
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373 ; neon_sat_mla_b_long
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374 ; neon_sat_mla_h_long
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375 ; neon_sat_mla_s_long
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376 ; neon_sat_mla_h_scalar_long
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377 ; neon_sat_mla_s_scalar_long
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378 ; neon_to_gp
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379 ; neon_to_gp_q
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380 ; neon_from_gp
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381 ; neon_from_gp_q
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382 ; neon_ldr
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|
|
383 ; neon_ldp
|
|
|
384 ; neon_ldp_q
|
|
|
385 ; neon_load1_1reg
|
|
|
386 ; neon_load1_1reg_q
|
|
|
387 ; neon_load1_2reg
|
|
|
388 ; neon_load1_2reg_q
|
|
|
389 ; neon_load1_3reg
|
|
|
390 ; neon_load1_3reg_q
|
|
|
391 ; neon_load1_4reg
|
|
|
392 ; neon_load1_4reg_q
|
|
|
393 ; neon_load1_all_lanes
|
|
|
394 ; neon_load1_all_lanes_q
|
|
|
395 ; neon_load1_one_lane
|
|
|
396 ; neon_load1_one_lane_q
|
|
|
397 ; neon_load2_2reg
|
|
|
398 ; neon_load2_2reg_q
|
|
|
399 ; neon_load2_4reg
|
|
|
400 ; neon_load2_4reg_q
|
|
|
401 ; neon_load2_all_lanes
|
|
|
402 ; neon_load2_all_lanes_q
|
|
|
403 ; neon_load2_one_lane
|
|
|
404 ; neon_load2_one_lane_q
|
|
|
405 ; neon_load3_3reg
|
|
|
406 ; neon_load3_3reg_q
|
|
|
407 ; neon_load3_all_lanes
|
|
|
408 ; neon_load3_all_lanes_q
|
|
|
409 ; neon_load3_one_lane
|
|
|
410 ; neon_load3_one_lane_q
|
|
|
411 ; neon_load4_4reg
|
|
|
412 ; neon_load4_4reg_q
|
|
|
413 ; neon_load4_all_lanes
|
|
|
414 ; neon_load4_all_lanes_q
|
|
|
415 ; neon_load4_one_lane
|
|
|
416 ; neon_load4_one_lane_q
|
|
|
417 ; neon_str
|
|
|
418 ; neon_stp
|
|
|
419 ; neon_stp_q
|
|
|
420 ; neon_store1_1reg
|
|
|
421 ; neon_store1_1reg_q
|
|
|
422 ; neon_store1_2reg
|
|
|
423 ; neon_store1_2reg_q
|
|
|
424 ; neon_store1_3reg
|
|
|
425 ; neon_store1_3reg_q
|
|
|
426 ; neon_store1_4reg
|
|
|
427 ; neon_store1_4reg_q
|
|
|
428 ; neon_store1_one_lane
|
|
|
429 ; neon_store1_one_lane_q
|
|
|
430 ; neon_store2_2reg
|
|
|
431 ; neon_store2_2reg_q
|
|
|
432 ; neon_store2_4reg
|
|
|
433 ; neon_store2_4reg_q
|
|
|
434 ; neon_store2_one_lane
|
|
|
435 ; neon_store2_one_lane_q
|
|
|
436 ; neon_store3_3reg
|
|
|
437 ; neon_store3_3reg_q
|
|
|
438 ; neon_store3_one_lane
|
|
|
439 ; neon_store3_one_lane_q
|
|
|
440 ; neon_store4_4reg
|
|
|
441 ; neon_store4_4reg_q
|
|
|
442 ; neon_store4_one_lane
|
|
|
443 ; neon_store4_one_lane_q
|
|
|
444 ; neon_fp_abs_s
|
|
|
445 ; neon_fp_abs_s_q
|
|
|
446 ; neon_fp_abs_d
|
|
|
447 ; neon_fp_abs_d_q
|
|
|
448 ; neon_fp_neg_s
|
|
|
449 ; neon_fp_neg_s_q
|
|
|
450 ; neon_fp_neg_d
|
|
|
451 ; neon_fp_neg_d_q
|
|
|
452 ; neon_fp_abd_s
|
|
|
453 ; neon_fp_abd_s_q
|
|
|
454 ; neon_fp_abd_d
|
|
|
455 ; neon_fp_abd_d_q
|
|
|
456 ; neon_fp_addsub_s
|
|
|
457 ; neon_fp_addsub_s_q
|
|
|
458 ; neon_fp_addsub_d
|
|
|
459 ; neon_fp_addsub_d_q
|
|
|
460 ; neon_fp_compare_s
|
|
|
461 ; neon_fp_compare_s_q
|
|
|
462 ; neon_fp_compare_d
|
|
|
463 ; neon_fp_compare_d_q
|
|
|
464 ; neon_fp_minmax_s
|
|
|
465 ; neon_fp_minmax_s_q
|
|
|
466 ; neon_fp_minmax_d
|
|
|
467 ; neon_fp_minmax_d_q
|
|
|
468 ; neon_fp_reduc_add_s
|
|
|
469 ; neon_fp_reduc_add_s_q
|
|
|
470 ; neon_fp_reduc_add_d
|
|
|
471 ; neon_fp_reduc_add_d_q
|
|
|
472 ; neon_fp_reduc_minmax_s
|
|
|
473 ; neon_fp_reduc_minmax_s_q
|
|
|
474 ; neon_fp_reduc_minmax_d
|
|
|
475 ; neon_fp_reduc_minmax_d_q
|
|
|
476 ; neon_fp_cvt_narrow_s_q
|
|
|
477 ; neon_fp_cvt_narrow_d_q
|
|
|
478 ; neon_fp_cvt_widen_h
|
|
|
479 ; neon_fp_cvt_widen_s
|
|
|
480 ; neon_fp_to_int_s
|
|
|
481 ; neon_fp_to_int_s_q
|
|
|
482 ; neon_fp_to_int_d
|
|
|
483 ; neon_fp_to_int_d_q
|
|
|
484 ; neon_int_to_fp_s
|
|
|
485 ; neon_int_to_fp_s_q
|
|
|
486 ; neon_int_to_fp_d
|
|
|
487 ; neon_int_to_fp_d_q
|
|
|
488 ; neon_fp_round_s
|
|
|
489 ; neon_fp_round_s_q
|
|
|
490 ; neon_fp_round_d
|
|
|
491 ; neon_fp_round_d_q
|
|
|
492 ; neon_fp_recpe_s
|
|
|
493 ; neon_fp_recpe_s_q
|
|
|
494 ; neon_fp_recpe_d
|
|
|
495 ; neon_fp_recpe_d_q
|
|
|
496 ; neon_fp_recps_s
|
|
|
497 ; neon_fp_recps_s_q
|
|
|
498 ; neon_fp_recps_d
|
|
|
499 ; neon_fp_recps_d_q
|
|
|
500 ; neon_fp_recpx_s
|
|
|
501 ; neon_fp_recpx_s_q
|
|
|
502 ; neon_fp_recpx_d
|
|
|
503 ; neon_fp_recpx_d_q
|
|
|
504 ; neon_fp_rsqrte_s
|
|
|
505 ; neon_fp_rsqrte_s_q
|
|
|
506 ; neon_fp_rsqrte_d
|
|
|
507 ; neon_fp_rsqrte_d_q
|
|
|
508 ; neon_fp_rsqrts_s
|
|
|
509 ; neon_fp_rsqrts_s_q
|
|
|
510 ; neon_fp_rsqrts_d
|
|
|
511 ; neon_fp_rsqrts_d_q
|
|
|
512 ; neon_fp_mul_s
|
|
|
513 ; neon_fp_mul_s_q
|
|
|
514 ; neon_fp_mul_s_scalar
|
|
|
515 ; neon_fp_mul_s_scalar_q
|
|
|
516 ; neon_fp_mul_d
|
|
|
517 ; neon_fp_mul_d_q
|
|
|
518 ; neon_fp_mul_d_scalar_q
|
|
|
519 ; neon_fp_mla_s
|
|
|
520 ; neon_fp_mla_s_q
|
|
|
521 ; neon_fp_mla_s_scalar
|
|
|
522 ; neon_fp_mla_s_scalar_q
|
|
|
523 ; neon_fp_mla_d
|
|
|
524 ; neon_fp_mla_d_q
|
|
|
525 ; neon_fp_mla_d_scalar_q
|
|
|
526 ; neon_fp_sqrt_s
|
|
|
527 ; neon_fp_sqrt_s_q
|
|
|
528 ; neon_fp_sqrt_d
|
|
|
529 ; neon_fp_sqrt_d_q
|
|
|
530 ; neon_fp_div_s
|
|
|
531 ; neon_fp_div_s_q
|
|
|
532 ; neon_fp_div_d
|
|
|
533 ; neon_fp_div_d_q
|
|
|
534 ;
|
|
|
535 ; The classification below is for Crypto instructions.
|
|
|
536 ;
|
|
|
537 ; crypto_aese
|
|
|
538 ; crypto_aesmc
|
|
|
539 ; crypto_sha1_xor
|
|
|
540 ; crypto_sha1_fast
|
|
|
541 ; crypto_sha1_slow
|
|
|
542 ; crypto_sha256_fast
|
|
|
543 ; crypto_sha256_slow
|
|
|
544 ; crypto_pmull
|
|
|
545 ;
|
|
|
546 ; The classification below is for coprocessor instructions
|
|
|
547 ;
|
|
|
548 ; coproc
|
|
145
|
549 ;
|
|
|
550 ; The classification below is for TME instructions
|
|
|
551 ;
|
|
|
552 ; tme
|
|
111
|
553
|
|
|
554 (define_attr "type"
|
|
|
555 "adc_imm,\
|
|
|
556 adc_reg,\
|
|
|
557 adcs_imm,\
|
|
|
558 adcs_reg,\
|
|
|
559 adr,\
|
|
|
560 alu_ext,\
|
|
|
561 alu_imm,\
|
|
|
562 alu_sreg,\
|
|
|
563 alu_shift_imm,\
|
|
|
564 alu_shift_reg,\
|
|
|
565 alu_dsp_reg,\
|
|
|
566 alus_ext,\
|
|
|
567 alus_imm,\
|
|
|
568 alus_sreg,\
|
|
|
569 alus_shift_imm,\
|
|
|
570 alus_shift_reg,\
|
|
|
571 bfm,\
|
|
|
572 bfx,\
|
|
|
573 block,\
|
|
|
574 branch,\
|
|
|
575 call,\
|
|
|
576 clz,\
|
|
|
577 no_insn,\
|
|
|
578 csel,\
|
|
|
579 crc,\
|
|
|
580 extend,\
|
|
|
581 f_cvt,\
|
|
|
582 f_cvtf2i,\
|
|
|
583 f_cvti2f,\
|
|
|
584 f_flag,\
|
|
|
585 f_loadd,\
|
|
|
586 f_loads,\
|
|
|
587 f_mcr,\
|
|
|
588 f_mcrr,\
|
|
|
589 f_minmaxd,\
|
|
|
590 f_minmaxs,\
|
|
|
591 f_mrc,\
|
|
|
592 f_mrrc,\
|
|
|
593 f_rintd,\
|
|
|
594 f_rints,\
|
|
|
595 f_stored,\
|
|
|
596 f_stores,\
|
|
|
597 faddd,\
|
|
|
598 fadds,\
|
|
|
599 fccmpd,\
|
|
|
600 fccmps,\
|
|
|
601 fcmpd,\
|
|
|
602 fcmps,\
|
|
|
603 fconstd,\
|
|
|
604 fconsts,\
|
|
|
605 fcsel,\
|
|
|
606 fdivd,\
|
|
|
607 fdivs,\
|
|
|
608 ffarithd,\
|
|
|
609 ffariths,\
|
|
|
610 ffmad,\
|
|
|
611 ffmas,\
|
|
|
612 float,\
|
|
|
613 fmacd,\
|
|
|
614 fmacs,\
|
|
|
615 fmov,\
|
|
|
616 fmuld,\
|
|
|
617 fmuls,\
|
|
|
618 fsqrts,\
|
|
|
619 fsqrtd,\
|
|
|
620 load_acq,\
|
|
|
621 load_byte,\
|
|
|
622 load_4,\
|
|
|
623 load_8,\
|
|
|
624 load_12,\
|
|
|
625 load_16,\
|
|
|
626 logic_imm,\
|
|
|
627 logic_reg,\
|
|
|
628 logic_shift_imm,\
|
|
|
629 logic_shift_reg,\
|
|
|
630 logics_imm,\
|
|
|
631 logics_reg,\
|
|
|
632 logics_shift_imm,\
|
|
|
633 logics_shift_reg,\
|
|
|
634 mla,\
|
|
|
635 mlas,\
|
|
|
636 mov_imm,\
|
|
|
637 mov_reg,\
|
|
|
638 mov_shift,\
|
|
|
639 mov_shift_reg,\
|
|
|
640 mrs,\
|
|
|
641 mul,\
|
|
|
642 muls,\
|
|
|
643 multiple,\
|
|
|
644 mvn_imm,\
|
|
|
645 mvn_reg,\
|
|
|
646 mvn_shift,\
|
|
|
647 mvn_shift_reg,\
|
|
|
648 nop,\
|
|
|
649 rbit,\
|
|
|
650 rev,\
|
|
|
651 rotate_imm,\
|
|
|
652 sdiv,\
|
|
|
653 shift_imm,\
|
|
|
654 shift_reg,\
|
|
|
655 smlad,\
|
|
|
656 smladx,\
|
|
|
657 smlal,\
|
|
|
658 smlald,\
|
|
|
659 smlals,\
|
|
|
660 smlalxy,\
|
|
|
661 smlawx,\
|
|
|
662 smlawy,\
|
|
|
663 smlaxy,\
|
|
|
664 smlsd,\
|
|
|
665 smlsdx,\
|
|
|
666 smlsld,\
|
|
|
667 smmla,\
|
|
|
668 smmul,\
|
|
|
669 smmulr,\
|
|
|
670 smuad,\
|
|
|
671 smuadx,\
|
|
|
672 smull,\
|
|
|
673 smulls,\
|
|
|
674 smulwy,\
|
|
|
675 smulxy,\
|
|
|
676 smusd,\
|
|
|
677 smusdx,\
|
|
|
678 store_rel,\
|
|
|
679 store_4,\
|
|
|
680 store_8,\
|
|
|
681 store_12,\
|
|
|
682 store_16,\
|
|
|
683 trap,\
|
|
|
684 udiv,\
|
|
|
685 umaal,\
|
|
|
686 umlal,\
|
|
|
687 umlals,\
|
|
|
688 umull,\
|
|
|
689 umulls,\
|
|
|
690 untyped,\
|
|
|
691 wmmx_tandc,\
|
|
|
692 wmmx_tbcst,\
|
|
|
693 wmmx_textrc,\
|
|
|
694 wmmx_textrm,\
|
|
|
695 wmmx_tinsr,\
|
|
|
696 wmmx_tmcr,\
|
|
|
697 wmmx_tmcrr,\
|
|
|
698 wmmx_tmia,\
|
|
|
699 wmmx_tmiaph,\
|
|
|
700 wmmx_tmiaxy,\
|
|
|
701 wmmx_tmrc,\
|
|
|
702 wmmx_tmrrc,\
|
|
|
703 wmmx_tmovmsk,\
|
|
|
704 wmmx_torc,\
|
|
|
705 wmmx_torvsc,\
|
|
|
706 wmmx_wabs,\
|
|
|
707 wmmx_wabsdiff,\
|
|
|
708 wmmx_wacc,\
|
|
|
709 wmmx_wadd,\
|
|
|
710 wmmx_waddbhus,\
|
|
|
711 wmmx_waddsubhx,\
|
|
|
712 wmmx_waligni,\
|
|
|
713 wmmx_walignr,\
|
|
|
714 wmmx_wand,\
|
|
|
715 wmmx_wandn,\
|
|
|
716 wmmx_wavg2,\
|
|
|
717 wmmx_wavg4,\
|
|
|
718 wmmx_wcmpeq,\
|
|
|
719 wmmx_wcmpgt,\
|
|
|
720 wmmx_wmac,\
|
|
|
721 wmmx_wmadd,\
|
|
|
722 wmmx_wmax,\
|
|
|
723 wmmx_wmerge,\
|
|
|
724 wmmx_wmiawxy,\
|
|
|
725 wmmx_wmiaxy,\
|
|
|
726 wmmx_wmin,\
|
|
|
727 wmmx_wmov,\
|
|
|
728 wmmx_wmul,\
|
|
|
729 wmmx_wmulw,\
|
|
|
730 wmmx_wldr,\
|
|
|
731 wmmx_wor,\
|
|
|
732 wmmx_wpack,\
|
|
|
733 wmmx_wqmiaxy,\
|
|
|
734 wmmx_wqmulm,\
|
|
|
735 wmmx_wqmulwm,\
|
|
|
736 wmmx_wror,\
|
|
|
737 wmmx_wsad,\
|
|
|
738 wmmx_wshufh,\
|
|
|
739 wmmx_wsll,\
|
|
|
740 wmmx_wsra,\
|
|
|
741 wmmx_wsrl,\
|
|
|
742 wmmx_wstr,\
|
|
|
743 wmmx_wsub,\
|
|
|
744 wmmx_wsubaddhx,\
|
|
|
745 wmmx_wunpckeh,\
|
|
|
746 wmmx_wunpckel,\
|
|
|
747 wmmx_wunpckih,\
|
|
|
748 wmmx_wunpckil,\
|
|
|
749 wmmx_wxor,\
|
|
|
750 \
|
|
|
751 neon_add,\
|
|
|
752 neon_add_q,\
|
|
|
753 neon_add_widen,\
|
|
|
754 neon_add_long,\
|
|
|
755 neon_qadd,\
|
|
|
756 neon_qadd_q,\
|
|
|
757 neon_add_halve,\
|
|
|
758 neon_add_halve_q,\
|
|
|
759 neon_add_halve_narrow_q,\
|
|
|
760 \
|
|
|
761 neon_sub,\
|
|
|
762 neon_sub_q,\
|
|
|
763 neon_sub_widen,\
|
|
|
764 neon_sub_long,\
|
|
|
765 neon_qsub,\
|
|
|
766 neon_qsub_q,\
|
|
|
767 neon_sub_halve,\
|
|
|
768 neon_sub_halve_q,\
|
|
|
769 neon_sub_halve_narrow_q,\
|
|
|
770 \
|
|
145
|
771 neon_fcadd,\
|
|
|
772 neon_fcmla,\
|
|
|
773 \
|
|
111
|
774 neon_abs,\
|
|
|
775 neon_abs_q,\
|
|
|
776 neon_dot,\
|
|
|
777 neon_dot_q,\
|
|
|
778 neon_neg,\
|
|
|
779 neon_neg_q,\
|
|
|
780 neon_qneg,\
|
|
|
781 neon_qneg_q,\
|
|
|
782 neon_qabs,\
|
|
|
783 neon_qabs_q,\
|
|
|
784 neon_abd,\
|
|
|
785 neon_abd_q,\
|
|
|
786 neon_abd_long,\
|
|
|
787 \
|
|
|
788 neon_minmax,\
|
|
|
789 neon_minmax_q,\
|
|
|
790 neon_compare,\
|
|
|
791 neon_compare_q,\
|
|
|
792 neon_compare_zero,\
|
|
|
793 neon_compare_zero_q,\
|
|
|
794 \
|
|
|
795 neon_arith_acc,\
|
|
|
796 neon_arith_acc_q,\
|
|
|
797 neon_reduc_add,\
|
|
|
798 neon_reduc_add_q,\
|
|
|
799 neon_reduc_add_long,\
|
|
|
800 neon_reduc_add_acc,\
|
|
|
801 neon_reduc_add_acc_q,\
|
|
|
802 neon_reduc_minmax,\
|
|
|
803 neon_reduc_minmax_q,\
|
|
|
804 neon_logic,\
|
|
|
805 neon_logic_q,\
|
|
|
806 neon_tst,\
|
|
|
807 neon_tst_q,\
|
|
|
808 \
|
|
|
809 neon_shift_imm,\
|
|
|
810 neon_shift_imm_q,\
|
|
|
811 neon_shift_imm_narrow_q,\
|
|
|
812 neon_shift_imm_long,\
|
|
|
813 neon_shift_reg,\
|
|
|
814 neon_shift_reg_q,\
|
|
|
815 neon_shift_acc,\
|
|
|
816 neon_shift_acc_q,\
|
|
|
817 neon_sat_shift_imm,\
|
|
|
818 neon_sat_shift_imm_q,\
|
|
|
819 neon_sat_shift_imm_narrow_q,\
|
|
|
820 neon_sat_shift_reg,\
|
|
|
821 neon_sat_shift_reg_q,\
|
|
|
822 \
|
|
|
823 neon_ins,\
|
|
|
824 neon_ins_q,\
|
|
|
825 neon_move,\
|
|
|
826 neon_move_q,\
|
|
|
827 neon_move_narrow_q,\
|
|
|
828 neon_permute,\
|
|
|
829 neon_permute_q,\
|
|
|
830 neon_zip,\
|
|
|
831 neon_zip_q,\
|
|
|
832 neon_tbl1,\
|
|
|
833 neon_tbl1_q,\
|
|
|
834 neon_tbl2,\
|
|
|
835 neon_tbl2_q,\
|
|
|
836 neon_tbl3,\
|
|
|
837 neon_tbl3_q,\
|
|
|
838 neon_tbl4,\
|
|
|
839 neon_tbl4_q,\
|
|
|
840 \
|
|
|
841 neon_bsl,\
|
|
|
842 neon_bsl_q,\
|
|
|
843 neon_cls,\
|
|
|
844 neon_cls_q,\
|
|
|
845 neon_cnt,\
|
|
|
846 neon_cnt_q,\
|
|
|
847 neon_dup,\
|
|
|
848 neon_dup_q,\
|
|
|
849 neon_ext,\
|
|
|
850 neon_ext_q,\
|
|
|
851 neon_rbit,\
|
|
|
852 neon_rbit_q,\
|
|
|
853 neon_rev,\
|
|
|
854 neon_rev_q,\
|
|
|
855 \
|
|
|
856 neon_mul_b,\
|
|
|
857 neon_mul_b_q,\
|
|
|
858 neon_mul_h,\
|
|
|
859 neon_mul_h_q,\
|
|
|
860 neon_mul_s,\
|
|
|
861 neon_mul_s_q,\
|
|
|
862 neon_mul_b_long,\
|
|
|
863 neon_mul_h_long,\
|
|
|
864 neon_mul_s_long,\
|
|
|
865 neon_mul_d_long,\
|
|
|
866 neon_mul_h_scalar,\
|
|
|
867 neon_mul_h_scalar_q,\
|
|
|
868 neon_mul_s_scalar,\
|
|
|
869 neon_mul_s_scalar_q,\
|
|
|
870 neon_mul_h_scalar_long,\
|
|
|
871 neon_mul_s_scalar_long,\
|
|
|
872 \
|
|
|
873 neon_sat_mul_b,\
|
|
|
874 neon_sat_mul_b_q,\
|
|
|
875 neon_sat_mul_h,\
|
|
|
876 neon_sat_mul_h_q,\
|
|
|
877 neon_sat_mul_s,\
|
|
|
878 neon_sat_mul_s_q,\
|
|
|
879 neon_sat_mul_b_long,\
|
|
|
880 neon_sat_mul_h_long,\
|
|
|
881 neon_sat_mul_s_long,\
|
|
|
882 neon_sat_mul_h_scalar,\
|
|
|
883 neon_sat_mul_h_scalar_q,\
|
|
|
884 neon_sat_mul_s_scalar,\
|
|
|
885 neon_sat_mul_s_scalar_q,\
|
|
|
886 neon_sat_mul_h_scalar_long,\
|
|
|
887 neon_sat_mul_s_scalar_long,\
|
|
|
888 \
|
|
|
889 neon_mla_b,\
|
|
|
890 neon_mla_b_q,\
|
|
|
891 neon_mla_h,\
|
|
|
892 neon_mla_h_q,\
|
|
|
893 neon_mla_s,\
|
|
|
894 neon_mla_s_q,\
|
|
|
895 neon_mla_b_long,\
|
|
|
896 neon_mla_h_long,\
|
|
|
897 neon_mla_s_long,\
|
|
|
898 neon_mla_h_scalar,\
|
|
|
899 neon_mla_h_scalar_q,\
|
|
|
900 neon_mla_s_scalar,\
|
|
|
901 neon_mla_s_scalar_q,\
|
|
|
902 neon_mla_h_scalar_long,\
|
|
|
903 neon_mla_s_scalar_long,\
|
|
|
904 \
|
|
|
905 neon_sat_mla_b_long,\
|
|
|
906 neon_sat_mla_h_long,\
|
|
|
907 neon_sat_mla_s_long,\
|
|
|
908 neon_sat_mla_h_scalar_long,\
|
|
|
909 neon_sat_mla_s_scalar_long,\
|
|
|
910 \
|
|
|
911 neon_to_gp,\
|
|
|
912 neon_to_gp_q,\
|
|
|
913 neon_from_gp,\
|
|
|
914 neon_from_gp_q,\
|
|
|
915 \
|
|
|
916 neon_ldr,\
|
|
|
917 neon_ldp,\
|
|
|
918 neon_ldp_q,\
|
|
|
919 neon_load1_1reg,\
|
|
|
920 neon_load1_1reg_q,\
|
|
|
921 neon_load1_2reg,\
|
|
|
922 neon_load1_2reg_q,\
|
|
|
923 neon_load1_3reg,\
|
|
|
924 neon_load1_3reg_q,\
|
|
|
925 neon_load1_4reg,\
|
|
|
926 neon_load1_4reg_q,\
|
|
|
927 neon_load1_all_lanes,\
|
|
|
928 neon_load1_all_lanes_q,\
|
|
|
929 neon_load1_one_lane,\
|
|
|
930 neon_load1_one_lane_q,\
|
|
|
931 \
|
|
|
932 neon_load2_2reg,\
|
|
|
933 neon_load2_2reg_q,\
|
|
|
934 neon_load2_4reg,\
|
|
|
935 neon_load2_4reg_q,\
|
|
|
936 neon_load2_all_lanes,\
|
|
|
937 neon_load2_all_lanes_q,\
|
|
|
938 neon_load2_one_lane,\
|
|
|
939 neon_load2_one_lane_q,\
|
|
|
940 \
|
|
|
941 neon_load3_3reg,\
|
|
|
942 neon_load3_3reg_q,\
|
|
|
943 neon_load3_all_lanes,\
|
|
|
944 neon_load3_all_lanes_q,\
|
|
|
945 neon_load3_one_lane,\
|
|
|
946 neon_load3_one_lane_q,\
|
|
|
947 \
|
|
|
948 neon_load4_4reg,\
|
|
|
949 neon_load4_4reg_q,\
|
|
|
950 neon_load4_all_lanes,\
|
|
|
951 neon_load4_all_lanes_q,\
|
|
|
952 neon_load4_one_lane,\
|
|
|
953 neon_load4_one_lane_q,\
|
|
|
954 \
|
|
|
955 neon_str,\
|
|
|
956 neon_stp,\
|
|
|
957 neon_stp_q,\
|
|
|
958 neon_store1_1reg,\
|
|
|
959 neon_store1_1reg_q,\
|
|
|
960 neon_store1_2reg,\
|
|
|
961 neon_store1_2reg_q,\
|
|
|
962 neon_store1_3reg,\
|
|
|
963 neon_store1_3reg_q,\
|
|
|
964 neon_store1_4reg,\
|
|
|
965 neon_store1_4reg_q,\
|
|
|
966 neon_store1_one_lane,\
|
|
|
967 neon_store1_one_lane_q,\
|
|
|
968 \
|
|
|
969 neon_store2_2reg,\
|
|
|
970 neon_store2_2reg_q,\
|
|
|
971 neon_store2_4reg,\
|
|
|
972 neon_store2_4reg_q,\
|
|
|
973 neon_store2_one_lane,\
|
|
|
974 neon_store2_one_lane_q,\
|
|
|
975 \
|
|
|
976 neon_store3_3reg,\
|
|
|
977 neon_store3_3reg_q,\
|
|
|
978 neon_store3_one_lane,\
|
|
|
979 neon_store3_one_lane_q,\
|
|
|
980 \
|
|
|
981 neon_store4_4reg,\
|
|
|
982 neon_store4_4reg_q,\
|
|
|
983 neon_store4_one_lane,\
|
|
|
984 neon_store4_one_lane_q,\
|
|
|
985 \
|
|
|
986 neon_fp_abs_s,\
|
|
|
987 neon_fp_abs_s_q,\
|
|
|
988 neon_fp_abs_d,\
|
|
|
989 neon_fp_abs_d_q,\
|
|
|
990 neon_fp_neg_s,\
|
|
|
991 neon_fp_neg_s_q,\
|
|
|
992 neon_fp_neg_d,\
|
|
|
993 neon_fp_neg_d_q,\
|
|
|
994 \
|
|
|
995 neon_fp_abd_s,\
|
|
|
996 neon_fp_abd_s_q,\
|
|
|
997 neon_fp_abd_d,\
|
|
|
998 neon_fp_abd_d_q,\
|
|
|
999 neon_fp_addsub_s,\
|
|
|
1000 neon_fp_addsub_s_q,\
|
|
|
1001 neon_fp_addsub_d,\
|
|
|
1002 neon_fp_addsub_d_q,\
|
|
|
1003 neon_fp_compare_s,\
|
|
|
1004 neon_fp_compare_s_q,\
|
|
|
1005 neon_fp_compare_d,\
|
|
|
1006 neon_fp_compare_d_q,\
|
|
|
1007 neon_fp_minmax_s,\
|
|
|
1008 neon_fp_minmax_s_q,\
|
|
|
1009 neon_fp_minmax_d,\
|
|
|
1010 neon_fp_minmax_d_q,\
|
|
|
1011 \
|
|
|
1012 neon_fp_reduc_add_s,\
|
|
|
1013 neon_fp_reduc_add_s_q,\
|
|
|
1014 neon_fp_reduc_add_d,\
|
|
|
1015 neon_fp_reduc_add_d_q,\
|
|
|
1016 neon_fp_reduc_minmax_s,\
|
|
|
1017 neon_fp_reduc_minmax_s_q,\
|
|
|
1018 neon_fp_reduc_minmax_d,\
|
|
|
1019 neon_fp_reduc_minmax_d_q,\
|
|
|
1020 \
|
|
|
1021 neon_fp_cvt_narrow_s_q,\
|
|
|
1022 neon_fp_cvt_narrow_d_q,\
|
|
|
1023 neon_fp_cvt_widen_h,\
|
|
|
1024 neon_fp_cvt_widen_s,\
|
|
|
1025 \
|
|
|
1026 neon_fp_to_int_s,\
|
|
|
1027 neon_fp_to_int_s_q,\
|
|
|
1028 neon_fp_to_int_d,\
|
|
|
1029 neon_fp_to_int_d_q,\
|
|
|
1030 neon_int_to_fp_s,\
|
|
|
1031 neon_int_to_fp_s_q,\
|
|
|
1032 neon_int_to_fp_d,\
|
|
|
1033 neon_int_to_fp_d_q,\
|
|
|
1034 neon_fp_round_s,\
|
|
|
1035 neon_fp_round_s_q,\
|
|
|
1036 neon_fp_round_d,\
|
|
|
1037 neon_fp_round_d_q,\
|
|
|
1038 \
|
|
|
1039 neon_fp_recpe_s,\
|
|
|
1040 neon_fp_recpe_s_q,\
|
|
|
1041 neon_fp_recpe_d,\
|
|
|
1042 neon_fp_recpe_d_q,\
|
|
|
1043 neon_fp_recps_s,\
|
|
|
1044 neon_fp_recps_s_q,\
|
|
|
1045 neon_fp_recps_d,\
|
|
|
1046 neon_fp_recps_d_q,\
|
|
|
1047 neon_fp_recpx_s,\
|
|
|
1048 neon_fp_recpx_s_q,\
|
|
|
1049 neon_fp_recpx_d,\
|
|
|
1050 neon_fp_recpx_d_q,\
|
|
|
1051 \
|
|
|
1052 neon_fp_rsqrte_s,\
|
|
|
1053 neon_fp_rsqrte_s_q,\
|
|
|
1054 neon_fp_rsqrte_d,\
|
|
|
1055 neon_fp_rsqrte_d_q,\
|
|
|
1056 neon_fp_rsqrts_s,\
|
|
|
1057 neon_fp_rsqrts_s_q,\
|
|
|
1058 neon_fp_rsqrts_d,\
|
|
|
1059 neon_fp_rsqrts_d_q,\
|
|
|
1060 \
|
|
|
1061 neon_fp_mul_s,\
|
|
|
1062 neon_fp_mul_s_q,\
|
|
|
1063 neon_fp_mul_s_scalar,\
|
|
|
1064 neon_fp_mul_s_scalar_q,\
|
|
|
1065 neon_fp_mul_d,\
|
|
|
1066 neon_fp_mul_d_q,\
|
|
|
1067 neon_fp_mul_d_scalar_q,\
|
|
|
1068 \
|
|
|
1069 neon_fp_mla_s,\
|
|
|
1070 neon_fp_mla_s_q,\
|
|
|
1071 neon_fp_mla_s_scalar,\
|
|
|
1072 neon_fp_mla_s_scalar_q,\
|
|
|
1073 neon_fp_mla_d,\
|
|
|
1074 neon_fp_mla_d_q,\
|
|
|
1075 neon_fp_mla_d_scalar_q,\
|
|
|
1076 \
|
|
|
1077 neon_fp_sqrt_s,\
|
|
|
1078 neon_fp_sqrt_s_q,\
|
|
|
1079 neon_fp_sqrt_d,\
|
|
|
1080 neon_fp_sqrt_d_q,\
|
|
|
1081 neon_fp_div_s,\
|
|
|
1082 neon_fp_div_s_q,\
|
|
|
1083 neon_fp_div_d,\
|
|
|
1084 neon_fp_div_d_q,\
|
|
|
1085 \
|
|
|
1086 crypto_aese,\
|
|
|
1087 crypto_aesmc,\
|
|
|
1088 crypto_sha1_xor,\
|
|
|
1089 crypto_sha1_fast,\
|
|
|
1090 crypto_sha1_slow,\
|
|
|
1091 crypto_sha256_fast,\
|
|
|
1092 crypto_sha256_slow,\
|
|
|
1093 crypto_pmull,\
|
|
131
|
1094 crypto_sha512,\
|
|
|
1095 crypto_sha3,\
|
|
|
1096 crypto_sm3,\
|
|
|
1097 crypto_sm4,\
|
|
145
|
1098 coproc,\
|
|
|
1099 tme,\
|
|
|
1100 memtag"
|
|
111
|
1101 (const_string "untyped"))
|
|
|
1102
|
|
|
1103 ; Is this an (integer side) multiply with a 32-bit (or smaller) result?
|
|
|
1104 (define_attr "mul32" "no,yes"
|
|
|
1105 (if_then_else
|
|
|
1106 (eq_attr "type"
|
|
|
1107 "smulxy,smlaxy,smulwy,smlawx,mul,muls,mla,mlas,smlawy,smuad,smuadx,\
|
|
|
1108 smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,smlald,smlsld")
|
|
|
1109 (const_string "yes")
|
|
|
1110 (const_string "no")))
|
|
|
1111
|
|
145
|
1112 ; Is this an (integer side) widening multiply with a 64-bit result?
|
|
|
1113 (define_attr "widen_mul64" "no,yes"
|
|
111
|
1114 (if_then_else
|
|
|
1115 (eq_attr "type"
|
|
|
1116 "smlalxy,umull,umulls,umaal,umlal,umlals,smull,smulls,smlal,smlals")
|
|
|
1117 (const_string "yes")
|
|
|
1118 (const_string "no")))
|
|
|
1119
|
|
|
1120 ; YES if the "type" attribute assigned to the insn denotes an
|
|
|
1121 ; Advanced SIMD instruction, NO otherwise.
|
|
|
1122 (define_attr "is_neon_type" "yes,no"
|
|
|
1123 (if_then_else (eq_attr "type"
|
|
|
1124 "neon_add, neon_add_q, neon_add_widen, neon_add_long,\
|
|
|
1125 neon_qadd, neon_qadd_q, neon_add_halve, neon_add_halve_q,\
|
|
|
1126 neon_add_halve_narrow_q,\
|
|
|
1127 neon_sub, neon_sub_q, neon_sub_widen, neon_sub_long, neon_qsub,\
|
|
|
1128 neon_qsub_q, neon_sub_halve, neon_sub_halve_q,\
|
|
|
1129 neon_sub_halve_narrow_q,\
|
|
|
1130 neon_abs, neon_abs_q, neon_dot, neon_dot_q, neon_neg, neon_neg_q,\
|
|
|
1131 neon_qneg, neon_qneg_q, neon_qabs, neon_qabs_q, neon_abd, neon_abd_q,\
|
|
|
1132 neon_abd_long, neon_minmax, neon_minmax_q, neon_compare,\
|
|
|
1133 neon_compare_q, neon_compare_zero, neon_compare_zero_q,\
|
|
|
1134 neon_arith_acc, neon_arith_acc_q, neon_reduc_add,\
|
|
|
1135 neon_reduc_add_q, neon_reduc_add_long, neon_reduc_add_acc,\
|
|
|
1136 neon_reduc_add_acc_q, neon_reduc_minmax, neon_reduc_minmax_q,\
|
|
|
1137 neon_logic, neon_logic_q, neon_tst, neon_tst_q,\
|
|
|
1138 neon_shift_imm, neon_shift_imm_q, neon_shift_imm_narrow_q,\
|
|
|
1139 neon_shift_imm_long, neon_shift_reg, neon_shift_reg_q,\
|
|
|
1140 neon_shift_acc, neon_shift_acc_q, neon_sat_shift_imm,\
|
|
|
1141 neon_sat_shift_imm_q, neon_sat_shift_imm_narrow_q,\
|
|
|
1142 neon_sat_shift_reg, neon_sat_shift_reg_q,\
|
|
|
1143 neon_ins, neon_ins_q, neon_move, neon_move_q, neon_move_narrow_q,\
|
|
|
1144 neon_permute, neon_permute_q, neon_zip, neon_zip_q, neon_tbl1,\
|
|
|
1145 neon_tbl1_q, neon_tbl2, neon_tbl2_q, neon_tbl3, neon_tbl3_q,\
|
|
|
1146 neon_tbl4, neon_tbl4_q, neon_bsl, neon_bsl_q, neon_cls,\
|
|
|
1147 neon_cls_q, neon_cnt, neon_cnt_q, neon_dup, neon_dup_q,\
|
|
|
1148 neon_ext, neon_ext_q, neon_rbit, neon_rbit_q,\
|
|
|
1149 neon_rev, neon_rev_q, neon_mul_b, neon_mul_b_q, neon_mul_h,\
|
|
|
1150 neon_mul_h_q, neon_mul_s, neon_mul_s_q, neon_mul_b_long,\
|
|
|
1151 neon_mul_h_long, neon_mul_s_long, neon_mul_d_long, neon_mul_h_scalar,\
|
|
|
1152 neon_mul_h_scalar_q, neon_mul_s_scalar, neon_mul_s_scalar_q,\
|
|
|
1153 neon_mul_h_scalar_long, neon_mul_s_scalar_long, neon_sat_mul_b,\
|
|
|
1154 neon_sat_mul_b_q, neon_sat_mul_h, neon_sat_mul_h_q,\
|
|
|
1155 neon_sat_mul_s, neon_sat_mul_s_q, neon_sat_mul_b_long,\
|
|
|
1156 neon_sat_mul_h_long, neon_sat_mul_s_long, neon_sat_mul_h_scalar,\
|
|
|
1157 neon_sat_mul_h_scalar_q, neon_sat_mul_s_scalar,\
|
|
|
1158 neon_sat_mul_s_scalar_q, neon_sat_mul_h_scalar_long,\
|
|
|
1159 neon_sat_mul_s_scalar_long, neon_mla_b, neon_mla_b_q, neon_mla_h,\
|
|
|
1160 neon_mla_h_q, neon_mla_s, neon_mla_s_q, neon_mla_b_long,\
|
|
|
1161 neon_mla_h_long, neon_mla_s_long, neon_mla_h_scalar,\
|
|
|
1162 neon_mla_h_scalar_q, neon_mla_s_scalar, neon_mla_s_scalar_q,\
|
|
|
1163 neon_mla_h_scalar_long, neon_mla_s_scalar_long,\
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1164 neon_sat_mla_b_long, neon_sat_mla_h_long,\
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1165 neon_sat_mla_s_long, neon_sat_mla_h_scalar_long,\
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1166 neon_sat_mla_s_scalar_long,\
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1167 neon_to_gp, neon_to_gp_q, neon_from_gp, neon_from_gp_q,\
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1168 neon_ldr, neon_ldp, neon_ldp_q,\
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1169 neon_load1_1reg, neon_load1_1reg_q, neon_load1_2reg,\
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1170 neon_load1_2reg_q, neon_load1_3reg, neon_load1_3reg_q,\
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1171 neon_load1_4reg, neon_load1_4reg_q, neon_load1_all_lanes,\
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1172 neon_load1_all_lanes_q, neon_load1_one_lane, neon_load1_one_lane_q,\
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1173 neon_load2_2reg, neon_load2_2reg_q, neon_load2_4reg,\
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1174 neon_load2_4reg_q, neon_load2_all_lanes, neon_load2_all_lanes_q,\
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1175 neon_load2_one_lane, neon_load2_one_lane_q,\
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1176 neon_load3_3reg, neon_load3_3reg_q, neon_load3_all_lanes,\
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1177 neon_load3_all_lanes_q, neon_load3_one_lane, neon_load3_one_lane_q,\
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1178 neon_load4_4reg, neon_load4_4reg_q, neon_load4_all_lanes,\
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1179 neon_load4_all_lanes_q, neon_load4_one_lane, neon_load4_one_lane_q,\
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1180 neon_str, neon_stp, neon_stp_q,\
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1181 neon_store1_1reg, neon_store1_1reg_q, neon_store1_2reg,\
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1182 neon_store1_2reg_q, neon_store1_3reg, neon_store1_3reg_q,\
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1183 neon_store1_4reg, neon_store1_4reg_q, neon_store1_one_lane,\
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1184 neon_store1_one_lane_q, neon_store2_2reg, neon_store2_2reg_q,\
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1185 neon_store2_4reg, neon_store2_4reg_q, neon_store2_one_lane,\
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1186 neon_store2_one_lane_q, neon_store3_3reg, neon_store3_3reg_q,\
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1187 neon_store3_one_lane, neon_store3_one_lane_q, neon_store4_4reg,\
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1188 neon_store4_4reg_q, neon_store4_one_lane, neon_store4_one_lane_q,\
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1189 neon_fp_abd_s, neon_fp_abd_s_q, neon_fp_abd_d, neon_fp_abd_d_q,\
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1190 neon_fp_abs_s, neon_fp_abs_s_q, neon_fp_abs_d, neon_fp_abs_d_q,\
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1191 neon_fp_addsub_s, neon_fp_addsub_s_q, neon_fp_addsub_d,\
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1192 neon_fp_addsub_d_q, neon_fp_compare_s, neon_fp_compare_s_q,\
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1193 neon_fp_compare_d, neon_fp_compare_d_q, neon_fp_minmax_s,\
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1194 neon_fp_minmax_s_q, neon_fp_minmax_d, neon_fp_minmax_d_q,\
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1195 neon_fp_neg_s, neon_fp_neg_s_q, neon_fp_neg_d, neon_fp_neg_d_q,\
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1196 neon_fp_reduc_add_s, neon_fp_reduc_add_s_q, neon_fp_reduc_add_d,\
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1197 neon_fp_reduc_add_d_q, neon_fp_reduc_minmax_s,
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1198 neon_fp_reduc_minmax_s_q, neon_fp_reduc_minmax_d,\
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1199 neon_fp_reduc_minmax_d_q,\
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1200 neon_fp_cvt_narrow_s_q, neon_fp_cvt_narrow_d_q,\
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1201 neon_fp_cvt_widen_h, neon_fp_cvt_widen_s, neon_fp_to_int_s,\
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1202 neon_fp_to_int_s_q, neon_int_to_fp_s, neon_int_to_fp_s_q,\
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1203 neon_fp_to_int_d, neon_fp_to_int_d_q,\
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1204 neon_int_to_fp_d, neon_int_to_fp_d_q,\
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1205 neon_fp_round_s, neon_fp_round_s_q, neon_fp_recpe_s,\
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1206 neon_fp_recpe_s_q,\
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1207 neon_fp_recpe_d, neon_fp_recpe_d_q, neon_fp_recps_s,\
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1208 neon_fp_recps_s_q, neon_fp_recps_d, neon_fp_recps_d_q,\
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1209 neon_fp_recpx_s, neon_fp_recpx_s_q, neon_fp_recpx_d,\
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1210 neon_fp_recpx_d_q, neon_fp_rsqrte_s, neon_fp_rsqrte_s_q,\
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1211 neon_fp_rsqrte_d, neon_fp_rsqrte_d_q, neon_fp_rsqrts_s,\
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1212 neon_fp_rsqrts_s_q, neon_fp_rsqrts_d, neon_fp_rsqrts_d_q,\
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1213 neon_fp_mul_s, neon_fp_mul_s_q, neon_fp_mul_s_scalar,\
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1214 neon_fp_mul_s_scalar_q, neon_fp_mul_d, neon_fp_mul_d_q,\
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1215 neon_fp_mul_d_scalar_q, neon_fp_mla_s, neon_fp_mla_s_q,\
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1216 neon_fp_mla_s_scalar, neon_fp_mla_s_scalar_q, neon_fp_mla_d,\
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1217 neon_fp_mla_d_q, neon_fp_mla_d_scalar_q, neon_fp_sqrt_s,\
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1218 neon_fp_sqrt_s_q, neon_fp_sqrt_d, neon_fp_sqrt_d_q,\
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1219 neon_fp_div_s, neon_fp_div_s_q, neon_fp_div_d, neon_fp_div_d_q, crypto_aese,\
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1220 crypto_aesmc, crypto_sha1_xor, crypto_sha1_fast, crypto_sha1_slow,\
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1221 crypto_sha256_fast, crypto_sha256_slow")
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1222 (const_string "yes")
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1223 (const_string "no")))
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145
|
1224
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1225 (define_insn_reservation "no_reservation" 0
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1226 (eq_attr "type" "no_insn")
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1227 "nothing")
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