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1 ;; Slivermont(SLM) Scheduling
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2 ;; Copyright (C) 2009-2020 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19 ;;
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20 ;; Silvermont has 2 out-of-order IEC, 2 in-order FEC and 1 in-order MEC.
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21
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22
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23 (define_automaton "slm")
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24
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25 ;; EU: Execution Unit
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26 ;; Silvermont EUs are connected by port 0 or port 1.
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27
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28 ;; SLM has two ports: port 0 and port 1 connecting to all execution units
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29 (define_cpu_unit "slm-port-0,slm-port-1" "slm")
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30
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31 (define_cpu_unit "slm-ieu-0, slm-ieu-1,
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32 slm-imul, slm-feu-0, slm-feu-1"
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33 "slm")
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34
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35 (define_reservation "slm-all-ieu" "(slm-ieu-0 + slm-ieu-1 + slm-imul)")
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36 (define_reservation "slm-all-feu" "(slm-feu-0 + slm-feu-1)")
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37 (define_reservation "slm-all-eu" "(slm-all-ieu + slm-all-feu)")
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38 (define_reservation "slm-fp-0" "(slm-port-0 + slm-feu-0)")
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39
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40 ;; Some EUs have duplicated copied and can be accessed via either
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41 ;; port 0 or port 1
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42 ;; (define_reservation "slm-port-either" "(slm-port-0 | slm-port-1)"
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43 (define_reservation "slm-port-dual" "(slm-port-0 + slm-port-1)")
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44
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45 ;;; fmul insn can have 4 or 5 cycles latency
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46 (define_reservation "slm-fmul-5c"
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47 "(slm-port-0 + slm-feu-0), slm-feu-0, nothing*3")
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48 (define_reservation "slm-fmul-4c" "(slm-port-0 + slm-feu-0), nothing*3")
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49
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50 ;;; fadd can has 3 cycles latency depends on instruction forms
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51 (define_reservation "slm-fadd-3c" "(slm-port-1 + slm-feu-1), nothing*2")
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52 (define_reservation "slm-fadd-4c"
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53 "(slm-port-1 + slm-feu-1), slm-feu-1, nothing*2")
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54
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55 ;;; imul insn has 3 cycles latency for SI operands
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56 (define_reservation "slm-imul-32"
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57 "(slm-port-1 + slm-imul), nothing*2")
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58 (define_reservation "slm-imul-mem-32"
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59 "(slm-port-1 + slm-imul + slm-port-0), nothing*2")
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60 ;;; imul has 4 cycles latency for DI operands with 1/2 tput
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61 (define_reservation "slm-imul-64"
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62 "(slm-port-1 + slm-imul), slm-imul, nothing*2")
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63
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64 ;;; dual-execution instructions can have 1,2,4,5 cycles latency depends on
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65 ;;; instruction forms
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66 (define_reservation "slm-dual-1c" "(slm-port-dual + slm-all-eu)")
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67 (define_reservation "slm-dual-2c"
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68 "(slm-port-dual + slm-all-eu, nothing)")
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69
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70 ;;; Most of simple ALU instructions have 1 cycle latency. Some of them
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71 ;;; issue in port 0, some in port 0 and some in either port.
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72 (define_reservation "slm-simple-0" "(slm-port-0 + slm-ieu-0)")
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73 (define_reservation "slm-simple-1" "(slm-port-1 + slm-ieu-1)")
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74 (define_reservation "slm-simple-either" "(slm-simple-0 | slm-simple-1)")
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75
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76 ;;; Complex macro-instruction has variants of latency, and uses both ports.
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77 (define_reservation "slm-complex" "(slm-port-dual + slm-all-eu)")
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78
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79 (define_insn_reservation "slm_other" 9
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80 (and (eq_attr "cpu" "slm")
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81 (and (eq_attr "type" "other")
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82 (eq_attr "atom_unit" "!jeu")))
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83 "slm-complex, slm-all-eu*8")
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84
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85 ;; return has type "other" with atom_unit "jeu"
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86 (define_insn_reservation "slm_other_2" 1
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87 (and (eq_attr "cpu" "slm")
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88 (and (eq_attr "type" "other")
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89 (eq_attr "atom_unit" "jeu")))
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90 "slm-dual-1c")
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91
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92 (define_insn_reservation "slm_multi" 9
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93 (and (eq_attr "cpu" "slm")
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94 (eq_attr "type" "multi"))
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95 "slm-complex, slm-all-eu*8")
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96
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97 ;; Normal alu insns without carry
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98 (define_insn_reservation "slm_alu" 1
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99 (and (eq_attr "cpu" "slm")
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100 (and (eq_attr "type" "alu")
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101 (and (eq_attr "memory" "none")
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102 (eq_attr "use_carry" "0"))))
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103 "slm-simple-either")
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104
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105 ;; Normal alu insns without carry, but use MEC.
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106 (define_insn_reservation "slm_alu_mem" 1
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107 (and (eq_attr "cpu" "slm")
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108 (and (eq_attr "type" "alu")
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109 (and (eq_attr "memory" "!none")
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110 (eq_attr "use_carry" "0"))))
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111 "slm-simple-either")
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112
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113 ;; Alu insn consuming CF, such as add/sbb
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114 (define_insn_reservation "slm_alu_carry" 2
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115 (and (eq_attr "cpu" "slm")
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116 (and (eq_attr "type" "alu")
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117 (and (eq_attr "memory" "none")
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118 (eq_attr "use_carry" "1"))))
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119 "slm-simple-either, nothing")
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120
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121 ;; Alu insn consuming CF, such as add/sbb
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122 (define_insn_reservation "slm_alu_carry_mem" 2
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123 (and (eq_attr "cpu" "slm")
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124 (and (eq_attr "type" "alu")
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125 (and (eq_attr "memory" "!none")
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126 (eq_attr "use_carry" "1"))))
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127 "slm-simple-either, nothing")
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128
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129 (define_insn_reservation "slm_alu1" 1
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130 (and (eq_attr "cpu" "slm")
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131 (and (eq_attr "type" "alu1")
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132 (eq_attr "memory" "none") (eq_attr "prefix_0f" "0")))
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133 "slm-simple-either")
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134
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135 ;; bsf and bsf insn
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136 (define_insn_reservation "slm_alu1_1" 10
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137 (and (eq_attr "cpu" "slm")
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138 (and (eq_attr "type" "alu1")
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139 (eq_attr "memory" "none") (eq_attr "prefix_0f" "1")))
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140 "slm-simple-1, slm-ieu-1*9")
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141
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142 (define_insn_reservation "slm_alu1_mem" 1
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143 (and (eq_attr "cpu" "slm")
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144 (and (eq_attr "type" "alu1")
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145 (eq_attr "memory" "!none")))
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146 "slm-simple-either")
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147
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148 (define_insn_reservation "slm_negnot" 1
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149 (and (eq_attr "cpu" "slm")
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150 (and (eq_attr "type" "negnot")
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151 (eq_attr "memory" "none")))
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152 "slm-simple-either")
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153
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154 (define_insn_reservation "slm_negnot_mem" 1
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155 (and (eq_attr "cpu" "slm")
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156 (and (eq_attr "type" "negnot")
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157 (eq_attr "memory" "!none")))
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158 "slm-simple-either")
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159
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160 (define_insn_reservation "slm_imov" 1
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161 (and (eq_attr "cpu" "slm")
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162 (and (eq_attr "type" "imov")
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163 (eq_attr "memory" "none")))
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164 "slm-simple-either")
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165
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166 (define_insn_reservation "slm_imov_mem" 1
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167 (and (eq_attr "cpu" "slm")
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168 (and (eq_attr "type" "imov")
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169 (eq_attr "memory" "!none")))
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170 "slm-simple-0")
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171
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172 ;; 16<-16, 32<-32
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173 (define_insn_reservation "slm_imovx" 1
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174 (and (eq_attr "cpu" "slm")
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175 (and (eq_attr "type" "imovx")
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176 (and (eq_attr "memory" "none")
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177 (ior (and (match_operand:HI 0 "register_operand")
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178 (match_operand:HI 1 "general_operand"))
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179 (and (match_operand:SI 0 "register_operand")
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180 (match_operand:SI 1 "general_operand"))))))
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181 "slm-simple-either")
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182
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183 ;; 16<-16, 32<-32, mem
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184 (define_insn_reservation "slm_imovx_mem" 1
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185 (and (eq_attr "cpu" "slm")
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186 (and (eq_attr "type" "imovx")
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187 (and (eq_attr "memory" "!none")
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188 (ior (and (match_operand:HI 0 "register_operand")
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189 (match_operand:HI 1 "general_operand"))
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190 (and (match_operand:SI 0 "register_operand")
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191 (match_operand:SI 1 "general_operand"))))))
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192 "slm-simple-either")
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193
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194 ;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8
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195 (define_insn_reservation "slm_imovx_2" 1
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196 (and (eq_attr "cpu" "slm")
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197 (and (eq_attr "type" "imovx")
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198 (and (eq_attr "memory" "none")
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199 (ior (match_operand:QI 0 "register_operand")
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200 (ior (and (match_operand:SI 0 "register_operand")
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201 (not (match_operand:SI 1 "general_operand")))
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202 (match_operand:DI 0 "register_operand"))))))
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203 "slm-simple-either")
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204
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205 ;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8, mem
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206 (define_insn_reservation "slm_imovx_2_mem" 1
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207 (and (eq_attr "cpu" "slm")
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208 (and (eq_attr "type" "imovx")
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209 (and (eq_attr "memory" "!none")
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210 (ior (match_operand:QI 0 "register_operand")
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211 (ior (and (match_operand:SI 0 "register_operand")
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212 (not (match_operand:SI 1 "general_operand")))
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213 (match_operand:DI 0 "register_operand"))))))
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214 "slm-simple-0")
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215
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216 ;; 16<-8
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217 (define_insn_reservation "slm_imovx_3" 3
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218 (and (eq_attr "cpu" "slm")
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219 (and (eq_attr "type" "imovx")
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220 (and (match_operand:HI 0 "register_operand")
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221 (match_operand:QI 1 "general_operand"))))
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222 "slm-simple-0, nothing*2")
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223
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224 (define_insn_reservation "slm_lea" 1
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225 (and (eq_attr "cpu" "slm")
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226 (and (eq_attr "type" "lea")
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227 (eq_attr "mode" "!HI")))
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228 "slm-simple-either")
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229
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230 ;; lea 16bit address is complex insn
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231 (define_insn_reservation "slm_lea_2" 2
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232 (and (eq_attr "cpu" "slm")
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233 (and (eq_attr "type" "lea")
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234 (eq_attr "mode" "HI")))
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235 "slm-complex, slm-all-eu")
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236
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237 (define_insn_reservation "slm_incdec" 1
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238 (and (eq_attr "cpu" "slm")
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239 (and (eq_attr "type" "incdec")
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240 (eq_attr "memory" "none")))
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241 "slm-simple-0")
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242
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243 (define_insn_reservation "slm_incdec_mem" 3
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244 (and (eq_attr "cpu" "slm")
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245 (and (eq_attr "type" "incdec")
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246 (eq_attr "memory" "!none")))
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247 "slm-simple-0, nothing*2")
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248
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249 ;; simple shift instruction use SHIFT eu, none memory
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250 (define_insn_reservation "slm_ishift" 1
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251 (and (eq_attr "cpu" "slm")
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252 (and (eq_attr "type" "ishift")
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253 (and (eq_attr "memory" "none") (eq_attr "prefix_0f" "0"))))
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254 "slm-simple-0")
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255
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256 ;; simple shift instruction use SHIFT eu, memory
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257 (define_insn_reservation "slm_ishift_mem" 1
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258 (and (eq_attr "cpu" "slm")
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259 (and (eq_attr "type" "ishift")
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260 (and (eq_attr "memory" "!none") (eq_attr "prefix_0f" "0"))))
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261 "slm-simple-0")
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262
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263 ;; DF shift (prefixed with 0f) is complex insn with latency of 4 cycles
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264 (define_insn_reservation "slm_ishift_3" 4
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265 (and (eq_attr "cpu" "slm")
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266 (and (eq_attr "type" "ishift")
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267 (eq_attr "prefix_0f" "1")))
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268 "slm-complex, slm-all-eu*3")
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269
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270 (define_insn_reservation "slm_ishift1" 1
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271 (and (eq_attr "cpu" "slm")
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272 (and (eq_attr "type" "ishift1")
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273 (eq_attr "memory" "none")))
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274 "slm-simple-0")
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275
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276 (define_insn_reservation "slm_ishift1_mem" 1
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277 (and (eq_attr "cpu" "slm")
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278 (and (eq_attr "type" "ishift1")
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279 (eq_attr "memory" "!none")))
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280 "slm-simple-0")
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281
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282 (define_insn_reservation "slm_rotate" 1
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283 (and (eq_attr "cpu" "slm")
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284 (and (eq_attr "type" "rotate")
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285 (eq_attr "memory" "none")))
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286 "slm-simple-0")
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287
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288 (define_insn_reservation "slm_rotate_mem" 1
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289 (and (eq_attr "cpu" "slm")
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290 (and (eq_attr "type" "rotate")
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291 (eq_attr "memory" "!none")))
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292 "slm-simple-0")
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293
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294 (define_insn_reservation "slm_rotate1" 1
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295 (and (eq_attr "cpu" "slm")
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296 (and (eq_attr "type" "rotate1")
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297 (eq_attr "memory" "none")))
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298 "slm-simple-0")
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299
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300 (define_insn_reservation "slm_rotate1_mem" 1
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301 (and (eq_attr "cpu" "slm")
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302 (and (eq_attr "type" "rotate1")
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303 (eq_attr "memory" "!none")))
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304 "slm-simple-0")
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305
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306 (define_insn_reservation "slm_imul" 3
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307 (and (eq_attr "cpu" "slm")
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308 (and (eq_attr "type" "imul")
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309 (and (eq_attr "memory" "none") (eq_attr "mode" "SI"))))
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310 "slm-imul-32")
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311
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312 (define_insn_reservation "slm_imul_mem" 3
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313 (and (eq_attr "cpu" "slm")
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314 (and (eq_attr "type" "imul")
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315 (and (eq_attr "memory" "!none") (eq_attr "mode" "SI"))))
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316 "slm-imul-mem-32")
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317
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318 ;; latency set to 4 as common 64x64 imul with 1/2 tput
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319 (define_insn_reservation "slm_imul_3" 4
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320 (and (eq_attr "cpu" "slm")
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321 (and (eq_attr "type" "imul")
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322 (eq_attr "mode" "!SI")))
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323 "slm-imul-64")
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324
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325 (define_insn_reservation "slm_idiv" 33
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326 (and (eq_attr "cpu" "slm")
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327 (eq_attr "type" "idiv"))
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328 "slm-complex, slm-all-eu*16, nothing*16")
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329
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330 (define_insn_reservation "slm_icmp" 1
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331 (and (eq_attr "cpu" "slm")
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332 (and (eq_attr "type" "icmp")
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333 (eq_attr "memory" "none")))
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334 "slm-simple-either")
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335
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336 (define_insn_reservation "slm_icmp_mem" 1
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337 (and (eq_attr "cpu" "slm")
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338 (and (eq_attr "type" "icmp")
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339 (eq_attr "memory" "!none")))
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340 "slm-simple-either")
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341
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342 (define_insn_reservation "slm_test" 1
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343 (and (eq_attr "cpu" "slm")
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344 (and (eq_attr "type" "test")
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345 (eq_attr "memory" "none")))
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346 "slm-simple-either")
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347
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348 (define_insn_reservation "slm_test_mem" 1
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349 (and (eq_attr "cpu" "slm")
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350 (and (eq_attr "type" "test")
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351 (eq_attr "memory" "!none")))
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352 "slm-simple-either")
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353
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354 (define_insn_reservation "slm_ibr" 1
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355 (and (eq_attr "cpu" "slm")
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356 (and (eq_attr "type" "ibr")
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357 (eq_attr "memory" "!load")))
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358 "slm-simple-1")
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359
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360 ;; complex if jump target is from address
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361 (define_insn_reservation "slm_ibr_2" 2
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362 (and (eq_attr "cpu" "slm")
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363 (and (eq_attr "type" "ibr")
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364 (eq_attr "memory" "load")))
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365 "slm-complex, slm-all-eu")
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366
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367 (define_insn_reservation "slm_setcc" 1
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368 (and (eq_attr "cpu" "slm")
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369 (and (eq_attr "type" "setcc")
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370 (eq_attr "memory" "!store")))
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371 "slm-simple-either")
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372
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373 ;; 2 cycles complex if target is in memory
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374 (define_insn_reservation "slm_setcc_2" 2
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375 (and (eq_attr "cpu" "slm")
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376 (and (eq_attr "type" "setcc")
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377 (eq_attr "memory" "store")))
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378 "slm-complex, slm-all-eu")
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379
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380 (define_insn_reservation "slm_icmov" 2
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381 (and (eq_attr "cpu" "slm")
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382 (and (eq_attr "type" "icmov")
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383 (eq_attr "memory" "none")))
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384 "slm-simple-either, nothing")
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385
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386 (define_insn_reservation "slm_icmov_mem" 2
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387 (and (eq_attr "cpu" "slm")
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388 (and (eq_attr "type" "icmov")
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389 (eq_attr "memory" "!none")))
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390 "slm-simple-0, nothing")
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391
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392 ;; UCODE if segreg, ignored
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393 (define_insn_reservation "slm_push" 2
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394 (and (eq_attr "cpu" "slm")
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395 (eq_attr "type" "push"))
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396 "slm-dual-2c")
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397
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398 ;; pop r64 is 1 cycle. UCODE if segreg, ignored
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399 (define_insn_reservation "slm_pop" 1
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400 (and (eq_attr "cpu" "slm")
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401 (and (eq_attr "type" "pop")
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402 (eq_attr "mode" "DI")))
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403 "slm-dual-1c")
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404
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405 ;; pop non-r64 is 2 cycles. UCODE if segreg, ignored
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406 (define_insn_reservation "slm_pop_2" 2
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407 (and (eq_attr "cpu" "slm")
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408 (and (eq_attr "type" "pop")
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409 (eq_attr "mode" "!DI")))
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410 "slm-dual-2c")
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411
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412 ;; UCODE if segreg, ignored
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413 (define_insn_reservation "slm_call" 1
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414 (and (eq_attr "cpu" "slm")
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415 (eq_attr "type" "call"))
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416 "slm-dual-1c")
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417
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418 (define_insn_reservation "slm_callv" 1
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419 (and (eq_attr "cpu" "slm")
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420 (eq_attr "type" "callv"))
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|
421 "slm-dual-1c")
|
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422
|
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423 (define_insn_reservation "slm_leave" 3
|
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|
424 (and (eq_attr "cpu" "slm")
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425 (eq_attr "type" "leave"))
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426 "slm-complex, slm-all-eu*2")
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427
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428 (define_insn_reservation "slm_str" 3
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|
429 (and (eq_attr "cpu" "slm")
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430 (eq_attr "type" "str"))
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|
431 "slm-complex, slm-all-eu*2")
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432
|
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433 (define_insn_reservation "slm_sselog" 1
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434 (and (eq_attr "cpu" "slm")
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|
435 (and (eq_attr "type" "sselog")
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436 (eq_attr "memory" "none")))
|
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437 "slm-simple-either")
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438
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|
439 (define_insn_reservation "slm_sselog_mem" 1
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440 (and (eq_attr "cpu" "slm")
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|
441 (and (eq_attr "type" "sselog")
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|
|
442 (eq_attr "memory" "!none")))
|
|
|
443 "slm-simple-either")
|
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444
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|
445 (define_insn_reservation "slm_sselog1" 1
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446 (and (eq_attr "cpu" "slm")
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|
|
447 (and (eq_attr "type" "sselog1")
|
|
|
448 (eq_attr "memory" "none")))
|
|
|
449 "slm-simple-0")
|
|
|
450
|
|
|
451 (define_insn_reservation "slm_sselog1_mem" 1
|
|
|
452 (and (eq_attr "cpu" "slm")
|
|
|
453 (and (eq_attr "type" "sselog1")
|
|
|
454 (eq_attr "memory" "!none")))
|
|
|
455 "slm-simple-0")
|
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|
456
|
|
|
457 ;; not pmad, not psad
|
|
|
458 (define_insn_reservation "slm_sseiadd" 1
|
|
|
459 (and (eq_attr "cpu" "slm")
|
|
|
460 (and (eq_attr "type" "sseiadd")
|
|
|
461 (and (not (match_operand:V2DI 0 "register_operand"))
|
|
|
462 (and (eq_attr "atom_unit" "!simul")
|
|
|
463 (eq_attr "atom_unit" "!complex")))))
|
|
|
464 "slm-simple-either")
|
|
|
465
|
|
|
466 ;; pmad, psad and 64
|
|
|
467 (define_insn_reservation "slm_sseiadd_2" 4
|
|
|
468 (and (eq_attr "cpu" "slm")
|
|
|
469 (and (eq_attr "type" "sseiadd")
|
|
|
470 (and (not (match_operand:V2DI 0 "register_operand"))
|
|
|
471 (and (eq_attr "atom_unit" "simul" )
|
|
|
472 (eq_attr "mode" "DI")))))
|
|
|
473 "slm-fmul-4c")
|
|
|
474
|
|
|
475 ;; pmad, psad and 128
|
|
|
476 (define_insn_reservation "slm_sseiadd_3" 5
|
|
|
477 (and (eq_attr "cpu" "slm")
|
|
|
478 (and (eq_attr "type" "sseiadd")
|
|
|
479 (and (not (match_operand:V2DI 0 "register_operand"))
|
|
|
480 (and (eq_attr "atom_unit" "simul" )
|
|
|
481 (eq_attr "mode" "TI")))))
|
|
|
482 "slm-fmul-5c")
|
|
|
483
|
|
|
484 ;; if paddq(64 bit op), phadd/phsub
|
|
|
485 (define_insn_reservation "slm_sseiadd_4" 4
|
|
|
486 (and (eq_attr "cpu" "slm")
|
|
|
487 (and (eq_attr "type" "sseiadd")
|
|
|
488 (ior (match_operand:V2DI 0 "register_operand")
|
|
|
489 (eq_attr "atom_unit" "complex"))))
|
|
|
490 "slm-fadd-4c")
|
|
|
491
|
|
|
492 ;; if immediate op.
|
|
|
493 (define_insn_reservation "slm_sseishft" 1
|
|
|
494 (and (eq_attr "cpu" "slm")
|
|
|
495 (and (eq_attr "type" "sseishft")
|
|
|
496 (and (eq_attr "atom_unit" "!sishuf")
|
|
|
497 (match_operand 2 "immediate_operand"))))
|
|
|
498 "slm-simple-either")
|
|
|
499
|
|
|
500 ;; if palignr or psrldq
|
|
|
501 (define_insn_reservation "slm_sseishft_2" 1
|
|
|
502 (and (eq_attr "cpu" "slm")
|
|
|
503 (ior (eq_attr "type" "sseishft1")
|
|
|
504 (and (eq_attr "type" "sseishft")
|
|
|
505 (and (eq_attr "atom_unit" "sishuf")
|
|
|
506 (match_operand 2 "immediate_operand")))))
|
|
|
507 "slm-simple-0")
|
|
|
508
|
|
|
509 ;; if reg/mem op
|
|
|
510 (define_insn_reservation "slm_sseishft_3" 2
|
|
|
511 (and (eq_attr "cpu" "slm")
|
|
|
512 (and (eq_attr "type" "sseishft")
|
|
|
513 (not (match_operand 2 "immediate_operand"))))
|
|
|
514 "slm-complex, slm-all-eu")
|
|
|
515
|
|
|
516 (define_insn_reservation "slm_sseimul" 5
|
|
|
517 (and (eq_attr "cpu" "slm")
|
|
|
518 (eq_attr "type" "sseimul"))
|
|
|
519 "slm-fmul-5c")
|
|
|
520
|
|
|
521 ;; rcpss or rsqrtss
|
|
|
522 (define_insn_reservation "slm_sse" 4
|
|
|
523 (and (eq_attr "cpu" "slm")
|
|
|
524 (and (eq_attr "type" "sse")
|
|
|
525 (and (eq_attr "atom_sse_attr" "rcp") (eq_attr "mode" "SF"))))
|
|
|
526 "slm-fmul-4c")
|
|
|
527
|
|
|
528 ;; movshdup, movsldup. Suggest to type sseishft
|
|
|
529 (define_insn_reservation "slm_sse_2" 1
|
|
|
530 (and (eq_attr "cpu" "slm")
|
|
|
531 (and (eq_attr "type" "sse")
|
|
|
532 (eq_attr "atom_sse_attr" "movdup")))
|
|
|
533 "slm-simple-0")
|
|
|
534
|
|
|
535 ;; lfence
|
|
|
536 (define_insn_reservation "slm_sse_3" 1
|
|
|
537 (and (eq_attr "cpu" "slm")
|
|
|
538 (and (eq_attr "type" "sse")
|
|
|
539 (eq_attr "atom_sse_attr" "lfence")))
|
|
|
540 "slm-simple-either")
|
|
|
541
|
|
|
542 ;; sfence,clflush,mfence, prefetch
|
|
|
543 (define_insn_reservation "slm_sse_4" 1
|
|
|
544 (and (eq_attr "cpu" "slm")
|
|
|
545 (and (eq_attr "type" "sse")
|
|
|
546 (ior (eq_attr "atom_sse_attr" "fence")
|
|
|
547 (eq_attr "atom_sse_attr" "prefetch"))))
|
|
|
548 "slm-simple-0")
|
|
|
549
|
|
|
550 ;; rcpps, rsqrtss, sqrt, ldmxcsr
|
|
|
551 (define_insn_reservation "slm_sse_5" 9
|
|
|
552 (and (eq_attr "cpu" "slm")
|
|
|
553 (and (eq_attr "type" "sse")
|
|
|
554 (ior (ior (eq_attr "atom_sse_attr" "sqrt")
|
|
|
555 (eq_attr "atom_sse_attr" "mxcsr"))
|
|
|
556 (and (eq_attr "atom_sse_attr" "rcp")
|
|
|
557 (eq_attr "mode" "V4SF")))))
|
|
|
558 "slm-complex, slm-all-eu*7, nothing")
|
|
|
559
|
|
|
560 ;; xmm->xmm
|
|
|
561 (define_insn_reservation "slm_ssemov" 1
|
|
|
562 (and (eq_attr "cpu" "slm")
|
|
|
563 (and (eq_attr "type" "ssemov")
|
|
|
564 (and (match_operand 0 "register_operand" "xy")
|
|
|
565 (match_operand 1 "register_operand" "xy"))))
|
|
|
566 "slm-simple-either")
|
|
|
567
|
|
|
568 ;; reg->xmm
|
|
|
569 (define_insn_reservation "slm_ssemov_2" 1
|
|
|
570 (and (eq_attr "cpu" "slm")
|
|
|
571 (and (eq_attr "type" "ssemov")
|
|
|
572 (and (match_operand 0 "register_operand" "xy")
|
|
|
573 (match_operand 1 "register_operand" "r"))))
|
|
|
574 "slm-simple-0")
|
|
|
575
|
|
|
576 ;; xmm->reg
|
|
|
577 (define_insn_reservation "slm_ssemov_3" 3
|
|
|
578 (and (eq_attr "cpu" "slm")
|
|
|
579 (and (eq_attr "type" "ssemov")
|
|
|
580 (and (match_operand 0 "register_operand" "r")
|
|
|
581 (match_operand 1 "register_operand" "xy"))))
|
|
|
582 "slm-simple-0, nothing*2")
|
|
|
583
|
|
|
584 ;; mov mem
|
|
|
585 (define_insn_reservation "slm_ssemov_4" 1
|
|
|
586 (and (eq_attr "cpu" "slm")
|
|
|
587 (and (eq_attr "type" "ssemov")
|
|
|
588 (and (eq_attr "movu" "0") (eq_attr "memory" "!none"))))
|
|
|
589 "slm-simple-0")
|
|
|
590
|
|
|
591 ;; movu mem
|
|
|
592 (define_insn_reservation "slm_ssemov_5" 2
|
|
|
593 (and (eq_attr "cpu" "slm")
|
|
|
594 (and (eq_attr "type" "ssemov")
|
|
|
595 (ior (eq_attr "movu" "1") (eq_attr "memory" "!none"))))
|
|
|
596 "slm-simple-0, nothing")
|
|
|
597
|
|
|
598 ;; no memory simple
|
|
|
599 (define_insn_reservation "slm_sseadd" 3
|
|
|
600 (and (eq_attr "cpu" "slm")
|
|
|
601 (and (eq_attr "type" "sseadd")
|
|
|
602 (and (eq_attr "memory" "none")
|
|
|
603 (and (eq_attr "mode" "!V2DF")
|
|
|
604 (eq_attr "atom_unit" "!complex")))))
|
|
|
605 "slm-fadd-3c")
|
|
|
606
|
|
|
607 ;; memory simple
|
|
|
608 (define_insn_reservation "slm_sseadd_mem" 3
|
|
|
609 (and (eq_attr "cpu" "slm")
|
|
|
610 (and (eq_attr "type" "sseadd")
|
|
|
611 (and (eq_attr "memory" "!none")
|
|
|
612 (and (eq_attr "mode" "!V2DF")
|
|
|
613 (eq_attr "atom_unit" "!complex")))))
|
|
|
614 "slm-fadd-3c")
|
|
|
615
|
|
|
616 ;; maxps, minps, *pd, hadd, hsub
|
|
|
617 (define_insn_reservation "slm_sseadd_3" 4
|
|
|
618 (and (eq_attr "cpu" "slm")
|
|
|
619 (and (eq_attr "type" "sseadd")
|
|
|
620 (ior (eq_attr "mode" "V2DF") (eq_attr "atom_unit" "complex"))))
|
|
|
621 "slm-fadd-4c")
|
|
|
622
|
|
|
623 ;; Except dppd/dpps
|
|
|
624 (define_insn_reservation "slm_ssemul" 5
|
|
|
625 (and (eq_attr "cpu" "slm")
|
|
|
626 (and (eq_attr "type" "ssemul")
|
|
|
627 (eq_attr "mode" "!SF")))
|
|
|
628 "slm-fmul-5c")
|
|
|
629
|
|
|
630 ;; Except dppd/dpps, 4 cycle if mulss
|
|
|
631 (define_insn_reservation "slm_ssemul_2" 4
|
|
|
632 (and (eq_attr "cpu" "slm")
|
|
|
633 (and (eq_attr "type" "ssemul")
|
|
|
634 (eq_attr "mode" "SF")))
|
|
|
635 "slm-fmul-4c")
|
|
|
636
|
|
|
637 (define_insn_reservation "slm_ssecmp" 1
|
|
|
638 (and (eq_attr "cpu" "slm")
|
|
|
639 (eq_attr "type" "ssecmp"))
|
|
|
640 "slm-simple-either")
|
|
|
641
|
|
|
642 (define_insn_reservation "slm_ssecomi" 1
|
|
|
643 (and (eq_attr "cpu" "slm")
|
|
|
644 (eq_attr "type" "ssecomi"))
|
|
|
645 "slm-simple-0")
|
|
|
646
|
|
|
647 ;; no memory and cvtpi2ps, cvtps2pi, cvttps2pi
|
|
|
648 (define_insn_reservation "slm_ssecvt" 5
|
|
|
649 (and (eq_attr "cpu" "slm")
|
|
|
650 (and (eq_attr "type" "ssecvt")
|
|
|
651 (ior (and (match_operand:V2SI 0 "register_operand")
|
|
|
652 (match_operand:V4SF 1 "register_operand"))
|
|
|
653 (and (match_operand:V4SF 0 "register_operand")
|
|
|
654 (match_operand:V2SI 1 "register_operand")))))
|
|
|
655 "slm-fp-0, slm-feu-0, nothing*3")
|
|
|
656
|
|
|
657 ;; memory and cvtpi2ps, cvtps2pi, cvttps2pi
|
|
|
658 (define_insn_reservation "slm_ssecvt_mem" 5
|
|
|
659 (and (eq_attr "cpu" "slm")
|
|
|
660 (and (eq_attr "type" "ssecvt")
|
|
|
661 (ior (and (match_operand:V2SI 0 "register_operand")
|
|
|
662 (match_operand:V4SF 1 "memory_operand"))
|
|
|
663 (and (match_operand:V4SF 0 "register_operand")
|
|
|
664 (match_operand:V2SI 1 "memory_operand")))))
|
|
|
665 "slm-fp-0, slm-feu-0, nothing*3")
|
|
|
666
|
|
|
667 ;; cvtpd2pi, cvtpi2pd
|
|
|
668 (define_insn_reservation "slm_ssecvt_1" 2
|
|
|
669 (and (eq_attr "cpu" "slm")
|
|
|
670 (and (eq_attr "type" "ssecvt")
|
|
|
671 (ior (and (match_operand:V2DF 0 "register_operand")
|
|
|
672 (match_operand:V2SI 1 "register_operand"))
|
|
|
673 (and (match_operand:V2SI 0 "register_operand")
|
|
|
674 (match_operand:V2DF 1 "register_operand")))))
|
|
|
675 "slm-fp-0, slm-feu-0")
|
|
|
676
|
|
|
677 ;; memory and cvtpd2pi, cvtpi2pd
|
|
|
678 (define_insn_reservation "slm_ssecvt_1_mem" 2
|
|
|
679 (and (eq_attr "cpu" "slm")
|
|
|
680 (and (eq_attr "type" "ssecvt")
|
|
|
681 (ior (and (match_operand:V2DF 0 "register_operand")
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682 (match_operand:V2SI 1 "memory_operand"))
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683 (and (match_operand:V2SI 0 "register_operand")
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684 (match_operand:V2DF 1 "memory_operand")))))
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685 "slm-fp-0, slm-feu-0")
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686
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687 ;; otherwise. 4 cycles average for cvtss2sd
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688 (define_insn_reservation "slm_ssecvt_3" 4
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689 (and (eq_attr "cpu" "slm")
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690 (and (eq_attr "type" "ssecvt")
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691 (not (ior (and (match_operand:V2SI 0 "register_operand")
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692 (match_operand:V4SF 1 "nonimmediate_operand"))
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693 (and (match_operand:V4SF 0 "register_operand")
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694 (match_operand:V2SI 1 "nonimmediate_operand"))))))
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695 "slm-fp-0, nothing*3")
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696
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697 ;; memory and cvtsi2sd
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698 (define_insn_reservation "slm_sseicvt" 1
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699 (and (eq_attr "cpu" "slm")
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700 (and (eq_attr "type" "sseicvt")
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701 (and (match_operand:V2DF 0 "register_operand")
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702 (match_operand:SI 1 "nonimmediate_operand"))))
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703 "slm-fp-0")
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704
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705 ;; otherwise. 8 cycles average for cvtsd2si
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706 (define_insn_reservation "slm_sseicvt_2" 4
|
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707 (and (eq_attr "cpu" "slm")
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708 (and (eq_attr "type" "sseicvt")
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709 (not (and (match_operand:V2DF 0 "register_operand")
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710 (match_operand:SI 1 "memory_operand")))))
|
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711 "slm-fp-0, nothing*3")
|
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|
712
|
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|
713 (define_insn_reservation "slm_ssediv" 13
|
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714 (and (eq_attr "cpu" "slm")
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715 (eq_attr "type" "ssediv"))
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716 "slm-fp-0, slm-feu-0*10, nothing*2")
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717
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718 ;; simple for fmov
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719 (define_insn_reservation "slm_fmov" 1
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|
720 (and (eq_attr "cpu" "slm")
|
|
|
721 (and (eq_attr "type" "fmov")
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722 (eq_attr "memory" "none")))
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723 "slm-simple-either")
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724
|
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|
725 ;; simple for fmov
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726 (define_insn_reservation "slm_fmov_mem" 1
|
|
|
727 (and (eq_attr "cpu" "slm")
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|
|
728 (and (eq_attr "type" "fmov")
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729 (eq_attr "memory" "!none")))
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730 "slm-simple-either")
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|
|
731
|
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|
732 ;; Define bypass here
|
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|
733
|
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|
734 ;; There will be 0 cycle stall from cmp/test to jcc
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|
735
|
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|
736 ;; There will be 1 cycle stall from flag producer to cmov and adc/sbb
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737 (define_bypass 2 "slm_icmp, slm_test, slm_alu, slm_alu_carry,
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|
738 slm_alu1, slm_negnot, slm_incdec, slm_ishift,
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739 slm_ishift1, slm_rotate, slm_rotate1"
|
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|
740 "slm_icmov, slm_alu_carry")
|
|
|
741
|
|
|
742 ;; lea to shift source stall is 1 cycle
|
|
|
743 (define_bypass 2 "slm_lea"
|
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|
744 "slm_ishift, slm_ishift1, slm_rotate, slm_rotate1"
|
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745 "!ix86_dep_by_shift_count")
|
|
|
746
|
|
|
747 ;; non-lea to shift count stall is 1 cycle
|
|
|
748 (define_bypass 2 "slm_alu_carry,
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|
|
749 slm_alu,slm_alu1,slm_negnot,slm_imov,slm_imovx,
|
|
|
750 slm_incdec,slm_ishift,slm_ishift1,slm_rotate,
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|
751 slm_rotate1, slm_setcc, slm_icmov, slm_pop,
|
|
|
752 slm_alu_mem, slm_alu_carry_mem, slm_alu1_mem,
|
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|
753 slm_imovx_mem, slm_imovx_2_mem,
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|
754 slm_imov_mem, slm_icmov_mem, slm_fmov_mem"
|
|
|
755 "slm_ishift, slm_ishift1, slm_rotate, slm_rotate1,
|
|
|
756 slm_ishift_mem, slm_ishift1_mem,
|
|
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757 slm_rotate_mem, slm_rotate1_mem"
|
|
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758 "ix86_dep_by_shift_count")
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