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1 ;; DFA-based pipeline description for the VR1x000.
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2 ;; Copyright (C) 2005-2020 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published
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8 ;; by the Free Software Foundation; either version 3, or (at your
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9 ;; option) any later version.
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10
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11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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14 ;; License for more details.
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15
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20
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21 ;; R12K/R14K/R16K are derivatives of R10K, thus copy its description
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22 ;; until specific tuning for each is added.
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23
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24 ;; R10000 has an int queue, fp queue, address queue.
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25 ;; The int queue feeds ALU1 and ALU2.
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26 ;; The fp queue feeds the fp-adder and fp-multiplier.
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27 ;; The addr queue feeds the Load/Store unit.
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28 ;;
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29 ;; However, we define the fp-adder and fp-multiplier as
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30 ;; separate automatons, because the fp-multiplier is
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31 ;; divided into fp-multiplier, fp-division, and
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32 ;; fp-squareroot units, all of which share the same
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33 ;; issue and completion logic, yet can operate in
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34 ;; parallel.
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35 ;;
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36 ;; This is based on the model described in the R10K Manual
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37 ;; and it helps to reduce the size of the automata.
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38 (define_automaton "r10k_a_int, r10k_a_fpadder, r10k_a_addr,
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39 r10k_a_fpmpy, r10k_a_fpdiv, r10k_a_fpsqrt")
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40
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41 (define_cpu_unit "r10k_alu1" "r10k_a_int")
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42 (define_cpu_unit "r10k_alu2" "r10k_a_int")
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43 (define_cpu_unit "r10k_fpadd" "r10k_a_fpadder")
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44 (define_cpu_unit "r10k_fpmpy" "r10k_a_fpmpy")
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45 (define_cpu_unit "r10k_fpdiv" "r10k_a_fpdiv")
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46 (define_cpu_unit "r10k_fpsqrt" "r10k_a_fpsqrt")
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47 (define_cpu_unit "r10k_loadstore" "r10k_a_addr")
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48
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49
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50 ;; R10k Loads and Stores.
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51 (define_insn_reservation "r10k_load" 2
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52 (and (eq_attr "cpu" "r10000")
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53 (eq_attr "type" "load,prefetch,prefetchx"))
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54 "r10k_loadstore")
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55
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56 (define_insn_reservation "r10k_store" 0
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57 (and (eq_attr "cpu" "r10000")
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58 (eq_attr "type" "store,fpstore,fpidxstore"))
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59 "r10k_loadstore")
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60
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61 (define_insn_reservation "r10k_fpload" 3
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62 (and (eq_attr "cpu" "r10000")
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63 (eq_attr "type" "fpload,fpidxload"))
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64 "r10k_loadstore")
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65
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66
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67 ;; Integer add/sub + logic ops, and mt hi/lo can be done by alu1 or alu2.
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68 ;; Miscellaneous arith goes here too (this is a guess).
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69 (define_insn_reservation "r10k_arith" 1
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70 (and (eq_attr "cpu" "r10000")
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71 (eq_attr "type" "arith,mthi,mtlo,slt,clz,const,nop,trap,logical"))
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72 "r10k_alu1 | r10k_alu2")
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73
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74 ;; We treat mfhilo differently, because we need to know when
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75 ;; it's HI and when it's LO.
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76 (define_insn_reservation "r10k_mfhi" 1
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77 (and (eq_attr "cpu" "r10000")
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78 (eq_attr "type" "mfhi"))
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79 "r10k_alu1 | r10k_alu2")
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80
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81 (define_insn_reservation "r10k_mflo" 1
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82 (and (eq_attr "cpu" "r10000")
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83 (eq_attr "type" "mflo"))
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84 "r10k_alu1 | r10k_alu2")
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85
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86
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87 ;; ALU1 handles shifts, branch eval, and condmove.
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88 ;;
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89 ;; Brancher is separate, but part of ALU1, but can only
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90 ;; do one branch per cycle (is this even implementable?).
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91 ;;
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92 ;; Unsure if the brancher handles jumps and calls as well, but since
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93 ;; they're related, we'll add them here for now.
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94 (define_insn_reservation "r10k_brancher" 1
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95 (and (eq_attr "cpu" "r10000")
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96 (eq_attr "type" "shift,branch,jump,call"))
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97 "r10k_alu1")
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98
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99 (define_insn_reservation "r10k_int_cmove" 1
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100 (and (eq_attr "cpu" "r10000")
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101 (and (eq_attr "type" "condmove")
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102 (eq_attr "mode" "SI,DI")))
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103 "r10k_alu1")
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104
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105
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106 ;; Coprocessor Moves.
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107 ;; mtc1/dmtc1 are handled by ALU1.
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108 ;; mfc1/dmfc1 are handled by the fp-multiplier.
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109 (define_insn_reservation "r10k_mt_xfer" 3
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110 (and (eq_attr "cpu" "r10000")
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111 (eq_attr "type" "mtc"))
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112 "r10k_alu1")
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113
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114 (define_insn_reservation "r10k_mf_xfer" 2
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115 (and (eq_attr "cpu" "r10000")
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116 (eq_attr "type" "mfc"))
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117 "r10k_fpmpy")
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118
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119
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120 ;; Only ALU2 does int multiplications and divisions.
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121 ;;
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122 ;; According to the Vr10000 series user manual,
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123 ;; integer mult and div insns can be issued one
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124 ;; cycle earlier if using register Lo. We model
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125 ;; this by using the Lo value by default, as it
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126 ;; is the more common value, and use a bypass
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127 ;; for the Hi value when needed.
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128 ;;
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129 ;; Also of note, There are different latencies
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130 ;; for MULT/DMULT (Lo 5/Hi 6) and MULTU/DMULTU (Lo 6/Hi 7).
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131 ;; However, gcc does not have separate types
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132 ;; for these insns. Thus to strike a balance,
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133 ;; we use the Hi latency value for imul
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134 ;; operations until the imul type can be split.
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135 (define_insn_reservation "r10k_imul_single" 6
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136 (and (eq_attr "cpu" "r10000")
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137 (and (eq_attr "type" "imul,imul3")
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138 (eq_attr "mode" "SI")))
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139 "r10k_alu2 * 6")
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140
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141 (define_insn_reservation "r10k_imul_double" 10
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142 (and (eq_attr "cpu" "r10000")
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143 (and (eq_attr "type" "imul,imul3")
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144 (eq_attr "mode" "DI")))
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145 "r10k_alu2 * 10")
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146
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147 ;; Divides keep ALU2 busy.
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148 (define_insn_reservation "r10k_idiv_single" 34
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149 (and (eq_attr "cpu" "r10000")
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150 (and (eq_attr "type" "idiv")
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151 (eq_attr "mode" "SI")))
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152 "r10k_alu2 * 35")
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153
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154 (define_insn_reservation "r10k_idiv_double" 66
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155 (and (eq_attr "cpu" "r10000")
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156 (and (eq_attr "type" "idiv")
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157 (eq_attr "mode" "DI")))
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158 "r10k_alu2 * 67")
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159
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160 (define_bypass 35 "r10k_idiv_single" "r10k_mfhi")
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161 (define_bypass 67 "r10k_idiv_double" "r10k_mfhi")
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162
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163
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164 ;; Floating point add/sub, mul, abs value, neg, comp, & moves.
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165 (define_insn_reservation "r10k_fp_miscadd" 2
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166 (and (eq_attr "cpu" "r10000")
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167 (eq_attr "type" "fadd,fabs,fneg,fcmp"))
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168 "r10k_fpadd")
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169
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170 (define_insn_reservation "r10k_fp_miscmul" 2
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171 (and (eq_attr "cpu" "r10000")
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172 (eq_attr "type" "fmul,fmove"))
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173 "r10k_fpmpy")
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174
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175 (define_insn_reservation "r10k_fp_cmove" 2
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176 (and (eq_attr "cpu" "r10000")
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177 (and (eq_attr "type" "condmove")
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178 (eq_attr "mode" "SF,DF")))
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179 "r10k_fpmpy")
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180
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181
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182 ;; The fcvt.s.[wl] insn has latency 4, repeat 2.
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183 ;; All other fcvt insns have latency 2, repeat 1.
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184 (define_insn_reservation "r10k_fcvt_single" 4
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185 (and (eq_attr "cpu" "r10000")
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186 (and (eq_attr "type" "fcvt")
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187 (eq_attr "cnv_mode" "I2S")))
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188 "r10k_fpadd * 2")
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189
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190 (define_insn_reservation "r10k_fcvt_other" 2
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191 (and (eq_attr "cpu" "r10000")
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192 (and (eq_attr "type" "fcvt")
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193 (eq_attr "cnv_mode" "!I2S")))
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194 "r10k_fpadd")
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195
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196
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197 ;; Run the fmadd insn through fp-adder first, then fp-multiplier.
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198 ;;
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199 ;; The latency for fmadd is 2 cycles if the result is used
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200 ;; by another fmadd instruction.
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201 (define_insn_reservation "r10k_fmadd" 4
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202 (and (eq_attr "cpu" "r10000")
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203 (eq_attr "type" "fmadd"))
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204 "r10k_fpadd, r10k_fpmpy")
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205
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206 (define_bypass 2 "r10k_fmadd" "r10k_fmadd")
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207
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208
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209 ;; Floating point Divisions & square roots.
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210 (define_insn_reservation "r10k_fdiv_single" 12
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211 (and (eq_attr "cpu" "r10000")
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212 (and (eq_attr "type" "fdiv,frdiv")
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213 (eq_attr "mode" "SF")))
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214 "r10k_fpdiv * 14")
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215
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216 (define_insn_reservation "r10k_fdiv_double" 19
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217 (and (eq_attr "cpu" "r10000")
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218 (and (eq_attr "type" "fdiv,frdiv")
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219 (eq_attr "mode" "DF")))
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220 "r10k_fpdiv * 21")
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221
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222 (define_insn_reservation "r10k_fsqrt_single" 18
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223 (and (eq_attr "cpu" "r10000")
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224 (and (eq_attr "type" "fsqrt")
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225 (eq_attr "mode" "SF")))
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226 "r10k_fpsqrt * 20")
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227
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228 (define_insn_reservation "r10k_fsqrt_double" 33
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229 (and (eq_attr "cpu" "r10000")
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230 (and (eq_attr "type" "fsqrt")
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231 (eq_attr "mode" "DF")))
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232 "r10k_fpsqrt * 35")
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233
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234 (define_insn_reservation "r10k_frsqrt_single" 30
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235 (and (eq_attr "cpu" "r10000")
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236 (and (eq_attr "type" "frsqrt")
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237 (eq_attr "mode" "SF")))
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238 "r10k_fpsqrt * 20")
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239
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240 (define_insn_reservation "r10k_frsqrt_double" 52
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241 (and (eq_attr "cpu" "r10000")
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242 (and (eq_attr "type" "frsqrt")
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243 (eq_attr "mode" "DF")))
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244 "r10k_fpsqrt * 35")
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245
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246
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247 ;; Handle unknown/multi insns here (this is a guess).
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248 (define_insn_reservation "r10k_unknown" 1
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249 (and (eq_attr "cpu" "r10000")
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111
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250 (eq_attr "type" "unknown,multi,atomic,syncloop"))
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251 "r10k_alu1 + r10k_alu2")
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