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annotate gcc/config/rs6000/dfp.md @ 158:494b0b89df80 default tip

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author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Mon, 25 May 2020 18:13:55 +0900
parents 1830386684a0
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 ;; Decimal Floating Point (DFP) patterns.
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2 ;; Copyright (C) 2007-2020 Free Software Foundation, Inc.
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3 ;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner
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4 ;; (bergner@vnet.ibm.com).
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5
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6 ;; This file is part of GCC.
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7
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8 ;; GCC is free software; you can redistribute it and/or modify it
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9 ;; under the terms of the GNU General Public License as published
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10 ;; by the Free Software Foundation; either version 3, or (at your
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11 ;; option) any later version.
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12
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13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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16 ;; License for more details.
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17
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 ;;
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23 ;; UNSPEC usage
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24 ;;
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25
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26 (define_c_enum "unspec"
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27 [UNSPEC_MOVSD_LOAD
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28 UNSPEC_MOVSD_STORE
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29 ])
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30
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31 ; Either of the two decimal modes.
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32 (define_mode_iterator DDTD [DD TD])
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33
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34 (define_mode_attr q [(DD "") (TD "q")])
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35
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36
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37 (define_insn "movsd_store"
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38 [(set (match_operand:DD 0 "nonimmediate_operand" "=m")
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39 (unspec:DD [(match_operand:SD 1 "input_operand" "d")]
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40 UNSPEC_MOVSD_STORE))]
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41 "(gpc_reg_operand (operands[0], DDmode)
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42 || gpc_reg_operand (operands[1], SDmode))
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43 && TARGET_HARD_FLOAT"
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44 "stfd%U0%X0 %1,%0"
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45 [(set_attr "type" "fpstore")])
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46
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47 (define_insn "movsd_load"
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48 [(set (match_operand:SD 0 "nonimmediate_operand" "=f")
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49 (unspec:SD [(match_operand:DD 1 "input_operand" "m")]
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50 UNSPEC_MOVSD_LOAD))]
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51 "(gpc_reg_operand (operands[0], SDmode)
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52 || gpc_reg_operand (operands[1], DDmode))
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53 && TARGET_HARD_FLOAT"
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54 "lfd%U1%X1 %0,%1"
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55 [(set_attr "type" "fpload")])
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56
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57 ;; Hardware support for decimal floating point operations.
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58
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59 (define_insn "extendsddd2"
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60 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
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61 (float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))]
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62 "TARGET_DFP"
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63 "dctdp %0,%1"
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64 [(set_attr "type" "dfp")])
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65
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66 (define_expand "extendsdtd2"
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67 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
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68 (float_extend:TD (match_operand:SD 1 "gpc_reg_operand" "d")))]
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69 "TARGET_DFP"
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70 {
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71 rtx tmp = gen_reg_rtx (DDmode);
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72 emit_insn (gen_extendsddd2 (tmp, operands[1]));
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73 emit_insn (gen_extendddtd2 (operands[0], tmp));
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74 DONE;
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75 })
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76
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77 (define_insn "truncddsd2"
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78 [(set (match_operand:SD 0 "gpc_reg_operand" "=f")
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79 (float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "d")))]
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80 "TARGET_DFP"
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81 "drsp %0,%1"
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82 [(set_attr "type" "dfp")])
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83
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84 (define_insn "negdd2"
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85 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
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86 (neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
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87 "TARGET_HARD_FLOAT"
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88 "fneg %0,%1"
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89 [(set_attr "type" "fpsimple")])
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91 (define_insn "absdd2"
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92 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
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93 (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
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94 "TARGET_HARD_FLOAT"
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95 "fabs %0,%1"
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96 [(set_attr "type" "fpsimple")])
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97
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98 (define_insn "*nabsdd2_fpr"
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99 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
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100 (neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))]
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101 "TARGET_HARD_FLOAT"
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102 "fnabs %0,%1"
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103 [(set_attr "type" "fpsimple")])
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104
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105 (define_insn "negtd2"
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106 [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
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107 (neg:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
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108 "TARGET_HARD_FLOAT"
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109 "@
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110 fneg %0,%1
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111 fneg %0,%1\;fmr %L0,%L1"
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112 [(set_attr "type" "fpsimple")
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113 (set_attr "length" "4,8")])
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114
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115 (define_insn "abstd2"
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116 [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
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117 (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
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118 "TARGET_HARD_FLOAT"
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119 "@
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120 fabs %0,%1
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121 fabs %0,%1\;fmr %L0,%L1"
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122 [(set_attr "type" "fpsimple")
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123 (set_attr "length" "4,8")])
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124
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125 (define_insn "*nabstd2_fpr"
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126 [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
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127 (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))]
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128 "TARGET_HARD_FLOAT"
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129 "@
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130 fnabs %0,%1
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131 fnabs %0,%1\;fmr %L0,%L1"
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132 [(set_attr "type" "fpsimple")
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133 (set_attr "length" "4,8")])
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134
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135 ;; Hardware support for decimal floating point operations.
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136
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137 (define_insn "extendddtd2"
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138 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
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139 (float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))]
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140 "TARGET_DFP"
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141 "dctqpq %0,%1"
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142 [(set_attr "type" "dfp")])
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143
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144 ;; The result of drdpq is an even/odd register pair with the converted
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145 ;; value in the even register and zero in the odd register.
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146 ;; FIXME: Avoid the register move by using a reload constraint to ensure
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147 ;; that the result is the first of the pair receiving the result of drdpq.
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148
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149 (define_insn "trunctddd2"
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150 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
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151 (float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "d")))
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152 (clobber (match_scratch:TD 2 "=d"))]
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153 "TARGET_DFP"
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154 "drdpq %2,%1\;fmr %0,%2"
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155 [(set_attr "type" "dfp")
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156 (set_attr "length" "8")])
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157
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158 (define_insn "add<mode>3"
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159 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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160 (plus:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "%d")
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161 (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
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162 "TARGET_DFP"
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163 "dadd<q> %0,%1,%2"
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164 [(set_attr "type" "dfp")])
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165
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166 (define_insn "sub<mode>3"
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167 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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168 (minus:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")
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169 (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
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170 "TARGET_DFP"
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171 "dsub<q> %0,%1,%2"
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172 [(set_attr "type" "dfp")])
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173
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174 (define_insn "mul<mode>3"
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175 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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176 (mult:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "%d")
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177 (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
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178 "TARGET_DFP"
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179 "dmul<q> %0,%1,%2"
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180 [(set_attr "type" "dfp")])
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181
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182 (define_insn "div<mode>3"
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183 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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184 (div:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")
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185 (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
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186 "TARGET_DFP"
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187 "ddiv<q> %0,%1,%2"
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188 [(set_attr "type" "dfp")])
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189
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190 (define_insn "*cmp<mode>_internal1"
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191 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
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192 (compare:CCFP (match_operand:DDTD 1 "gpc_reg_operand" "d")
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193 (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
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194 "TARGET_DFP"
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195 "dcmpu<q> %0,%1,%2"
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196 [(set_attr "type" "dfp")])
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197
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198 (define_insn "floatdidd2"
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199 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
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200 (float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
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201 "TARGET_DFP && TARGET_POPCNTD"
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202 "dcffix %0,%1"
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203 [(set_attr "type" "dfp")])
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204
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205 (define_insn "floatditd2"
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206 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
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207 (float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))]
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208 "TARGET_DFP"
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209 "dcffixq %0,%1"
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210 [(set_attr "type" "dfp")])
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211
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212 ;; Convert a decimal64/128 to a decimal64/128 whose value is an integer.
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213 ;; This is the first stage of converting it to an integer type.
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214
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215 (define_insn "ftrunc<mode>2"
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216 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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217 (fix:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")))]
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218 "TARGET_DFP"
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219 "drintn<q>. 0,%0,%1,1"
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220 [(set_attr "type" "dfp")])
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221
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222 ;; Convert a decimal64/128 whose value is an integer to an actual integer.
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223 ;; This is the second stage of converting decimal float to integer type.
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224
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225 (define_insn "fix<mode>di2"
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226 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
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227 (fix:DI (match_operand:DDTD 1 "gpc_reg_operand" "d")))]
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228 "TARGET_DFP"
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229 "dctfix<q> %0,%1"
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230 [(set_attr "type" "dfp")])
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231
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232 ;; Decimal builtin support
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233
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234 (define_c_enum "unspec"
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235 [UNSPEC_DDEDPD
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236 UNSPEC_DENBCD
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237 UNSPEC_DXEX
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238 UNSPEC_DIEX
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239 UNSPEC_DSCLI
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240 UNSPEC_DTSTSFI
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241 UNSPEC_DSCRI])
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242
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243 (define_code_iterator DFP_TEST [eq lt gt unordered])
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244
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245 (define_insn "dfp_ddedpd_<mode>"
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246 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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247 (unspec:DDTD [(match_operand:QI 1 "const_0_to_3_operand" "i")
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248 (match_operand:DDTD 2 "gpc_reg_operand" "d")]
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249 UNSPEC_DDEDPD))]
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250 "TARGET_DFP"
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251 "ddedpd<q> %1,%0,%2"
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252 [(set_attr "type" "dfp")])
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253
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254 (define_insn "dfp_denbcd_<mode>"
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255 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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256 (unspec:DDTD [(match_operand:QI 1 "const_0_to_1_operand" "i")
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257 (match_operand:DDTD 2 "gpc_reg_operand" "d")]
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258 UNSPEC_DENBCD))]
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259 "TARGET_DFP"
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260 "denbcd<q> %1,%0,%2"
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261 [(set_attr "type" "dfp")])
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262
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263 (define_insn "dfp_dxex_<mode>"
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264 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
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265 (unspec:DI [(match_operand:DDTD 1 "gpc_reg_operand" "d")]
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266 UNSPEC_DXEX))]
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267 "TARGET_DFP"
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268 "dxex<q> %0,%1"
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269 [(set_attr "type" "dfp")])
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270
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271 (define_insn "dfp_diex_<mode>"
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272 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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273 (unspec:DDTD [(match_operand:DI 1 "gpc_reg_operand" "d")
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274 (match_operand:DDTD 2 "gpc_reg_operand" "d")]
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275 UNSPEC_DXEX))]
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276 "TARGET_DFP"
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277 "diex<q> %0,%1,%2"
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278 [(set_attr "type" "dfp")])
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279
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280 (define_expand "dfptstsfi_<code>_<mode>"
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281 [(set (match_dup 3)
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282 (compare:CCFP (unspec:DDTD [(match_operand:SI 1 "const_int_operand")
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283 (match_operand:DDTD 2 "gpc_reg_operand")]
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284 UNSPEC_DTSTSFI)
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285 (const_int 0)))
131
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286 (set (match_operand:SI 0 "register_operand")
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287 (DFP_TEST:SI (match_dup 3)
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288 (const_int 0)))
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289 ]
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290 "TARGET_P9_MISC"
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291 {
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292 if (<CODE> == UNORDERED && !HONOR_NANS (<MODE>mode))
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293 {
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294 emit_move_insn (operands[0], const0_rtx);
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295 DONE;
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296 }
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297
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298 operands[3] = gen_reg_rtx (CCFPmode);
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299 })
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300
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301 (define_insn "*dfp_sgnfcnc_<mode>"
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302 [(set (match_operand:CCFP 0 "" "=y")
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303 (compare:CCFP
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304 (unspec:DDTD [(match_operand:SI 1 "const_int_operand" "n")
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305 (match_operand:DDTD 2 "gpc_reg_operand" "d")]
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306 UNSPEC_DTSTSFI)
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307 (match_operand:SI 3 "zero_constant" "j")))]
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308 "TARGET_P9_MISC"
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309 {
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310 /* If immediate operand is greater than 63, it will behave as if
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311 the value had been 63. The code generator does not support
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312 immediate operand values greater than 63. */
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313 if (!(IN_RANGE (INTVAL (operands[1]), 0, 63)))
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314 operands[1] = GEN_INT (63);
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315 return "dtstsfi<q> %0,%1,%2";
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316 }
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317 [(set_attr "type" "fp")])
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318
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319 (define_insn "dfp_dscli_<mode>"
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320 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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321 (unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
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322 (match_operand:QI 2 "immediate_operand" "i")]
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323 UNSPEC_DSCLI))]
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324 "TARGET_DFP"
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325 "dscli<q> %0,%1,%2"
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326 [(set_attr "type" "dfp")])
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327
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328 (define_insn "dfp_dscri_<mode>"
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329 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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330 (unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
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331 (match_operand:QI 2 "immediate_operand" "i")]
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332 UNSPEC_DSCRI))]
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333 "TARGET_DFP"
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334 "dscri<q> %0,%1,%2"
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335 [(set_attr "type" "dfp")])