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1 /* IBM RS/6000 CPU names..
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2 Copyright (C) 1991-2020 Free Software Foundation, Inc.
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3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it
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8 under the terms of the GNU General Public License as published
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9 by the Free Software Foundation; either version 3, or (at your
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10 option) any later version.
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11
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12 GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21 /* ISA masks. */
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22 #ifndef ISA_2_1_MASKS
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23 #define ISA_2_1_MASKS OPTION_MASK_MFCRF
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24 #define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
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25 #define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND)
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26
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27 /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on
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28 power6. In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented
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29 as optional. Group masks by server and embedded. */
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30 #define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \
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31 | OPTION_MASK_CMPB \
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32 | OPTION_MASK_RECIP_PRECISION \
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33 | OPTION_MASK_PPC_GFXOPT \
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34 | OPTION_MASK_PPC_GPOPT)
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35
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36 #define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)
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37
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38 /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
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39 altivec is a win so enable it. */
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40 #define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
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41 #define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
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42 | OPTION_MASK_POPCNTD \
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43 | OPTION_MASK_ALTIVEC \
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44 | OPTION_MASK_VSX)
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45
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46 /* For now, don't provide an embedded version of ISA 2.07. Do not set power8
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47 fusion here, instead set it in rs6000.c if we are tuning for a power8
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48 system. */
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49 #define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
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50 | OPTION_MASK_P8_VECTOR \
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51 | OPTION_MASK_CRYPTO \
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52 | OPTION_MASK_DIRECT_MOVE \
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53 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
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54 | OPTION_MASK_HTM \
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55 | OPTION_MASK_QUAD_MEMORY \
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56 | OPTION_MASK_QUAD_MEMORY_ATOMIC)
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57
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58 /* ISA masks setting fusion options. */
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59 #define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \
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60 | OPTION_MASK_P8_FUSION_SIGN)
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61
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111
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62 /* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
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63 FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
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64 #define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \
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65 | OPTION_MASK_ISEL \
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66 | OPTION_MASK_MODULO \
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67 | OPTION_MASK_P9_MINMAX \
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68 | OPTION_MASK_P9_MISC \
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69 | OPTION_MASK_P9_VECTOR) \
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70 & ~OTHER_FUSION_MASKS)
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71
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72 /* Support for the IEEE 128-bit floating point hardware requires a lot of the
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73 VSX instructions that are part of ISA 3.0. */
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74 #define ISA_3_0_MASKS_IEEE (OPTION_MASK_VSX \
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75 | OPTION_MASK_P8_VECTOR \
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76 | OPTION_MASK_P9_VECTOR)
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77
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78 /* Support for a future processor's features. Do not enable -mpcrel until it
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79 is fully functional. */
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80 #define ISA_FUTURE_MASKS_SERVER (ISA_3_0_MASKS_SERVER \
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81 | OPTION_MASK_FUTURE \
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82 | OPTION_MASK_PREFIXED)
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83
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84 /* Flags that need to be turned off if -mno-future. */
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85 #define OTHER_FUTURE_MASKS (OPTION_MASK_PCREL \
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86 | OPTION_MASK_PREFIXED)
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87
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88 /* Flags that need to be turned off if -mno-power9-vector. */
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89 #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
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90 | OPTION_MASK_P9_MINMAX)
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91
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92 /* Flags that need to be turned off if -mno-power8-vector. */
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93 #define OTHER_P8_VECTOR_MASKS (OTHER_P9_VECTOR_MASKS \
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94 | OPTION_MASK_P9_VECTOR \
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95 | OPTION_MASK_DIRECT_MOVE \
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96 | OPTION_MASK_CRYPTO)
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97
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98 /* Flags that need to be turned off if -mno-vsx. */
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99 #define OTHER_VSX_VECTOR_MASKS (OTHER_P8_VECTOR_MASKS \
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100 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
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101 | OPTION_MASK_FLOAT128_KEYWORD \
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102 | OPTION_MASK_P8_VECTOR)
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103
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104 #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
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105
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106 /* Deal with ports that do not have -mstrict-align. */
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107 #ifdef OPTION_MASK_STRICT_ALIGN
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108 #define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
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109 #else
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110 #define OPTION_MASK_STRICT_ALIGN 0
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111 #define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
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112 #ifndef MASK_STRICT_ALIGN
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113 #define MASK_STRICT_ALIGN 0
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114 #endif
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115 #endif
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116
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117 /* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
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118 #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
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119 | OPTION_MASK_CMPB \
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120 | OPTION_MASK_CRYPTO \
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121 | OPTION_MASK_DFP \
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122 | OPTION_MASK_DIRECT_MOVE \
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123 | OPTION_MASK_DLMZB \
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124 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
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125 | OPTION_MASK_FLOAT128_HW \
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126 | OPTION_MASK_FLOAT128_KEYWORD \
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127 | OPTION_MASK_FPRND \
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128 | OPTION_MASK_FUTURE \
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129 | OPTION_MASK_HTM \
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130 | OPTION_MASK_ISEL \
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131 | OPTION_MASK_MFCRF \
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132 | OPTION_MASK_MODULO \
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133 | OPTION_MASK_MULHW \
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134 | OPTION_MASK_NO_UPDATE \
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135 | OPTION_MASK_P8_FUSION \
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136 | OPTION_MASK_P8_VECTOR \
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137 | OPTION_MASK_P9_MINMAX \
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138 | OPTION_MASK_P9_MISC \
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139 | OPTION_MASK_P9_VECTOR \
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140 | OPTION_MASK_PCREL \
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141 | OPTION_MASK_POPCNTB \
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142 | OPTION_MASK_POPCNTD \
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143 | OPTION_MASK_POWERPC64 \
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144 | OPTION_MASK_PPC_GFXOPT \
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145 | OPTION_MASK_PPC_GPOPT \
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146 | OPTION_MASK_PREFIXED \
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147 | OPTION_MASK_QUAD_MEMORY \
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148 | OPTION_MASK_QUAD_MEMORY_ATOMIC \
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149 | OPTION_MASK_RECIP_PRECISION \
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150 | OPTION_MASK_SOFT_FLOAT \
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151 | OPTION_MASK_STRICT_ALIGN_OPTIONAL \
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152 | OPTION_MASK_VSX)
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153
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154 #endif
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155
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156 /* This table occasionally claims that a processor does not support a
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157 particular feature even though it does, but the feature is slower than the
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158 alternative. Thus, it shouldn't be relied on as a complete description of
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159 the processor's support.
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160
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161 Please keep this list in order, and don't forget to update the documentation
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162 in invoke.texi when adding a new processor or flag.
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163
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164 Before including this file, define a macro:
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165
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166 RS6000_CPU (NAME, CPU, FLAGS)
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167
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168 where the arguments are the fields of struct rs6000_ptt. */
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169
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170 RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
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171 RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
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172 RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
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173 RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
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174 RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
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175 RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
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176 RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
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177 RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
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178 RS6000_CPU ("476", PROCESSOR_PPC476,
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179 MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
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180 | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
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181 RS6000_CPU ("476fp", PROCESSOR_PPC476,
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182 MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
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183 | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
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184 RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
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185 RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE)
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186 RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
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187 RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
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188 RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
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189 RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
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190 RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
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191 RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
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192 RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
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193 RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
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194 RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
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195 RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
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196 RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
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197 RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
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198 RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
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199 RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
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200 RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL)
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201 RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL)
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202 RS6000_CPU ("a2", PROCESSOR_PPCA2,
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203 MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB
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204 | MASK_NO_UPDATE)
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205 RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
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206 RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
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207 RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL)
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208 RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
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209 MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
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210 RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
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211 MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
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212 RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
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213 | MASK_MFCRF | MASK_ISEL)
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214 RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
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215 RS6000_CPU ("970", PROCESSOR_POWER4,
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216 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
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217 RS6000_CPU ("cell", PROCESSOR_CELL,
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218 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
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219 RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
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220 RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
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221 RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK)
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222 RS6000_CPU ("G5", PROCESSOR_POWER4,
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223 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
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224 RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB)
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225 RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
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226 RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
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227 | MASK_PPC_GFXOPT | MASK_MFCRF)
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228 RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
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229 | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB)
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230 RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
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231 | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
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232 RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
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233 | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
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234 | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
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235 RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
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236 | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
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237 | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
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238 RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
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239 RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
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240 RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER)
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241 RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
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242 RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
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243 RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
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244 RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)
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245 RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64
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246 | ISA_FUTURE_MASKS_SERVER)
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