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1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
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2 Copyright (C) 2002-2020 Free Software Foundation, Inc.
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3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it
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8 under the terms of the GNU General Public License as published
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9 by the Free Software Foundation; either version 3, or (at your
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10 option) any later version.
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11
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12 GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21 /* We order the 3 128-bit floating point types so that IFmode (IBM 128-bit
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22 floating point) is the 128-bit floating point type with the highest
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23 precision (128 bits). This so that machine independent parts of the
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24 compiler do not try to widen IFmode to TFmode on ISA 3.0 (power9) that has
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25 hardware support for IEEE 128-bit. We set TFmode (long double mode) in
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26 between, and KFmode (explicit __float128) below it.
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27
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28 Previously, IFmode and KFmode were defined to be fractional modes and TFmode
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29 was the standard mode. Since IFmode does not define the normal arithmetic
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30 insns (other than neg/abs), on a ISA 3.0 system, the machine independent
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31 parts of the compiler would see that TFmode has the necessary hardware
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32 support, and widen the operation from IFmode to TFmode. However, IEEE
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33 128-bit is not strictly a super-set of IBM extended double and the
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34 conversion to/from IEEE 128-bit was a function call.
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35
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36 We now make IFmode the highest fractional mode, which means its values are
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37 not considered for widening. Since we don't define insns for IFmode, the
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38 IEEE 128-bit modes would not widen to IFmode. */
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39
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40 #ifndef RS6000_MODES_H
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41 #include "config/rs6000/rs6000-modes.h"
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42 #endif
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43
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44 /* IBM 128-bit floating point. */
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45 FRACTIONAL_FLOAT_MODE (IF, FLOAT_PRECISION_IFmode, 16, ibm_extended_format);
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46
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47 /* Explicit IEEE 128-bit floating point. */
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48 FRACTIONAL_FLOAT_MODE (KF, FLOAT_PRECISION_KFmode, 16, ieee_quad_format);
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49
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50 /* 128-bit floating point, either IBM 128-bit or IEEE 128-bit. This is
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51 adjusted in rs6000_option_override_internal to be the appropriate floating
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52 point type. */
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53 FRACTIONAL_FLOAT_MODE (TF, FLOAT_PRECISION_TFmode, 16, ieee_quad_format);
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54
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55 /* Add any extra modes needed to represent the condition code.
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56
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57 For the RS/6000, we need separate modes when unsigned (logical) comparisons
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58 are being done and we need a separate mode for floating-point. We also
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59 use a mode for the case when we are comparing the results of two
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60 comparisons, as then only the EQ bit is valid in the register. */
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61
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62 CC_MODE (CCUNS);
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63 CC_MODE (CCFP);
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64 CC_MODE (CCEQ);
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65
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66 /* Vector modes. */
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67
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68 /* VMX/VSX. */
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69 VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */
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70 VECTOR_MODE (INT, TI, 1); /* V1TI */
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71 VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */
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72
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73 /* Two VMX/VSX vectors (for permute, select, concat, etc.) */
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74 VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */
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75 VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */
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76
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77 /* Half VMX/VSX vector (for internal use) */
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78 VECTOR_MODE (FLOAT, SF, 2); /* V2SF */
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79 VECTOR_MODE (INT, SI, 2); /* V2SI */
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80
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81 /* Replacement for TImode that only is allowed in GPRs. We also use PTImode
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82 for quad memory atomic operations to force getting an even/odd register
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83 combination. */
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84 PARTIAL_INT_MODE (TI, 128, PTI);
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